1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/of_address.h> 8 #include <linux/platform_device.h> 9 10 #include "ccu_common.h" 11 #include "ccu_reset.h" 12 13 #include "ccu_div.h" 14 #include "ccu_gate.h" 15 #include "ccu_mp.h" 16 #include "ccu_nm.h" 17 18 #include "ccu-sun8i-r.h" 19 20 static const struct clk_parent_data ar100_parents[] = { 21 { .fw_name = "losc" }, 22 { .fw_name = "hosc" }, 23 { .fw_name = "pll-periph" }, 24 { .fw_name = "iosc" }, 25 }; 26 27 static const struct ccu_mux_var_prediv ar100_predivs[] = { 28 { .index = 2, .shift = 8, .width = 5 }, 29 }; 30 31 static struct ccu_div ar100_clk = { 32 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 33 34 .mux = { 35 .shift = 16, 36 .width = 2, 37 38 .var_predivs = ar100_predivs, 39 .n_var_predivs = ARRAY_SIZE(ar100_predivs), 40 }, 41 42 .common = { 43 .reg = 0x00, 44 .features = CCU_FEATURE_VARIABLE_PREDIV, 45 .hw.init = CLK_HW_INIT_PARENTS_DATA("ar100", 46 ar100_parents, 47 &ccu_div_ops, 48 0), 49 }, 50 }; 51 52 static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0); 53 54 static SUNXI_CCU_M(apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0); 55 56 /* 57 * Define the parent as an array that can be reused to save space 58 * instead of having compound literals for each gate. Also have it 59 * non-const so we can change it on the A83T. 60 */ 61 static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw }; 62 static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio", 63 apb0_gate_parent, 0x28, BIT(0), 0); 64 static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir", 65 apb0_gate_parent, 0x28, BIT(1), 0); 66 static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer", 67 apb0_gate_parent, 0x28, BIT(2), 0); 68 static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb", 69 apb0_gate_parent, 0x28, BIT(3), 0); 70 static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart", 71 apb0_gate_parent, 0x28, BIT(4), 0); 72 static SUNXI_CCU_GATE_HWS(apb0_i2c_clk, "apb0-i2c", 73 apb0_gate_parent, 0x28, BIT(6), 0); 74 static SUNXI_CCU_GATE_HWS(apb0_twd_clk, "apb0-twd", 75 apb0_gate_parent, 0x28, BIT(7), 0); 76 77 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; 78 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", 79 r_mod0_default_parents, 0x54, 80 0, 4, /* M */ 81 16, 2, /* P */ 82 24, 2, /* mux */ 83 BIT(31), /* gate */ 84 0); 85 86 static const struct clk_parent_data a83t_r_mod0_parents[] = { 87 { .fw_name = "iosc" }, 88 { .fw_name = "hosc" }, 89 }; 90 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = { 91 { .index = 0, .div = 16 }, 92 }; 93 static struct ccu_mp a83t_ir_clk = { 94 .enable = BIT(31), 95 96 .m = _SUNXI_CCU_DIV(0, 4), 97 .p = _SUNXI_CCU_DIV(16, 2), 98 99 .mux = { 100 .shift = 24, 101 .width = 2, 102 .fixed_predivs = a83t_ir_predivs, 103 .n_predivs = ARRAY_SIZE(a83t_ir_predivs), 104 }, 105 106 .common = { 107 .reg = 0x54, 108 .features = CCU_FEATURE_VARIABLE_PREDIV, 109 .hw.init = CLK_HW_INIT_PARENTS_DATA("ir", 110 a83t_r_mod0_parents, 111 &ccu_mp_ops, 112 0), 113 }, 114 }; 115 116 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = { 117 &ar100_clk.common, 118 &apb0_clk.common, 119 &apb0_pio_clk.common, 120 &apb0_ir_clk.common, 121 &apb0_timer_clk.common, 122 &apb0_rsb_clk.common, 123 &apb0_uart_clk.common, 124 &apb0_i2c_clk.common, 125 &apb0_twd_clk.common, 126 &a83t_ir_clk.common, 127 }; 128 129 static struct ccu_common *sun8i_h3_r_ccu_clks[] = { 130 &ar100_clk.common, 131 &apb0_clk.common, 132 &apb0_pio_clk.common, 133 &apb0_ir_clk.common, 134 &apb0_timer_clk.common, 135 &apb0_uart_clk.common, 136 &apb0_i2c_clk.common, 137 &apb0_twd_clk.common, 138 &ir_clk.common, 139 }; 140 141 static struct ccu_common *sun50i_a64_r_ccu_clks[] = { 142 &ar100_clk.common, 143 &apb0_clk.common, 144 &apb0_pio_clk.common, 145 &apb0_ir_clk.common, 146 &apb0_timer_clk.common, 147 &apb0_rsb_clk.common, 148 &apb0_uart_clk.common, 149 &apb0_i2c_clk.common, 150 &apb0_twd_clk.common, 151 &ir_clk.common, 152 }; 153 154 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = { 155 .hws = { 156 [CLK_AR100] = &ar100_clk.common.hw, 157 [CLK_AHB0] = &ahb0_clk.hw, 158 [CLK_APB0] = &apb0_clk.common.hw, 159 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 160 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 161 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 162 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 163 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 164 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 165 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 166 [CLK_IR] = &a83t_ir_clk.common.hw, 167 }, 168 .num = CLK_NUMBER, 169 }; 170 171 static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { 172 .hws = { 173 [CLK_AR100] = &ar100_clk.common.hw, 174 [CLK_AHB0] = &ahb0_clk.hw, 175 [CLK_APB0] = &apb0_clk.common.hw, 176 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 177 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 178 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 179 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 180 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 181 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 182 [CLK_IR] = &ir_clk.common.hw, 183 }, 184 .num = CLK_NUMBER, 185 }; 186 187 static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { 188 .hws = { 189 [CLK_AR100] = &ar100_clk.common.hw, 190 [CLK_AHB0] = &ahb0_clk.hw, 191 [CLK_APB0] = &apb0_clk.common.hw, 192 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 193 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 194 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 195 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 196 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 197 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 198 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 199 [CLK_IR] = &ir_clk.common.hw, 200 }, 201 .num = CLK_NUMBER, 202 }; 203 204 static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = { 205 [RST_APB0_IR] = { 0xb0, BIT(1) }, 206 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 207 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 208 [RST_APB0_UART] = { 0xb0, BIT(4) }, 209 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 210 }; 211 212 static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { 213 [RST_APB0_IR] = { 0xb0, BIT(1) }, 214 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 215 [RST_APB0_UART] = { 0xb0, BIT(4) }, 216 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 217 }; 218 219 static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { 220 [RST_APB0_IR] = { 0xb0, BIT(1) }, 221 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 222 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 223 [RST_APB0_UART] = { 0xb0, BIT(4) }, 224 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 225 }; 226 227 static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = { 228 .ccu_clks = sun8i_a83t_r_ccu_clks, 229 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks), 230 231 .hw_clks = &sun8i_a83t_r_hw_clks, 232 233 .resets = sun8i_a83t_r_ccu_resets, 234 .num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets), 235 }; 236 237 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { 238 .ccu_clks = sun8i_h3_r_ccu_clks, 239 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), 240 241 .hw_clks = &sun8i_h3_r_hw_clks, 242 243 .resets = sun8i_h3_r_ccu_resets, 244 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), 245 }; 246 247 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { 248 .ccu_clks = sun50i_a64_r_ccu_clks, 249 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), 250 251 .hw_clks = &sun50i_a64_r_hw_clks, 252 253 .resets = sun50i_a64_r_ccu_resets, 254 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), 255 }; 256 257 static void __init sunxi_r_ccu_init(struct device_node *node, 258 const struct sunxi_ccu_desc *desc) 259 { 260 void __iomem *reg; 261 262 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 263 if (IS_ERR(reg)) { 264 pr_err("%pOF: Could not map the clock registers\n", node); 265 return; 266 } 267 268 sunxi_ccu_probe(node, reg, desc); 269 } 270 271 static void __init sun8i_a83t_r_ccu_setup(struct device_node *node) 272 { 273 sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc); 274 } 275 CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu", 276 sun8i_a83t_r_ccu_setup); 277 278 static void __init sun8i_h3_r_ccu_setup(struct device_node *node) 279 { 280 sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); 281 } 282 CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", 283 sun8i_h3_r_ccu_setup); 284 285 static void __init sun50i_a64_r_ccu_setup(struct device_node *node) 286 { 287 sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); 288 } 289 CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", 290 sun50i_a64_r_ccu_setup); 291