10577e485SMaxime Ripard /* 20577e485SMaxime Ripard * Copyright 2016 Maxime Ripard 30577e485SMaxime Ripard * 40577e485SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 50577e485SMaxime Ripard * 60577e485SMaxime Ripard * This program is free software; you can redistribute it and/or modify 70577e485SMaxime Ripard * it under the terms of the GNU General Public License as published by 80577e485SMaxime Ripard * the Free Software Foundation; either version 2 of the License, or 90577e485SMaxime Ripard * (at your option) any later version. 100577e485SMaxime Ripard * 110577e485SMaxime Ripard * This program is distributed in the hope that it will be useful, 120577e485SMaxime Ripard * but WITHOUT ANY WARRANTY; without even the implied warranty of 130577e485SMaxime Ripard * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 140577e485SMaxime Ripard * GNU General Public License for more details. 150577e485SMaxime Ripard */ 160577e485SMaxime Ripard 170577e485SMaxime Ripard #ifndef _CCU_SUN8I_H3_H_ 180577e485SMaxime Ripard #define _CCU_SUN8I_H3_H_ 190577e485SMaxime Ripard 200577e485SMaxime Ripard #include <dt-bindings/clock/sun8i-h3-ccu.h> 210577e485SMaxime Ripard #include <dt-bindings/reset/sun8i-h3-ccu.h> 220577e485SMaxime Ripard 230577e485SMaxime Ripard #define CLK_PLL_CPUX 0 240577e485SMaxime Ripard #define CLK_PLL_AUDIO_BASE 1 250577e485SMaxime Ripard #define CLK_PLL_AUDIO 2 260577e485SMaxime Ripard #define CLK_PLL_AUDIO_2X 3 270577e485SMaxime Ripard #define CLK_PLL_AUDIO_4X 4 280577e485SMaxime Ripard #define CLK_PLL_AUDIO_8X 5 29*55de0f31SJernej Skrabec 30*55de0f31SJernej Skrabec /* PLL_VIDEO is exported */ 31*55de0f31SJernej Skrabec 320577e485SMaxime Ripard #define CLK_PLL_VE 7 330577e485SMaxime Ripard #define CLK_PLL_DDR 8 34c4be8c68SChen-Yu Tsai 35c4be8c68SChen-Yu Tsai /* PLL_PERIPH0 exported for PRCM */ 36c4be8c68SChen-Yu Tsai 370577e485SMaxime Ripard #define CLK_PLL_PERIPH0_2X 10 380577e485SMaxime Ripard #define CLK_PLL_GPU 11 390577e485SMaxime Ripard #define CLK_PLL_PERIPH1 12 400577e485SMaxime Ripard #define CLK_PLL_DE 13 410577e485SMaxime Ripard 420577e485SMaxime Ripard /* The CPUX clock is exported */ 430577e485SMaxime Ripard 440577e485SMaxime Ripard #define CLK_AXI 15 450577e485SMaxime Ripard #define CLK_AHB1 16 460577e485SMaxime Ripard #define CLK_APB1 17 470577e485SMaxime Ripard #define CLK_APB2 18 480577e485SMaxime Ripard #define CLK_AHB2 19 490577e485SMaxime Ripard 500577e485SMaxime Ripard /* All the bus gates are exported */ 510577e485SMaxime Ripard 520577e485SMaxime Ripard /* The first bunch of module clocks are exported */ 530577e485SMaxime Ripard 540577e485SMaxime Ripard #define CLK_DRAM 96 550577e485SMaxime Ripard 560577e485SMaxime Ripard /* All the DRAM gates are exported */ 570577e485SMaxime Ripard 580577e485SMaxime Ripard /* Some more module clocks are exported */ 590577e485SMaxime Ripard 600577e485SMaxime Ripard #define CLK_MBUS 113 610577e485SMaxime Ripard 620577e485SMaxime Ripard /* And the GPU module clock is exported */ 630577e485SMaxime Ripard 649be1c8afSIcenowy Zheng #define CLK_NUMBER_H3 (CLK_GPU + 1) 659be1c8afSIcenowy Zheng #define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1) 660577e485SMaxime Ripard 670577e485SMaxime Ripard #endif /* _CCU_SUN8I_H3_H_ */ 68