1c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2d05c748bSMaxime Ripard /* 3d05c748bSMaxime Ripard * Copyright 2016 Maxime Ripard 4d05c748bSMaxime Ripard * 5d05c748bSMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 6d05c748bSMaxime Ripard */ 7d05c748bSMaxime Ripard 8d05c748bSMaxime Ripard #ifndef _CCU_SUN8I_A23_A33_H_ 9d05c748bSMaxime Ripard #define _CCU_SUN8I_A23_A33_H_ 10d05c748bSMaxime Ripard 11d05c748bSMaxime Ripard #include <dt-bindings/clock/sun8i-a23-a33-ccu.h> 12d05c748bSMaxime Ripard #include <dt-bindings/reset/sun8i-a23-a33-ccu.h> 13d05c748bSMaxime Ripard 14d05c748bSMaxime Ripard #define CLK_PLL_CPUX 0 15d05c748bSMaxime Ripard #define CLK_PLL_AUDIO_BASE 1 16d05c748bSMaxime Ripard #define CLK_PLL_AUDIO 2 17d05c748bSMaxime Ripard #define CLK_PLL_AUDIO_2X 3 18d05c748bSMaxime Ripard #define CLK_PLL_AUDIO_4X 4 19d05c748bSMaxime Ripard #define CLK_PLL_AUDIO_8X 5 20d05c748bSMaxime Ripard #define CLK_PLL_VIDEO 6 21d05c748bSMaxime Ripard #define CLK_PLL_VIDEO_2X 7 22d05c748bSMaxime Ripard #define CLK_PLL_VE 8 23d05c748bSMaxime Ripard #define CLK_PLL_DDR0 9 24d05c748bSMaxime Ripard #define CLK_PLL_PERIPH 10 25d05c748bSMaxime Ripard #define CLK_PLL_PERIPH_2X 11 26d05c748bSMaxime Ripard #define CLK_PLL_GPU 12 27*9c232d32SMaxime Ripard 28*9c232d32SMaxime Ripard /* The PLL MIPI clock is exported */ 29*9c232d32SMaxime Ripard 30d05c748bSMaxime Ripard #define CLK_PLL_HSIC 14 31d05c748bSMaxime Ripard #define CLK_PLL_DE 15 32d05c748bSMaxime Ripard #define CLK_PLL_DDR1 16 33d05c748bSMaxime Ripard #define CLK_PLL_DDR 17 34d05c748bSMaxime Ripard 35d05c748bSMaxime Ripard /* The CPUX clock is exported */ 36d05c748bSMaxime Ripard 37d05c748bSMaxime Ripard #define CLK_AXI 19 38d05c748bSMaxime Ripard #define CLK_AHB1 20 39d05c748bSMaxime Ripard #define CLK_APB1 21 40d05c748bSMaxime Ripard #define CLK_APB2 22 41d05c748bSMaxime Ripard 42d05c748bSMaxime Ripard /* All the bus gates are exported */ 43d05c748bSMaxime Ripard 44d05c748bSMaxime Ripard /* The first part of the mod clocks is exported */ 45d05c748bSMaxime Ripard 46d05c748bSMaxime Ripard #define CLK_DRAM 79 47d05c748bSMaxime Ripard 48d05c748bSMaxime Ripard /* Some more module clocks are exported */ 49d05c748bSMaxime Ripard 50d05c748bSMaxime Ripard #define CLK_MBUS 95 51d05c748bSMaxime Ripard 52d05c748bSMaxime Ripard /* And the last module clocks are exported */ 53d05c748bSMaxime Ripard 54d05c748bSMaxime Ripard #define CLK_NUMBER (CLK_ATS + 1) 55d05c748bSMaxime Ripard 56d05c748bSMaxime Ripard #endif /* _CCU_SUN8I_A23_A33_H_ */ 57