1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 25e737617SMaxime Ripard /* 35e737617SMaxime Ripard * Copyright 2016 Maxime Ripard 45e737617SMaxime Ripard * 55e737617SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 65e737617SMaxime Ripard */ 75e737617SMaxime Ripard 85e737617SMaxime Ripard #ifndef _CCU_SUN5I_H_ 95e737617SMaxime Ripard #define _CCU_SUN5I_H_ 105e737617SMaxime Ripard 115e737617SMaxime Ripard #include <dt-bindings/clock/sun5i-ccu.h> 125e737617SMaxime Ripard #include <dt-bindings/reset/sun5i-ccu.h> 135e737617SMaxime Ripard 145e737617SMaxime Ripard /* The HOSC is exported */ 155e737617SMaxime Ripard #define CLK_PLL_CORE 2 165e737617SMaxime Ripard #define CLK_PLL_AUDIO_BASE 3 175e737617SMaxime Ripard #define CLK_PLL_AUDIO 4 185e737617SMaxime Ripard #define CLK_PLL_AUDIO_2X 5 195e737617SMaxime Ripard #define CLK_PLL_AUDIO_4X 6 205e737617SMaxime Ripard #define CLK_PLL_AUDIO_8X 7 215e737617SMaxime Ripard #define CLK_PLL_VIDEO0 8 220adad031SMaxime Ripard 230adad031SMaxime Ripard /* The PLL_VIDEO0_2X is exported for HDMI */ 240adad031SMaxime Ripard 255e737617SMaxime Ripard #define CLK_PLL_VE 10 265e737617SMaxime Ripard #define CLK_PLL_DDR_BASE 11 275e737617SMaxime Ripard #define CLK_PLL_DDR 12 285e737617SMaxime Ripard #define CLK_PLL_DDR_OTHER 13 295e737617SMaxime Ripard #define CLK_PLL_PERIPH 14 305e737617SMaxime Ripard #define CLK_PLL_VIDEO1 15 315e737617SMaxime Ripard 320adad031SMaxime Ripard /* The PLL_VIDEO1_2X is exported for HDMI */ 335e737617SMaxime Ripard /* The CPU clock is exported */ 345e737617SMaxime Ripard 355e737617SMaxime Ripard #define CLK_AXI 18 365e737617SMaxime Ripard #define CLK_AHB 19 375e737617SMaxime Ripard #define CLK_APB0 20 385e737617SMaxime Ripard #define CLK_APB1 21 395e737617SMaxime Ripard #define CLK_DRAM_AXI 22 405e737617SMaxime Ripard 415e737617SMaxime Ripard /* AHB gates are exported */ 425e737617SMaxime Ripard /* APB0 gates are exported */ 435e737617SMaxime Ripard /* APB1 gates are exported */ 445e737617SMaxime Ripard /* Modules clocks are exported */ 455e737617SMaxime Ripard /* USB clocks are exported */ 465e737617SMaxime Ripard /* GPS clock is exported */ 475e737617SMaxime Ripard /* DRAM gates are exported */ 485e737617SMaxime Ripard /* More display modules clocks are exported */ 495e737617SMaxime Ripard 505e737617SMaxime Ripard #define CLK_TCON_CH1_SCLK 91 515e737617SMaxime Ripard 525e737617SMaxime Ripard /* The rest of the module clocks are exported */ 535e737617SMaxime Ripard 545e737617SMaxime Ripard #define CLK_NUMBER (CLK_IEP + 1) 555e737617SMaxime Ripard 565e737617SMaxime Ripard #endif /* _CCU_SUN5I_H_ */ 57