1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2023-2024 Arm Ltd. 4 * Based on the D1 CCU driver: 5 * Copyright (c) 2020 huangzhenwei@allwinnertech.com 6 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 14 #include "../clk.h" 15 16 #include "ccu_common.h" 17 #include "ccu_reset.h" 18 19 #include "ccu_div.h" 20 #include "ccu_gate.h" 21 #include "ccu_mp.h" 22 #include "ccu_mult.h" 23 #include "ccu_nk.h" 24 #include "ccu_nkm.h" 25 #include "ccu_nkmp.h" 26 #include "ccu_nm.h" 27 28 #include "ccu-sun55i-a523.h" 29 30 /* 31 * The 24 MHz oscillator, the root of most of the clock tree. 32 * .fw_name is the string used in the DT "clock-names" property, used to 33 * identify the corresponding clock in the "clocks" property. 34 */ 35 static const struct clk_parent_data osc24M[] = { 36 { .fw_name = "hosc" } 37 }; 38 39 /************************************************************************** 40 * PLLs * 41 **************************************************************************/ 42 43 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ 44 #define SUN55I_A523_PLL_DDR0_REG 0x010 45 static struct ccu_nkmp pll_ddr_clk = { 46 .enable = BIT(27), 47 .lock = BIT(28), 48 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 49 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 50 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 51 .common = { 52 .reg = 0x010, 53 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M, 54 &ccu_nkmp_ops, 55 CLK_SET_RATE_GATE | 56 CLK_IS_CRITICAL), 57 }, 58 }; 59 60 /* 61 * There is no actual clock output with that frequency (2.4 GHz), instead it 62 * has multiple outputs with adjustable dividers from that base frequency. 63 * Model them separately as divider clocks based on that parent here. 64 */ 65 #define SUN55I_A523_PLL_PERIPH0_REG 0x020 66 static struct ccu_nm pll_periph0_4x_clk = { 67 .enable = BIT(27), 68 .lock = BIT(28), 69 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 70 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 71 .common = { 72 .reg = 0x020, 73 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x", 74 osc24M, &ccu_nm_ops, 75 CLK_SET_RATE_GATE), 76 }, 77 }; 78 /* 79 * Most clock-defining macros expect an *array* of parent clocks, even if 80 * they do not contain a muxer to select between different parents. 81 * The macros ending in just _HW take a simple clock pointer, but then create 82 * a single-entry array out of that. The macros using _HWS take such an 83 * array (even when it is a single entry one), this avoids having those 84 * helper arrays created inside *every* clock definition. 85 * This means for every clock that is referenced more than once it is 86 * useful to create such a dummy array and use _HWS. 87 */ 88 static const struct clk_hw *pll_periph0_4x_hws[] = { 89 &pll_periph0_4x_clk.common.hw 90 }; 91 92 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x", 93 pll_periph0_4x_hws, 0x020, 16, 3, 0); 94 static const struct clk_hw *pll_periph0_2x_hws[] = { 95 &pll_periph0_2x_clk.common.hw 96 }; 97 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M", 98 pll_periph0_4x_hws, 0x020, 20, 3, 0); 99 static SUNXI_CCU_M_HWS(pll_periph0_480M_clk, "pll-periph0-480M", 100 pll_periph0_4x_hws, 0x020, 2, 3, 0); 101 static const struct clk_hw *pll_periph0_480M_hws[] = { 102 &pll_periph0_480M_clk.common.hw 103 }; 104 static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M", 105 pll_periph0_2x_hws, 2, 1, 0); 106 static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M", 107 pll_periph0_2x_hws, 3, 1, 0); 108 static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M", 109 pll_periph0_2x_hws, 4, 1, 0); 110 static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", 111 pll_periph0_2x_hws, 6, 1, 0); 112 static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", 113 pll_periph0_2x_hws, 8, 1, 0); 114 static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M", 115 pll_periph0_480M_hws, 3, 1, 0); 116 static const struct clk_hw *pll_periph0_150M_hws[] = { 117 &pll_periph0_150M_clk.hw 118 }; 119 120 #define SUN55I_A523_PLL_PERIPH1_REG 0x028 121 static struct ccu_nm pll_periph1_4x_clk = { 122 .enable = BIT(27), 123 .lock = BIT(28), 124 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 125 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 126 .common = { 127 .reg = 0x028, 128 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph1-4x", 129 osc24M, &ccu_nm_ops, 130 CLK_SET_RATE_GATE), 131 }, 132 }; 133 134 static const struct clk_hw *pll_periph1_4x_hws[] = { 135 &pll_periph1_4x_clk.common.hw 136 }; 137 static SUNXI_CCU_M_HWS(pll_periph1_2x_clk, "pll-periph1-2x", 138 pll_periph1_4x_hws, 0x028, 16, 3, 0); 139 static SUNXI_CCU_M_HWS(pll_periph1_800M_clk, "pll-periph1-800M", 140 pll_periph1_4x_hws, 0x028, 20, 3, 0); 141 static SUNXI_CCU_M_HWS(pll_periph1_480M_clk, "pll-periph1-480M", 142 pll_periph1_4x_hws, 0x028, 2, 3, 0); 143 144 static const struct clk_hw *pll_periph1_2x_hws[] = { 145 &pll_periph1_2x_clk.common.hw 146 }; 147 static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M", 148 pll_periph1_2x_hws, 2, 1, 0); 149 static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M", 150 pll_periph1_2x_hws, 3, 1, 0); 151 static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M", 152 pll_periph1_2x_hws, 4, 1, 0); 153 static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M", 154 pll_periph1_2x_hws, 6, 1, 0); 155 static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M", 156 pll_periph1_2x_hws, 8, 1, 0); 157 static const struct clk_hw *pll_periph1_480M_hws[] = { 158 &pll_periph1_480M_clk.common.hw 159 }; 160 static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M", 161 pll_periph1_480M_hws, 3, 1, 0); 162 163 #define SUN55I_A523_PLL_GPU_REG 0x030 164 static struct ccu_nkmp pll_gpu_clk = { 165 .enable = BIT(27), 166 .lock = BIT(28), 167 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 168 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 169 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 170 .common = { 171 .reg = 0x030, 172 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-gpu", osc24M, 173 &ccu_nkmp_ops, 174 CLK_SET_RATE_GATE), 175 }, 176 }; 177 178 #define SUN55I_A523_PLL_VIDEO0_REG 0x040 179 static struct ccu_nm pll_video0_8x_clk = { 180 .enable = BIT(27), 181 .lock = BIT(28), 182 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 183 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 184 .common = { 185 .reg = 0x040, 186 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video0-8x", 187 osc24M, &ccu_nm_ops, 188 CLK_SET_RATE_GATE), 189 }, 190 }; 191 192 static const struct clk_hw *pll_video0_8x_hws[] = { 193 &pll_video0_8x_clk.common.hw 194 }; 195 static SUNXI_CCU_M_HWS(pll_video0_4x_clk, "pll-video0-4x", 196 pll_video0_8x_hws, 0x040, 0, 1, 0); 197 static CLK_FIXED_FACTOR_HWS(pll_video0_3x_clk, "pll-video0-3x", 198 pll_video0_8x_hws, 3, 1, CLK_SET_RATE_PARENT); 199 200 #define SUN55I_A523_PLL_VIDEO1_REG 0x048 201 static struct ccu_nm pll_video1_8x_clk = { 202 .enable = BIT(27), 203 .lock = BIT(28), 204 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 205 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 206 .common = { 207 .reg = 0x048, 208 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video1-8x", 209 osc24M, &ccu_nm_ops, 210 CLK_SET_RATE_GATE), 211 }, 212 }; 213 214 static const struct clk_hw *pll_video1_8x_hws[] = { 215 &pll_video1_8x_clk.common.hw 216 }; 217 static SUNXI_CCU_M_HWS(pll_video1_4x_clk, "pll-video1-4x", 218 pll_video1_8x_hws, 0x048, 0, 1, 0); 219 static CLK_FIXED_FACTOR_HWS(pll_video1_3x_clk, "pll-video1-3x", 220 pll_video1_8x_hws, 3, 1, CLK_SET_RATE_PARENT); 221 222 #define SUN55I_A523_PLL_VIDEO2_REG 0x050 223 static struct ccu_nm pll_video2_8x_clk = { 224 .enable = BIT(27), 225 .lock = BIT(28), 226 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 227 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 228 .common = { 229 .reg = 0x050, 230 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video2-8x", 231 osc24M, &ccu_nm_ops, 232 CLK_SET_RATE_GATE), 233 }, 234 }; 235 236 static const struct clk_hw *pll_video2_8x_hws[] = { 237 &pll_video2_8x_clk.common.hw 238 }; 239 static SUNXI_CCU_M_HWS(pll_video2_4x_clk, "pll-video2-4x", 240 pll_video2_8x_hws, 0x050, 0, 1, 0); 241 static CLK_FIXED_FACTOR_HWS(pll_video2_3x_clk, "pll-video2-3x", 242 pll_video2_8x_hws, 3, 1, CLK_SET_RATE_PARENT); 243 244 #define SUN55I_A523_PLL_VE_REG 0x058 245 static struct ccu_nkmp pll_ve_clk = { 246 .enable = BIT(27), 247 .lock = BIT(28), 248 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 249 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 250 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 251 .common = { 252 .reg = 0x058, 253 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M, 254 &ccu_nkmp_ops, 255 CLK_SET_RATE_GATE), 256 }, 257 }; 258 259 #define SUN55I_A523_PLL_VIDEO3_REG 0x068 260 static struct ccu_nm pll_video3_8x_clk = { 261 .enable = BIT(27), 262 .lock = BIT(28), 263 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 264 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 265 .common = { 266 .reg = 0x068, 267 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video3-8x", 268 osc24M, &ccu_nm_ops, 269 CLK_SET_RATE_GATE), 270 }, 271 }; 272 273 static const struct clk_hw *pll_video3_8x_hws[] = { 274 &pll_video3_8x_clk.common.hw 275 }; 276 static SUNXI_CCU_M_HWS(pll_video3_4x_clk, "pll-video3-4x", 277 pll_video3_8x_hws, 0x068, 0, 1, 0); 278 static CLK_FIXED_FACTOR_HWS(pll_video3_3x_clk, "pll-video3-3x", 279 pll_video3_8x_hws, 3, 1, CLK_SET_RATE_PARENT); 280 281 /* 282 * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors. 283 * Since we only need some fixed frequency from this PLL (22.5792MHz x 4 and 284 * 24.576MHz x 4), ignore those dividers and force both of them to 1 (encoded 285 * as 0), in the probe function below. 286 * The M factor must be an even number to produce a 50% duty cycle output. 287 */ 288 #define SUN55I_A523_PLL_AUDIO0_REG 0x078 289 static struct ccu_sdm_setting pll_audio0_sdm_table[] = { 290 { .rate = 90316800, .pattern = 0xc000872b, .m = 20, .n = 75 }, 291 { .rate = 98304000, .pattern = 0xc0004dd3, .m = 12, .n = 49 }, 292 293 }; 294 295 static struct ccu_nm pll_audio0_4x_clk = { 296 .enable = BIT(27), 297 .lock = BIT(28), 298 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 299 .m = _SUNXI_CCU_DIV(16, 6), 300 .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24), 301 0x178, BIT(31)), 302 .min_rate = 180000000U, 303 .max_rate = 3000000000U, 304 .common = { 305 .reg = 0x078, 306 .features = CCU_FEATURE_SIGMA_DELTA_MOD, 307 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x", 308 osc24M, &ccu_nm_ops, 309 CLK_SET_RATE_GATE), 310 }, 311 }; 312 313 static CLK_FIXED_FACTOR_HW(pll_audio0_2x_clk, "pll-audio0-2x", 314 &pll_audio0_4x_clk.common.hw, 2, 1, 0); 315 static CLK_FIXED_FACTOR_HW(pll_audio0_clk, "pll-audio0", 316 &pll_audio0_4x_clk.common.hw, 4, 1, 0); 317 318 #define SUN55I_A523_PLL_NPU_REG 0x080 319 static struct ccu_nm pll_npu_4x_clk = { 320 .enable = BIT(27), 321 .lock = BIT(28), 322 .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), 323 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 324 .common = { 325 .reg = 0x0080, 326 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-npu-4x", 327 osc24M, &ccu_nm_ops, 328 CLK_SET_RATE_GATE), 329 }, 330 }; 331 static CLK_FIXED_FACTOR_HW(pll_npu_2x_clk, "pll-npu-2x", 332 &pll_npu_4x_clk.common.hw, 2, 1, CLK_SET_RATE_PARENT); 333 334 static CLK_FIXED_FACTOR_HW(pll_npu_1x_clk, "pll-npu-1x", 335 &pll_npu_4x_clk.common.hw, 4, 1, 0); 336 337 338 /************************************************************************** 339 * bus clocks * 340 **************************************************************************/ 341 342 static const struct clk_parent_data ahb_apb0_parents[] = { 343 { .fw_name = "hosc" }, 344 { .fw_name = "losc" }, 345 { .fw_name = "iosc" }, 346 { .hw = &pll_periph0_600M_clk.hw }, 347 }; 348 349 static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb0_parents, 0x510, 350 0, 5, /* M */ 351 24, 2, /* mux */ 352 0); 353 static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw }; 354 355 static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb0_parents, 0x520, 356 0, 5, /* M */ 357 24, 2, /* mux */ 358 0); 359 static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw }; 360 361 static const struct clk_parent_data apb1_parents[] = { 362 { .fw_name = "hosc" }, 363 { .fw_name = "losc" }, 364 { .fw_name = "iosc" }, 365 { .hw = &pll_periph0_600M_clk.hw }, 366 { .hw = &pll_periph0_480M_clk.common.hw }, 367 }; 368 static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x524, 369 0, 5, /* M */ 370 24, 3, /* mux */ 371 0); 372 static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw }; 373 374 static const struct clk_parent_data mbus_parents[] = { 375 { .hw = &pll_ddr_clk.common.hw }, 376 { .hw = &pll_periph1_600M_clk.hw }, 377 { .hw = &pll_periph1_480M_clk.common.hw }, 378 { .hw = &pll_periph1_400M_clk.hw }, 379 { .hw = &pll_periph1_150M_clk.hw }, 380 { .fw_name = "hosc" }, 381 }; 382 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 383 0x540, 384 0, 5, /* M */ 385 0, 0, /* no P */ 386 24, 3, /* mux */ 387 BIT(31), /* gate */ 388 CLK_IS_CRITICAL, 389 CCU_FEATURE_UPDATE_BIT); 390 391 static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw }; 392 393 /************************************************************************** 394 * mod clocks with gates * 395 **************************************************************************/ 396 397 static const struct clk_hw *de_parents[] = { 398 &pll_periph0_300M_clk.hw, 399 &pll_periph0_400M_clk.hw, 400 &pll_video3_4x_clk.common.hw, 401 &pll_video3_3x_clk.hw, 402 }; 403 404 static SUNXI_CCU_M_HW_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, 405 0, 5, /* M */ 406 24, 3, /* mux */ 407 BIT(31), /* gate */ 408 CLK_SET_RATE_PARENT); 409 410 static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws, 0x60c, BIT(0), 0); 411 412 static const struct clk_hw *di_parents[] = { 413 &pll_periph0_300M_clk.hw, 414 &pll_periph0_400M_clk.hw, 415 &pll_video0_4x_clk.common.hw, 416 &pll_video1_4x_clk.common.hw, 417 }; 418 419 static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0x620, 420 0, 5, /* M */ 421 24, 3, /* mux */ 422 BIT(31), /* gate */ 423 CLK_SET_RATE_PARENT); 424 425 static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", ahb_hws, 0x62c, BIT(0), 0); 426 427 static const struct clk_hw *g2d_parents[] = { 428 &pll_periph0_400M_clk.hw, 429 &pll_periph0_300M_clk.hw, 430 &pll_video0_4x_clk.common.hw, 431 &pll_video1_4x_clk.common.hw, 432 }; 433 434 static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0x630, 435 0, 5, /* M */ 436 24, 3, /* mux */ 437 BIT(31), /* gate */ 438 0); 439 440 static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws, 0x63c, BIT(0), 0); 441 442 static const struct clk_hw *gpu_parents[] = { 443 &pll_gpu_clk.common.hw, 444 &pll_periph0_800M_clk.common.hw, 445 &pll_periph0_600M_clk.hw, 446 &pll_periph0_400M_clk.hw, 447 &pll_periph0_300M_clk.hw, 448 &pll_periph0_200M_clk.hw, 449 }; 450 451 static SUNXI_CCU_M_HW_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, 452 0, 4, /* M */ 453 24, 3, /* mux */ 454 BIT(31), /* gate */ 455 CLK_SET_RATE_PARENT); 456 457 static SUNXI_CCU_GATE_HWS(bus_gpu_clk, "bus-gpu", ahb_hws, 0x67c, BIT(0), 0); 458 459 static const struct clk_parent_data ce_parents[] = { 460 { .fw_name = "hosc" }, 461 { .hw = &pll_periph0_480M_clk.common.hw }, 462 { .hw = &pll_periph0_400M_clk.hw }, 463 { .hw = &pll_periph0_300M_clk.hw }, 464 }; 465 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680, 466 0, 5, /* M */ 467 24, 3, /* mux */ 468 BIT(31), /* gate */ 469 0); 470 471 static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws, 0x68c, BIT(0), 0); 472 static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, "bus-ce-sys", ahb_hws, 0x68c, 473 BIT(1), 0); 474 475 static const struct clk_hw *ve_parents[] = { 476 &pll_ve_clk.common.hw, 477 &pll_periph0_480M_clk.common.hw, 478 &pll_periph0_400M_clk.hw, 479 &pll_periph0_300M_clk.hw, 480 }; 481 static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, 482 0, 5, /* M */ 483 24, 3, /* mux */ 484 BIT(31), /* gate */ 485 CLK_SET_RATE_PARENT); 486 487 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0); 488 489 static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), 0); 490 491 static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c, 492 BIT(0), 0); 493 494 static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws, 0x72c, 495 BIT(0), 0); 496 497 static const struct clk_parent_data hstimer_parents[] = { 498 { .fw_name = "hosc" }, 499 { .fw_name = "iosc" }, 500 { .fw_name = "losc" }, 501 { .hw = &pll_periph0_200M_clk.hw }, 502 }; 503 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer0_clk, "hstimer0", 504 hstimer_parents, 0x730, 505 0, 0, /* M */ 506 0, 3, /* P */ 507 24, 3, /* mux */ 508 BIT(31), /* gate */ 509 0); 510 511 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer1_clk, "hstimer1", 512 hstimer_parents, 513 0x734, 514 0, 0, /* M */ 515 0, 3, /* P */ 516 24, 3, /* mux */ 517 BIT(31), /* gate */ 518 0); 519 520 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer2_clk, "hstimer2", 521 hstimer_parents, 522 0x738, 523 0, 0, /* M */ 524 0, 3, /* P */ 525 24, 3, /* mux */ 526 BIT(31), /* gate */ 527 0); 528 529 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer3_clk, "hstimer3", 530 hstimer_parents, 531 0x73c, 532 0, 0, /* M */ 533 0, 3, /* P */ 534 24, 3, /* mux */ 535 BIT(31), /* gate */ 536 0); 537 538 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer4_clk, "hstimer4", 539 hstimer_parents, 540 0x740, 541 0, 0, /* M */ 542 0, 3, /* P */ 543 24, 3, /* mux */ 544 BIT(31), /* gate */ 545 0); 546 547 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(hstimer5_clk, "hstimer5", 548 hstimer_parents, 549 0x744, 550 0, 0, /* M */ 551 0, 3, /* P */ 552 24, 3, /* mux */ 553 BIT(31), /* gate */ 554 0); 555 556 static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws, 0x74c, 557 BIT(0), 0); 558 559 static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", ahb_hws, 0x78c, 560 BIT(0), 0); 561 562 static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb1_hws, 0x7ac, BIT(0), 0); 563 static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, "bus-pwm1", apb1_hws, 0x7ac, BIT(1), 0); 564 565 static const struct clk_parent_data iommu_parents[] = { 566 { .hw = &pll_periph0_600M_clk.hw }, 567 { .hw = &pll_ddr_clk.common.hw }, 568 { .hw = &pll_periph0_480M_clk.common.hw }, 569 { .hw = &pll_periph0_400M_clk.hw }, 570 { .hw = &pll_periph0_150M_clk.hw }, 571 { .fw_name = "hosc" }, 572 }; 573 574 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(iommu_clk, "iommu", iommu_parents, 575 0x7b0, 576 0, 5, /* M */ 577 0, 0, /* no P */ 578 24, 3, /* mux */ 579 BIT(31), /* gate */ 580 CLK_SET_RATE_PARENT, 581 CCU_FEATURE_UPDATE_BIT); 582 583 static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc, 584 BIT(0), 0); 585 586 static const struct clk_parent_data dram_parents[] = { 587 { .hw = &pll_ddr_clk.common.hw }, 588 { .hw = &pll_periph0_600M_clk.hw }, 589 { .hw = &pll_periph0_480M_clk.common.hw }, 590 { .hw = &pll_periph0_400M_clk.hw }, 591 { .hw = &pll_periph0_150M_clk.hw }, 592 }; 593 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram_clk, "dram", dram_parents, 594 0x800, 595 0, 5, /* M */ 596 0, 0, /* no P */ 597 24, 3, /* mux */ 598 BIT(31), /* gate */ 599 CLK_IS_CRITICAL, 600 CCU_FEATURE_UPDATE_BIT); 601 602 static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws, 603 0x804, BIT(0), 0); 604 static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws, 605 0x804, BIT(1), 0); 606 static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws, 607 0x804, BIT(2), 0); 608 static SUNXI_CCU_GATE_HWS(mbus_nand_clk, "mbus-nand", mbus_hws, 609 0x804, BIT(5), 0); 610 static SUNXI_CCU_GATE_HWS(mbus_usb3_clk, "mbus-usb3", mbus_hws, 611 0x804, BIT(6), 0); 612 static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws, 613 0x804, BIT(8), 0); 614 static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws, 615 0x804, BIT(9), 0); 616 static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, "mbus-gmac1", mbus_hws, 617 0x804, BIT(12), 0); 618 619 static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws, 0x80c, 620 BIT(0), CLK_IS_CRITICAL); 621 622 static const struct clk_parent_data nand_mmc_parents[] = { 623 { .fw_name = "hosc" }, 624 { .hw = &pll_periph0_400M_clk.hw }, 625 { .hw = &pll_periph0_300M_clk.hw }, 626 { .hw = &pll_periph1_400M_clk.hw }, 627 { .hw = &pll_periph1_300M_clk.hw }, 628 }; 629 630 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk, "nand0", nand_mmc_parents, 631 0x810, 632 0, 5, /* M */ 633 24, 3, /* mux */ 634 BIT(31), /* gate */ 635 0); 636 637 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand1_clk, "nand1", nand_mmc_parents, 638 0x814, 639 0, 5, /* M */ 640 24, 3, /* mux */ 641 BIT(31), /* gate */ 642 0); 643 644 static SUNXI_CCU_GATE_HWS(bus_nand_clk, "bus-nand", ahb_hws, 0x82c, 645 BIT(0), 0); 646 647 static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents, 648 0x830, 649 0, 5, /* M */ 650 8, 5, /* P */ 651 24, 3, /* mux */ 652 BIT(31), /* gate */ 653 2, /* post div */ 654 0); 655 656 static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents, 657 0x834, 658 0, 5, /* M */ 659 8, 5, /* P */ 660 24, 3, /* mux */ 661 BIT(31), /* gate */ 662 2, /* post div */ 663 0); 664 665 static const struct clk_parent_data mmc2_parents[] = { 666 { .fw_name = "hosc" }, 667 { .hw = &pll_periph0_800M_clk.common.hw }, 668 { .hw = &pll_periph0_600M_clk.hw }, 669 { .hw = &pll_periph1_800M_clk.common.hw }, 670 { .hw = &pll_periph1_600M_clk.hw }, 671 }; 672 673 static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_parents, 674 0x838, 675 0, 5, /* M */ 676 8, 5, /* P */ 677 24, 3, /* mux */ 678 BIT(31), /* gate */ 679 2, /* post div */ 680 0); 681 682 static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws, 0x84c, BIT(0), 0); 683 static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws, 0x84c, BIT(1), 0); 684 static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws, 0x84c, BIT(2), 0); 685 686 static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws, 0x88c, 687 BIT(0), 0); 688 689 static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws, 0x90c, 690 BIT(0), 0); 691 static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws, 0x90c, 692 BIT(1), 0); 693 static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws, 0x90c, 694 BIT(2), 0); 695 static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws, 0x90c, 696 BIT(3), 0); 697 static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws, 0x90c, 698 BIT(4), 0); 699 static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws, 0x90c, 700 BIT(5), 0); 701 static SUNXI_CCU_GATE_HWS(bus_uart6_clk, "bus-uart6", apb1_hws, 0x90c, 702 BIT(6), 0); 703 static SUNXI_CCU_GATE_HWS(bus_uart7_clk, "bus-uart7", apb1_hws, 0x90c, 704 BIT(7), 0); 705 706 static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0x91c, BIT(0), 0); 707 static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0x91c, BIT(1), 0); 708 static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 0x91c, BIT(2), 0); 709 static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0x91c, BIT(3), 0); 710 static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws, 0x91c, BIT(4), 0); 711 static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, "bus-i2c5", apb1_hws, 0x91c, BIT(5), 0); 712 713 static SUNXI_CCU_GATE_HWS(bus_can_clk, "bus-can", apb1_hws, 0x92c, BIT(0), 0); 714 715 static const struct clk_parent_data spi_parents[] = { 716 { .fw_name = "hosc" }, 717 { .hw = &pll_periph0_300M_clk.hw }, 718 { .hw = &pll_periph0_200M_clk.hw }, 719 { .hw = &pll_periph1_300M_clk.hw }, 720 { .hw = &pll_periph1_200M_clk.hw }, 721 }; 722 static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0x940, 723 0, 5, /* M */ 724 8, 5, /* P */ 725 24, 3, /* mux */ 726 BIT(31), /* gate */ 727 0); 728 static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0x944, 729 0, 5, /* M */ 730 8, 5, /* P */ 731 24, 3, /* mux */ 732 BIT(31), /* gate */ 733 0); 734 static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0x948, 735 0, 5, /* M */ 736 8, 5, /* P */ 737 24, 3, /* mux */ 738 BIT(31), /* gate */ 739 0); 740 static SUNXI_CCU_DUALDIV_MUX_GATE(spifc_clk, "spifc", nand_mmc_parents, 0x950, 741 0, 5, /* M */ 742 8, 5, /* P */ 743 24, 3, /* mux */ 744 BIT(31), /* gate */ 745 0); 746 static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws, 0x96c, BIT(0), 0); 747 static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws, 0x96c, BIT(1), 0); 748 static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws, 0x96c, BIT(2), 0); 749 static SUNXI_CCU_GATE_HWS(bus_spifc_clk, "bus-spifc", ahb_hws, 0x96c, 750 BIT(3), 0); 751 752 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac0_25M_clk, "emac0-25M", 753 pll_periph0_150M_hws, 754 0x970, BIT(31) | BIT(30), 6, 0); 755 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac1_25M_clk, "emac1-25M", 756 pll_periph0_150M_hws, 757 0x974, BIT(31) | BIT(30), 6, 0); 758 static SUNXI_CCU_GATE_HWS(bus_emac0_clk, "bus-emac0", ahb_hws, 0x97c, 759 BIT(0), 0); 760 static SUNXI_CCU_GATE_HWS(bus_emac1_clk, "bus-emac1", ahb_hws, 0x98c, 761 BIT(0), 0); 762 763 static const struct clk_parent_data ir_rx_parents[] = { 764 { .fw_name = "losc" }, 765 { .fw_name = "hosc" }, 766 }; 767 768 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_rx_parents, 0x990, 769 0, 5, /* M */ 770 24, 1, /* mux */ 771 BIT(31), /* gate */ 772 0); 773 static SUNXI_CCU_GATE_HWS(bus_ir_rx_clk, "bus-ir-rx", apb0_hws, 0x99c, 774 BIT(0), 0); 775 776 static const struct clk_parent_data ir_tx_ledc_parents[] = { 777 { .fw_name = "hosc" }, 778 { .hw = &pll_periph1_600M_clk.hw }, 779 }; 780 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents, 781 0x9c0, 782 0, 5, /* M */ 783 24, 1, /* mux */ 784 BIT(31), /* gate */ 785 0); 786 static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws, 0x9cc, 787 BIT(0), 0); 788 789 static SUNXI_CCU_M_WITH_GATE(gpadc0_clk, "gpadc0", "hosc", 0x9e0, 790 0, 5, /* M */ 791 BIT(31), /* gate */ 792 0); 793 static SUNXI_CCU_M_WITH_GATE(gpadc1_clk, "gpadc1", "hosc", 0x9e4, 794 0, 5, /* M */ 795 BIT(31), /* gate */ 796 0); 797 static SUNXI_CCU_GATE_HWS(bus_gpadc0_clk, "bus-gpadc0", ahb_hws, 0x9ec, 798 BIT(0), 0); 799 static SUNXI_CCU_GATE_HWS(bus_gpadc1_clk, "bus-gpadc1", ahb_hws, 0x9ec, 800 BIT(1), 0); 801 802 static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws, 0x9fc, BIT(0), 0); 803 804 /* 805 * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is 806 * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by 807 * the OHCI module. 808 */ 809 static const struct clk_parent_data usb_ohci_parents[] = { 810 { .hw = &pll_periph0_4x_clk.common.hw }, 811 { .fw_name = "hosc" }, 812 { .fw_name = "losc" }, 813 { .fw_name = "iosc" }, 814 }; 815 static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = { 816 { .index = 0, .div = 50 }, 817 { .index = 1, .div = 2 }, 818 }; 819 820 static struct ccu_mux usb_ohci0_clk = { 821 .enable = BIT(31), 822 .mux = { 823 .shift = 24, 824 .width = 2, 825 .fixed_predivs = usb_ohci_predivs, 826 .n_predivs = ARRAY_SIZE(usb_ohci_predivs), 827 }, 828 .common = { 829 .reg = 0xa70, 830 .features = CCU_FEATURE_FIXED_PREDIV, 831 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0", 832 usb_ohci_parents, 833 &ccu_mux_ops, 834 0), 835 }, 836 }; 837 838 static struct ccu_mux usb_ohci1_clk = { 839 .enable = BIT(31), 840 .mux = { 841 .shift = 24, 842 .width = 2, 843 .fixed_predivs = usb_ohci_predivs, 844 .n_predivs = ARRAY_SIZE(usb_ohci_predivs), 845 }, 846 .common = { 847 .reg = 0xa74, 848 .features = CCU_FEATURE_FIXED_PREDIV, 849 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1", 850 usb_ohci_parents, 851 &ccu_mux_ops, 852 0), 853 }, 854 }; 855 856 static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0xa8c, 857 BIT(0), 0); 858 static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0xa8c, 859 BIT(1), 0); 860 static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", ahb_hws, 0xa8c, 861 BIT(4), 0); 862 static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", ahb_hws, 0xa8c, 863 BIT(5), 0); 864 static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0xa8c, BIT(8), 0); 865 866 static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0xa9c, 867 BIT(0), 0); 868 869 static const struct clk_parent_data losc_hosc_parents[] = { 870 { .fw_name = "hosc" }, 871 { .fw_name = "losc" }, 872 }; 873 874 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux", 875 losc_hosc_parents, 0xaa0, 876 0, 5, /* M */ 877 24, 1, /* mux */ 878 BIT(31), /* gate */ 879 0); 880 881 static SUNXI_CCU_GATE_HWS(bus_display0_top_clk, "bus-display0-top", ahb_hws, 882 0xabc, BIT(0), 0); 883 static SUNXI_CCU_GATE_HWS(bus_display1_top_clk, "bus-display1-top", ahb_hws, 884 0xacc, BIT(0), 0); 885 886 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(31), 0); 887 888 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", 889 pll_periph0_2x_hws, 890 0xb10, BIT(30), 36621, 0); 891 892 static const struct clk_parent_data hdmi_cec_parents[] = { 893 { .fw_name = "losc" }, 894 { .hw = &hdmi_cec_32k_clk.common.hw }, 895 }; 896 static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 897 0xb10, 898 24, 1, /* mux */ 899 BIT(31), /* gate */ 900 0); 901 902 static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", ahb_hws, 0xb1c, BIT(0), 0); 903 904 static const struct clk_parent_data mipi_dsi_parents[] = { 905 { .fw_name = "hosc" }, 906 { .hw = &pll_periph0_200M_clk.hw }, 907 { .hw = &pll_periph0_150M_clk.hw }, 908 }; 909 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi0_clk, "mipi-dsi0", 910 mipi_dsi_parents, 0xb24, 911 0, 5, /* M */ 912 24, 3, /* mux */ 913 BIT(31), /* gate */ 914 0); 915 916 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi1_clk, "mipi-dsi1", 917 mipi_dsi_parents, 0xb28, 918 0, 5, /* M */ 919 24, 3, /* mux */ 920 BIT(31), /* gate */ 921 0); 922 923 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi0_clk, "bus-mipi-dsi0", ahb_hws, 0xb4c, 924 BIT(0), 0); 925 926 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi1_clk, "bus-mipi-dsi1", ahb_hws, 0xb4c, 927 BIT(1), 0); 928 929 static const struct clk_hw *tcon_parents[] = { 930 &pll_video0_4x_clk.common.hw, 931 &pll_video1_4x_clk.common.hw, 932 &pll_video2_4x_clk.common.hw, 933 &pll_video3_4x_clk.common.hw, 934 &pll_periph0_2x_clk.common.hw, 935 &pll_video0_3x_clk.hw, 936 &pll_video1_3x_clk.hw, 937 }; 938 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents, 939 0xb60, 940 0, 5, /* M */ 941 24, 3, /* mux */ 942 BIT(31), /* gate */ 943 CLK_SET_RATE_PARENT); 944 945 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents, 946 0xb64, 947 0, 5, /* M */ 948 24, 3, /* mux */ 949 BIT(31), /* gate */ 950 CLK_SET_RATE_PARENT); 951 952 static const struct clk_hw *tcon_tv_parents[] = { 953 &pll_video0_4x_clk.common.hw, 954 &pll_video1_4x_clk.common.hw, 955 &pll_video2_4x_clk.common.hw, 956 &pll_video3_4x_clk.common.hw, 957 &pll_periph0_2x_clk.common.hw, 958 }; 959 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2", 960 tcon_tv_parents, 0xb68, 961 0, 5, /* M */ 962 24, 3, /* mux */ 963 BIT(31), /* gate */ 964 CLK_SET_RATE_PARENT); 965 966 static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi0_clk, "combophy-dsi0", 967 tcon_parents, 0xb6c, 968 0, 5, /* M */ 969 24, 3, /* mux */ 970 BIT(31), /* gate */ 971 CLK_SET_RATE_PARENT); 972 973 static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi1_clk, "combophy-dsi1", 974 tcon_parents, 0xb70, 975 0, 5, /* M */ 976 24, 3, /* mux */ 977 BIT(31), /* gate */ 978 CLK_SET_RATE_PARENT); 979 980 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", ahb_hws, 0xb7c, 981 BIT(0), 0); 982 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, "bus-tcon-lcd1", ahb_hws, 0xb7c, 983 BIT(1), 0); 984 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, "bus-tcon-lcd2", ahb_hws, 0xb7c, 985 BIT(2), 0); 986 987 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_tv_parents, 988 0xb80, 989 0, 4, /* M */ 990 24, 3, /* mux */ 991 BIT(31), /* gate */ 992 CLK_SET_RATE_PARENT); 993 994 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_tv_parents, 995 0xb84, 996 0, 4, /* M */ 997 24, 3, /* mux */ 998 BIT(31), /* gate */ 999 CLK_SET_RATE_PARENT); 1000 1001 static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, "bus-tcon-tv0", ahb_hws, 0xb9c, 1002 BIT(0), 0); 1003 static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, "bus-tcon-tv1", ahb_hws, 0xb9c, 1004 BIT(1), 0); 1005 1006 static const struct clk_hw *edp_parents[] = { 1007 &pll_video0_4x_clk.common.hw, 1008 &pll_video1_4x_clk.common.hw, 1009 &pll_video2_4x_clk.common.hw, 1010 &pll_video3_4x_clk.common.hw, 1011 &pll_periph0_2x_clk.common.hw, 1012 }; 1013 static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_clk, "edp", edp_parents, 0xbb0, 1014 0, 4, /* M */ 1015 24, 3, /* mux */ 1016 BIT(31), /* gate */ 1017 CLK_SET_RATE_PARENT); 1018 1019 static SUNXI_CCU_GATE_HWS(bus_edp_clk, "bus-edp", ahb_hws, 0xbbc, BIT(0), 0); 1020 1021 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ir_tx_ledc_parents, 1022 0xbf0, 1023 0, 4, /* M */ 1024 24, 1, /* mux */ 1025 BIT(31), /* gate */ 1026 0); 1027 1028 static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", apb0_hws, 0xbfc, BIT(0), 0); 1029 1030 static const struct clk_hw *csi_top_parents[] = { 1031 &pll_periph0_300M_clk.hw, 1032 &pll_periph0_400M_clk.hw, 1033 &pll_periph0_480M_clk.common.hw, 1034 &pll_video3_4x_clk.common.hw, 1035 &pll_video3_3x_clk.hw, 1036 }; 1037 static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents, 1038 0xc04, 1039 0, 5, /* M */ 1040 24, 3, /* mux */ 1041 BIT(31), /* gate */ 1042 0); 1043 1044 static const struct clk_parent_data csi_mclk_parents[] = { 1045 { .fw_name = "hosc" }, 1046 { .hw = &pll_video3_4x_clk.common.hw }, 1047 { .hw = &pll_video0_4x_clk.common.hw }, 1048 { .hw = &pll_video1_4x_clk.common.hw }, 1049 { .hw = &pll_video2_4x_clk.common.hw }, 1050 }; 1051 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents, 1052 0xc08, 1053 0, 5, /* M */ 1054 8, 5, /* P */ 1055 24, 3, /* mux */ 1056 BIT(31), /* gate */ 1057 0); 1058 1059 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents, 1060 0xc0c, 1061 0, 5, /* M */ 1062 8, 5, /* P */ 1063 24, 3, /* mux */ 1064 BIT(31), /* gate */ 1065 0); 1066 1067 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents, 1068 0xc10, 1069 0, 5, /* M */ 1070 8, 5, /* P */ 1071 24, 3, /* mux */ 1072 BIT(31), /* gate */ 1073 0); 1074 1075 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk3_clk, "csi-mclk3", csi_mclk_parents, 1076 0xc14, 1077 0, 5, /* M */ 1078 8, 5, /* P */ 1079 24, 3, /* mux */ 1080 BIT(31), /* gate */ 1081 0); 1082 1083 static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws, 0xc1c, BIT(0), 0); 1084 1085 static const struct clk_hw *isp_parents[] = { 1086 &pll_periph0_300M_clk.hw, 1087 &pll_periph0_400M_clk.hw, 1088 &pll_video2_4x_clk.common.hw, 1089 &pll_video3_4x_clk.common.hw, 1090 }; 1091 static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0xc20, 1092 0, 5, /* M */ 1093 24, 3, /* mux */ 1094 BIT(31), /* gate */ 1095 0); 1096 1097 static const struct clk_parent_data dsp_parents[] = { 1098 { .fw_name = "hosc" }, 1099 { .fw_name = "losc" }, 1100 { .fw_name = "iosc" }, 1101 { .hw = &pll_periph0_2x_clk.common.hw }, 1102 { .hw = &pll_periph0_480M_clk.common.hw, }, 1103 }; 1104 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "dsp", dsp_parents, 0xc70, 1105 0, 5, /* M */ 1106 24, 3, /* mux */ 1107 BIT(31), /* gate */ 1108 0); 1109 1110 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M, 1111 0xf30, BIT(0), 0); 1112 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M, 1113 0xf30, BIT(1), 2, 0); 1114 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", 1115 pll_periph0_480M_hws, 1116 0xf30, BIT(2), 30, 0); 1117 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", 1118 pll_periph0_2x_hws, 1119 0xf30, BIT(3), 48, 0); 1120 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_50M_clk, "fanout-50M", 1121 pll_periph0_2x_hws, 1122 0xf30, BIT(4), 24, 0); 1123 1124 static const struct clk_parent_data fanout_27M_parents[] = { 1125 { .hw = &pll_video0_4x_clk.common.hw }, 1126 { .hw = &pll_video1_4x_clk.common.hw }, 1127 { .hw = &pll_video2_4x_clk.common.hw }, 1128 { .hw = &pll_video3_4x_clk.common.hw }, 1129 }; 1130 static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M", 1131 fanout_27M_parents, 0xf34, 1132 0, 5, /* div0 */ 1133 8, 5, /* div1 */ 1134 24, 2, /* mux */ 1135 BIT(31), /* gate */ 1136 0); 1137 1138 static const struct clk_parent_data fanout_pclk_parents[] = { 1139 { .hw = &apb0_clk.common.hw } 1140 }; 1141 static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk", 1142 fanout_pclk_parents, 1143 0xf38, 1144 0, 5, /* div0 */ 1145 5, 5, /* div1 */ 1146 0, 0, /* mux */ 1147 BIT(31), /* gate */ 1148 0); 1149 1150 static const struct clk_parent_data fanout_parents[] = { 1151 { .fw_name = "losc-fanout" }, 1152 { .hw = &fanout_12M_clk.common.hw, }, 1153 { .hw = &fanout_16M_clk.common.hw, }, 1154 { .hw = &fanout_24M_clk.common.hw, }, 1155 { .hw = &fanout_25M_clk.common.hw, }, 1156 { .hw = &fanout_27M_clk.common.hw, }, 1157 { .hw = &fanout_pclk_clk.common.hw, }, 1158 { .hw = &fanout_50M_clk.common.hw, }, 1159 }; 1160 static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 1161 0xf3c, 1162 0, 3, /* mux */ 1163 BIT(21), /* gate */ 1164 0); 1165 static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 1166 0xf3c, 1167 3, 3, /* mux */ 1168 BIT(22), /* gate */ 1169 0); 1170 static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 1171 0xf3c, 1172 6, 3, /* mux */ 1173 BIT(23), /* gate */ 1174 0); 1175 1176 /* 1177 * Contains all clocks that are controlled by a hardware register. They 1178 * have a (sunxi) .common member, which needs to be initialised by the common 1179 * sunxi CCU code, to be filled with the MMIO base address and the shared lock. 1180 */ 1181 static struct ccu_common *sun55i_a523_ccu_clks[] = { 1182 &pll_ddr_clk.common, 1183 &pll_periph0_4x_clk.common, 1184 &pll_periph0_2x_clk.common, 1185 &pll_periph0_800M_clk.common, 1186 &pll_periph0_480M_clk.common, 1187 &pll_periph1_4x_clk.common, 1188 &pll_periph1_2x_clk.common, 1189 &pll_periph1_800M_clk.common, 1190 &pll_periph1_480M_clk.common, 1191 &pll_gpu_clk.common, 1192 &pll_video0_8x_clk.common, 1193 &pll_video0_4x_clk.common, 1194 &pll_video1_8x_clk.common, 1195 &pll_video1_4x_clk.common, 1196 &pll_video2_8x_clk.common, 1197 &pll_video2_4x_clk.common, 1198 &pll_video3_8x_clk.common, 1199 &pll_video3_4x_clk.common, 1200 &pll_ve_clk.common, 1201 &pll_audio0_4x_clk.common, 1202 &pll_npu_4x_clk.common, 1203 &ahb_clk.common, 1204 &apb0_clk.common, 1205 &apb1_clk.common, 1206 &mbus_clk.common, 1207 &de_clk.common, 1208 &bus_de_clk.common, 1209 &di_clk.common, 1210 &bus_di_clk.common, 1211 &g2d_clk.common, 1212 &bus_g2d_clk.common, 1213 &gpu_clk.common, 1214 &bus_gpu_clk.common, 1215 &ce_clk.common, 1216 &bus_ce_clk.common, 1217 &bus_ce_sys_clk.common, 1218 &ve_clk.common, 1219 &bus_ve_clk.common, 1220 &bus_dma_clk.common, 1221 &bus_msgbox_clk.common, 1222 &bus_spinlock_clk.common, 1223 &hstimer0_clk.common, 1224 &hstimer1_clk.common, 1225 &hstimer2_clk.common, 1226 &hstimer3_clk.common, 1227 &hstimer4_clk.common, 1228 &hstimer5_clk.common, 1229 &bus_hstimer_clk.common, 1230 &bus_dbg_clk.common, 1231 &bus_pwm0_clk.common, 1232 &bus_pwm1_clk.common, 1233 &iommu_clk.common, 1234 &bus_iommu_clk.common, 1235 &dram_clk.common, 1236 &mbus_dma_clk.common, 1237 &mbus_ve_clk.common, 1238 &mbus_ce_clk.common, 1239 &mbus_nand_clk.common, 1240 &mbus_usb3_clk.common, 1241 &mbus_csi_clk.common, 1242 &mbus_isp_clk.common, 1243 &mbus_gmac1_clk.common, 1244 &bus_dram_clk.common, 1245 &nand0_clk.common, 1246 &nand1_clk.common, 1247 &bus_nand_clk.common, 1248 &mmc0_clk.common, 1249 &mmc1_clk.common, 1250 &mmc2_clk.common, 1251 &bus_sysdap_clk.common, 1252 &bus_mmc0_clk.common, 1253 &bus_mmc1_clk.common, 1254 &bus_mmc2_clk.common, 1255 &bus_uart0_clk.common, 1256 &bus_uart1_clk.common, 1257 &bus_uart2_clk.common, 1258 &bus_uart3_clk.common, 1259 &bus_uart4_clk.common, 1260 &bus_uart5_clk.common, 1261 &bus_uart6_clk.common, 1262 &bus_uart7_clk.common, 1263 &bus_i2c0_clk.common, 1264 &bus_i2c1_clk.common, 1265 &bus_i2c2_clk.common, 1266 &bus_i2c3_clk.common, 1267 &bus_i2c4_clk.common, 1268 &bus_i2c5_clk.common, 1269 &bus_can_clk.common, 1270 &spi0_clk.common, 1271 &spi1_clk.common, 1272 &spi2_clk.common, 1273 &spifc_clk.common, 1274 &bus_spi0_clk.common, 1275 &bus_spi1_clk.common, 1276 &bus_spi2_clk.common, 1277 &bus_spifc_clk.common, 1278 &emac0_25M_clk.common, 1279 &emac1_25M_clk.common, 1280 &bus_emac0_clk.common, 1281 &bus_emac1_clk.common, 1282 &ir_rx_clk.common, 1283 &bus_ir_rx_clk.common, 1284 &ir_tx_clk.common, 1285 &bus_ir_tx_clk.common, 1286 &gpadc0_clk.common, 1287 &gpadc1_clk.common, 1288 &bus_gpadc0_clk.common, 1289 &bus_gpadc1_clk.common, 1290 &bus_ths_clk.common, 1291 &usb_ohci0_clk.common, 1292 &usb_ohci1_clk.common, 1293 &bus_ohci0_clk.common, 1294 &bus_ohci1_clk.common, 1295 &bus_ehci0_clk.common, 1296 &bus_ehci1_clk.common, 1297 &bus_otg_clk.common, 1298 &bus_lradc_clk.common, 1299 &pcie_aux_clk.common, 1300 &bus_display0_top_clk.common, 1301 &bus_display1_top_clk.common, 1302 &hdmi_24M_clk.common, 1303 &hdmi_cec_32k_clk.common, 1304 &hdmi_cec_clk.common, 1305 &bus_hdmi_clk.common, 1306 &mipi_dsi0_clk.common, 1307 &mipi_dsi1_clk.common, 1308 &bus_mipi_dsi0_clk.common, 1309 &bus_mipi_dsi1_clk.common, 1310 &tcon_lcd0_clk.common, 1311 &tcon_lcd1_clk.common, 1312 &tcon_lcd2_clk.common, 1313 &combophy_dsi0_clk.common, 1314 &combophy_dsi1_clk.common, 1315 &bus_tcon_lcd0_clk.common, 1316 &bus_tcon_lcd1_clk.common, 1317 &bus_tcon_lcd2_clk.common, 1318 &tcon_tv0_clk.common, 1319 &tcon_tv1_clk.common, 1320 &bus_tcon_tv0_clk.common, 1321 &bus_tcon_tv1_clk.common, 1322 &edp_clk.common, 1323 &bus_edp_clk.common, 1324 &ledc_clk.common, 1325 &bus_ledc_clk.common, 1326 &csi_top_clk.common, 1327 &csi_mclk0_clk.common, 1328 &csi_mclk1_clk.common, 1329 &csi_mclk2_clk.common, 1330 &csi_mclk3_clk.common, 1331 &bus_csi_clk.common, 1332 &isp_clk.common, 1333 &dsp_clk.common, 1334 &fanout_24M_clk.common, 1335 &fanout_12M_clk.common, 1336 &fanout_16M_clk.common, 1337 &fanout_25M_clk.common, 1338 &fanout_27M_clk.common, 1339 &fanout_pclk_clk.common, 1340 &fanout0_clk.common, 1341 &fanout1_clk.common, 1342 &fanout2_clk.common, 1343 }; 1344 1345 static struct clk_hw_onecell_data sun55i_a523_hw_clks = { 1346 .num = CLK_NUMBER, 1347 .hws = { 1348 [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw, 1349 [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw, 1350 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw, 1351 [CLK_PLL_PERIPH0_800M] = &pll_periph0_800M_clk.common.hw, 1352 [CLK_PLL_PERIPH0_480M] = &pll_periph0_480M_clk.common.hw, 1353 [CLK_PLL_PERIPH0_600M] = &pll_periph0_600M_clk.hw, 1354 [CLK_PLL_PERIPH0_400M] = &pll_periph0_400M_clk.hw, 1355 [CLK_PLL_PERIPH0_300M] = &pll_periph0_300M_clk.hw, 1356 [CLK_PLL_PERIPH0_200M] = &pll_periph0_200M_clk.hw, 1357 [CLK_PLL_PERIPH0_160M] = &pll_periph0_160M_clk.hw, 1358 [CLK_PLL_PERIPH0_150M] = &pll_periph0_150M_clk.hw, 1359 [CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.common.hw, 1360 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.common.hw, 1361 [CLK_PLL_PERIPH1_800M] = &pll_periph1_800M_clk.common.hw, 1362 [CLK_PLL_PERIPH1_480M] = &pll_periph1_480M_clk.common.hw, 1363 [CLK_PLL_PERIPH1_600M] = &pll_periph1_600M_clk.hw, 1364 [CLK_PLL_PERIPH1_400M] = &pll_periph1_400M_clk.hw, 1365 [CLK_PLL_PERIPH1_300M] = &pll_periph1_300M_clk.hw, 1366 [CLK_PLL_PERIPH1_200M] = &pll_periph1_200M_clk.hw, 1367 [CLK_PLL_PERIPH1_160M] = &pll_periph1_160M_clk.hw, 1368 [CLK_PLL_PERIPH1_150M] = &pll_periph1_150M_clk.hw, 1369 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 1370 [CLK_PLL_VIDEO0_8X] = &pll_video0_8x_clk.common.hw, 1371 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw, 1372 [CLK_PLL_VIDEO0_3X] = &pll_video0_3x_clk.hw, 1373 [CLK_PLL_VIDEO1_8X] = &pll_video1_8x_clk.common.hw, 1374 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw, 1375 [CLK_PLL_VIDEO1_3X] = &pll_video1_3x_clk.hw, 1376 [CLK_PLL_VIDEO2_8X] = &pll_video2_8x_clk.common.hw, 1377 [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.common.hw, 1378 [CLK_PLL_VIDEO2_3X] = &pll_video2_3x_clk.hw, 1379 [CLK_PLL_VIDEO3_8X] = &pll_video3_8x_clk.common.hw, 1380 [CLK_PLL_VIDEO3_4X] = &pll_video3_4x_clk.common.hw, 1381 [CLK_PLL_VIDEO3_3X] = &pll_video3_3x_clk.hw, 1382 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 1383 [CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw, 1384 [CLK_PLL_AUDIO0_2X] = &pll_audio0_2x_clk.hw, 1385 [CLK_PLL_AUDIO0] = &pll_audio0_clk.hw, 1386 [CLK_PLL_NPU_4X] = &pll_npu_4x_clk.common.hw, 1387 [CLK_PLL_NPU_2X] = &pll_npu_2x_clk.hw, 1388 [CLK_PLL_NPU] = &pll_npu_1x_clk.hw, 1389 [CLK_AHB] = &ahb_clk.common.hw, 1390 [CLK_APB0] = &apb0_clk.common.hw, 1391 [CLK_APB1] = &apb1_clk.common.hw, 1392 [CLK_MBUS] = &mbus_clk.common.hw, 1393 [CLK_DE] = &de_clk.common.hw, 1394 [CLK_BUS_DE] = &bus_de_clk.common.hw, 1395 [CLK_DI] = &di_clk.common.hw, 1396 [CLK_BUS_DI] = &bus_di_clk.common.hw, 1397 [CLK_G2D] = &g2d_clk.common.hw, 1398 [CLK_BUS_G2D] = &bus_g2d_clk.common.hw, 1399 [CLK_GPU] = &gpu_clk.common.hw, 1400 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 1401 [CLK_CE] = &ce_clk.common.hw, 1402 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 1403 [CLK_BUS_CE_SYS] = &bus_ce_sys_clk.common.hw, 1404 [CLK_VE] = &ve_clk.common.hw, 1405 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 1406 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 1407 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 1408 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 1409 [CLK_HSTIMER0] = &hstimer0_clk.common.hw, 1410 [CLK_HSTIMER1] = &hstimer1_clk.common.hw, 1411 [CLK_HSTIMER2] = &hstimer2_clk.common.hw, 1412 [CLK_HSTIMER3] = &hstimer3_clk.common.hw, 1413 [CLK_HSTIMER4] = &hstimer4_clk.common.hw, 1414 [CLK_HSTIMER5] = &hstimer5_clk.common.hw, 1415 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 1416 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 1417 [CLK_BUS_PWM0] = &bus_pwm0_clk.common.hw, 1418 [CLK_BUS_PWM1] = &bus_pwm1_clk.common.hw, 1419 [CLK_IOMMU] = &iommu_clk.common.hw, 1420 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw, 1421 [CLK_DRAM] = &dram_clk.common.hw, 1422 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw, 1423 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw, 1424 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw, 1425 [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw, 1426 [CLK_MBUS_ISP] = &mbus_isp_clk.common.hw, 1427 [CLK_MBUS_EMAC1] = &mbus_gmac1_clk.common.hw, 1428 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 1429 [CLK_NAND0] = &nand0_clk.common.hw, 1430 [CLK_NAND1] = &nand1_clk.common.hw, 1431 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 1432 [CLK_MMC0] = &mmc0_clk.common.hw, 1433 [CLK_MMC1] = &mmc1_clk.common.hw, 1434 [CLK_MMC2] = &mmc2_clk.common.hw, 1435 [CLK_BUS_SYSDAP] = &bus_sysdap_clk.common.hw, 1436 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 1437 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 1438 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 1439 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 1440 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 1441 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 1442 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 1443 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 1444 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, 1445 [CLK_BUS_UART6] = &bus_uart6_clk.common.hw, 1446 [CLK_BUS_UART7] = &bus_uart7_clk.common.hw, 1447 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 1448 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 1449 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 1450 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, 1451 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, 1452 [CLK_BUS_I2C5] = &bus_i2c5_clk.common.hw, 1453 [CLK_BUS_CAN] = &bus_can_clk.common.hw, 1454 [CLK_SPI0] = &spi0_clk.common.hw, 1455 [CLK_SPI1] = &spi1_clk.common.hw, 1456 [CLK_SPI2] = &spi2_clk.common.hw, 1457 [CLK_SPIFC] = &spifc_clk.common.hw, 1458 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 1459 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 1460 [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw, 1461 [CLK_BUS_SPIFC] = &bus_spifc_clk.common.hw, 1462 [CLK_EMAC0_25M] = &emac0_25M_clk.common.hw, 1463 [CLK_EMAC1_25M] = &emac1_25M_clk.common.hw, 1464 [CLK_BUS_EMAC0] = &bus_emac0_clk.common.hw, 1465 [CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw, 1466 [CLK_IR_RX] = &ir_rx_clk.common.hw, 1467 [CLK_BUS_IR_RX] = &bus_ir_rx_clk.common.hw, 1468 [CLK_IR_TX] = &ir_tx_clk.common.hw, 1469 [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw, 1470 [CLK_GPADC0] = &gpadc0_clk.common.hw, 1471 [CLK_GPADC1] = &gpadc1_clk.common.hw, 1472 [CLK_BUS_GPADC0] = &bus_gpadc0_clk.common.hw, 1473 [CLK_BUS_GPADC1] = &bus_gpadc1_clk.common.hw, 1474 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 1475 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 1476 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 1477 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 1478 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, 1479 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 1480 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 1481 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 1482 [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw, 1483 [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw, 1484 [CLK_BUS_DISPLAY0_TOP] = &bus_display0_top_clk.common.hw, 1485 [CLK_BUS_DISPLAY1_TOP] = &bus_display1_top_clk.common.hw, 1486 [CLK_HDMI_24M] = &hdmi_24M_clk.common.hw, 1487 [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw, 1488 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, 1489 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 1490 [CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw, 1491 [CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw, 1492 [CLK_BUS_MIPI_DSI0] = &bus_mipi_dsi0_clk.common.hw, 1493 [CLK_BUS_MIPI_DSI1] = &bus_mipi_dsi1_clk.common.hw, 1494 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, 1495 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw, 1496 [CLK_TCON_LCD2] = &tcon_lcd2_clk.common.hw, 1497 [CLK_COMBOPHY_DSI0] = &combophy_dsi0_clk.common.hw, 1498 [CLK_COMBOPHY_DSI1] = &combophy_dsi1_clk.common.hw, 1499 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw, 1500 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw, 1501 [CLK_BUS_TCON_LCD2] = &bus_tcon_lcd2_clk.common.hw, 1502 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw, 1503 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw, 1504 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, 1505 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw, 1506 [CLK_EDP] = &edp_clk.common.hw, 1507 [CLK_BUS_EDP] = &bus_edp_clk.common.hw, 1508 [CLK_LEDC] = &ledc_clk.common.hw, 1509 [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw, 1510 [CLK_CSI_TOP] = &csi_top_clk.common.hw, 1511 [CLK_CSI_MCLK0] = &csi_mclk0_clk.common.hw, 1512 [CLK_CSI_MCLK1] = &csi_mclk1_clk.common.hw, 1513 [CLK_CSI_MCLK2] = &csi_mclk2_clk.common.hw, 1514 [CLK_CSI_MCLK3] = &csi_mclk3_clk.common.hw, 1515 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 1516 [CLK_ISP] = &isp_clk.common.hw, 1517 [CLK_DSP] = &dsp_clk.common.hw, 1518 [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw, 1519 [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw, 1520 [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw, 1521 [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw, 1522 [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw, 1523 [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw, 1524 [CLK_FANOUT0] = &fanout0_clk.common.hw, 1525 [CLK_FANOUT1] = &fanout1_clk.common.hw, 1526 [CLK_FANOUT2] = &fanout2_clk.common.hw, 1527 }, 1528 }; 1529 1530 static struct ccu_reset_map sun55i_a523_ccu_resets[] = { 1531 [RST_MBUS] = { 0x540, BIT(30) }, 1532 [RST_BUS_NSI] = { 0x54c, BIT(16) }, 1533 [RST_BUS_DE] = { 0x60c, BIT(16) }, 1534 [RST_BUS_DI] = { 0x62c, BIT(16) }, 1535 [RST_BUS_G2D] = { 0x63c, BIT(16) }, 1536 [RST_BUS_SYS] = { 0x64c, BIT(16) }, 1537 [RST_BUS_GPU] = { 0x67c, BIT(16) }, 1538 [RST_BUS_CE] = { 0x68c, BIT(16) }, 1539 [RST_BUS_SYS_CE] = { 0x68c, BIT(17) }, 1540 [RST_BUS_VE] = { 0x69c, BIT(16) }, 1541 [RST_BUS_DMA] = { 0x70c, BIT(16) }, 1542 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) }, 1543 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) }, 1544 [RST_BUS_CPUXTIMER] = { 0x74c, BIT(16) }, 1545 [RST_BUS_DBG] = { 0x78c, BIT(16) }, 1546 [RST_BUS_PWM0] = { 0x7ac, BIT(16) }, 1547 [RST_BUS_PWM1] = { 0x7ac, BIT(17) }, 1548 [RST_BUS_DRAM] = { 0x80c, BIT(16) }, 1549 [RST_BUS_NAND] = { 0x82c, BIT(16) }, 1550 [RST_BUS_MMC0] = { 0x84c, BIT(16) }, 1551 [RST_BUS_MMC1] = { 0x84c, BIT(17) }, 1552 [RST_BUS_MMC2] = { 0x84c, BIT(18) }, 1553 [RST_BUS_SYSDAP] = { 0x88c, BIT(16) }, 1554 [RST_BUS_UART0] = { 0x90c, BIT(16) }, 1555 [RST_BUS_UART1] = { 0x90c, BIT(17) }, 1556 [RST_BUS_UART2] = { 0x90c, BIT(18) }, 1557 [RST_BUS_UART3] = { 0x90c, BIT(19) }, 1558 [RST_BUS_UART4] = { 0x90c, BIT(20) }, 1559 [RST_BUS_UART5] = { 0x90c, BIT(21) }, 1560 [RST_BUS_UART6] = { 0x90c, BIT(22) }, 1561 [RST_BUS_UART7] = { 0x90c, BIT(23) }, 1562 [RST_BUS_I2C0] = { 0x91c, BIT(16) }, 1563 [RST_BUS_I2C1] = { 0x91c, BIT(17) }, 1564 [RST_BUS_I2C2] = { 0x91c, BIT(18) }, 1565 [RST_BUS_I2C3] = { 0x91c, BIT(19) }, 1566 [RST_BUS_I2C4] = { 0x91c, BIT(20) }, 1567 [RST_BUS_I2C5] = { 0x91c, BIT(21) }, 1568 [RST_BUS_CAN] = { 0x92c, BIT(16) }, 1569 [RST_BUS_SPI0] = { 0x96c, BIT(16) }, 1570 [RST_BUS_SPI1] = { 0x96c, BIT(17) }, 1571 [RST_BUS_SPI2] = { 0x96c, BIT(18) }, 1572 [RST_BUS_SPIFC] = { 0x96c, BIT(19) }, 1573 [RST_BUS_EMAC0] = { 0x97c, BIT(16) }, 1574 [RST_BUS_EMAC1] = { 0x98c, BIT(16) | BIT(17) }, /* GMAC1-AXI */ 1575 [RST_BUS_IR_RX] = { 0x99c, BIT(16) }, 1576 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) }, 1577 [RST_BUS_GPADC0] = { 0x9ec, BIT(16) }, 1578 [RST_BUS_GPADC1] = { 0x9ec, BIT(17) }, 1579 [RST_BUS_THS] = { 0x9fc, BIT(16) }, 1580 [RST_USB_PHY0] = { 0xa70, BIT(30) }, 1581 [RST_USB_PHY1] = { 0xa74, BIT(30) }, 1582 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) }, 1583 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) }, 1584 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) }, 1585 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) }, 1586 [RST_BUS_OTG] = { 0xa8c, BIT(24) }, 1587 [RST_BUS_3] = { 0xa8c, BIT(25) }, /* BSP + register */ 1588 [RST_BUS_LRADC] = { 0xa9c, BIT(16) }, 1589 [RST_BUS_PCIE_USB3] = { 0xaac, BIT(16) }, 1590 [RST_BUS_DISPLAY0_TOP] = { 0xabc, BIT(16) }, 1591 [RST_BUS_DISPLAY1_TOP] = { 0xacc, BIT(16) }, 1592 [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) }, 1593 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) }, 1594 [RST_BUS_MIPI_DSI0] = { 0xb4c, BIT(16) }, 1595 [RST_BUS_MIPI_DSI1] = { 0xb4c, BIT(17) }, 1596 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) }, 1597 [RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) }, 1598 [RST_BUS_TCON_LCD2] = { 0xb7c, BIT(18) }, 1599 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) }, 1600 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) }, 1601 [RST_BUS_LVDS0] = { 0xbac, BIT(16) }, 1602 [RST_BUS_LVDS1] = { 0xbac, BIT(17) }, 1603 [RST_BUS_EDP] = { 0xbbc, BIT(16) }, 1604 [RST_BUS_VIDEO_OUT0] = { 0xbcc, BIT(16) }, 1605 [RST_BUS_VIDEO_OUT1] = { 0xbcc, BIT(17) }, 1606 [RST_BUS_LEDC] = { 0xbfc, BIT(16) }, 1607 [RST_BUS_CSI] = { 0xc1c, BIT(16) }, 1608 [RST_BUS_ISP] = { 0xc2c, BIT(16) }, /* BSP + register */ 1609 }; 1610 1611 static const struct sunxi_ccu_desc sun55i_a523_ccu_desc = { 1612 .ccu_clks = sun55i_a523_ccu_clks, 1613 .num_ccu_clks = ARRAY_SIZE(sun55i_a523_ccu_clks), 1614 1615 .hw_clks = &sun55i_a523_hw_clks, 1616 1617 .resets = sun55i_a523_ccu_resets, 1618 .num_resets = ARRAY_SIZE(sun55i_a523_ccu_resets), 1619 }; 1620 1621 static const u32 pll_regs[] = { 1622 SUN55I_A523_PLL_DDR0_REG, 1623 SUN55I_A523_PLL_PERIPH0_REG, 1624 SUN55I_A523_PLL_PERIPH1_REG, 1625 SUN55I_A523_PLL_GPU_REG, 1626 SUN55I_A523_PLL_VIDEO0_REG, 1627 SUN55I_A523_PLL_VIDEO1_REG, 1628 SUN55I_A523_PLL_VIDEO2_REG, 1629 SUN55I_A523_PLL_VE_REG, 1630 SUN55I_A523_PLL_VIDEO3_REG, 1631 SUN55I_A523_PLL_AUDIO0_REG, 1632 SUN55I_A523_PLL_NPU_REG, 1633 }; 1634 1635 static int sun55i_a523_ccu_probe(struct platform_device *pdev) 1636 { 1637 void __iomem *reg; 1638 u32 val; 1639 int i, ret; 1640 1641 reg = devm_platform_ioremap_resource(pdev, 0); 1642 if (IS_ERR(reg)) 1643 return PTR_ERR(reg); 1644 1645 /* 1646 * The PLL clock code does not model all bits, for instance it does 1647 * not support a separate enable and gate bit. We present the 1648 * gate bit(27) as the enable bit, but then have to set the 1649 * PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here. 1650 */ 1651 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { 1652 val = readl(reg + pll_regs[i]); 1653 val |= BIT(31) | BIT(30) | BIT(29); 1654 writel(val, reg + pll_regs[i]); 1655 } 1656 1657 /* Enforce m1 = 0, m0 = 0 for PLL_AUDIO0 */ 1658 val = readl(reg + SUN55I_A523_PLL_AUDIO0_REG); 1659 val &= ~(BIT(1) | BIT(0)); 1660 writel(val, reg + SUN55I_A523_PLL_AUDIO0_REG); 1661 1662 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_ccu_desc); 1663 if (ret) 1664 return ret; 1665 1666 return 0; 1667 } 1668 1669 static const struct of_device_id sun55i_a523_ccu_ids[] = { 1670 { .compatible = "allwinner,sun55i-a523-ccu" }, 1671 { } 1672 }; 1673 1674 static struct platform_driver sun55i_a523_ccu_driver = { 1675 .probe = sun55i_a523_ccu_probe, 1676 .driver = { 1677 .name = "sun55i-a523-ccu", 1678 .suppress_bind_attrs = true, 1679 .of_match_table = sun55i_a523_ccu_ids, 1680 }, 1681 }; 1682 module_platform_driver(sun55i_a523_ccu_driver); 1683 1684 MODULE_IMPORT_NS("SUNXI_CCU"); 1685 MODULE_DESCRIPTION("Support for the Allwinner A523 CCU"); 1686 MODULE_LICENSE("GPL"); 1687