1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Arm Ltd. 4 * Based on the H6 CCU driver, which is: 5 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 13 #include "ccu_common.h" 14 #include "ccu_reset.h" 15 16 #include "ccu_div.h" 17 #include "ccu_gate.h" 18 #include "ccu_mp.h" 19 #include "ccu_mult.h" 20 #include "ccu_nk.h" 21 #include "ccu_nkm.h" 22 #include "ccu_nkmp.h" 23 #include "ccu_nm.h" 24 25 #include "ccu-sun50i-h616.h" 26 27 /* 28 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However 29 * P should only be used for output frequencies lower than 288 MHz. 30 * 31 * For now we can just model it as a multiplier clock, and force P to /1. 32 * 33 * The M factor is present in the register's description, but not in the 34 * frequency formula, and it's documented as "M is only used for backdoor 35 * testing", so it's not modelled and then force to 0. 36 */ 37 #define SUN50I_H616_PLL_CPUX_REG 0x000 38 static struct ccu_mult pll_cpux_clk = { 39 .enable = BIT(31), 40 .lock = BIT(28), 41 .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12), 42 .common = { 43 .reg = 0x000, 44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", 45 &ccu_mult_ops, 46 CLK_SET_RATE_UNGATE), 47 }, 48 }; 49 50 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ 51 #define SUN50I_H616_PLL_DDR0_REG 0x010 52 static struct ccu_nkmp pll_ddr0_clk = { 53 .enable = BIT(31), 54 .lock = BIT(28), 55 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 56 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 57 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 58 .common = { 59 .reg = 0x010, 60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M", 61 &ccu_nkmp_ops, 62 CLK_SET_RATE_UNGATE), 63 }, 64 }; 65 66 #define SUN50I_H616_PLL_DDR1_REG 0x018 67 static struct ccu_nkmp pll_ddr1_clk = { 68 .enable = BIT(31), 69 .lock = BIT(28), 70 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 71 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 72 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 73 .common = { 74 .reg = 0x018, 75 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M", 76 &ccu_nkmp_ops, 77 CLK_SET_RATE_UNGATE), 78 }, 79 }; 80 81 #define SUN50I_H616_PLL_PERIPH0_REG 0x020 82 static struct ccu_nkmp pll_periph0_clk = { 83 .enable = BIT(31), 84 .lock = BIT(28), 85 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 86 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 87 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 88 .fixed_post_div = 2, 89 .common = { 90 .reg = 0x020, 91 .features = CCU_FEATURE_FIXED_POSTDIV, 92 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 93 &ccu_nkmp_ops, 94 CLK_SET_RATE_UNGATE), 95 }, 96 }; 97 98 #define SUN50I_H616_PLL_PERIPH1_REG 0x028 99 static struct ccu_nkmp pll_periph1_clk = { 100 .enable = BIT(31), 101 .lock = BIT(28), 102 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 103 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 104 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 105 .fixed_post_div = 2, 106 .common = { 107 .reg = 0x028, 108 .features = CCU_FEATURE_FIXED_POSTDIV, 109 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 110 &ccu_nkmp_ops, 111 CLK_SET_RATE_UNGATE), 112 }, 113 }; 114 115 #define SUN50I_H616_PLL_GPU_REG 0x030 116 static struct ccu_nkmp pll_gpu_clk = { 117 .enable = BIT(31), 118 .lock = BIT(28), 119 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 120 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 121 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 122 .common = { 123 .reg = 0x030, 124 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", 125 &ccu_nkmp_ops, 126 CLK_SET_RATE_UNGATE), 127 }, 128 }; 129 130 /* 131 * For Video PLLs, the output divider is described as "used for testing" 132 * in the user manual. So it's not modelled and forced to 0. 133 */ 134 #define SUN50I_H616_PLL_VIDEO0_REG 0x040 135 static struct ccu_nm pll_video0_clk = { 136 .enable = BIT(31), 137 .lock = BIT(28), 138 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 139 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 140 .fixed_post_div = 4, 141 .min_rate = 288000000, 142 .max_rate = 2400000000UL, 143 .common = { 144 .reg = 0x040, 145 .features = CCU_FEATURE_FIXED_POSTDIV, 146 .hw.init = CLK_HW_INIT("pll-video0", "osc24M", 147 &ccu_nm_ops, 148 CLK_SET_RATE_UNGATE), 149 }, 150 }; 151 152 #define SUN50I_H616_PLL_VIDEO1_REG 0x048 153 static struct ccu_nm pll_video1_clk = { 154 .enable = BIT(31), 155 .lock = BIT(28), 156 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 157 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 158 .fixed_post_div = 4, 159 .min_rate = 288000000, 160 .max_rate = 2400000000UL, 161 .common = { 162 .reg = 0x048, 163 .features = CCU_FEATURE_FIXED_POSTDIV, 164 .hw.init = CLK_HW_INIT("pll-video1", "osc24M", 165 &ccu_nm_ops, 166 CLK_SET_RATE_UNGATE), 167 }, 168 }; 169 170 #define SUN50I_H616_PLL_VIDEO2_REG 0x050 171 static struct ccu_nm pll_video2_clk = { 172 .enable = BIT(31), 173 .lock = BIT(28), 174 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 175 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 176 .fixed_post_div = 4, 177 .min_rate = 288000000, 178 .max_rate = 2400000000UL, 179 .common = { 180 .reg = 0x050, 181 .features = CCU_FEATURE_FIXED_POSTDIV, 182 .hw.init = CLK_HW_INIT("pll-video2", "osc24M", 183 &ccu_nm_ops, 184 CLK_SET_RATE_UNGATE), 185 }, 186 }; 187 188 #define SUN50I_H616_PLL_VE_REG 0x058 189 static struct ccu_nkmp pll_ve_clk = { 190 .enable = BIT(31), 191 .lock = BIT(28), 192 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 193 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 194 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 195 .common = { 196 .reg = 0x058, 197 .hw.init = CLK_HW_INIT("pll-ve", "osc24M", 198 &ccu_nkmp_ops, 199 CLK_SET_RATE_UNGATE), 200 }, 201 }; 202 203 #define SUN50I_H616_PLL_DE_REG 0x060 204 static struct ccu_nkmp pll_de_clk = { 205 .enable = BIT(31), 206 .lock = BIT(28), 207 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 208 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 209 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 210 .common = { 211 .reg = 0x060, 212 .hw.init = CLK_HW_INIT("pll-de", "osc24M", 213 &ccu_nkmp_ops, 214 CLK_SET_RATE_UNGATE), 215 }, 216 }; 217 218 /* 219 * Sigma-delta modulation settings table obtained from the vendor SDK driver. 220 * There are additional M0 and M1 divider bits not modelled here, so forced to 221 * fixed values in the probe routine. Sigma-delta modulation allows providing a 222 * fractional-N divider in the PLL, to help reaching those specific 223 * frequencies with less error. 224 */ 225 static struct ccu_sdm_setting pll_audio_sdm_table[] = { 226 { .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 }, 227 { .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 }, 228 }; 229 230 #define SUN50I_H616_PLL_AUDIO_REG 0x078 231 static struct ccu_nm pll_audio_hs_clk = { 232 .enable = BIT(31), 233 .lock = BIT(28), 234 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 235 .m = _SUNXI_CCU_DIV(16, 6), 236 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 237 BIT(24), 0x178, BIT(31)), 238 .fixed_post_div = 2, 239 .common = { 240 .features = CCU_FEATURE_FIXED_POSTDIV | 241 CCU_FEATURE_SIGMA_DELTA_MOD, 242 .reg = 0x078, 243 .hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M", 244 &ccu_nm_ops, 245 CLK_SET_RATE_UNGATE), 246 }, 247 }; 248 249 static const char * const cpux_parents[] = { "osc24M", "osc32k", 250 "iosc", "pll-cpux", "pll-periph0" }; 251 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 252 0x500, 24, 3, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 253 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0); 254 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0); 255 256 static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k", 257 "iosc", "pll-periph0" }; 258 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2", 259 psi_ahb1_ahb2_parents, 260 0x510, 261 0, 2, /* M */ 262 8, 2, /* P */ 263 24, 2, /* mux */ 264 0); 265 266 static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k", 267 "psi-ahb1-ahb2", 268 "pll-periph0" }; 269 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c, 270 0, 2, /* M */ 271 8, 2, /* P */ 272 24, 2, /* mux */ 273 0); 274 275 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520, 276 0, 2, /* M */ 277 8, 2, /* P */ 278 24, 2, /* mux */ 279 0); 280 281 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524, 282 0, 2, /* M */ 283 8, 2, /* P */ 284 24, 2, /* mux */ 285 0); 286 287 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 288 "pll-ddr0", "pll-ddr1" }; 289 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540, 290 0, 3, /* M */ 291 24, 2, /* mux */ 292 BIT(31), /* gate */ 293 CLK_IS_CRITICAL); 294 295 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" }; 296 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, 297 0, 4, /* M */ 298 24, 1, /* mux */ 299 BIT(31), /* gate */ 300 CLK_SET_RATE_PARENT); 301 302 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2", 303 0x60c, BIT(0), 0); 304 305 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", 306 de_parents, 307 0x620, 308 0, 4, /* M */ 309 24, 1, /* mux */ 310 BIT(31), /* gate */ 311 0); 312 313 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2", 314 0x62c, BIT(0), 0); 315 316 static SUNXI_CCU_M_WITH_MUX_GATE(g2d_clk, "g2d", de_parents, 0x630, 317 0, 4, /* M */ 318 24, 1, /* mux */ 319 BIT(31), /* gate */ 320 0); 321 322 static SUNXI_CCU_GATE(bus_g2d_clk, "bus-g2d", "psi-ahb1-ahb2", 323 0x63c, BIT(0), 0); 324 325 static const char * const gpu0_parents[] = { "pll-gpu", "gpu1" }; 326 static SUNXI_CCU_M_WITH_MUX_GATE(gpu0_clk, "gpu0", gpu0_parents, 0x670, 327 0, 2, /* M */ 328 24, 1, /* mux */ 329 BIT(31), /* gate */ 330 CLK_SET_RATE_PARENT); 331 static SUNXI_CCU_M_WITH_GATE(gpu1_clk, "gpu1", "pll-periph0-2x", 0x674, 332 0, 2, /* M */ 333 BIT(31),/* gate */ 334 0); 335 336 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", 337 0x67c, BIT(0), 0); 338 339 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" }; 340 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680, 341 0, 4, /* M */ 342 8, 2, /* N */ 343 24, 1, /* mux */ 344 BIT(31),/* gate */ 345 0); 346 347 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2", 348 0x68c, BIT(0), 0); 349 350 static const char * const ve_parents[] = { "pll-ve" }; 351 static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, 352 0, 3, /* M */ 353 24, 1, /* mux */ 354 BIT(31), /* gate */ 355 CLK_SET_RATE_PARENT); 356 357 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", 358 0x69c, BIT(0), 0); 359 360 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2", 361 0x70c, BIT(0), 0); 362 363 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2", 364 0x73c, BIT(0), 0); 365 366 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0); 367 368 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2", 369 0x78c, BIT(0), 0); 370 371 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2", 372 0x79c, BIT(0), 0); 373 374 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0); 375 376 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); 377 378 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; 379 static struct ccu_div dram_clk = { 380 .div = _SUNXI_CCU_DIV(0, 2), 381 .mux = _SUNXI_CCU_MUX(24, 2), 382 .common = { 383 .reg = 0x800, 384 .hw.init = CLK_HW_INIT_PARENTS("dram", 385 dram_parents, 386 &ccu_div_ops, 387 CLK_IS_CRITICAL), 388 }, 389 }; 390 391 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus", 392 0x804, BIT(0), 0); 393 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus", 394 0x804, BIT(1), 0); 395 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus", 396 0x804, BIT(2), 0); 397 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus", 398 0x804, BIT(3), 0); 399 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus", 400 0x804, BIT(5), 0); 401 static SUNXI_CCU_GATE(mbus_g2d_clk, "mbus-g2d", "mbus", 402 0x804, BIT(10), 0); 403 404 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2", 405 0x80c, BIT(0), CLK_IS_CRITICAL); 406 407 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0", 408 "pll-periph1", "pll-periph0-2x", 409 "pll-periph1-2x" }; 410 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810, 411 0, 4, /* M */ 412 8, 2, /* N */ 413 24, 3, /* mux */ 414 BIT(31),/* gate */ 415 0); 416 417 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814, 418 0, 4, /* M */ 419 8, 2, /* N */ 420 24, 3, /* mux */ 421 BIT(31),/* gate */ 422 0); 423 424 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0); 425 426 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", 427 "pll-periph1-2x" }; 428 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 429 0, 4, /* M */ 430 8, 2, /* N */ 431 24, 2, /* mux */ 432 BIT(31), /* gate */ 433 2, /* post-div */ 434 0); 435 436 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 437 0, 4, /* M */ 438 8, 2, /* N */ 439 24, 2, /* mux */ 440 BIT(31), /* gate */ 441 2, /* post-div */ 442 0); 443 444 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 445 0, 4, /* M */ 446 8, 2, /* N */ 447 24, 2, /* mux */ 448 BIT(31), /* gate */ 449 2, /* post-div */ 450 0); 451 452 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); 453 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); 454 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0); 455 456 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0); 457 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0); 458 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0); 459 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0); 460 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 0x90c, BIT(4), 0); 461 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2", 0x90c, BIT(5), 0); 462 463 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0); 464 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0); 465 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0); 466 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0); 467 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2", 0x91c, BIT(4), 0); 468 469 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940, 470 0, 4, /* M */ 471 8, 2, /* N */ 472 24, 3, /* mux */ 473 BIT(31),/* gate */ 474 0); 475 476 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944, 477 0, 4, /* M */ 478 8, 2, /* N */ 479 24, 3, /* mux */ 480 BIT(31),/* gate */ 481 0); 482 483 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0); 484 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0); 485 486 static SUNXI_CCU_GATE(emac_25m_clk, "emac-25m", "ahb3", 0x970, 487 BIT(31) | BIT(30), 0); 488 489 static SUNXI_CCU_GATE(bus_emac0_clk, "bus-emac0", "ahb3", 0x97c, BIT(0), 0); 490 static SUNXI_CCU_GATE(bus_emac1_clk, "bus-emac1", "ahb3", 0x97c, BIT(1), 0); 491 492 static const char * const ts_parents[] = { "osc24M", "pll-periph0" }; 493 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0, 494 0, 4, /* M */ 495 8, 2, /* N */ 496 24, 1, /* mux */ 497 BIT(31),/* gate */ 498 0); 499 500 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0); 501 502 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0); 503 504 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0); 505 506 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x", 507 "pll-audio-4x", "pll-audio-hs" }; 508 static struct ccu_div spdif_clk = { 509 .enable = BIT(31), 510 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 511 .mux = _SUNXI_CCU_MUX(24, 2), 512 .common = { 513 .reg = 0xa20, 514 .hw.init = CLK_HW_INIT_PARENTS("spdif", 515 audio_parents, 516 &ccu_div_ops, 517 0), 518 }, 519 }; 520 521 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0); 522 523 static struct ccu_div dmic_clk = { 524 .enable = BIT(31), 525 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 526 .mux = _SUNXI_CCU_MUX(24, 2), 527 .common = { 528 .reg = 0xa40, 529 .hw.init = CLK_HW_INIT_PARENTS("dmic", 530 audio_parents, 531 &ccu_div_ops, 532 0), 533 }, 534 }; 535 536 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0); 537 538 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_1x_clk, "audio-codec-1x", 539 audio_parents, 0xa50, 540 0, 4, /* M */ 541 24, 2, /* mux */ 542 BIT(31), /* gate */ 543 CLK_SET_RATE_PARENT); 544 static SUNXI_CCU_M_WITH_MUX_GATE(audio_codec_4x_clk, "audio-codec-4x", 545 audio_parents, 0xa54, 546 0, 4, /* M */ 547 24, 2, /* mux */ 548 BIT(31), /* gate */ 549 CLK_SET_RATE_PARENT); 550 551 static SUNXI_CCU_GATE(bus_audio_codec_clk, "bus-audio-codec", "apb1", 0xa5c, 552 BIT(0), 0); 553 554 static struct ccu_div audio_hub_clk = { 555 .enable = BIT(31), 556 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 557 .mux = _SUNXI_CCU_MUX(24, 2), 558 .common = { 559 .reg = 0xa60, 560 .hw.init = CLK_HW_INIT_PARENTS("audio-hub", 561 audio_parents, 562 &ccu_div_ops, 563 0), 564 }, 565 }; 566 567 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0); 568 569 /* 570 * There are OHCI 12M clock source selection bits for the four USB 2.0 ports. 571 * We will force them to 0 (12M divided from 48M). 572 */ 573 #define SUN50I_H616_USB0_CLK_REG 0xa70 574 #define SUN50I_H616_USB1_CLK_REG 0xa74 575 #define SUN50I_H616_USB2_CLK_REG 0xa78 576 #define SUN50I_H616_USB3_CLK_REG 0xa7c 577 578 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0); 579 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0); 580 581 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M", 0xa74, BIT(31), 0); 582 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0); 583 584 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M", 0xa78, BIT(31), 0); 585 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 0xa78, BIT(29), 0); 586 587 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0); 588 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc24M", 0xa7c, BIT(29), 0); 589 590 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0); 591 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb3", 0xa8c, BIT(1), 0); 592 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb3", 0xa8c, BIT(2), 0); 593 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0); 594 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0); 595 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb3", 0xa8c, BIT(5), 0); 596 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb3", 0xa8c, BIT(6), 0); 597 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0); 598 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0); 599 600 static SUNXI_CCU_GATE(bus_keyadc_clk, "bus-keyadc", "apb1", 0xa9c, BIT(0), 0); 601 602 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-4x", 603 "pll-video2", "pll-video2-4x" }; 604 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00, 605 0, 4, /* M */ 606 24, 2, /* mux */ 607 BIT(31), /* gate */ 608 0); 609 610 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0); 611 612 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; 613 static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { 614 { .index = 1, .div = 36621 }, 615 }; 616 617 #define SUN50I_H616_HDMI_CEC_CLK_REG 0xb10 618 static struct ccu_mux hdmi_cec_clk = { 619 .enable = BIT(31) | BIT(30), 620 621 .mux = { 622 .shift = 24, 623 .width = 2, 624 625 .fixed_predivs = hdmi_cec_predivs, 626 .n_predivs = ARRAY_SIZE(hdmi_cec_predivs), 627 }, 628 629 .common = { 630 .reg = 0xb10, 631 .features = CCU_FEATURE_FIXED_PREDIV, 632 .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec", 633 hdmi_cec_parents, 634 &ccu_mux_ops, 635 0), 636 }, 637 }; 638 639 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0); 640 641 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3", 642 0xb5c, BIT(0), 0); 643 644 static const char * const tcon_tv_parents[] = { "pll-video0", 645 "pll-video0-4x", 646 "pll-video1", 647 "pll-video1-4x" }; 648 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", 649 tcon_tv_parents, 0xb80, 650 0, 4, /* M */ 651 8, 2, /* P */ 652 24, 3, /* mux */ 653 BIT(31), /* gate */ 654 CLK_SET_RATE_PARENT); 655 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", 656 tcon_tv_parents, 0xb84, 657 0, 4, /* M */ 658 8, 2, /* P */ 659 24, 3, /* mux */ 660 BIT(31), /* gate */ 661 CLK_SET_RATE_PARENT); 662 663 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", 664 0xb9c, BIT(0), 0); 665 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb3", 666 0xb9c, BIT(1), 0); 667 668 static SUNXI_CCU_MP_WITH_MUX_GATE(tve0_clk, "tve0", 669 tcon_tv_parents, 0xbb0, 670 0, 4, /* M */ 671 8, 2, /* P */ 672 24, 3, /* mux */ 673 BIT(31), /* gate */ 674 CLK_SET_RATE_PARENT); 675 676 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb3", 677 0xbbc, BIT(0), 0); 678 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb3", 679 0xbbc, BIT(1), 0); 680 681 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" }; 682 static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40, 683 0, 4, /* M */ 684 24, 2, /* mux */ 685 BIT(31), /* gate */ 686 0); 687 688 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0); 689 690 /* Fixed factor clocks */ 691 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0); 692 693 static const struct clk_hw *clk_parent_pll_audio[] = { 694 &pll_audio_hs_clk.common.hw 695 }; 696 697 /* 698 * The PLL_AUDIO_4X clock defaults to 24.5714 MHz according to the manual, with 699 * a final divider of 1. The 2X and 1X clocks use 2 and 4 respectively. The 1x 700 * clock is set to either 24576000 or 22579200 for 48Khz and 44.1Khz (and 701 * multiples). 702 */ 703 static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x", 704 clk_parent_pll_audio, 705 4, 1, CLK_SET_RATE_PARENT); 706 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", 707 clk_parent_pll_audio, 708 2, 1, CLK_SET_RATE_PARENT); 709 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", 710 clk_parent_pll_audio, 711 1, 1, CLK_SET_RATE_PARENT); 712 713 static const struct clk_hw *pll_periph0_parents[] = { 714 &pll_periph0_clk.common.hw 715 }; 716 717 static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x", 718 pll_periph0_parents, 719 1, 2, 0); 720 721 static const struct clk_hw *pll_periph0_2x_hws[] = { 722 &pll_periph0_2x_clk.hw 723 }; 724 725 static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k", 726 pll_periph0_2x_hws, 36621, 1, 0); 727 728 static const struct clk_hw *pll_periph1_parents[] = { 729 &pll_periph1_clk.common.hw 730 }; 731 732 static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x", 733 pll_periph1_parents, 734 1, 2, 0); 735 736 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x", 737 &pll_video0_clk.common.hw, 738 1, 4, CLK_SET_RATE_PARENT); 739 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x", 740 &pll_video1_clk.common.hw, 741 1, 4, CLK_SET_RATE_PARENT); 742 static CLK_FIXED_FACTOR_HW(pll_video2_4x_clk, "pll-video2-4x", 743 &pll_video2_clk.common.hw, 744 1, 4, CLK_SET_RATE_PARENT); 745 746 static struct ccu_common *sun50i_h616_ccu_clks[] = { 747 &pll_cpux_clk.common, 748 &pll_ddr0_clk.common, 749 &pll_ddr1_clk.common, 750 &pll_periph0_clk.common, 751 &pll_periph1_clk.common, 752 &pll_gpu_clk.common, 753 &pll_video0_clk.common, 754 &pll_video1_clk.common, 755 &pll_video2_clk.common, 756 &pll_ve_clk.common, 757 &pll_de_clk.common, 758 &pll_audio_hs_clk.common, 759 &cpux_clk.common, 760 &axi_clk.common, 761 &cpux_apb_clk.common, 762 &psi_ahb1_ahb2_clk.common, 763 &ahb3_clk.common, 764 &apb1_clk.common, 765 &apb2_clk.common, 766 &mbus_clk.common, 767 &de_clk.common, 768 &bus_de_clk.common, 769 &deinterlace_clk.common, 770 &bus_deinterlace_clk.common, 771 &g2d_clk.common, 772 &bus_g2d_clk.common, 773 &gpu0_clk.common, 774 &bus_gpu_clk.common, 775 &gpu1_clk.common, 776 &ce_clk.common, 777 &bus_ce_clk.common, 778 &ve_clk.common, 779 &bus_ve_clk.common, 780 &bus_dma_clk.common, 781 &bus_hstimer_clk.common, 782 &avs_clk.common, 783 &bus_dbg_clk.common, 784 &bus_psi_clk.common, 785 &bus_pwm_clk.common, 786 &bus_iommu_clk.common, 787 &dram_clk.common, 788 &mbus_dma_clk.common, 789 &mbus_ve_clk.common, 790 &mbus_ce_clk.common, 791 &mbus_ts_clk.common, 792 &mbus_nand_clk.common, 793 &mbus_g2d_clk.common, 794 &bus_dram_clk.common, 795 &nand0_clk.common, 796 &nand1_clk.common, 797 &bus_nand_clk.common, 798 &mmc0_clk.common, 799 &mmc1_clk.common, 800 &mmc2_clk.common, 801 &bus_mmc0_clk.common, 802 &bus_mmc1_clk.common, 803 &bus_mmc2_clk.common, 804 &bus_uart0_clk.common, 805 &bus_uart1_clk.common, 806 &bus_uart2_clk.common, 807 &bus_uart3_clk.common, 808 &bus_uart4_clk.common, 809 &bus_uart5_clk.common, 810 &bus_i2c0_clk.common, 811 &bus_i2c1_clk.common, 812 &bus_i2c2_clk.common, 813 &bus_i2c3_clk.common, 814 &bus_i2c4_clk.common, 815 &spi0_clk.common, 816 &spi1_clk.common, 817 &bus_spi0_clk.common, 818 &bus_spi1_clk.common, 819 &emac_25m_clk.common, 820 &bus_emac0_clk.common, 821 &bus_emac1_clk.common, 822 &ts_clk.common, 823 &bus_ts_clk.common, 824 &bus_gpadc_clk.common, 825 &bus_ths_clk.common, 826 &spdif_clk.common, 827 &bus_spdif_clk.common, 828 &dmic_clk.common, 829 &bus_dmic_clk.common, 830 &audio_codec_1x_clk.common, 831 &audio_codec_4x_clk.common, 832 &bus_audio_codec_clk.common, 833 &audio_hub_clk.common, 834 &bus_audio_hub_clk.common, 835 &usb_ohci0_clk.common, 836 &usb_phy0_clk.common, 837 &usb_ohci1_clk.common, 838 &usb_phy1_clk.common, 839 &usb_ohci2_clk.common, 840 &usb_phy2_clk.common, 841 &usb_ohci3_clk.common, 842 &usb_phy3_clk.common, 843 &bus_ohci0_clk.common, 844 &bus_ohci1_clk.common, 845 &bus_ohci2_clk.common, 846 &bus_ohci3_clk.common, 847 &bus_ehci0_clk.common, 848 &bus_ehci1_clk.common, 849 &bus_ehci2_clk.common, 850 &bus_ehci3_clk.common, 851 &bus_otg_clk.common, 852 &bus_keyadc_clk.common, 853 &hdmi_clk.common, 854 &hdmi_slow_clk.common, 855 &hdmi_cec_clk.common, 856 &bus_hdmi_clk.common, 857 &bus_tcon_top_clk.common, 858 &tcon_tv0_clk.common, 859 &tcon_tv1_clk.common, 860 &bus_tcon_tv0_clk.common, 861 &bus_tcon_tv1_clk.common, 862 &tve0_clk.common, 863 &bus_tve_top_clk.common, 864 &bus_tve0_clk.common, 865 &hdcp_clk.common, 866 &bus_hdcp_clk.common, 867 }; 868 869 static struct clk_hw_onecell_data sun50i_h616_hw_clks = { 870 .hws = { 871 [CLK_OSC12M] = &osc12M_clk.hw, 872 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 873 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 874 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 875 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 876 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 877 [CLK_PLL_SYSTEM_32K] = &pll_system_32k_clk.hw, 878 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 879 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 880 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 881 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 882 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw, 883 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 884 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw, 885 [CLK_PLL_VIDEO2] = &pll_video2_clk.common.hw, 886 [CLK_PLL_VIDEO2_4X] = &pll_video2_4x_clk.hw, 887 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 888 [CLK_PLL_DE] = &pll_de_clk.common.hw, 889 [CLK_PLL_AUDIO_HS] = &pll_audio_hs_clk.common.hw, 890 [CLK_PLL_AUDIO_1X] = &pll_audio_1x_clk.hw, 891 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 892 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 893 [CLK_CPUX] = &cpux_clk.common.hw, 894 [CLK_AXI] = &axi_clk.common.hw, 895 [CLK_CPUX_APB] = &cpux_apb_clk.common.hw, 896 [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw, 897 [CLK_AHB3] = &ahb3_clk.common.hw, 898 [CLK_APB1] = &apb1_clk.common.hw, 899 [CLK_APB2] = &apb2_clk.common.hw, 900 [CLK_MBUS] = &mbus_clk.common.hw, 901 [CLK_DE] = &de_clk.common.hw, 902 [CLK_BUS_DE] = &bus_de_clk.common.hw, 903 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 904 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 905 [CLK_G2D] = &g2d_clk.common.hw, 906 [CLK_BUS_G2D] = &bus_g2d_clk.common.hw, 907 [CLK_GPU0] = &gpu0_clk.common.hw, 908 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 909 [CLK_GPU1] = &gpu1_clk.common.hw, 910 [CLK_CE] = &ce_clk.common.hw, 911 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 912 [CLK_VE] = &ve_clk.common.hw, 913 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 914 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 915 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 916 [CLK_AVS] = &avs_clk.common.hw, 917 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 918 [CLK_BUS_PSI] = &bus_psi_clk.common.hw, 919 [CLK_BUS_PWM] = &bus_pwm_clk.common.hw, 920 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw, 921 [CLK_DRAM] = &dram_clk.common.hw, 922 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw, 923 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw, 924 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw, 925 [CLK_MBUS_TS] = &mbus_ts_clk.common.hw, 926 [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw, 927 [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw, 928 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 929 [CLK_NAND0] = &nand0_clk.common.hw, 930 [CLK_NAND1] = &nand1_clk.common.hw, 931 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 932 [CLK_MMC0] = &mmc0_clk.common.hw, 933 [CLK_MMC1] = &mmc1_clk.common.hw, 934 [CLK_MMC2] = &mmc2_clk.common.hw, 935 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 936 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 937 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 938 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 939 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 940 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 941 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 942 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 943 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, 944 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 945 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 946 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 947 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, 948 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, 949 [CLK_SPI0] = &spi0_clk.common.hw, 950 [CLK_SPI1] = &spi1_clk.common.hw, 951 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 952 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 953 [CLK_EMAC_25M] = &emac_25m_clk.common.hw, 954 [CLK_BUS_EMAC0] = &bus_emac0_clk.common.hw, 955 [CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw, 956 [CLK_TS] = &ts_clk.common.hw, 957 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 958 [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw, 959 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 960 [CLK_SPDIF] = &spdif_clk.common.hw, 961 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 962 [CLK_DMIC] = &dmic_clk.common.hw, 963 [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw, 964 [CLK_AUDIO_CODEC_1X] = &audio_codec_1x_clk.common.hw, 965 [CLK_AUDIO_CODEC_4X] = &audio_codec_4x_clk.common.hw, 966 [CLK_BUS_AUDIO_CODEC] = &bus_audio_codec_clk.common.hw, 967 [CLK_AUDIO_HUB] = &audio_hub_clk.common.hw, 968 [CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw, 969 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 970 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 971 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 972 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 973 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, 974 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw, 975 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw, 976 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw, 977 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 978 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, 979 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw, 980 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw, 981 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 982 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 983 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw, 984 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw, 985 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 986 [CLK_BUS_KEYADC] = &bus_keyadc_clk.common.hw, 987 [CLK_HDMI] = &hdmi_clk.common.hw, 988 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, 989 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, 990 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 991 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw, 992 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw, 993 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw, 994 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, 995 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw, 996 [CLK_TVE0] = &tve0_clk.common.hw, 997 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw, 998 [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw, 999 [CLK_HDCP] = &hdcp_clk.common.hw, 1000 [CLK_BUS_HDCP] = &bus_hdcp_clk.common.hw, 1001 }, 1002 .num = CLK_NUMBER, 1003 }; 1004 1005 static const struct ccu_reset_map sun50i_h616_ccu_resets[] = { 1006 [RST_MBUS] = { 0x540, BIT(30) }, 1007 1008 [RST_BUS_DE] = { 0x60c, BIT(16) }, 1009 [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) }, 1010 [RST_BUS_GPU] = { 0x67c, BIT(16) }, 1011 [RST_BUS_CE] = { 0x68c, BIT(16) }, 1012 [RST_BUS_VE] = { 0x69c, BIT(16) }, 1013 [RST_BUS_DMA] = { 0x70c, BIT(16) }, 1014 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) }, 1015 [RST_BUS_DBG] = { 0x78c, BIT(16) }, 1016 [RST_BUS_PSI] = { 0x79c, BIT(16) }, 1017 [RST_BUS_PWM] = { 0x7ac, BIT(16) }, 1018 [RST_BUS_IOMMU] = { 0x7bc, BIT(16) }, 1019 [RST_BUS_DRAM] = { 0x80c, BIT(16) }, 1020 [RST_BUS_NAND] = { 0x82c, BIT(16) }, 1021 [RST_BUS_MMC0] = { 0x84c, BIT(16) }, 1022 [RST_BUS_MMC1] = { 0x84c, BIT(17) }, 1023 [RST_BUS_MMC2] = { 0x84c, BIT(18) }, 1024 [RST_BUS_UART0] = { 0x90c, BIT(16) }, 1025 [RST_BUS_UART1] = { 0x90c, BIT(17) }, 1026 [RST_BUS_UART2] = { 0x90c, BIT(18) }, 1027 [RST_BUS_UART3] = { 0x90c, BIT(19) }, 1028 [RST_BUS_UART4] = { 0x90c, BIT(20) }, 1029 [RST_BUS_UART5] = { 0x90c, BIT(21) }, 1030 [RST_BUS_I2C0] = { 0x91c, BIT(16) }, 1031 [RST_BUS_I2C1] = { 0x91c, BIT(17) }, 1032 [RST_BUS_I2C2] = { 0x91c, BIT(18) }, 1033 [RST_BUS_I2C3] = { 0x91c, BIT(19) }, 1034 [RST_BUS_I2C4] = { 0x91c, BIT(20) }, 1035 [RST_BUS_SPI0] = { 0x96c, BIT(16) }, 1036 [RST_BUS_SPI1] = { 0x96c, BIT(17) }, 1037 [RST_BUS_EMAC0] = { 0x97c, BIT(16) }, 1038 [RST_BUS_EMAC1] = { 0x97c, BIT(17) }, 1039 [RST_BUS_TS] = { 0x9bc, BIT(16) }, 1040 [RST_BUS_GPADC] = { 0x9ec, BIT(16) }, 1041 [RST_BUS_THS] = { 0x9fc, BIT(16) }, 1042 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) }, 1043 [RST_BUS_DMIC] = { 0xa4c, BIT(16) }, 1044 [RST_BUS_AUDIO_CODEC] = { 0xa5c, BIT(16) }, 1045 [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) }, 1046 1047 [RST_USB_PHY0] = { 0xa70, BIT(30) }, 1048 [RST_USB_PHY1] = { 0xa74, BIT(30) }, 1049 [RST_USB_PHY2] = { 0xa78, BIT(30) }, 1050 [RST_USB_PHY3] = { 0xa7c, BIT(30) }, 1051 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) }, 1052 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) }, 1053 [RST_BUS_OHCI2] = { 0xa8c, BIT(18) }, 1054 [RST_BUS_OHCI3] = { 0xa8c, BIT(19) }, 1055 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) }, 1056 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) }, 1057 [RST_BUS_EHCI2] = { 0xa8c, BIT(22) }, 1058 [RST_BUS_EHCI3] = { 0xa8c, BIT(23) }, 1059 [RST_BUS_OTG] = { 0xa8c, BIT(24) }, 1060 [RST_BUS_KEYADC] = { 0xa9c, BIT(16) }, 1061 1062 [RST_BUS_HDMI] = { 0xb1c, BIT(16) }, 1063 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) }, 1064 [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) }, 1065 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) }, 1066 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) }, 1067 [RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) }, 1068 [RST_BUS_TVE0] = { 0xbbc, BIT(17) }, 1069 [RST_BUS_HDCP] = { 0xc4c, BIT(16) }, 1070 }; 1071 1072 static const struct sunxi_ccu_desc sun50i_h616_ccu_desc = { 1073 .ccu_clks = sun50i_h616_ccu_clks, 1074 .num_ccu_clks = ARRAY_SIZE(sun50i_h616_ccu_clks), 1075 1076 .hw_clks = &sun50i_h616_hw_clks, 1077 1078 .resets = sun50i_h616_ccu_resets, 1079 .num_resets = ARRAY_SIZE(sun50i_h616_ccu_resets), 1080 }; 1081 1082 static const u32 pll_regs[] = { 1083 SUN50I_H616_PLL_CPUX_REG, 1084 SUN50I_H616_PLL_DDR0_REG, 1085 SUN50I_H616_PLL_DDR1_REG, 1086 SUN50I_H616_PLL_PERIPH0_REG, 1087 SUN50I_H616_PLL_PERIPH1_REG, 1088 SUN50I_H616_PLL_GPU_REG, 1089 SUN50I_H616_PLL_VIDEO0_REG, 1090 SUN50I_H616_PLL_VIDEO1_REG, 1091 SUN50I_H616_PLL_VIDEO2_REG, 1092 SUN50I_H616_PLL_VE_REG, 1093 SUN50I_H616_PLL_DE_REG, 1094 SUN50I_H616_PLL_AUDIO_REG, 1095 }; 1096 1097 static const u32 pll_video_regs[] = { 1098 SUN50I_H616_PLL_VIDEO0_REG, 1099 SUN50I_H616_PLL_VIDEO1_REG, 1100 SUN50I_H616_PLL_VIDEO2_REG, 1101 }; 1102 1103 static const u32 usb2_clk_regs[] = { 1104 SUN50I_H616_USB0_CLK_REG, 1105 SUN50I_H616_USB1_CLK_REG, 1106 SUN50I_H616_USB2_CLK_REG, 1107 SUN50I_H616_USB3_CLK_REG, 1108 }; 1109 1110 static int sun50i_h616_ccu_probe(struct platform_device *pdev) 1111 { 1112 void __iomem *reg; 1113 u32 val; 1114 int i; 1115 1116 reg = devm_platform_ioremap_resource(pdev, 0); 1117 if (IS_ERR(reg)) 1118 return PTR_ERR(reg); 1119 1120 /* Enable the lock bits and the output enable bits on all PLLs */ 1121 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { 1122 val = readl(reg + pll_regs[i]); 1123 val |= BIT(29) | BIT(27); 1124 writel(val, reg + pll_regs[i]); 1125 } 1126 1127 /* 1128 * Force the output divider of video PLLs to 0. 1129 * 1130 * See the comment before pll-video0 definition for the reason. 1131 */ 1132 for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) { 1133 val = readl(reg + pll_video_regs[i]); 1134 val &= ~BIT(0); 1135 writel(val, reg + pll_video_regs[i]); 1136 } 1137 1138 /* 1139 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz) 1140 * 1141 * This clock mux is still mysterious, and the code just enforces 1142 * it to have a valid clock parent. 1143 */ 1144 for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) { 1145 val = readl(reg + usb2_clk_regs[i]); 1146 val &= ~GENMASK(25, 24); 1147 writel(val, reg + usb2_clk_regs[i]); 1148 } 1149 1150 /* 1151 * Set the output-divider for the pll-audio clocks (M0) to 2 and the 1152 * input divider (M1) to 1 as recommended by the manual when using 1153 * SDM. 1154 */ 1155 val = readl(reg + SUN50I_H616_PLL_AUDIO_REG); 1156 val &= ~BIT(1); 1157 val |= BIT(0); 1158 writel(val, reg + SUN50I_H616_PLL_AUDIO_REG); 1159 1160 /* 1161 * First clock parent (osc32K) is unusable for CEC. But since there 1162 * is no good way to force parent switch (both run with same frequency), 1163 * just set second clock parent here. 1164 */ 1165 val = readl(reg + SUN50I_H616_HDMI_CEC_CLK_REG); 1166 val |= BIT(24); 1167 writel(val, reg + SUN50I_H616_HDMI_CEC_CLK_REG); 1168 1169 return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h616_ccu_desc); 1170 } 1171 1172 static const struct of_device_id sun50i_h616_ccu_ids[] = { 1173 { .compatible = "allwinner,sun50i-h616-ccu" }, 1174 { } 1175 }; 1176 MODULE_DEVICE_TABLE(of, sun50i_h616_ccu_ids); 1177 1178 static struct platform_driver sun50i_h616_ccu_driver = { 1179 .probe = sun50i_h616_ccu_probe, 1180 .driver = { 1181 .name = "sun50i-h616-ccu", 1182 .suppress_bind_attrs = true, 1183 .of_match_table = sun50i_h616_ccu_ids, 1184 }, 1185 }; 1186 module_platform_driver(sun50i_h616_ccu_driver); 1187 1188 MODULE_IMPORT_NS(SUNXI_CCU); 1189 MODULE_DESCRIPTION("Support for the Allwinner H616 CCU"); 1190 MODULE_LICENSE("GPL"); 1191