1 /* 2 * Copyright (c) 2016 Maxime Ripard. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 18 #include "ccu_common.h" 19 #include "ccu_reset.h" 20 21 #include "ccu_div.h" 22 #include "ccu_gate.h" 23 #include "ccu_mp.h" 24 #include "ccu_mult.h" 25 #include "ccu_nk.h" 26 #include "ccu_nkm.h" 27 #include "ccu_nkmp.h" 28 #include "ccu_nm.h" 29 #include "ccu_phase.h" 30 31 #include "ccu-sun50i-a64.h" 32 33 static struct ccu_nkmp pll_cpux_clk = { 34 .enable = BIT(31), 35 .lock = BIT(28), 36 .n = _SUNXI_CCU_MULT(8, 5), 37 .k = _SUNXI_CCU_MULT(4, 2), 38 .m = _SUNXI_CCU_DIV(0, 2), 39 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), 40 .common = { 41 .reg = 0x000, 42 .hw.init = CLK_HW_INIT("pll-cpux", 43 "osc24M", 44 &ccu_nkmp_ops, 45 CLK_SET_RATE_UNGATE), 46 }, 47 }; 48 49 /* 50 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 51 * the base (2x, 4x and 8x), and one variable divider (the one true 52 * pll audio). 53 * 54 * We don't have any need for the variable divider for now, so we just 55 * hardcode it to match with the clock names 56 */ 57 #define SUN50I_A64_PLL_AUDIO_REG 0x008 58 59 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 60 "osc24M", 0x008, 61 8, 7, /* N */ 62 0, 5, /* M */ 63 BIT(31), /* gate */ 64 BIT(28), /* lock */ 65 CLK_SET_RATE_UNGATE); 66 67 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", 68 "osc24M", 0x010, 69 8, 7, /* N */ 70 0, 4, /* M */ 71 BIT(24), /* frac enable */ 72 BIT(25), /* frac select */ 73 270000000, /* frac rate 0 */ 74 297000000, /* frac rate 1 */ 75 BIT(31), /* gate */ 76 BIT(28), /* lock */ 77 CLK_SET_RATE_UNGATE); 78 79 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 80 "osc24M", 0x018, 81 8, 7, /* N */ 82 0, 4, /* M */ 83 BIT(24), /* frac enable */ 84 BIT(25), /* frac select */ 85 270000000, /* frac rate 0 */ 86 297000000, /* frac rate 1 */ 87 BIT(31), /* gate */ 88 BIT(28), /* lock */ 89 CLK_SET_RATE_UNGATE); 90 91 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", 92 "osc24M", 0x020, 93 8, 5, /* N */ 94 4, 2, /* K */ 95 0, 2, /* M */ 96 BIT(31), /* gate */ 97 BIT(28), /* lock */ 98 CLK_SET_RATE_UNGATE); 99 100 static struct ccu_nk pll_periph0_clk = { 101 .enable = BIT(31), 102 .lock = BIT(28), 103 .n = _SUNXI_CCU_MULT(8, 5), 104 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 105 .fixed_post_div = 2, 106 .common = { 107 .reg = 0x028, 108 .features = CCU_FEATURE_FIXED_POSTDIV, 109 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 110 &ccu_nk_ops, CLK_SET_RATE_UNGATE), 111 }, 112 }; 113 114 static struct ccu_nk pll_periph1_clk = { 115 .enable = BIT(31), 116 .lock = BIT(28), 117 .n = _SUNXI_CCU_MULT(8, 5), 118 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 119 .fixed_post_div = 2, 120 .common = { 121 .reg = 0x02c, 122 .features = CCU_FEATURE_FIXED_POSTDIV, 123 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 124 &ccu_nk_ops, CLK_SET_RATE_UNGATE), 125 }, 126 }; 127 128 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", 129 "osc24M", 0x030, 130 8, 7, /* N */ 131 0, 4, /* M */ 132 BIT(24), /* frac enable */ 133 BIT(25), /* frac select */ 134 270000000, /* frac rate 0 */ 135 297000000, /* frac rate 1 */ 136 BIT(31), /* gate */ 137 BIT(28), /* lock */ 138 CLK_SET_RATE_UNGATE); 139 140 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 141 "osc24M", 0x038, 142 8, 7, /* N */ 143 0, 4, /* M */ 144 BIT(24), /* frac enable */ 145 BIT(25), /* frac select */ 146 270000000, /* frac rate 0 */ 147 297000000, /* frac rate 1 */ 148 BIT(31), /* gate */ 149 BIT(28), /* lock */ 150 CLK_SET_RATE_UNGATE); 151 152 /* 153 * The output function can be changed to something more complex that 154 * we do not handle yet. 155 * 156 * Hardcode the mode so that we don't fall in that case. 157 */ 158 #define SUN50I_A64_PLL_MIPI_REG 0x040 159 160 static struct ccu_nkm pll_mipi_clk = { 161 .enable = BIT(31), 162 .lock = BIT(28), 163 .n = _SUNXI_CCU_MULT(8, 4), 164 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 165 .m = _SUNXI_CCU_DIV(0, 4), 166 .common = { 167 .reg = 0x040, 168 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0", 169 &ccu_nkm_ops, CLK_SET_RATE_UNGATE), 170 }, 171 }; 172 173 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", 174 "osc24M", 0x044, 175 8, 7, /* N */ 176 0, 4, /* M */ 177 BIT(24), /* frac enable */ 178 BIT(25), /* frac select */ 179 270000000, /* frac rate 0 */ 180 297000000, /* frac rate 1 */ 181 BIT(31), /* gate */ 182 BIT(28), /* lock */ 183 CLK_SET_RATE_UNGATE); 184 185 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 186 "osc24M", 0x048, 187 8, 7, /* N */ 188 0, 4, /* M */ 189 BIT(24), /* frac enable */ 190 BIT(25), /* frac select */ 191 270000000, /* frac rate 0 */ 192 297000000, /* frac rate 1 */ 193 BIT(31), /* gate */ 194 BIT(28), /* lock */ 195 CLK_SET_RATE_UNGATE); 196 197 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", 198 "osc24M", 0x04c, 199 8, 7, /* N */ 200 0, 2, /* M */ 201 BIT(31), /* gate */ 202 BIT(28), /* lock */ 203 CLK_SET_RATE_UNGATE); 204 205 static const char * const cpux_parents[] = { "osc32k", "osc24M", 206 "pll-cpux", "pll-cpux" }; 207 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 208 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 209 210 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); 211 212 static const char * const ahb1_parents[] = { "osc32k", "osc24M", 213 "axi", "pll-periph0" }; 214 static struct ccu_div ahb1_clk = { 215 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 216 217 .mux = { 218 .shift = 12, 219 .width = 2, 220 221 .variable_prediv = { 222 .index = 3, 223 .shift = 6, 224 .width = 2, 225 }, 226 }, 227 228 .common = { 229 .reg = 0x054, 230 .features = CCU_FEATURE_VARIABLE_PREDIV, 231 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 232 ahb1_parents, 233 &ccu_div_ops, 234 0), 235 }, 236 }; 237 238 static struct clk_div_table apb1_div_table[] = { 239 { .val = 0, .div = 2 }, 240 { .val = 1, .div = 2 }, 241 { .val = 2, .div = 4 }, 242 { .val = 3, .div = 8 }, 243 { /* Sentinel */ }, 244 }; 245 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 246 0x054, 8, 2, apb1_div_table, 0); 247 248 static const char * const apb2_parents[] = { "osc32k", "osc24M", 249 "pll-periph0-2x", 250 "pll-periph0-2x" }; 251 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 252 0, 5, /* M */ 253 16, 2, /* P */ 254 24, 2, /* mux */ 255 0); 256 257 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" }; 258 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { 259 { .index = 1, .div = 2 }, 260 }; 261 static struct ccu_mux ahb2_clk = { 262 .mux = { 263 .shift = 0, 264 .width = 1, 265 .fixed_predivs = ahb2_fixed_predivs, 266 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), 267 }, 268 269 .common = { 270 .reg = 0x05c, 271 .features = CCU_FEATURE_FIXED_PREDIV, 272 .hw.init = CLK_HW_INIT_PARENTS("ahb2", 273 ahb2_parents, 274 &ccu_mux_ops, 275 0), 276 }, 277 }; 278 279 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 280 0x060, BIT(1), 0); 281 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 282 0x060, BIT(5), 0); 283 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 284 0x060, BIT(6), 0); 285 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 286 0x060, BIT(8), 0); 287 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 288 0x060, BIT(9), 0); 289 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 290 0x060, BIT(10), 0); 291 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 292 0x060, BIT(13), 0); 293 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 294 0x060, BIT(14), 0); 295 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 296 0x060, BIT(17), 0); 297 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", 298 0x060, BIT(18), 0); 299 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 300 0x060, BIT(19), 0); 301 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 302 0x060, BIT(20), 0); 303 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 304 0x060, BIT(21), 0); 305 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 306 0x060, BIT(23), 0); 307 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 308 0x060, BIT(24), 0); 309 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", 310 0x060, BIT(25), 0); 311 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 312 0x060, BIT(28), 0); 313 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2", 314 0x060, BIT(29), 0); 315 316 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 317 0x064, BIT(0), 0); 318 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 319 0x064, BIT(3), 0); 320 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", 321 0x064, BIT(4), 0); 322 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", 323 0x064, BIT(5), 0); 324 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 325 0x064, BIT(8), 0); 326 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", 327 0x064, BIT(11), 0); 328 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 329 0x064, BIT(12), 0); 330 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 331 0x064, BIT(20), 0); 332 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 333 0x064, BIT(21), 0); 334 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 335 0x064, BIT(22), 0); 336 337 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 338 0x068, BIT(0), 0); 339 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 340 0x068, BIT(1), 0); 341 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 342 0x068, BIT(5), 0); 343 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 344 0x068, BIT(8), 0); 345 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 346 0x068, BIT(12), 0); 347 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 348 0x068, BIT(13), 0); 349 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 350 0x068, BIT(14), 0); 351 352 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 353 0x06c, BIT(0), 0); 354 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 355 0x06c, BIT(1), 0); 356 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 357 0x06c, BIT(2), 0); 358 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 359 0x06c, BIT(5), 0); 360 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 361 0x06c, BIT(16), 0); 362 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 363 0x06c, BIT(17), 0); 364 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 365 0x06c, BIT(18), 0); 366 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 367 0x06c, BIT(19), 0); 368 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 369 0x06c, BIT(20), 0); 370 371 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 372 0x070, BIT(7), 0); 373 374 static struct clk_div_table ths_div_table[] = { 375 { .val = 0, .div = 1 }, 376 { .val = 1, .div = 2 }, 377 { .val = 2, .div = 4 }, 378 { .val = 3, .div = 6 }, 379 }; 380 static const char * const ths_parents[] = { "osc24M" }; 381 static struct ccu_div ths_clk = { 382 .enable = BIT(31), 383 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table), 384 .mux = _SUNXI_CCU_MUX(24, 2), 385 .common = { 386 .reg = 0x074, 387 .hw.init = CLK_HW_INIT_PARENTS("ths", 388 ths_parents, 389 &ccu_div_ops, 390 0), 391 }, 392 }; 393 394 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", 395 "pll-periph1" }; 396 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 397 0, 4, /* M */ 398 16, 2, /* P */ 399 24, 2, /* mux */ 400 BIT(31), /* gate */ 401 0); 402 403 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", 404 "pll-periph1-2x" }; 405 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088, 406 0, 4, /* M */ 407 16, 2, /* P */ 408 24, 2, /* mux */ 409 BIT(31), /* gate */ 410 0); 411 412 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c, 413 0, 4, /* M */ 414 16, 2, /* P */ 415 24, 2, /* mux */ 416 BIT(31), /* gate */ 417 0); 418 419 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090, 420 0, 4, /* M */ 421 16, 2, /* P */ 422 24, 2, /* mux */ 423 BIT(31), /* gate */ 424 0); 425 426 static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; 427 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, 428 0, 4, /* M */ 429 16, 2, /* P */ 430 24, 4, /* mux */ 431 BIT(31), /* gate */ 432 0); 433 434 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c, 435 0, 4, /* M */ 436 16, 2, /* P */ 437 24, 2, /* mux */ 438 BIT(31), /* gate */ 439 0); 440 441 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 442 0, 4, /* M */ 443 16, 2, /* P */ 444 24, 2, /* mux */ 445 BIT(31), /* gate */ 446 0); 447 448 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 449 0, 4, /* M */ 450 16, 2, /* P */ 451 24, 2, /* mux */ 452 BIT(31), /* gate */ 453 0); 454 455 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", 456 "pll-audio-2x", "pll-audio" }; 457 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 458 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 459 460 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 461 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 462 463 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, 464 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 465 466 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", 467 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 468 469 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 470 0x0cc, BIT(8), 0); 471 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 472 0x0cc, BIT(9), 0); 473 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 474 0x0cc, BIT(10), 0); 475 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 476 0x0cc, BIT(11), 0); 477 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 478 0x0cc, BIT(16), 0); 479 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", 480 0x0cc, BIT(17), 0); 481 482 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; 483 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 484 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); 485 486 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 487 0x100, BIT(0), 0); 488 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 489 0x100, BIT(1), 0); 490 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", 491 0x100, BIT(2), 0); 492 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 493 0x100, BIT(3), 0); 494 495 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; 496 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 497 0x104, 0, 4, 24, 3, BIT(31), 0); 498 499 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; 500 static const u8 tcon0_table[] = { 0, 2, }; 501 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, 502 tcon0_table, 0x118, 24, 3, BIT(31), 503 CLK_SET_RATE_PARENT); 504 505 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; 506 static const u8 tcon1_table[] = { 0, 2, }; 507 static struct ccu_div tcon1_clk = { 508 .enable = BIT(31), 509 .div = _SUNXI_CCU_DIV(0, 4), 510 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table), 511 .common = { 512 .reg = 0x11c, 513 .hw.init = CLK_HW_INIT_PARENTS("tcon1", 514 tcon1_parents, 515 &ccu_div_ops, 516 CLK_SET_RATE_PARENT), 517 }, 518 }; 519 520 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; 521 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, 522 0x124, 0, 4, 24, 3, BIT(31), 0); 523 524 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 525 0x130, BIT(31), 0); 526 527 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; 528 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 529 0x134, 16, 4, 24, 3, BIT(31), 0); 530 531 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" }; 532 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 533 0x134, 0, 5, 8, 3, BIT(15), 0); 534 535 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 536 0x13c, 16, 3, BIT(31), 0); 537 538 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 539 0x140, BIT(31), CLK_SET_RATE_PARENT); 540 541 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 542 0x140, BIT(30), CLK_SET_RATE_PARENT); 543 544 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 545 0x144, BIT(31), 0); 546 547 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; 548 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 549 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); 550 551 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 552 0x154, BIT(31), 0); 553 554 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 555 "pll-ddr0", "pll-ddr1" }; 556 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 557 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 558 559 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; 560 static const u8 dsi_dphy_table[] = { 0, 2, }; 561 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", 562 dsi_dphy_parents, dsi_dphy_table, 563 0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT); 564 565 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 566 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); 567 568 /* Fixed Factor clocks */ 569 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0); 570 571 /* We hardcode the divider to 4 for now */ 572 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 573 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 574 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 575 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 576 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 577 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 578 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 579 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 580 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", 581 "pll-periph0", 1, 2, 0); 582 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", 583 "pll-periph1", 1, 2, 0); 584 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", 585 "pll-video0", 1, 2, CLK_SET_RATE_PARENT); 586 587 static struct ccu_common *sun50i_a64_ccu_clks[] = { 588 &pll_cpux_clk.common, 589 &pll_audio_base_clk.common, 590 &pll_video0_clk.common, 591 &pll_ve_clk.common, 592 &pll_ddr0_clk.common, 593 &pll_periph0_clk.common, 594 &pll_periph1_clk.common, 595 &pll_video1_clk.common, 596 &pll_gpu_clk.common, 597 &pll_mipi_clk.common, 598 &pll_hsic_clk.common, 599 &pll_de_clk.common, 600 &pll_ddr1_clk.common, 601 &cpux_clk.common, 602 &axi_clk.common, 603 &ahb1_clk.common, 604 &apb1_clk.common, 605 &apb2_clk.common, 606 &ahb2_clk.common, 607 &bus_mipi_dsi_clk.common, 608 &bus_ce_clk.common, 609 &bus_dma_clk.common, 610 &bus_mmc0_clk.common, 611 &bus_mmc1_clk.common, 612 &bus_mmc2_clk.common, 613 &bus_nand_clk.common, 614 &bus_dram_clk.common, 615 &bus_emac_clk.common, 616 &bus_ts_clk.common, 617 &bus_hstimer_clk.common, 618 &bus_spi0_clk.common, 619 &bus_spi1_clk.common, 620 &bus_otg_clk.common, 621 &bus_ehci0_clk.common, 622 &bus_ehci1_clk.common, 623 &bus_ohci0_clk.common, 624 &bus_ohci1_clk.common, 625 &bus_ve_clk.common, 626 &bus_tcon0_clk.common, 627 &bus_tcon1_clk.common, 628 &bus_deinterlace_clk.common, 629 &bus_csi_clk.common, 630 &bus_hdmi_clk.common, 631 &bus_de_clk.common, 632 &bus_gpu_clk.common, 633 &bus_msgbox_clk.common, 634 &bus_spinlock_clk.common, 635 &bus_codec_clk.common, 636 &bus_spdif_clk.common, 637 &bus_pio_clk.common, 638 &bus_ths_clk.common, 639 &bus_i2s0_clk.common, 640 &bus_i2s1_clk.common, 641 &bus_i2s2_clk.common, 642 &bus_i2c0_clk.common, 643 &bus_i2c1_clk.common, 644 &bus_i2c2_clk.common, 645 &bus_scr_clk.common, 646 &bus_uart0_clk.common, 647 &bus_uart1_clk.common, 648 &bus_uart2_clk.common, 649 &bus_uart3_clk.common, 650 &bus_uart4_clk.common, 651 &bus_dbg_clk.common, 652 &ths_clk.common, 653 &nand_clk.common, 654 &mmc0_clk.common, 655 &mmc1_clk.common, 656 &mmc2_clk.common, 657 &ts_clk.common, 658 &ce_clk.common, 659 &spi0_clk.common, 660 &spi1_clk.common, 661 &i2s0_clk.common, 662 &i2s1_clk.common, 663 &i2s2_clk.common, 664 &spdif_clk.common, 665 &usb_phy0_clk.common, 666 &usb_phy1_clk.common, 667 &usb_hsic_clk.common, 668 &usb_hsic_12m_clk.common, 669 &usb_ohci0_clk.common, 670 &usb_ohci1_clk.common, 671 &dram_clk.common, 672 &dram_ve_clk.common, 673 &dram_csi_clk.common, 674 &dram_deinterlace_clk.common, 675 &dram_ts_clk.common, 676 &de_clk.common, 677 &tcon0_clk.common, 678 &tcon1_clk.common, 679 &deinterlace_clk.common, 680 &csi_misc_clk.common, 681 &csi_sclk_clk.common, 682 &csi_mclk_clk.common, 683 &ve_clk.common, 684 &ac_dig_clk.common, 685 &ac_dig_4x_clk.common, 686 &avs_clk.common, 687 &hdmi_clk.common, 688 &hdmi_ddc_clk.common, 689 &mbus_clk.common, 690 &dsi_dphy_clk.common, 691 &gpu_clk.common, 692 }; 693 694 static struct clk_hw_onecell_data sun50i_a64_hw_clks = { 695 .hws = { 696 [CLK_OSC_12M] = &osc12M_clk.hw, 697 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 698 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 699 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 700 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 701 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 702 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 703 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 704 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, 705 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 706 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 707 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 708 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 709 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 710 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 711 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 712 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 713 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, 714 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, 715 [CLK_PLL_DE] = &pll_de_clk.common.hw, 716 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 717 [CLK_CPUX] = &cpux_clk.common.hw, 718 [CLK_AXI] = &axi_clk.common.hw, 719 [CLK_AHB1] = &ahb1_clk.common.hw, 720 [CLK_APB1] = &apb1_clk.common.hw, 721 [CLK_APB2] = &apb2_clk.common.hw, 722 [CLK_AHB2] = &ahb2_clk.common.hw, 723 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 724 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 725 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 726 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 727 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 728 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 729 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 730 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 731 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 732 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 733 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 734 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 735 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 736 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 737 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 738 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 739 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 740 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, 741 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 742 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, 743 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, 744 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 745 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 746 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 747 [CLK_BUS_DE] = &bus_de_clk.common.hw, 748 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 749 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 750 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 751 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 752 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 753 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 754 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 755 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 756 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 757 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, 758 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 759 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 760 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 761 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 762 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 763 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 764 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 765 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 766 [CLK_BUS_SCR] = &bus_scr_clk.common.hw, 767 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 768 [CLK_THS] = &ths_clk.common.hw, 769 [CLK_NAND] = &nand_clk.common.hw, 770 [CLK_MMC0] = &mmc0_clk.common.hw, 771 [CLK_MMC1] = &mmc1_clk.common.hw, 772 [CLK_MMC2] = &mmc2_clk.common.hw, 773 [CLK_TS] = &ts_clk.common.hw, 774 [CLK_CE] = &ce_clk.common.hw, 775 [CLK_SPI0] = &spi0_clk.common.hw, 776 [CLK_SPI1] = &spi1_clk.common.hw, 777 [CLK_I2S0] = &i2s0_clk.common.hw, 778 [CLK_I2S1] = &i2s1_clk.common.hw, 779 [CLK_I2S2] = &i2s2_clk.common.hw, 780 [CLK_SPDIF] = &spdif_clk.common.hw, 781 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 782 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 783 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 784 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, 785 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 786 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 787 [CLK_DRAM] = &dram_clk.common.hw, 788 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 789 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 790 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, 791 [CLK_DRAM_TS] = &dram_ts_clk.common.hw, 792 [CLK_DE] = &de_clk.common.hw, 793 [CLK_TCON0] = &tcon0_clk.common.hw, 794 [CLK_TCON1] = &tcon1_clk.common.hw, 795 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 796 [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 797 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 798 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, 799 [CLK_VE] = &ve_clk.common.hw, 800 [CLK_AC_DIG] = &ac_dig_clk.common.hw, 801 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, 802 [CLK_AVS] = &avs_clk.common.hw, 803 [CLK_HDMI] = &hdmi_clk.common.hw, 804 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, 805 [CLK_MBUS] = &mbus_clk.common.hw, 806 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, 807 [CLK_GPU] = &gpu_clk.common.hw, 808 }, 809 .num = CLK_NUMBER, 810 }; 811 812 static struct ccu_reset_map sun50i_a64_ccu_resets[] = { 813 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 814 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 815 [RST_USB_HSIC] = { 0x0cc, BIT(2) }, 816 817 [RST_DRAM] = { 0x0f4, BIT(31) }, 818 [RST_MBUS] = { 0x0fc, BIT(31) }, 819 820 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, 821 [RST_BUS_CE] = { 0x2c0, BIT(5) }, 822 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 823 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 824 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 825 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 826 [RST_BUS_NAND] = { 0x2c0, BIT(13) }, 827 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 828 [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 829 [RST_BUS_TS] = { 0x2c0, BIT(18) }, 830 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 831 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 832 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 833 [RST_BUS_OTG] = { 0x2c0, BIT(23) }, 834 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, 835 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, 836 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, 837 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, 838 839 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 840 [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, 841 [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, 842 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, 843 [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 844 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, 845 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, 846 [RST_BUS_DE] = { 0x2c4, BIT(12) }, 847 [RST_BUS_GPU] = { 0x2c4, BIT(20) }, 848 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, 849 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, 850 [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 851 852 [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, 853 854 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 855 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, 856 [RST_BUS_THS] = { 0x2d0, BIT(8) }, 857 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 858 [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, 859 [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, 860 861 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 862 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 863 [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, 864 [RST_BUS_SCR] = { 0x2d8, BIT(5) }, 865 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 866 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 867 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 868 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 869 [RST_BUS_UART4] = { 0x2d8, BIT(20) }, 870 }; 871 872 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { 873 .ccu_clks = sun50i_a64_ccu_clks, 874 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), 875 876 .hw_clks = &sun50i_a64_hw_clks, 877 878 .resets = sun50i_a64_ccu_resets, 879 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), 880 }; 881 882 static int sun50i_a64_ccu_probe(struct platform_device *pdev) 883 { 884 struct resource *res; 885 void __iomem *reg; 886 u32 val; 887 888 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 889 reg = devm_ioremap_resource(&pdev->dev, res); 890 if (IS_ERR(reg)) 891 return PTR_ERR(reg); 892 893 /* Force the PLL-Audio-1x divider to 4 */ 894 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); 895 val &= ~GENMASK(19, 16); 896 writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); 897 898 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); 899 900 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); 901 } 902 903 static const struct of_device_id sun50i_a64_ccu_ids[] = { 904 { .compatible = "allwinner,sun50i-a64-ccu" }, 905 { } 906 }; 907 908 static struct platform_driver sun50i_a64_ccu_driver = { 909 .probe = sun50i_a64_ccu_probe, 910 .driver = { 911 .name = "sun50i-a64-ccu", 912 .of_match_table = sun50i_a64_ccu_ids, 913 }, 914 }; 915 builtin_platform_driver(sun50i_a64_ccu_driver); 916