1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2017 Priit Laes 4 * 5 * Priit Laes <plaes@plaes.org> 6 */ 7 8 #ifndef _CCU_SUN4I_A10_H_ 9 #define _CCU_SUN4I_A10_H_ 10 11 #include <dt-bindings/clock/sun4i-a10-ccu.h> 12 #include <dt-bindings/clock/sun7i-a20-ccu.h> 13 #include <dt-bindings/reset/sun4i-a10-ccu.h> 14 15 /* The HOSC is exported */ 16 #define CLK_PLL_CORE 2 17 #define CLK_PLL_AUDIO_BASE 3 18 #define CLK_PLL_AUDIO 4 19 #define CLK_PLL_AUDIO_2X 5 20 #define CLK_PLL_AUDIO_4X 6 21 #define CLK_PLL_AUDIO_8X 7 22 #define CLK_PLL_VIDEO0 8 23 /* The PLL_VIDEO0_2X clock is exported */ 24 #define CLK_PLL_VE 10 25 #define CLK_PLL_DDR_BASE 11 26 #define CLK_PLL_DDR 12 27 #define CLK_PLL_DDR_OTHER 13 28 #define CLK_PLL_PERIPH_BASE 14 29 #define CLK_PLL_PERIPH 15 30 #define CLK_PLL_PERIPH_SATA 16 31 #define CLK_PLL_VIDEO1 17 32 /* The PLL_VIDEO1_2X clock is exported */ 33 #define CLK_PLL_GPU 19 34 35 /* The CPU clock is exported */ 36 #define CLK_AXI 21 37 #define CLK_AXI_DRAM 22 38 #define CLK_AHB 23 39 #define CLK_APB0 24 40 #define CLK_APB1 25 41 42 /* AHB gates are exported (23..68) */ 43 /* APB0 gates are exported (69..78) */ 44 /* APB1 gates are exported (79..95) */ 45 /* IP module clocks are exported (96..128) */ 46 /* DRAM gates are exported (129..142)*/ 47 /* Media (display engine clocks & etc) are exported (143..169) */ 48 49 #define CLK_NUMBER_SUN4I (CLK_MBUS + 1) 50 #define CLK_NUMBER_SUN7I (CLK_OUT_B + 1) 51 52 #endif /* _CCU_SUN4I_A10_H_ */ 53