1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. 5 */ 6 7 #include <linux/bus/stm32_firewall_device.h> 8 #include <linux/clk-provider.h> 9 #include <linux/io.h> 10 #include <linux/platform_device.h> 11 12 #include "clk-stm32-core.h" 13 #include "reset-stm32.h" 14 #include "stm32mp21_rcc.h" 15 16 #include <dt-bindings/clock/st,stm32mp21-rcc.h> 17 #include <dt-bindings/reset/st,stm32mp21-rcc.h> 18 19 /* Max clock binding value */ 20 #define STM32MP21_LAST_CLK CK_SCMI_KER_ETR 21 22 /* Clock security definition */ 23 #define SECF_NONE -1 24 25 #define RCC_REG_SIZE 32 26 #define RCC_SECCFGR(x) (((x) / RCC_REG_SIZE) * 0x4 + RCC_SECCFGR0) 27 #define RCC_CIDCFGR(x) ((x) * 0x8 + RCC_R0CIDCFGR) 28 #define RCC_SEMCR(x) ((x) * 0x8 + RCC_R0SEMCR) 29 #define RCC_CID1 1 30 31 /* Register: RIFSC_CIDCFGR */ 32 #define RCC_CIDCFGR_CFEN BIT(0) 33 #define RCC_CIDCFGR_SEM_EN BIT(1) 34 #define RCC_CIDCFGR_SEMWLC1_EN BIT(17) 35 #define RCC_CIDCFGR_SCID_MASK GENMASK(6, 4) 36 37 /* Register: RIFSC_SEMCR */ 38 #define RCC_SEMCR_SEMCID_MASK GENMASK(6, 4) 39 40 #define MP21_RIF_RCC_MCO1 108 41 #define MP21_RIF_RCC_MCO2 109 42 43 #define SEC_RIFSC_FLAG BIT(31) 44 #define SEC_RIFSC(_id) ((_id) | SEC_RIFSC_FLAG) 45 46 enum { 47 HSE, 48 HSI, 49 MSI, 50 LSE, 51 LSI, 52 HSE_DIV2, 53 ICN_HS_MCU, 54 ICN_LS_MCU, 55 ICN_SDMMC, 56 ICN_DDR, 57 ICN_DISPLAY, 58 ICN_HSL, 59 ICN_NIC, 60 FLEXGEN_07, 61 FLEXGEN_08, 62 FLEXGEN_09, 63 FLEXGEN_10, 64 FLEXGEN_11, 65 FLEXGEN_12, 66 FLEXGEN_13, 67 FLEXGEN_14, 68 FLEXGEN_16, 69 FLEXGEN_17, 70 FLEXGEN_18, 71 FLEXGEN_19, 72 FLEXGEN_20, 73 FLEXGEN_21, 74 FLEXGEN_22, 75 FLEXGEN_23, 76 FLEXGEN_24, 77 FLEXGEN_25, 78 FLEXGEN_26, 79 FLEXGEN_27, 80 FLEXGEN_29, 81 FLEXGEN_30, 82 FLEXGEN_31, 83 FLEXGEN_33, 84 FLEXGEN_36, 85 FLEXGEN_37, 86 FLEXGEN_38, 87 FLEXGEN_39, 88 FLEXGEN_40, 89 FLEXGEN_41, 90 FLEXGEN_42, 91 FLEXGEN_43, 92 FLEXGEN_44, 93 FLEXGEN_45, 94 FLEXGEN_46, 95 FLEXGEN_47, 96 FLEXGEN_48, 97 FLEXGEN_50, 98 FLEXGEN_51, 99 FLEXGEN_52, 100 FLEXGEN_53, 101 FLEXGEN_54, 102 FLEXGEN_55, 103 FLEXGEN_56, 104 FLEXGEN_57, 105 FLEXGEN_58, 106 FLEXGEN_61, 107 FLEXGEN_62, 108 FLEXGEN_63, 109 ICN_APB1, 110 ICN_APB2, 111 ICN_APB3, 112 ICN_APB4, 113 ICN_APB5, 114 ICN_APBDBG, 115 TIMG1, 116 TIMG2, 117 }; 118 119 static const struct clk_parent_data adc1_src[] = { 120 { .index = FLEXGEN_46 }, 121 { .index = ICN_LS_MCU }, 122 }; 123 124 static const struct clk_parent_data adc2_src[] = { 125 { .index = FLEXGEN_47 }, 126 { .index = ICN_LS_MCU }, 127 { .index = FLEXGEN_46 }, 128 }; 129 130 static const struct clk_parent_data usb2phy1_src[] = { 131 { .index = FLEXGEN_57 }, 132 { .index = HSE_DIV2 }, 133 }; 134 135 static const struct clk_parent_data usb2phy2_src[] = { 136 { .index = FLEXGEN_58 }, 137 { .index = HSE_DIV2 }, 138 }; 139 140 static const struct clk_parent_data dts_src[] = { 141 { .index = HSI }, 142 { .index = HSE }, 143 { .index = MSI }, 144 }; 145 146 static const struct clk_parent_data mco1_src[] = { 147 { .index = FLEXGEN_61 }, 148 }; 149 150 static const struct clk_parent_data mco2_src[] = { 151 { .index = FLEXGEN_62 }, 152 }; 153 154 enum enum_mux_cfg { 155 MUX_ADC1, 156 MUX_ADC2, 157 MUX_DTS, 158 MUX_MCO1, 159 MUX_MCO2, 160 MUX_USB2PHY1, 161 MUX_USB2PHY2, 162 MUX_NB 163 }; 164 165 #define MUX_CFG(id, _offset, _shift, _width) \ 166 [id] = { \ 167 .offset = (_offset), \ 168 .shift = (_shift), \ 169 .width = (_width), \ 170 } 171 172 static const struct stm32_mux_cfg stm32mp21_muxes[MUX_NB] = { 173 MUX_CFG(MUX_ADC1, RCC_ADC1CFGR, 12, 1), 174 MUX_CFG(MUX_ADC2, RCC_ADC2CFGR, 12, 2), 175 MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2), 176 MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1), 177 MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1), 178 MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1), 179 MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1), 180 }; 181 182 enum enum_gate_cfg { 183 GATE_ADC1, 184 GATE_ADC2, 185 GATE_CRC, 186 GATE_CRYP1, 187 GATE_CRYP2, 188 GATE_CSI, 189 GATE_DCMIPP, 190 GATE_DCMIPSSI, 191 GATE_DDRPERFM, 192 GATE_DTS, 193 GATE_ETH1, 194 GATE_ETH1MAC, 195 GATE_ETH1RX, 196 GATE_ETH1STP, 197 GATE_ETH1TX, 198 GATE_ETH2, 199 GATE_ETH2MAC, 200 GATE_ETH2RX, 201 GATE_ETH2STP, 202 GATE_ETH2TX, 203 GATE_FDCAN, 204 GATE_HASH1, 205 GATE_HASH2, 206 GATE_HDP, 207 GATE_I2C1, 208 GATE_I2C2, 209 GATE_I2C3, 210 GATE_I3C1, 211 GATE_I3C2, 212 GATE_I3C3, 213 GATE_IWDG1, 214 GATE_IWDG2, 215 GATE_IWDG3, 216 GATE_IWDG4, 217 GATE_LPTIM1, 218 GATE_LPTIM2, 219 GATE_LPTIM3, 220 GATE_LPTIM4, 221 GATE_LPTIM5, 222 GATE_LPUART1, 223 GATE_LTDC, 224 GATE_MCO1, 225 GATE_MCO2, 226 GATE_MDF1, 227 GATE_OTG, 228 GATE_PKA, 229 GATE_RNG1, 230 GATE_RNG2, 231 GATE_SAES, 232 GATE_SAI1, 233 GATE_SAI2, 234 GATE_SAI3, 235 GATE_SAI4, 236 GATE_SDMMC1, 237 GATE_SDMMC2, 238 GATE_SDMMC3, 239 GATE_SERC, 240 GATE_SPDIFRX, 241 GATE_SPI1, 242 GATE_SPI2, 243 GATE_SPI3, 244 GATE_SPI4, 245 GATE_SPI5, 246 GATE_SPI6, 247 GATE_TIM1, 248 GATE_TIM10, 249 GATE_TIM11, 250 GATE_TIM12, 251 GATE_TIM13, 252 GATE_TIM14, 253 GATE_TIM15, 254 GATE_TIM16, 255 GATE_TIM17, 256 GATE_TIM2, 257 GATE_TIM3, 258 GATE_TIM4, 259 GATE_TIM5, 260 GATE_TIM6, 261 GATE_TIM7, 262 GATE_TIM8, 263 GATE_UART4, 264 GATE_UART5, 265 GATE_UART7, 266 GATE_USART1, 267 GATE_USART2, 268 GATE_USART3, 269 GATE_USART6, 270 GATE_USB2PHY1, 271 GATE_USB2PHY2, 272 GATE_USBH, 273 GATE_VREF, 274 GATE_WWDG1, 275 GATE_NB 276 }; 277 278 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr) \ 279 [id] = { \ 280 .offset = (_offset), \ 281 .bit_idx = (_bit_idx), \ 282 .set_clr = (_offset_clr), \ 283 } 284 285 static const struct stm32_gate_cfg stm32mp21_gates[GATE_NB] = { 286 GATE_CFG(GATE_ADC1, RCC_ADC1CFGR, 1, 0), 287 GATE_CFG(GATE_ADC2, RCC_ADC2CFGR, 1, 0), 288 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0), 289 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0), 290 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0), 291 GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0), 292 GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0), 293 GATE_CFG(GATE_DCMIPSSI, RCC_DCMIPSSICFGR, 1, 0), 294 GATE_CFG(GATE_DDRPERFM, RCC_DDRPERFMCFGR, 1, 0), 295 GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0), 296 GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0), 297 GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0), 298 GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0), 299 GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0), 300 GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0), 301 GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0), 302 GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0), 303 GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0), 304 GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0), 305 GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0), 306 GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0), 307 GATE_CFG(GATE_HASH1, RCC_HASH1CFGR, 1, 0), 308 GATE_CFG(GATE_HASH2, RCC_HASH2CFGR, 1, 0), 309 GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0), 310 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0), 311 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0), 312 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0), 313 GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0), 314 GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0), 315 GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0), 316 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0), 317 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0), 318 GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0), 319 GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0), 320 GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0), 321 GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0), 322 GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0), 323 GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0), 324 GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0), 325 GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0), 326 GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0), 327 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0), 328 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0), 329 GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0), 330 GATE_CFG(GATE_OTG, RCC_OTGCFGR, 1, 0), 331 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0), 332 GATE_CFG(GATE_RNG1, RCC_RNG1CFGR, 1, 0), 333 GATE_CFG(GATE_RNG2, RCC_RNG2CFGR, 1, 0), 334 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0), 335 GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0), 336 GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0), 337 GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0), 338 GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0), 339 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0), 340 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0), 341 GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0), 342 GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0), 343 GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0), 344 GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0), 345 GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0), 346 GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0), 347 GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0), 348 GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0), 349 GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0), 350 GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0), 351 GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0), 352 GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0), 353 GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0), 354 GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0), 355 GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0), 356 GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0), 357 GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0), 358 GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0), 359 GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0), 360 GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0), 361 GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0), 362 GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0), 363 GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0), 364 GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0), 365 GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0), 366 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0), 367 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0), 368 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0), 369 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0), 370 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0), 371 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0), 372 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), 373 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), 374 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), 375 GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0), 376 GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0), 377 GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0), 378 }; 379 380 #define CLK_HW_INIT_INDEX(_name, _parent, _ops, _flags) \ 381 (&(struct clk_init_data) { \ 382 .flags = _flags, \ 383 .name = _name, \ 384 .parent_data = (const struct clk_parent_data[]) { \ 385 { .index = _parent }, \ 386 }, \ 387 .num_parents = 1, \ 388 .ops = _ops, \ 389 }) 390 391 /* ADC */ 392 static struct clk_stm32_gate ck_icn_p_adc1 = { 393 .gate_id = GATE_ADC1, 394 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc1", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 395 }; 396 397 static struct clk_stm32_composite ck_ker_adc1 = { 398 .gate_id = GATE_ADC1, 399 .mux_id = MUX_ADC1, 400 .div_id = NO_STM32_DIV, 401 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc1", adc1_src, &clk_stm32_composite_ops, 0), 402 }; 403 404 static struct clk_stm32_gate ck_icn_p_adc2 = { 405 .gate_id = GATE_ADC2, 406 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_adc2", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 407 }; 408 409 static struct clk_stm32_composite ck_ker_adc2 = { 410 .gate_id = GATE_ADC2, 411 .mux_id = MUX_ADC2, 412 .div_id = NO_STM32_DIV, 413 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_adc2", adc2_src, &clk_stm32_composite_ops, 0), 414 }; 415 416 /* CSI-HOST */ 417 static struct clk_stm32_gate ck_icn_p_csi = { 418 .gate_id = GATE_CSI, 419 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_csi", ICN_APB4, &clk_stm32_gate_ops, 0), 420 }; 421 422 static struct clk_stm32_gate ck_ker_csi = { 423 .gate_id = GATE_CSI, 424 .hw.init = CLK_HW_INIT_INDEX("ck_ker_csi", FLEXGEN_29, &clk_stm32_gate_ops, 0), 425 }; 426 427 static struct clk_stm32_gate ck_ker_csitxesc = { 428 .gate_id = GATE_CSI, 429 .hw.init = CLK_HW_INIT_INDEX("ck_ker_csitxesc", FLEXGEN_30, &clk_stm32_gate_ops, 0), 430 }; 431 432 /* CSI-PHY */ 433 static struct clk_stm32_gate ck_ker_csiphy = { 434 .gate_id = GATE_CSI, 435 .hw.init = CLK_HW_INIT_INDEX("ck_ker_csiphy", FLEXGEN_31, &clk_stm32_gate_ops, 0), 436 }; 437 438 /* DCMIPP */ 439 static struct clk_stm32_gate ck_icn_p_dcmipp = { 440 .gate_id = GATE_DCMIPP, 441 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dcmipp", ICN_APB4, &clk_stm32_gate_ops, 0), 442 }; 443 444 static struct clk_stm32_gate ck_icn_p_dcmipssi = { 445 .gate_id = GATE_DCMIPSSI, 446 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_dcmipssi", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 447 }; 448 449 /* DDRPERMF */ 450 static struct clk_stm32_gate ck_icn_p_ddrperfm = { 451 .gate_id = GATE_DDRPERFM, 452 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ddrperfm", ICN_APB4, &clk_stm32_gate_ops, 0), 453 }; 454 455 /* CRC */ 456 static struct clk_stm32_gate ck_icn_p_crc = { 457 .gate_id = GATE_CRC, 458 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_crc", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 459 }; 460 461 /* CRYP */ 462 static struct clk_stm32_gate ck_icn_p_cryp1 = { 463 .gate_id = GATE_CRYP1, 464 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp1", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 465 }; 466 467 static struct clk_stm32_gate ck_icn_p_cryp2 = { 468 .gate_id = GATE_CRYP2, 469 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_cryp2", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 470 }; 471 472 /* DBG & TRACE */ 473 /* Trace and debug clocks are managed by SCMI */ 474 475 /* LTDC */ 476 static struct clk_stm32_gate ck_icn_p_ltdc = { 477 .gate_id = GATE_LTDC, 478 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_ltdc", ICN_APB4, &clk_stm32_gate_ops, 0), 479 }; 480 481 static struct clk_stm32_gate ck_ker_ltdc = { 482 .gate_id = GATE_LTDC, 483 .hw.init = CLK_HW_INIT_INDEX("ck_ker_ltdc", FLEXGEN_27, &clk_stm32_gate_ops, 484 CLK_SET_RATE_PARENT), 485 }; 486 487 /* DTS */ 488 static struct clk_stm32_composite ck_ker_dts = { 489 .gate_id = GATE_DTS, 490 .mux_id = MUX_DTS, 491 .div_id = NO_STM32_DIV, 492 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_dts", dts_src, 493 &clk_stm32_composite_ops, 0), 494 }; 495 496 /* ETHERNET */ 497 static struct clk_stm32_gate ck_icn_p_eth1 = { 498 .gate_id = GATE_ETH1, 499 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth1", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 500 }; 501 502 static struct clk_stm32_gate ck_ker_eth1stp = { 503 .gate_id = GATE_ETH1STP, 504 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 505 }; 506 507 static struct clk_stm32_gate ck_ker_eth1 = { 508 .gate_id = GATE_ETH1, 509 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1", FLEXGEN_54, &clk_stm32_gate_ops, 0), 510 }; 511 512 static struct clk_stm32_gate ck_ker_eth1ptp = { 513 .gate_id = GATE_ETH1, 514 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0), 515 }; 516 517 static struct clk_stm32_gate ck_ker_eth1mac = { 518 .gate_id = GATE_ETH1MAC, 519 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 520 }; 521 522 static struct clk_stm32_gate ck_ker_eth1tx = { 523 .gate_id = GATE_ETH1TX, 524 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 525 }; 526 527 static struct clk_stm32_gate ck_ker_eth1rx = { 528 .gate_id = GATE_ETH1RX, 529 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth1rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 530 }; 531 532 static struct clk_stm32_gate ck_icn_p_eth2 = { 533 .gate_id = GATE_ETH2, 534 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_eth2", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 535 }; 536 537 static struct clk_stm32_gate ck_ker_eth2stp = { 538 .gate_id = GATE_ETH2STP, 539 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2stp", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 540 }; 541 542 static struct clk_stm32_gate ck_ker_eth2 = { 543 .gate_id = GATE_ETH2, 544 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2", FLEXGEN_55, &clk_stm32_gate_ops, 0), 545 }; 546 547 static struct clk_stm32_gate ck_ker_eth2ptp = { 548 .gate_id = GATE_ETH2, 549 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2ptp", FLEXGEN_56, &clk_stm32_gate_ops, 0), 550 }; 551 552 static struct clk_stm32_gate ck_ker_eth2mac = { 553 .gate_id = GATE_ETH2MAC, 554 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2mac", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 555 }; 556 557 static struct clk_stm32_gate ck_ker_eth2tx = { 558 .gate_id = GATE_ETH2TX, 559 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2tx", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 560 }; 561 562 static struct clk_stm32_gate ck_ker_eth2rx = { 563 .gate_id = GATE_ETH2RX, 564 .hw.init = CLK_HW_INIT_INDEX("ck_ker_eth2rx", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 565 }; 566 567 /* FDCAN */ 568 static struct clk_stm32_gate ck_icn_p_fdcan = { 569 .gate_id = GATE_FDCAN, 570 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_fdcan", ICN_APB2, &clk_stm32_gate_ops, 0), 571 }; 572 573 static struct clk_stm32_gate ck_ker_fdcan = { 574 .gate_id = GATE_FDCAN, 575 .hw.init = CLK_HW_INIT_INDEX("ck_ker_fdcan", FLEXGEN_26, &clk_stm32_gate_ops, 0), 576 }; 577 578 /* HASH */ 579 static struct clk_stm32_gate ck_icn_p_hash1 = { 580 .gate_id = GATE_HASH1, 581 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hash1", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 582 }; 583 584 static struct clk_stm32_gate ck_icn_p_hash2 = { 585 .gate_id = GATE_HASH2, 586 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hash2", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 587 }; 588 589 /* HDP */ 590 static struct clk_stm32_gate ck_icn_p_hdp = { 591 .gate_id = GATE_HDP, 592 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_hdp", ICN_APB3, &clk_stm32_gate_ops, 0), 593 }; 594 595 /* I2C */ 596 static struct clk_stm32_gate ck_icn_p_i2c1 = { 597 .gate_id = GATE_I2C1, 598 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c1", ICN_APB1, &clk_stm32_gate_ops, 0), 599 }; 600 601 static struct clk_stm32_gate ck_icn_p_i2c2 = { 602 .gate_id = GATE_I2C2, 603 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c2", ICN_APB1, &clk_stm32_gate_ops, 0), 604 }; 605 606 static struct clk_stm32_gate ck_icn_p_i2c3 = { 607 .gate_id = GATE_I2C3, 608 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i2c3", ICN_APB5, &clk_stm32_gate_ops, 0), 609 }; 610 611 static struct clk_stm32_gate ck_ker_i2c1 = { 612 .gate_id = GATE_I2C1, 613 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c1", FLEXGEN_13, &clk_stm32_gate_ops, 0), 614 }; 615 616 static struct clk_stm32_gate ck_ker_i2c2 = { 617 .gate_id = GATE_I2C2, 618 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c2", FLEXGEN_13, &clk_stm32_gate_ops, 0), 619 }; 620 621 static struct clk_stm32_gate ck_ker_i2c3 = { 622 .gate_id = GATE_I2C3, 623 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i2c3", FLEXGEN_38, &clk_stm32_gate_ops, 0), 624 }; 625 626 /* I3C */ 627 static struct clk_stm32_gate ck_icn_p_i3c1 = { 628 .gate_id = GATE_I3C1, 629 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c1", ICN_APB1, &clk_stm32_gate_ops, 0), 630 }; 631 632 static struct clk_stm32_gate ck_icn_p_i3c2 = { 633 .gate_id = GATE_I3C2, 634 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c2", ICN_APB1, &clk_stm32_gate_ops, 0), 635 }; 636 637 static struct clk_stm32_gate ck_icn_p_i3c3 = { 638 .gate_id = GATE_I3C3, 639 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_i3c3", ICN_APB5, &clk_stm32_gate_ops, 0), 640 }; 641 642 static struct clk_stm32_gate ck_ker_i3c1 = { 643 .gate_id = GATE_I3C1, 644 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c1", FLEXGEN_14, &clk_stm32_gate_ops, 0), 645 }; 646 647 static struct clk_stm32_gate ck_ker_i3c2 = { 648 .gate_id = GATE_I3C2, 649 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c2", FLEXGEN_14, &clk_stm32_gate_ops, 0), 650 }; 651 652 static struct clk_stm32_gate ck_ker_i3c3 = { 653 .gate_id = GATE_I3C3, 654 .hw.init = CLK_HW_INIT_INDEX("ck_ker_i3c3", FLEXGEN_36, &clk_stm32_gate_ops, 0), 655 }; 656 657 /* IWDG */ 658 static struct clk_stm32_gate ck_icn_p_iwdg1 = { 659 .gate_id = GATE_IWDG1, 660 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg1", ICN_APB3, &clk_stm32_gate_ops, 0), 661 }; 662 663 static struct clk_stm32_gate ck_icn_p_iwdg2 = { 664 .gate_id = GATE_IWDG2, 665 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg2", ICN_APB3, &clk_stm32_gate_ops, 0), 666 }; 667 668 static struct clk_stm32_gate ck_icn_p_iwdg3 = { 669 .gate_id = GATE_IWDG3, 670 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg3", ICN_APB3, &clk_stm32_gate_ops, 0), 671 }; 672 673 static struct clk_stm32_gate ck_icn_p_iwdg4 = { 674 .gate_id = GATE_IWDG4, 675 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg4", ICN_APB3, &clk_stm32_gate_ops, 0), 676 }; 677 678 /* LPTIM */ 679 static struct clk_stm32_gate ck_icn_p_lptim1 = { 680 .gate_id = GATE_LPTIM1, 681 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim1", ICN_APB1, &clk_stm32_gate_ops, 0), 682 }; 683 684 static struct clk_stm32_gate ck_icn_p_lptim2 = { 685 .gate_id = GATE_LPTIM2, 686 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim2", ICN_APB1, &clk_stm32_gate_ops, 0), 687 }; 688 689 static struct clk_stm32_gate ck_icn_p_lptim3 = { 690 .gate_id = GATE_LPTIM3, 691 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim3", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 692 }; 693 694 static struct clk_stm32_gate ck_icn_p_lptim4 = { 695 .gate_id = GATE_LPTIM4, 696 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim4", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 697 }; 698 699 static struct clk_stm32_gate ck_icn_p_lptim5 = { 700 .gate_id = GATE_LPTIM5, 701 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lptim5", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 702 }; 703 704 static struct clk_stm32_gate ck_ker_lptim1 = { 705 .gate_id = GATE_LPTIM1, 706 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim1", FLEXGEN_07, &clk_stm32_gate_ops, 0), 707 }; 708 709 static struct clk_stm32_gate ck_ker_lptim2 = { 710 .gate_id = GATE_LPTIM2, 711 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim2", FLEXGEN_07, &clk_stm32_gate_ops, 0), 712 }; 713 714 static struct clk_stm32_gate ck_ker_lptim3 = { 715 .gate_id = GATE_LPTIM3, 716 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim3", FLEXGEN_40, &clk_stm32_gate_ops, 0), 717 }; 718 719 static struct clk_stm32_gate ck_ker_lptim4 = { 720 .gate_id = GATE_LPTIM4, 721 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim4", FLEXGEN_41, &clk_stm32_gate_ops, 0), 722 }; 723 724 static struct clk_stm32_gate ck_ker_lptim5 = { 725 .gate_id = GATE_LPTIM5, 726 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lptim5", FLEXGEN_42, &clk_stm32_gate_ops, 0), 727 }; 728 729 /* LPUART */ 730 static struct clk_stm32_gate ck_icn_p_lpuart1 = { 731 .gate_id = GATE_LPUART1, 732 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_lpuart1", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 733 }; 734 735 static struct clk_stm32_gate ck_ker_lpuart1 = { 736 .gate_id = GATE_LPUART1, 737 .hw.init = CLK_HW_INIT_INDEX("ck_ker_lpuart1", FLEXGEN_39, &clk_stm32_gate_ops, 0), 738 }; 739 740 /* MCO1 & MCO2 */ 741 static struct clk_stm32_composite ck_mco1 = { 742 .gate_id = GATE_MCO1, 743 .mux_id = MUX_MCO1, 744 .div_id = NO_STM32_DIV, 745 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco1", mco1_src, &clk_stm32_composite_ops, 0), 746 }; 747 748 static struct clk_stm32_composite ck_mco2 = { 749 .gate_id = GATE_MCO2, 750 .mux_id = MUX_MCO2, 751 .div_id = NO_STM32_DIV, 752 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_mco2", mco2_src, &clk_stm32_composite_ops, 0), 753 }; 754 755 /* MDF */ 756 static struct clk_stm32_gate ck_icn_p_mdf1 = { 757 .gate_id = GATE_MDF1, 758 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_mdf1", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 759 }; 760 761 static struct clk_stm32_gate ck_ker_mdf1 = { 762 .gate_id = GATE_MDF1, 763 .hw.init = CLK_HW_INIT_INDEX("ck_ker_mdf1", FLEXGEN_21, &clk_stm32_gate_ops, 0), 764 }; 765 766 /* OTG */ 767 static struct clk_stm32_gate ck_icn_m_otg = { 768 .gate_id = GATE_OTG, 769 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_otg", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 770 }; 771 772 /* PKA */ 773 static struct clk_stm32_gate ck_icn_p_pka = { 774 .gate_id = GATE_PKA, 775 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pka", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 776 }; 777 778 /* RNG */ 779 static struct clk_stm32_gate ck_icn_p_rng1 = { 780 .gate_id = GATE_RNG1, 781 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_rng1", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 782 }; 783 784 static struct clk_stm32_gate ck_icn_p_rng2 = { 785 .gate_id = GATE_RNG2, 786 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_rng2", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 787 }; 788 789 /* SAES */ 790 static struct clk_stm32_gate ck_icn_p_saes = { 791 .gate_id = GATE_SAES, 792 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_saes", ICN_LS_MCU, &clk_stm32_gate_ops, 0), 793 }; 794 795 /* SAI */ 796 static struct clk_stm32_gate ck_icn_p_sai1 = { 797 .gate_id = GATE_SAI1, 798 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai1", ICN_APB2, &clk_stm32_gate_ops, 0), 799 }; 800 801 static struct clk_stm32_gate ck_icn_p_sai2 = { 802 .gate_id = GATE_SAI2, 803 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai2", ICN_APB2, &clk_stm32_gate_ops, 0), 804 }; 805 806 static struct clk_stm32_gate ck_icn_p_sai3 = { 807 .gate_id = GATE_SAI3, 808 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai3", ICN_APB2, &clk_stm32_gate_ops, 0), 809 }; 810 811 static struct clk_stm32_gate ck_icn_p_sai4 = { 812 .gate_id = GATE_SAI4, 813 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_sai4", ICN_APB2, &clk_stm32_gate_ops, 0), 814 }; 815 816 static struct clk_stm32_gate ck_ker_sai1 = { 817 .gate_id = GATE_SAI1, 818 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai1", FLEXGEN_22, &clk_stm32_gate_ops, 819 CLK_SET_RATE_PARENT), 820 }; 821 822 static struct clk_stm32_gate ck_ker_sai2 = { 823 .gate_id = GATE_SAI2, 824 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai2", FLEXGEN_23, &clk_stm32_gate_ops, 825 CLK_SET_RATE_PARENT), 826 }; 827 828 static struct clk_stm32_gate ck_ker_sai3 = { 829 .gate_id = GATE_SAI3, 830 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai3", FLEXGEN_24, &clk_stm32_gate_ops, 831 CLK_SET_RATE_PARENT), 832 }; 833 834 static struct clk_stm32_gate ck_ker_sai4 = { 835 .gate_id = GATE_SAI4, 836 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sai4", FLEXGEN_25, &clk_stm32_gate_ops, 837 CLK_SET_RATE_PARENT), 838 }; 839 840 /* SDMMC */ 841 static struct clk_stm32_gate ck_icn_m_sdmmc1 = { 842 .gate_id = GATE_SDMMC1, 843 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc1", ICN_SDMMC, &clk_stm32_gate_ops, 0), 844 }; 845 846 static struct clk_stm32_gate ck_icn_m_sdmmc2 = { 847 .gate_id = GATE_SDMMC2, 848 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc2", ICN_SDMMC, &clk_stm32_gate_ops, 0), 849 }; 850 851 static struct clk_stm32_gate ck_icn_m_sdmmc3 = { 852 .gate_id = GATE_SDMMC3, 853 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_sdmmc3", ICN_SDMMC, &clk_stm32_gate_ops, 0), 854 }; 855 856 static struct clk_stm32_gate ck_ker_sdmmc1 = { 857 .gate_id = GATE_SDMMC1, 858 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc1", FLEXGEN_51, &clk_stm32_gate_ops, 0), 859 }; 860 861 static struct clk_stm32_gate ck_ker_sdmmc2 = { 862 .gate_id = GATE_SDMMC2, 863 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc2", FLEXGEN_52, &clk_stm32_gate_ops, 0), 864 }; 865 866 static struct clk_stm32_gate ck_ker_sdmmc3 = { 867 .gate_id = GATE_SDMMC3, 868 .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc3", FLEXGEN_53, &clk_stm32_gate_ops, 0), 869 }; 870 871 /* SERC */ 872 static struct clk_stm32_gate ck_icn_p_serc = { 873 .gate_id = GATE_SERC, 874 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_serc", ICN_APB3, &clk_stm32_gate_ops, 0), 875 }; 876 877 /* SPDIF */ 878 static struct clk_stm32_gate ck_icn_p_spdifrx = { 879 .gate_id = GATE_SPDIFRX, 880 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spdifrx", ICN_APB1, &clk_stm32_gate_ops, 0), 881 }; 882 883 static struct clk_stm32_gate ck_ker_spdifrx = { 884 .gate_id = GATE_SPDIFRX, 885 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spdifrx", FLEXGEN_12, &clk_stm32_gate_ops, 0), 886 }; 887 888 /* SPI */ 889 static struct clk_stm32_gate ck_icn_p_spi1 = { 890 .gate_id = GATE_SPI1, 891 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi1", ICN_APB2, &clk_stm32_gate_ops, 0), 892 }; 893 894 static struct clk_stm32_gate ck_icn_p_spi2 = { 895 .gate_id = GATE_SPI2, 896 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi2", ICN_APB1, &clk_stm32_gate_ops, 0), 897 }; 898 899 static struct clk_stm32_gate ck_icn_p_spi3 = { 900 .gate_id = GATE_SPI3, 901 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi3", ICN_APB1, &clk_stm32_gate_ops, 0), 902 }; 903 904 static struct clk_stm32_gate ck_icn_p_spi4 = { 905 .gate_id = GATE_SPI4, 906 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi4", ICN_APB2, &clk_stm32_gate_ops, 0), 907 }; 908 909 static struct clk_stm32_gate ck_icn_p_spi5 = { 910 .gate_id = GATE_SPI5, 911 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi5", ICN_APB2, &clk_stm32_gate_ops, 0), 912 }; 913 914 static struct clk_stm32_gate ck_icn_p_spi6 = { 915 .gate_id = GATE_SPI6, 916 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_spi6", ICN_APB2, &clk_stm32_gate_ops, 0), 917 }; 918 919 static struct clk_stm32_gate ck_ker_spi1 = { 920 .gate_id = GATE_SPI1, 921 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi1", FLEXGEN_16, &clk_stm32_gate_ops, 922 CLK_SET_RATE_PARENT), 923 }; 924 925 static struct clk_stm32_gate ck_ker_spi2 = { 926 .gate_id = GATE_SPI2, 927 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi2", FLEXGEN_10, &clk_stm32_gate_ops, 928 CLK_SET_RATE_PARENT), 929 }; 930 931 static struct clk_stm32_gate ck_ker_spi3 = { 932 .gate_id = GATE_SPI3, 933 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi3", FLEXGEN_11, &clk_stm32_gate_ops, 934 CLK_SET_RATE_PARENT), 935 }; 936 937 static struct clk_stm32_gate ck_ker_spi4 = { 938 .gate_id = GATE_SPI4, 939 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi4", FLEXGEN_17, &clk_stm32_gate_ops, 0), 940 }; 941 942 static struct clk_stm32_gate ck_ker_spi5 = { 943 .gate_id = GATE_SPI5, 944 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi5", FLEXGEN_17, &clk_stm32_gate_ops, 0), 945 }; 946 947 static struct clk_stm32_gate ck_ker_spi6 = { 948 .gate_id = GATE_SPI6, 949 .hw.init = CLK_HW_INIT_INDEX("ck_ker_spi6", FLEXGEN_37, &clk_stm32_gate_ops, 0), 950 }; 951 952 /* Timers */ 953 static struct clk_stm32_gate ck_icn_p_tim2 = { 954 .gate_id = GATE_TIM2, 955 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim2", ICN_APB1, &clk_stm32_gate_ops, 0), 956 }; 957 958 static struct clk_stm32_gate ck_icn_p_tim3 = { 959 .gate_id = GATE_TIM3, 960 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim3", ICN_APB1, &clk_stm32_gate_ops, 0), 961 }; 962 963 static struct clk_stm32_gate ck_icn_p_tim4 = { 964 .gate_id = GATE_TIM4, 965 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim4", ICN_APB1, &clk_stm32_gate_ops, 0), 966 }; 967 968 static struct clk_stm32_gate ck_icn_p_tim5 = { 969 .gate_id = GATE_TIM5, 970 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim5", ICN_APB1, &clk_stm32_gate_ops, 0), 971 }; 972 973 static struct clk_stm32_gate ck_icn_p_tim6 = { 974 .gate_id = GATE_TIM6, 975 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim6", ICN_APB1, &clk_stm32_gate_ops, 0), 976 }; 977 978 static struct clk_stm32_gate ck_icn_p_tim7 = { 979 .gate_id = GATE_TIM7, 980 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim7", ICN_APB1, &clk_stm32_gate_ops, 0), 981 }; 982 983 static struct clk_stm32_gate ck_icn_p_tim10 = { 984 .gate_id = GATE_TIM10, 985 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim10", ICN_APB1, &clk_stm32_gate_ops, 0), 986 }; 987 988 static struct clk_stm32_gate ck_icn_p_tim11 = { 989 .gate_id = GATE_TIM11, 990 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim11", ICN_APB1, &clk_stm32_gate_ops, 0), 991 }; 992 993 static struct clk_stm32_gate ck_icn_p_tim12 = { 994 .gate_id = GATE_TIM12, 995 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim12", ICN_APB1, &clk_stm32_gate_ops, 0), 996 }; 997 998 static struct clk_stm32_gate ck_icn_p_tim13 = { 999 .gate_id = GATE_TIM13, 1000 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim13", ICN_APB1, &clk_stm32_gate_ops, 0), 1001 }; 1002 1003 static struct clk_stm32_gate ck_icn_p_tim14 = { 1004 .gate_id = GATE_TIM14, 1005 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim14", ICN_APB1, &clk_stm32_gate_ops, 0), 1006 }; 1007 1008 static struct clk_stm32_gate ck_icn_p_tim1 = { 1009 .gate_id = GATE_TIM1, 1010 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim1", ICN_APB2, &clk_stm32_gate_ops, 0), 1011 }; 1012 1013 static struct clk_stm32_gate ck_icn_p_tim8 = { 1014 .gate_id = GATE_TIM8, 1015 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim8", ICN_APB2, &clk_stm32_gate_ops, 0), 1016 }; 1017 1018 static struct clk_stm32_gate ck_icn_p_tim15 = { 1019 .gate_id = GATE_TIM15, 1020 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim15", ICN_APB2, &clk_stm32_gate_ops, 0), 1021 }; 1022 1023 static struct clk_stm32_gate ck_icn_p_tim16 = { 1024 .gate_id = GATE_TIM16, 1025 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim16", ICN_APB2, &clk_stm32_gate_ops, 0), 1026 }; 1027 1028 static struct clk_stm32_gate ck_icn_p_tim17 = { 1029 .gate_id = GATE_TIM17, 1030 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_tim17", ICN_APB2, &clk_stm32_gate_ops, 0), 1031 }; 1032 1033 static struct clk_stm32_gate ck_ker_tim2 = { 1034 .gate_id = GATE_TIM2, 1035 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim2", TIMG1, &clk_stm32_gate_ops, 0), 1036 }; 1037 1038 static struct clk_stm32_gate ck_ker_tim3 = { 1039 .gate_id = GATE_TIM3, 1040 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim3", TIMG1, &clk_stm32_gate_ops, 0), 1041 }; 1042 1043 static struct clk_stm32_gate ck_ker_tim4 = { 1044 .gate_id = GATE_TIM4, 1045 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim4", TIMG1, &clk_stm32_gate_ops, 0), 1046 }; 1047 1048 static struct clk_stm32_gate ck_ker_tim5 = { 1049 .gate_id = GATE_TIM5, 1050 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim5", TIMG1, &clk_stm32_gate_ops, 0), 1051 }; 1052 1053 static struct clk_stm32_gate ck_ker_tim6 = { 1054 .gate_id = GATE_TIM6, 1055 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim6", TIMG1, &clk_stm32_gate_ops, 0), 1056 }; 1057 1058 static struct clk_stm32_gate ck_ker_tim7 = { 1059 .gate_id = GATE_TIM7, 1060 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim7", TIMG1, &clk_stm32_gate_ops, 0), 1061 }; 1062 1063 static struct clk_stm32_gate ck_ker_tim10 = { 1064 .gate_id = GATE_TIM10, 1065 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim10", TIMG1, &clk_stm32_gate_ops, 0), 1066 }; 1067 1068 static struct clk_stm32_gate ck_ker_tim11 = { 1069 .gate_id = GATE_TIM11, 1070 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim11", TIMG1, &clk_stm32_gate_ops, 0), 1071 }; 1072 1073 static struct clk_stm32_gate ck_ker_tim12 = { 1074 .gate_id = GATE_TIM12, 1075 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim12", TIMG1, &clk_stm32_gate_ops, 0), 1076 }; 1077 1078 static struct clk_stm32_gate ck_ker_tim13 = { 1079 .gate_id = GATE_TIM13, 1080 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim13", TIMG1, &clk_stm32_gate_ops, 0), 1081 }; 1082 1083 static struct clk_stm32_gate ck_ker_tim14 = { 1084 .gate_id = GATE_TIM14, 1085 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim14", TIMG1, &clk_stm32_gate_ops, 0), 1086 }; 1087 1088 static struct clk_stm32_gate ck_ker_tim1 = { 1089 .gate_id = GATE_TIM1, 1090 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim1", TIMG2, &clk_stm32_gate_ops, 0), 1091 }; 1092 1093 static struct clk_stm32_gate ck_ker_tim8 = { 1094 .gate_id = GATE_TIM8, 1095 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim8", TIMG2, &clk_stm32_gate_ops, 0), 1096 }; 1097 1098 static struct clk_stm32_gate ck_ker_tim15 = { 1099 .gate_id = GATE_TIM15, 1100 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim15", TIMG2, &clk_stm32_gate_ops, 0), 1101 }; 1102 1103 static struct clk_stm32_gate ck_ker_tim16 = { 1104 .gate_id = GATE_TIM16, 1105 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim16", TIMG2, &clk_stm32_gate_ops, 0), 1106 }; 1107 1108 static struct clk_stm32_gate ck_ker_tim17 = { 1109 .gate_id = GATE_TIM17, 1110 .hw.init = CLK_HW_INIT_INDEX("ck_ker_tim17", TIMG2, &clk_stm32_gate_ops, 0), 1111 }; 1112 1113 /* UART/USART */ 1114 static struct clk_stm32_gate ck_icn_p_usart2 = { 1115 .gate_id = GATE_USART2, 1116 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart2", ICN_APB1, &clk_stm32_gate_ops, 0), 1117 }; 1118 1119 static struct clk_stm32_gate ck_icn_p_usart3 = { 1120 .gate_id = GATE_USART3, 1121 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart3", ICN_APB1, &clk_stm32_gate_ops, 0), 1122 }; 1123 1124 static struct clk_stm32_gate ck_icn_p_uart4 = { 1125 .gate_id = GATE_UART4, 1126 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart4", ICN_APB1, &clk_stm32_gate_ops, 0), 1127 }; 1128 1129 static struct clk_stm32_gate ck_icn_p_uart5 = { 1130 .gate_id = GATE_UART5, 1131 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart5", ICN_APB1, &clk_stm32_gate_ops, 0), 1132 }; 1133 1134 static struct clk_stm32_gate ck_icn_p_usart1 = { 1135 .gate_id = GATE_USART1, 1136 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart1", ICN_APB2, &clk_stm32_gate_ops, 0), 1137 }; 1138 1139 static struct clk_stm32_gate ck_icn_p_usart6 = { 1140 .gate_id = GATE_USART6, 1141 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_usart6", ICN_APB2, &clk_stm32_gate_ops, 0), 1142 }; 1143 1144 static struct clk_stm32_gate ck_icn_p_uart7 = { 1145 .gate_id = GATE_UART7, 1146 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_uart7", ICN_APB2, &clk_stm32_gate_ops, 0), 1147 }; 1148 1149 static struct clk_stm32_gate ck_ker_usart2 = { 1150 .gate_id = GATE_USART2, 1151 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart2", FLEXGEN_08, &clk_stm32_gate_ops, 0), 1152 }; 1153 1154 static struct clk_stm32_gate ck_ker_uart4 = { 1155 .gate_id = GATE_UART4, 1156 .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart4", FLEXGEN_08, &clk_stm32_gate_ops, 0), 1157 }; 1158 1159 static struct clk_stm32_gate ck_ker_usart3 = { 1160 .gate_id = GATE_USART3, 1161 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart3", FLEXGEN_09, &clk_stm32_gate_ops, 0), 1162 }; 1163 1164 static struct clk_stm32_gate ck_ker_uart5 = { 1165 .gate_id = GATE_UART5, 1166 .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart5", FLEXGEN_09, &clk_stm32_gate_ops, 0), 1167 }; 1168 1169 static struct clk_stm32_gate ck_ker_usart1 = { 1170 .gate_id = GATE_USART1, 1171 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart1", FLEXGEN_18, &clk_stm32_gate_ops, 0), 1172 }; 1173 1174 static struct clk_stm32_gate ck_ker_usart6 = { 1175 .gate_id = GATE_USART6, 1176 .hw.init = CLK_HW_INIT_INDEX("ck_ker_usart6", FLEXGEN_19, &clk_stm32_gate_ops, 0), 1177 }; 1178 1179 static struct clk_stm32_gate ck_ker_uart7 = { 1180 .gate_id = GATE_UART7, 1181 .hw.init = CLK_HW_INIT_INDEX("ck_ker_uart7", FLEXGEN_20, &clk_stm32_gate_ops, 0), 1182 }; 1183 1184 /* USB2PHY1 */ 1185 static struct clk_stm32_composite ck_ker_usb2phy1 = { 1186 .gate_id = GATE_USB2PHY1, 1187 .mux_id = MUX_USB2PHY1, 1188 .div_id = NO_STM32_DIV, 1189 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy1", usb2phy1_src, 1190 &clk_stm32_composite_ops, 0), 1191 }; 1192 1193 /* USBH */ 1194 static struct clk_stm32_gate ck_icn_m_usbhehci = { 1195 .gate_id = GATE_USBH, 1196 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usbhehci", ICN_HSL, &clk_stm32_gate_ops, 0), 1197 }; 1198 1199 static struct clk_stm32_gate ck_icn_m_usbhohci = { 1200 .gate_id = GATE_USBH, 1201 .hw.init = CLK_HW_INIT_INDEX("ck_icn_m_usbhohci", ICN_HSL, &clk_stm32_gate_ops, 0), 1202 }; 1203 1204 /* USB2PHY2 */ 1205 static struct clk_stm32_composite ck_ker_usb2phy2_en = { 1206 .gate_id = GATE_USB2PHY2, 1207 .mux_id = MUX_USB2PHY2, 1208 .div_id = NO_STM32_DIV, 1209 .hw.init = CLK_HW_INIT_PARENTS_DATA("ck_ker_usb2phy2_en", usb2phy2_src, 1210 &clk_stm32_composite_ops, 0), 1211 }; 1212 1213 /* VREF */ 1214 static struct clk_stm32_gate ck_icn_p_vref = { 1215 .gate_id = GATE_VREF, 1216 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_vref", ICN_APB3, &clk_stm32_gate_ops, 0), 1217 }; 1218 1219 /* WWDG */ 1220 static struct clk_stm32_gate ck_icn_p_wwdg1 = { 1221 .gate_id = GATE_WWDG1, 1222 .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_wwdg1", ICN_APB3, &clk_stm32_gate_ops, 0), 1223 }; 1224 1225 static int stm32_rcc_get_access(void __iomem *base, u32 index) 1226 { 1227 u32 seccfgr, cidcfgr, semcr; 1228 int bit, cid; 1229 1230 bit = index % RCC_REG_SIZE; 1231 1232 seccfgr = readl(base + RCC_SECCFGR(index)); 1233 if (seccfgr & BIT(bit)) 1234 return -EACCES; 1235 1236 cidcfgr = readl(base + RCC_CIDCFGR(index)); 1237 if (!(cidcfgr & RCC_CIDCFGR_CFEN)) 1238 /* CID filtering is turned off: access granted */ 1239 return 0; 1240 1241 if (!(cidcfgr & RCC_CIDCFGR_SEM_EN)) { 1242 /* Static CID mode */ 1243 cid = FIELD_GET(RCC_CIDCFGR_SCID_MASK, cidcfgr); 1244 if (cid != RCC_CID1) 1245 return -EACCES; 1246 return 0; 1247 } 1248 1249 /* Pass-list with semaphore mode */ 1250 if (!(cidcfgr & RCC_CIDCFGR_SEMWLC1_EN)) 1251 return -EACCES; 1252 1253 semcr = readl(base + RCC_SEMCR(index)); 1254 1255 cid = FIELD_GET(RCC_SEMCR_SEMCID_MASK, semcr); 1256 if (cid != RCC_CID1) 1257 return -EACCES; 1258 1259 return 0; 1260 } 1261 1262 static int stm32mp21_check_security(struct device_node *np, void __iomem *base, 1263 const struct clock_config *cfg) 1264 { 1265 int ret = 0; 1266 1267 if (cfg->sec_id != SECF_NONE) { 1268 struct stm32_firewall firewall; 1269 u32 index = (u32)cfg->sec_id; 1270 1271 if (index & SEC_RIFSC_FLAG) { 1272 ret = stm32_firewall_get_firewall(np, &firewall, 1); 1273 if (ret) 1274 return ret; 1275 ret = stm32_firewall_grant_access_by_id(&firewall, index & ~SEC_RIFSC_FLAG); 1276 } else { 1277 ret = stm32_rcc_get_access(base, cfg->sec_id & ~SEC_RIFSC_FLAG); 1278 } 1279 } 1280 1281 return ret; 1282 } 1283 1284 static const struct clock_config stm32mp21_clock_cfg[] = { 1285 STM32_GATE_CFG(CK_BUS_ETH1, ck_icn_p_eth1, SEC_RIFSC(60)), 1286 STM32_GATE_CFG(CK_BUS_ETH2, ck_icn_p_eth2, SEC_RIFSC(61)), 1287 STM32_GATE_CFG(CK_BUS_ADC1, ck_icn_p_adc1, SEC_RIFSC(58)), 1288 STM32_GATE_CFG(CK_BUS_ADC2, ck_icn_p_adc2, SEC_RIFSC(59)), 1289 STM32_GATE_CFG(CK_BUS_CRC, ck_icn_p_crc, SEC_RIFSC(109)), 1290 STM32_GATE_CFG(CK_BUS_MDF1, ck_icn_p_mdf1, SEC_RIFSC(54)), 1291 STM32_GATE_CFG(CK_BUS_HASH1, ck_icn_p_hash1, SEC_RIFSC(96)), 1292 STM32_GATE_CFG(CK_BUS_HASH2, ck_icn_p_hash2, SEC_RIFSC(97)), 1293 STM32_GATE_CFG(CK_BUS_RNG1, ck_icn_p_rng1, SEC_RIFSC(92)), 1294 STM32_GATE_CFG(CK_BUS_RNG2, ck_icn_p_rng2, SEC_RIFSC(93)), 1295 STM32_GATE_CFG(CK_BUS_CRYP1, ck_icn_p_cryp1, SEC_RIFSC(98)), 1296 STM32_GATE_CFG(CK_BUS_CRYP2, ck_icn_p_cryp2, SEC_RIFSC(99)), 1297 STM32_GATE_CFG(CK_BUS_SAES, ck_icn_p_saes, SEC_RIFSC(95)), 1298 STM32_GATE_CFG(CK_BUS_PKA, ck_icn_p_pka, SEC_RIFSC(94)), 1299 STM32_GATE_CFG(CK_BUS_LPUART1, ck_icn_p_lpuart1, SEC_RIFSC(40)), 1300 STM32_GATE_CFG(CK_BUS_LPTIM3, ck_icn_p_lptim3, SEC_RIFSC(19)), 1301 STM32_GATE_CFG(CK_BUS_LPTIM4, ck_icn_p_lptim4, SEC_RIFSC(20)), 1302 STM32_GATE_CFG(CK_BUS_LPTIM5, ck_icn_p_lptim5, SEC_RIFSC(21)), 1303 STM32_GATE_CFG(CK_BUS_SDMMC1, ck_icn_m_sdmmc1, SEC_RIFSC(76)), 1304 STM32_GATE_CFG(CK_BUS_SDMMC2, ck_icn_m_sdmmc2, SEC_RIFSC(77)), 1305 STM32_GATE_CFG(CK_BUS_SDMMC3, ck_icn_m_sdmmc3, SEC_RIFSC(78)), 1306 STM32_GATE_CFG(CK_BUS_USBHOHCI, ck_icn_m_usbhohci, SEC_RIFSC(63)), 1307 STM32_GATE_CFG(CK_BUS_USBHEHCI, ck_icn_m_usbhehci, SEC_RIFSC(63)), 1308 STM32_GATE_CFG(CK_BUS_OTG, ck_icn_m_otg, SEC_RIFSC(66)), 1309 STM32_GATE_CFG(CK_BUS_TIM2, ck_icn_p_tim2, SEC_RIFSC(1)), 1310 STM32_GATE_CFG(CK_BUS_TIM3, ck_icn_p_tim3, SEC_RIFSC(2)), 1311 STM32_GATE_CFG(CK_BUS_TIM4, ck_icn_p_tim4, SEC_RIFSC(3)), 1312 STM32_GATE_CFG(CK_BUS_TIM5, ck_icn_p_tim5, SEC_RIFSC(4)), 1313 STM32_GATE_CFG(CK_BUS_TIM6, ck_icn_p_tim6, SEC_RIFSC(5)), 1314 STM32_GATE_CFG(CK_BUS_TIM7, ck_icn_p_tim7, SEC_RIFSC(6)), 1315 STM32_GATE_CFG(CK_BUS_TIM10, ck_icn_p_tim10, SEC_RIFSC(8)), 1316 STM32_GATE_CFG(CK_BUS_TIM11, ck_icn_p_tim11, SEC_RIFSC(9)), 1317 STM32_GATE_CFG(CK_BUS_TIM12, ck_icn_p_tim12, SEC_RIFSC(10)), 1318 STM32_GATE_CFG(CK_BUS_TIM13, ck_icn_p_tim13, SEC_RIFSC(11)), 1319 STM32_GATE_CFG(CK_BUS_TIM14, ck_icn_p_tim14, SEC_RIFSC(12)), 1320 STM32_GATE_CFG(CK_BUS_LPTIM1, ck_icn_p_lptim1, SEC_RIFSC(17)), 1321 STM32_GATE_CFG(CK_BUS_LPTIM2, ck_icn_p_lptim2, SEC_RIFSC(18)), 1322 STM32_GATE_CFG(CK_BUS_SPI2, ck_icn_p_spi2, SEC_RIFSC(23)), 1323 STM32_GATE_CFG(CK_BUS_SPI3, ck_icn_p_spi3, SEC_RIFSC(24)), 1324 STM32_GATE_CFG(CK_BUS_SPDIFRX, ck_icn_p_spdifrx, SEC_RIFSC(30)), 1325 STM32_GATE_CFG(CK_BUS_USART2, ck_icn_p_usart2, SEC_RIFSC(32)), 1326 STM32_GATE_CFG(CK_BUS_USART3, ck_icn_p_usart3, SEC_RIFSC(33)), 1327 STM32_GATE_CFG(CK_BUS_UART4, ck_icn_p_uart4, SEC_RIFSC(34)), 1328 STM32_GATE_CFG(CK_BUS_UART5, ck_icn_p_uart5, SEC_RIFSC(35)), 1329 STM32_GATE_CFG(CK_BUS_I2C1, ck_icn_p_i2c1, SEC_RIFSC(41)), 1330 STM32_GATE_CFG(CK_BUS_I2C2, ck_icn_p_i2c2, SEC_RIFSC(42)), 1331 STM32_GATE_CFG(CK_BUS_I2C3, ck_icn_p_i2c3, SEC_RIFSC(43)), 1332 STM32_GATE_CFG(CK_BUS_I3C1, ck_icn_p_i3c1, SEC_RIFSC(114)), 1333 STM32_GATE_CFG(CK_BUS_I3C2, ck_icn_p_i3c2, SEC_RIFSC(115)), 1334 STM32_GATE_CFG(CK_BUS_I3C3, ck_icn_p_i3c3, SEC_RIFSC(116)), 1335 STM32_GATE_CFG(CK_BUS_TIM1, ck_icn_p_tim1, SEC_RIFSC(0)), 1336 STM32_GATE_CFG(CK_BUS_TIM8, ck_icn_p_tim8, SEC_RIFSC(7)), 1337 STM32_GATE_CFG(CK_BUS_TIM15, ck_icn_p_tim15, SEC_RIFSC(13)), 1338 STM32_GATE_CFG(CK_BUS_TIM16, ck_icn_p_tim16, SEC_RIFSC(14)), 1339 STM32_GATE_CFG(CK_BUS_TIM17, ck_icn_p_tim17, SEC_RIFSC(15)), 1340 STM32_GATE_CFG(CK_BUS_SAI1, ck_icn_p_sai1, SEC_RIFSC(49)), 1341 STM32_GATE_CFG(CK_BUS_SAI2, ck_icn_p_sai2, SEC_RIFSC(50)), 1342 STM32_GATE_CFG(CK_BUS_SAI3, ck_icn_p_sai3, SEC_RIFSC(51)), 1343 STM32_GATE_CFG(CK_BUS_SAI4, ck_icn_p_sai4, SEC_RIFSC(52)), 1344 STM32_GATE_CFG(CK_BUS_USART1, ck_icn_p_usart1, SEC_RIFSC(31)), 1345 STM32_GATE_CFG(CK_BUS_USART6, ck_icn_p_usart6, SEC_RIFSC(36)), 1346 STM32_GATE_CFG(CK_BUS_UART7, ck_icn_p_uart7, SEC_RIFSC(37)), 1347 STM32_GATE_CFG(CK_BUS_FDCAN, ck_icn_p_fdcan, SEC_RIFSC(56)), 1348 STM32_GATE_CFG(CK_BUS_SPI1, ck_icn_p_spi1, SEC_RIFSC(22)), 1349 STM32_GATE_CFG(CK_BUS_SPI4, ck_icn_p_spi4, SEC_RIFSC(25)), 1350 STM32_GATE_CFG(CK_BUS_SPI5, ck_icn_p_spi5, SEC_RIFSC(26)), 1351 STM32_GATE_CFG(CK_BUS_SPI6, ck_icn_p_spi6, SEC_RIFSC(27)), 1352 STM32_GATE_CFG(CK_BUS_IWDG1, ck_icn_p_iwdg1, SEC_RIFSC(100)), 1353 STM32_GATE_CFG(CK_BUS_IWDG2, ck_icn_p_iwdg2, SEC_RIFSC(101)), 1354 STM32_GATE_CFG(CK_BUS_IWDG3, ck_icn_p_iwdg3, SEC_RIFSC(102)), 1355 STM32_GATE_CFG(CK_BUS_IWDG4, ck_icn_p_iwdg4, SEC_RIFSC(103)), 1356 STM32_GATE_CFG(CK_BUS_WWDG1, ck_icn_p_wwdg1, SEC_RIFSC(104)), 1357 STM32_GATE_CFG(CK_BUS_VREF, ck_icn_p_vref, SEC_RIFSC(106)), 1358 STM32_GATE_CFG(CK_BUS_SERC, ck_icn_p_serc, SEC_RIFSC(110)), 1359 STM32_GATE_CFG(CK_BUS_HDP, ck_icn_p_hdp, SEC_RIFSC(57)), 1360 STM32_GATE_CFG(CK_BUS_LTDC, ck_icn_p_ltdc, SEC_RIFSC(80)), 1361 STM32_GATE_CFG(CK_BUS_CSI, ck_icn_p_csi, SEC_RIFSC(86)), 1362 STM32_GATE_CFG(CK_BUS_DCMIPP, ck_icn_p_dcmipp, SEC_RIFSC(87)), 1363 STM32_GATE_CFG(CK_BUS_DCMIPSSI, ck_icn_p_dcmipssi, SEC_RIFSC(88)), 1364 STM32_GATE_CFG(CK_BUS_DDRPERFM, ck_icn_p_ddrperfm, SEC_RIFSC(67)), 1365 STM32_GATE_CFG(CK_KER_TIM2, ck_ker_tim2, SEC_RIFSC(1)), 1366 STM32_GATE_CFG(CK_KER_TIM3, ck_ker_tim3, SEC_RIFSC(2)), 1367 STM32_GATE_CFG(CK_KER_TIM4, ck_ker_tim4, SEC_RIFSC(3)), 1368 STM32_GATE_CFG(CK_KER_TIM5, ck_ker_tim5, SEC_RIFSC(4)), 1369 STM32_GATE_CFG(CK_KER_TIM6, ck_ker_tim6, SEC_RIFSC(5)), 1370 STM32_GATE_CFG(CK_KER_TIM7, ck_ker_tim7, SEC_RIFSC(6)), 1371 STM32_GATE_CFG(CK_KER_TIM10, ck_ker_tim10, SEC_RIFSC(8)), 1372 STM32_GATE_CFG(CK_KER_TIM11, ck_ker_tim11, SEC_RIFSC(9)), 1373 STM32_GATE_CFG(CK_KER_TIM12, ck_ker_tim12, SEC_RIFSC(10)), 1374 STM32_GATE_CFG(CK_KER_TIM13, ck_ker_tim13, SEC_RIFSC(11)), 1375 STM32_GATE_CFG(CK_KER_TIM14, ck_ker_tim14, SEC_RIFSC(12)), 1376 STM32_GATE_CFG(CK_KER_TIM1, ck_ker_tim1, SEC_RIFSC(0)), 1377 STM32_GATE_CFG(CK_KER_TIM8, ck_ker_tim8, SEC_RIFSC(7)), 1378 STM32_GATE_CFG(CK_KER_TIM15, ck_ker_tim15, SEC_RIFSC(13)), 1379 STM32_GATE_CFG(CK_KER_TIM16, ck_ker_tim16, SEC_RIFSC(14)), 1380 STM32_GATE_CFG(CK_KER_TIM17, ck_ker_tim17, SEC_RIFSC(15)), 1381 STM32_GATE_CFG(CK_KER_LPTIM1, ck_ker_lptim1, SEC_RIFSC(17)), 1382 STM32_GATE_CFG(CK_KER_LPTIM2, ck_ker_lptim2, SEC_RIFSC(18)), 1383 STM32_GATE_CFG(CK_KER_USART2, ck_ker_usart2, SEC_RIFSC(32)), 1384 STM32_GATE_CFG(CK_KER_UART4, ck_ker_uart4, SEC_RIFSC(34)), 1385 STM32_GATE_CFG(CK_KER_USART3, ck_ker_usart3, SEC_RIFSC(33)), 1386 STM32_GATE_CFG(CK_KER_UART5, ck_ker_uart5, SEC_RIFSC(35)), 1387 STM32_GATE_CFG(CK_KER_SPI2, ck_ker_spi2, SEC_RIFSC(23)), 1388 STM32_GATE_CFG(CK_KER_SPI3, ck_ker_spi3, SEC_RIFSC(24)), 1389 STM32_GATE_CFG(CK_KER_SPDIFRX, ck_ker_spdifrx, SEC_RIFSC(30)), 1390 STM32_GATE_CFG(CK_KER_I2C1, ck_ker_i2c1, SEC_RIFSC(41)), 1391 STM32_GATE_CFG(CK_KER_I2C2, ck_ker_i2c2, SEC_RIFSC(42)), 1392 STM32_GATE_CFG(CK_KER_I3C1, ck_ker_i3c1, SEC_RIFSC(114)), 1393 STM32_GATE_CFG(CK_KER_I3C2, ck_ker_i3c2, SEC_RIFSC(115)), 1394 STM32_GATE_CFG(CK_KER_I2C3, ck_ker_i2c3, SEC_RIFSC(43)), 1395 STM32_GATE_CFG(CK_KER_I3C3, ck_ker_i3c3, SEC_RIFSC(116)), 1396 STM32_GATE_CFG(CK_KER_SPI1, ck_ker_spi1, SEC_RIFSC(22)), 1397 STM32_GATE_CFG(CK_KER_SPI4, ck_ker_spi4, SEC_RIFSC(25)), 1398 STM32_GATE_CFG(CK_KER_SPI5, ck_ker_spi5, SEC_RIFSC(26)), 1399 STM32_GATE_CFG(CK_KER_SPI6, ck_ker_spi6, SEC_RIFSC(27)), 1400 STM32_GATE_CFG(CK_KER_USART1, ck_ker_usart1, SEC_RIFSC(31)), 1401 STM32_GATE_CFG(CK_KER_USART6, ck_ker_usart6, SEC_RIFSC(36)), 1402 STM32_GATE_CFG(CK_KER_UART7, ck_ker_uart7, SEC_RIFSC(37)), 1403 STM32_GATE_CFG(CK_KER_MDF1, ck_ker_mdf1, SEC_RIFSC(54)), 1404 STM32_GATE_CFG(CK_KER_SAI1, ck_ker_sai1, SEC_RIFSC(49)), 1405 STM32_GATE_CFG(CK_KER_SAI2, ck_ker_sai2, SEC_RIFSC(50)), 1406 STM32_GATE_CFG(CK_KER_SAI3, ck_ker_sai3, SEC_RIFSC(51)), 1407 STM32_GATE_CFG(CK_KER_SAI4, ck_ker_sai4, SEC_RIFSC(52)), 1408 STM32_GATE_CFG(CK_KER_FDCAN, ck_ker_fdcan, SEC_RIFSC(56)), 1409 STM32_GATE_CFG(CK_KER_CSI, ck_ker_csi, SEC_RIFSC(86)), 1410 STM32_GATE_CFG(CK_KER_CSITXESC, ck_ker_csitxesc, SEC_RIFSC(86)), 1411 STM32_GATE_CFG(CK_KER_CSIPHY, ck_ker_csiphy, SEC_RIFSC(86)), 1412 STM32_GATE_CFG(CK_KER_LPUART1, ck_ker_lpuart1, SEC_RIFSC(40)), 1413 STM32_GATE_CFG(CK_KER_LPTIM3, ck_ker_lptim3, SEC_RIFSC(19)), 1414 STM32_GATE_CFG(CK_KER_LPTIM4, ck_ker_lptim4, SEC_RIFSC(20)), 1415 STM32_GATE_CFG(CK_KER_LPTIM5, ck_ker_lptim5, SEC_RIFSC(21)), 1416 STM32_GATE_CFG(CK_KER_SDMMC1, ck_ker_sdmmc1, SEC_RIFSC(76)), 1417 STM32_GATE_CFG(CK_KER_SDMMC2, ck_ker_sdmmc2, SEC_RIFSC(77)), 1418 STM32_GATE_CFG(CK_KER_SDMMC3, ck_ker_sdmmc3, SEC_RIFSC(78)), 1419 STM32_GATE_CFG(CK_KER_ETH1, ck_ker_eth1, SEC_RIFSC(60)), 1420 STM32_GATE_CFG(CK_ETH1_STP, ck_ker_eth1stp, SEC_RIFSC(60)), 1421 STM32_GATE_CFG(CK_KER_ETH2, ck_ker_eth2, SEC_RIFSC(61)), 1422 STM32_GATE_CFG(CK_ETH2_STP, ck_ker_eth2stp, SEC_RIFSC(61)), 1423 STM32_GATE_CFG(CK_KER_ETH1PTP, ck_ker_eth1ptp, SEC_RIFSC(60)), 1424 STM32_GATE_CFG(CK_KER_ETH2PTP, ck_ker_eth2ptp, SEC_RIFSC(61)), 1425 STM32_GATE_CFG(CK_ETH1_MAC, ck_ker_eth1mac, SEC_RIFSC(60)), 1426 STM32_GATE_CFG(CK_ETH1_TX, ck_ker_eth1tx, SEC_RIFSC(60)), 1427 STM32_GATE_CFG(CK_ETH1_RX, ck_ker_eth1rx, SEC_RIFSC(60)), 1428 STM32_GATE_CFG(CK_ETH2_MAC, ck_ker_eth2mac, SEC_RIFSC(61)), 1429 STM32_GATE_CFG(CK_ETH2_TX, ck_ker_eth2tx, SEC_RIFSC(61)), 1430 STM32_GATE_CFG(CK_ETH2_RX, ck_ker_eth2rx, SEC_RIFSC(61)), 1431 STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, MP21_RIF_RCC_MCO1), 1432 STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, MP21_RIF_RCC_MCO2), 1433 STM32_COMPOSITE_CFG(CK_KER_ADC1, ck_ker_adc1, SEC_RIFSC(58)), 1434 STM32_COMPOSITE_CFG(CK_KER_ADC2, ck_ker_adc2, SEC_RIFSC(59)), 1435 STM32_COMPOSITE_CFG(CK_KER_USB2PHY1, ck_ker_usb2phy1, SEC_RIFSC(63)), 1436 STM32_COMPOSITE_CFG(CK_KER_USB2PHY2EN, ck_ker_usb2phy2_en, SEC_RIFSC(66)), 1437 STM32_COMPOSITE_CFG(CK_KER_DTS, ck_ker_dts, SEC_RIFSC(107)), 1438 STM32_GATE_CFG(CK_KER_LTDC, ck_ker_ltdc, SEC_RIFSC(80)), 1439 }; 1440 1441 #define RESET_MP21(id, _offset, _bit_idx, _set_clr) \ 1442 [id] = &(struct stm32_reset_cfg){ \ 1443 .offset = (_offset), \ 1444 .bit_idx = (_bit_idx), \ 1445 .set_clr = (_set_clr), \ 1446 } 1447 1448 static const struct stm32_reset_cfg *stm32mp21_reset_cfg[] = { 1449 RESET_MP21(TIM1_R, RCC_TIM1CFGR, 0, 0), 1450 RESET_MP21(TIM2_R, RCC_TIM2CFGR, 0, 0), 1451 RESET_MP21(TIM3_R, RCC_TIM3CFGR, 0, 0), 1452 RESET_MP21(TIM4_R, RCC_TIM4CFGR, 0, 0), 1453 RESET_MP21(TIM5_R, RCC_TIM5CFGR, 0, 0), 1454 RESET_MP21(TIM6_R, RCC_TIM6CFGR, 0, 0), 1455 RESET_MP21(TIM7_R, RCC_TIM7CFGR, 0, 0), 1456 RESET_MP21(TIM8_R, RCC_TIM8CFGR, 0, 0), 1457 RESET_MP21(TIM10_R, RCC_TIM10CFGR, 0, 0), 1458 RESET_MP21(TIM11_R, RCC_TIM11CFGR, 0, 0), 1459 RESET_MP21(TIM12_R, RCC_TIM12CFGR, 0, 0), 1460 RESET_MP21(TIM13_R, RCC_TIM13CFGR, 0, 0), 1461 RESET_MP21(TIM14_R, RCC_TIM14CFGR, 0, 0), 1462 RESET_MP21(TIM15_R, RCC_TIM15CFGR, 0, 0), 1463 RESET_MP21(TIM16_R, RCC_TIM16CFGR, 0, 0), 1464 RESET_MP21(TIM17_R, RCC_TIM17CFGR, 0, 0), 1465 RESET_MP21(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0), 1466 RESET_MP21(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0), 1467 RESET_MP21(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0), 1468 RESET_MP21(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0), 1469 RESET_MP21(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0), 1470 RESET_MP21(SPI1_R, RCC_SPI1CFGR, 0, 0), 1471 RESET_MP21(SPI2_R, RCC_SPI2CFGR, 0, 0), 1472 RESET_MP21(SPI3_R, RCC_SPI3CFGR, 0, 0), 1473 RESET_MP21(SPI4_R, RCC_SPI4CFGR, 0, 0), 1474 RESET_MP21(SPI5_R, RCC_SPI5CFGR, 0, 0), 1475 RESET_MP21(SPI6_R, RCC_SPI6CFGR, 0, 0), 1476 RESET_MP21(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0), 1477 RESET_MP21(USART1_R, RCC_USART1CFGR, 0, 0), 1478 RESET_MP21(USART2_R, RCC_USART2CFGR, 0, 0), 1479 RESET_MP21(USART3_R, RCC_USART3CFGR, 0, 0), 1480 RESET_MP21(UART4_R, RCC_UART4CFGR, 0, 0), 1481 RESET_MP21(UART5_R, RCC_UART5CFGR, 0, 0), 1482 RESET_MP21(USART6_R, RCC_USART6CFGR, 0, 0), 1483 RESET_MP21(UART7_R, RCC_UART7CFGR, 0, 0), 1484 RESET_MP21(LPUART1_R, RCC_LPUART1CFGR, 0, 0), 1485 RESET_MP21(I2C1_R, RCC_I2C1CFGR, 0, 0), 1486 RESET_MP21(I2C2_R, RCC_I2C2CFGR, 0, 0), 1487 RESET_MP21(I2C3_R, RCC_I2C3CFGR, 0, 0), 1488 RESET_MP21(SAI1_R, RCC_SAI1CFGR, 0, 0), 1489 RESET_MP21(SAI2_R, RCC_SAI2CFGR, 0, 0), 1490 RESET_MP21(SAI3_R, RCC_SAI3CFGR, 0, 0), 1491 RESET_MP21(SAI4_R, RCC_SAI4CFGR, 0, 0), 1492 RESET_MP21(MDF1_R, RCC_MDF1CFGR, 0, 0), 1493 RESET_MP21(FDCAN_R, RCC_FDCANCFGR, 0, 0), 1494 RESET_MP21(HDP_R, RCC_HDPCFGR, 0, 0), 1495 RESET_MP21(ADC1_R, RCC_ADC1CFGR, 0, 0), 1496 RESET_MP21(ADC2_R, RCC_ADC2CFGR, 0, 0), 1497 RESET_MP21(ETH1_R, RCC_ETH1CFGR, 0, 0), 1498 RESET_MP21(ETH2_R, RCC_ETH2CFGR, 0, 0), 1499 RESET_MP21(OTG_R, RCC_OTGCFGR, 0, 0), 1500 RESET_MP21(USBH_R, RCC_USBHCFGR, 0, 0), 1501 RESET_MP21(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0), 1502 RESET_MP21(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0), 1503 RESET_MP21(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0), 1504 RESET_MP21(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0), 1505 RESET_MP21(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0), 1506 RESET_MP21(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0), 1507 RESET_MP21(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0), 1508 RESET_MP21(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0), 1509 RESET_MP21(LTDC_R, RCC_LTDCCFGR, 0, 0), 1510 RESET_MP21(CSI_R, RCC_CSICFGR, 0, 0), 1511 RESET_MP21(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0), 1512 RESET_MP21(DCMIPSSI_R, RCC_DCMIPSSICFGR, 0, 0), 1513 RESET_MP21(WWDG1_R, RCC_WWDG1CFGR, 0, 0), 1514 RESET_MP21(VREF_R, RCC_VREFCFGR, 0, 0), 1515 RESET_MP21(DTS_R, RCC_DTSCFGR, 0, 0), 1516 RESET_MP21(CRC_R, RCC_CRCCFGR, 0, 0), 1517 RESET_MP21(SERC_R, RCC_SERCCFGR, 0, 0), 1518 RESET_MP21(I3C1_R, RCC_I3C1CFGR, 0, 0), 1519 RESET_MP21(I3C2_R, RCC_I3C2CFGR, 0, 0), 1520 RESET_MP21(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1), 1521 RESET_MP21(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1), 1522 RESET_MP21(RNG1_R, RCC_RNG1CFGR, 0, 0), 1523 RESET_MP21(RNG2_R, RCC_RNG2CFGR, 0, 0), 1524 RESET_MP21(PKA_R, RCC_PKACFGR, 0, 0), 1525 RESET_MP21(SAES_R, RCC_SAESCFGR, 0, 0), 1526 RESET_MP21(HASH1_R, RCC_HASH1CFGR, 0, 0), 1527 RESET_MP21(HASH2_R, RCC_HASH2CFGR, 0, 0), 1528 RESET_MP21(CRYP1_R, RCC_CRYP1CFGR, 0, 0), 1529 RESET_MP21(CRYP2_R, RCC_CRYP2CFGR, 0, 0), 1530 }; 1531 1532 static u16 stm32mp21_cpt_gate[GATE_NB]; 1533 1534 static struct clk_stm32_clock_data stm32mp21_clock_data = { 1535 .gate_cpt = stm32mp21_cpt_gate, 1536 .gates = stm32mp21_gates, 1537 .muxes = stm32mp21_muxes, 1538 }; 1539 1540 static struct clk_stm32_reset_data stm32mp21_reset_data = { 1541 .reset_lines = stm32mp21_reset_cfg, 1542 .nr_lines = ARRAY_SIZE(stm32mp21_reset_cfg), 1543 }; 1544 1545 static const struct stm32_rcc_match_data stm32mp21_data = { 1546 .tab_clocks = stm32mp21_clock_cfg, 1547 .num_clocks = ARRAY_SIZE(stm32mp21_clock_cfg), 1548 .maxbinding = STM32MP21_LAST_CLK, 1549 .clock_data = &stm32mp21_clock_data, 1550 .reset_data = &stm32mp21_reset_data, 1551 .check_security = &stm32mp21_check_security, 1552 }; 1553 1554 static const struct of_device_id stm32mp21_match_data[] = { 1555 { .compatible = "st,stm32mp21-rcc", .data = &stm32mp21_data, }, 1556 { } 1557 }; 1558 MODULE_DEVICE_TABLE(of, stm32mp21_match_data); 1559 1560 static int stm32mp21_rcc_clocks_probe(struct platform_device *pdev) 1561 { 1562 struct device *dev = &pdev->dev; 1563 void __iomem *base; 1564 1565 base = devm_platform_ioremap_resource(pdev, 0); 1566 if (WARN_ON(IS_ERR(base))) 1567 return PTR_ERR(base); 1568 1569 return stm32_rcc_init(dev, stm32mp21_match_data, base); 1570 } 1571 1572 static struct platform_driver stm32mp21_rcc_clocks_driver = { 1573 .driver = { 1574 .name = "stm32mp21_rcc", 1575 .of_match_table = stm32mp21_match_data, 1576 }, 1577 .probe = stm32mp21_rcc_clocks_probe, 1578 }; 1579 1580 static int __init stm32mp21_clocks_init(void) 1581 { 1582 return platform_driver_register(&stm32mp21_rcc_clocks_driver); 1583 } 1584 1585 core_initcall(stm32mp21_clocks_init); 1586 1587