1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * StarFive JH7110 System-Top-Group Clock Driver 4 * 5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 6 * Copyright (C) 2022 StarFive Technology Co., Ltd. 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/io.h> 11 #include <linux/platform_device.h> 12 13 #include <dt-bindings/clock/starfive,jh7110-crg.h> 14 15 #include "clk-starfive-jh7110.h" 16 17 /* external clocks */ 18 #define JH7110_STGCLK_OSC (JH7110_STGCLK_END + 0) 19 #define JH7110_STGCLK_HIFI4_CORE (JH7110_STGCLK_END + 1) 20 #define JH7110_STGCLK_STG_AXIAHB (JH7110_STGCLK_END + 2) 21 #define JH7110_STGCLK_USB_125M (JH7110_STGCLK_END + 3) 22 #define JH7110_STGCLK_CPU_BUS (JH7110_STGCLK_END + 4) 23 #define JH7110_STGCLK_HIFI4_AXI (JH7110_STGCLK_END + 5) 24 #define JH7110_STGCLK_NOCSTG_BUS (JH7110_STGCLK_END + 6) 25 #define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7) 26 #define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8) 27 28 static const struct jh71x0_clk_data jh7110_stgclk_data[] = { 29 /* hifi4 */ 30 JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0, 31 JH7110_STGCLK_HIFI4_CORE), 32 /* usb */ 33 JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS), 34 JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS), 35 JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB), 36 JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC), 37 JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC), 38 JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M), 39 JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC), 40 /* pci-e */ 41 JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0, 42 JH7110_STGCLK_STG_AXIAHB), 43 JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS), 44 JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB), 45 JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0, 46 JH7110_STGCLK_STG_AXIAHB), 47 JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS), 48 JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB), 49 JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL, 50 JH7110_STGCLK_STG_AXIAHB), 51 /* security */ 52 JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB), 53 JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB), 54 /* stg mtrx */ 55 JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL, 56 JH7110_STGCLK_CPU_BUS), 57 JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL, 58 JH7110_STGCLK_NOCSTG_BUS), 59 JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL, 60 JH7110_STGCLK_STG_AXIAHB), 61 JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL, 62 JH7110_STGCLK_CPU_BUS), 63 JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL, 64 JH7110_STGCLK_NOCSTG_BUS), 65 JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL, 66 JH7110_STGCLK_STG_AXIAHB), 67 JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL, 68 JH7110_STGCLK_HIFI4_AXI), 69 /* e24_rvpi */ 70 JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC), 71 JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB), 72 JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB), 73 /* dw_sgdma1p */ 74 JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB), 75 JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB), 76 }; 77 78 static int jh7110_stgcrg_probe(struct platform_device *pdev) 79 { 80 struct jh71x0_clk_priv *priv; 81 unsigned int idx; 82 int ret; 83 84 priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END), 85 GFP_KERNEL); 86 if (!priv) 87 return -ENOMEM; 88 89 spin_lock_init(&priv->rmw_lock); 90 priv->num_reg = JH7110_STGCLK_END; 91 priv->dev = &pdev->dev; 92 priv->base = devm_platform_ioremap_resource(pdev, 0); 93 if (IS_ERR(priv->base)) 94 return PTR_ERR(priv->base); 95 96 for (idx = 0; idx < JH7110_STGCLK_END; idx++) { 97 u32 max = jh7110_stgclk_data[idx].max; 98 struct clk_parent_data parents[4] = {}; 99 struct clk_init_data init = { 100 .name = jh7110_stgclk_data[idx].name, 101 .ops = starfive_jh71x0_clk_ops(max), 102 .parent_data = parents, 103 .num_parents = 104 ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, 105 .flags = jh7110_stgclk_data[idx].flags, 106 }; 107 struct jh71x0_clk *clk = &priv->reg[idx]; 108 const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = { 109 "osc", 110 "hifi4_core", 111 "stg_axiahb", 112 "usb_125m", 113 "cpu_bus", 114 "hifi4_axi", 115 "nocstg_bus", 116 "apb_bus" 117 }; 118 unsigned int i; 119 120 for (i = 0; i < init.num_parents; i++) { 121 unsigned int pidx = jh7110_stgclk_data[idx].parents[i]; 122 123 if (pidx < JH7110_STGCLK_END) 124 parents[i].hw = &priv->reg[pidx].hw; 125 else if (pidx < JH7110_STGCLK_EXT_END) 126 parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END]; 127 } 128 129 clk->hw.init = &init; 130 clk->idx = idx; 131 clk->max_div = max & JH71X0_CLK_DIV_MASK; 132 133 ret = devm_clk_hw_register(&pdev->dev, &clk->hw); 134 if (ret) 135 return ret; 136 } 137 138 ret = devm_of_clk_add_hw_provider(&pdev->dev, jh71x0_clk_get, priv); 139 if (ret) 140 return ret; 141 142 return jh7110_reset_controller_register(priv, "rst-stg", 2); 143 } 144 145 static const struct of_device_id jh7110_stgcrg_match[] = { 146 { .compatible = "starfive,jh7110-stgcrg" }, 147 { /* sentinel */ } 148 }; 149 MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match); 150 151 static struct platform_driver jh7110_stgcrg_driver = { 152 .probe = jh7110_stgcrg_probe, 153 .driver = { 154 .name = "clk-starfive-jh7110-stg", 155 .of_match_table = jh7110_stgcrg_match, 156 }, 157 }; 158 module_platform_driver(jh7110_stgcrg_driver); 159 160 MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>"); 161 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>"); 162 MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver"); 163 MODULE_LICENSE("GPL"); 164