1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * StarFive JH7110 Image-Signal-Process Clock Driver 4 * 5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/io.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/reset.h> 14 15 #include <dt-bindings/clock/starfive,jh7110-crg.h> 16 17 #include "clk-starfive-jh7110.h" 18 19 /* external clocks */ 20 #define JH7110_ISPCLK_ISP_TOP_CORE (JH7110_ISPCLK_END + 0) 21 #define JH7110_ISPCLK_ISP_TOP_AXI (JH7110_ISPCLK_END + 1) 22 #define JH7110_ISPCLK_NOC_BUS_ISP_AXI (JH7110_ISPCLK_END + 2) 23 #define JH7110_ISPCLK_DVP_CLK (JH7110_ISPCLK_END + 3) 24 #define JH7110_ISPCLK_EXT_END (JH7110_ISPCLK_END + 4) 25 26 static struct clk_bulk_data jh7110_isp_top_clks[] = { 27 { .id = "isp_top_core" }, 28 { .id = "isp_top_axi" } 29 }; 30 31 static const struct jh71x0_clk_data jh7110_ispclk_data[] = { 32 /* syscon */ 33 JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15, 34 JH7110_ISPCLK_ISP_TOP_AXI), 35 JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8, 36 JH7110_ISPCLK_ISP_TOP_CORE), 37 JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK), 38 /* vin */ 39 JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16, 40 JH7110_ISPCLK_ISP_TOP_CORE), 41 JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16, 42 JH7110_ISPCLK_ISP_TOP_CORE), 43 JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60, 44 JH7110_ISPCLK_ISP_TOP_CORE), 45 JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0, 46 JH7110_ISPCLK_DOM4_APB_FUNC), 47 JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE), 48 JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0, 49 JH7110_ISPCLK_MIPI_RX0_PXL), 50 JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0, 51 JH7110_ISPCLK_MIPI_RX0_PXL), 52 JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0, 53 JH7110_ISPCLK_MIPI_RX0_PXL), 54 JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0, 55 JH7110_ISPCLK_MIPI_RX0_PXL), 56 JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 0, 2, 57 JH7110_ISPCLK_MIPI_RX0_PXL, 58 JH7110_ISPCLK_DVP_INV), 59 /* ispv2_top_wrapper */ 60 JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2, 61 JH7110_ISPCLK_MIPI_RX0_PXL, 62 JH7110_ISPCLK_DVP_INV), 63 }; 64 65 static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv) 66 { 67 struct reset_control *top_rsts; 68 69 /* The resets should be shared and other ISP modules will use its. */ 70 top_rsts = devm_reset_control_array_get_shared(priv->dev); 71 if (IS_ERR(top_rsts)) 72 return dev_err_probe(priv->dev, PTR_ERR(top_rsts), 73 "failed to get top resets\n"); 74 75 return reset_control_deassert(top_rsts); 76 } 77 78 #ifdef CONFIG_PM 79 static int jh7110_ispcrg_suspend(struct device *dev) 80 { 81 struct jh7110_top_sysclk *top = dev_get_drvdata(dev); 82 83 clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); 84 85 return 0; 86 } 87 88 static int jh7110_ispcrg_resume(struct device *dev) 89 { 90 struct jh7110_top_sysclk *top = dev_get_drvdata(dev); 91 92 return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); 93 } 94 95 static const struct dev_pm_ops jh7110_ispcrg_pm_ops = { 96 RUNTIME_PM_OPS(jh7110_ispcrg_suspend, jh7110_ispcrg_resume, NULL) 97 }; 98 #endif 99 100 static int jh7110_ispcrg_probe(struct platform_device *pdev) 101 { 102 struct jh71x0_clk_priv *priv; 103 struct jh7110_top_sysclk *top; 104 unsigned int idx; 105 int ret; 106 107 priv = devm_kzalloc(&pdev->dev, 108 struct_size(priv, reg, JH7110_ISPCLK_END), 109 GFP_KERNEL); 110 if (!priv) 111 return -ENOMEM; 112 113 top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL); 114 if (!top) 115 return -ENOMEM; 116 117 spin_lock_init(&priv->rmw_lock); 118 priv->num_reg = JH7110_ISPCLK_END; 119 priv->dev = &pdev->dev; 120 priv->base = devm_platform_ioremap_resource(pdev, 0); 121 if (IS_ERR(priv->base)) 122 return PTR_ERR(priv->base); 123 124 top->top_clks = jh7110_isp_top_clks; 125 top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks); 126 ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks); 127 if (ret) 128 return dev_err_probe(priv->dev, ret, "failed to get main clocks\n"); 129 dev_set_drvdata(priv->dev, top); 130 131 /* enable power domain and clocks */ 132 pm_runtime_enable(priv->dev); 133 ret = pm_runtime_get_sync(priv->dev); 134 if (ret < 0) 135 return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); 136 137 ret = jh7110_isp_top_rst_init(priv); 138 if (ret) 139 goto err_exit; 140 141 for (idx = 0; idx < JH7110_ISPCLK_END; idx++) { 142 u32 max = jh7110_ispclk_data[idx].max; 143 struct clk_parent_data parents[4] = {}; 144 struct clk_init_data init = { 145 .name = jh7110_ispclk_data[idx].name, 146 .ops = starfive_jh71x0_clk_ops(max), 147 .parent_data = parents, 148 .num_parents = 149 ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, 150 .flags = jh7110_ispclk_data[idx].flags, 151 }; 152 struct jh71x0_clk *clk = &priv->reg[idx]; 153 unsigned int i; 154 const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = { 155 "isp_top_core", 156 "isp_top_axi", 157 "noc_bus_isp_axi", 158 "dvp_clk" 159 }; 160 161 for (i = 0; i < init.num_parents; i++) { 162 unsigned int pidx = jh7110_ispclk_data[idx].parents[i]; 163 164 if (pidx < JH7110_ISPCLK_END) 165 parents[i].hw = &priv->reg[pidx].hw; 166 else 167 parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END]; 168 } 169 170 clk->hw.init = &init; 171 clk->idx = idx; 172 clk->max_div = max & JH71X0_CLK_DIV_MASK; 173 174 ret = devm_clk_hw_register(&pdev->dev, &clk->hw); 175 if (ret) 176 goto err_exit; 177 } 178 179 ret = devm_of_clk_add_hw_provider(&pdev->dev, jh71x0_clk_get, priv); 180 if (ret) 181 goto err_exit; 182 183 ret = jh7110_reset_controller_register(priv, "rst-isp", 3); 184 if (ret) 185 goto err_exit; 186 187 return 0; 188 189 err_exit: 190 pm_runtime_put_sync(priv->dev); 191 pm_runtime_disable(priv->dev); 192 return ret; 193 } 194 195 static void jh7110_ispcrg_remove(struct platform_device *pdev) 196 { 197 pm_runtime_put_sync(&pdev->dev); 198 pm_runtime_disable(&pdev->dev); 199 } 200 201 static const struct of_device_id jh7110_ispcrg_match[] = { 202 { .compatible = "starfive,jh7110-ispcrg" }, 203 { /* sentinel */ } 204 }; 205 MODULE_DEVICE_TABLE(of, jh7110_ispcrg_match); 206 207 static struct platform_driver jh7110_ispcrg_driver = { 208 .probe = jh7110_ispcrg_probe, 209 .remove = jh7110_ispcrg_remove, 210 .driver = { 211 .name = "clk-starfive-jh7110-isp", 212 .of_match_table = jh7110_ispcrg_match, 213 .pm = pm_ptr(&jh7110_ispcrg_pm_ops), 214 }, 215 }; 216 module_platform_driver(jh7110_ispcrg_driver); 217 218 MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>"); 219 MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver"); 220 MODULE_LICENSE("GPL"); 221