1 /* 2 * Copyright (C) 2014 STMicroelectronics (R&D) Limited 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 /* 12 * Authors: 13 * Stephen Gallimore <stephen.gallimore@st.com>, 14 * Pankaj Dev <pankaj.dev@st.com>. 15 */ 16 17 #include <linux/slab.h> 18 #include <linux/of_address.h> 19 #include <linux/clk.h> 20 #include <linux/clk-provider.h> 21 22 #include "clkgen.h" 23 24 static DEFINE_SPINLOCK(clkgena_c32_odf_lock); 25 26 /* 27 * Common PLL configuration register bits for PLL800 and PLL1600 C65 28 */ 29 #define C65_MDIV_PLL800_MASK (0xff) 30 #define C65_MDIV_PLL1600_MASK (0x7) 31 #define C65_NDIV_MASK (0xff) 32 #define C65_PDIV_MASK (0x7) 33 34 /* 35 * PLL configuration register bits for PLL3200 C32 36 */ 37 #define C32_NDIV_MASK (0xff) 38 #define C32_IDF_MASK (0x7) 39 #define C32_ODF_MASK (0x3f) 40 #define C32_LDF_MASK (0x7f) 41 42 #define C32_MAX_ODFS (4) 43 44 struct clkgen_pll_data { 45 struct clkgen_field pdn_status; 46 struct clkgen_field locked_status; 47 struct clkgen_field mdiv; 48 struct clkgen_field ndiv; 49 struct clkgen_field pdiv; 50 struct clkgen_field idf; 51 struct clkgen_field ldf; 52 unsigned int num_odfs; 53 struct clkgen_field odf[C32_MAX_ODFS]; 54 struct clkgen_field odf_gate[C32_MAX_ODFS]; 55 const struct clk_ops *ops; 56 }; 57 58 static const struct clk_ops st_pll1600c65_ops; 59 static const struct clk_ops st_pll800c65_ops; 60 static const struct clk_ops stm_pll3200c32_ops; 61 static const struct clk_ops st_pll1200c32_ops; 62 63 static const struct clkgen_pll_data st_pll1600c65_ax = { 64 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19), 65 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31), 66 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0), 67 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8), 68 .ops = &st_pll1600c65_ops 69 }; 70 71 static const struct clkgen_pll_data st_pll800c65_ax = { 72 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19), 73 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31), 74 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0), 75 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8), 76 .pdiv = CLKGEN_FIELD(0x0, C65_PDIV_MASK, 16), 77 .ops = &st_pll800c65_ops 78 }; 79 80 static const struct clkgen_pll_data st_pll3200c32_a1x_0 = { 81 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 31), 82 .locked_status = CLKGEN_FIELD(0x4, 0x1, 31), 83 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 0x0), 84 .idf = CLKGEN_FIELD(0x4, C32_IDF_MASK, 0x0), 85 .num_odfs = 4, 86 .odf = { CLKGEN_FIELD(0x54, C32_ODF_MASK, 4), 87 CLKGEN_FIELD(0x54, C32_ODF_MASK, 10), 88 CLKGEN_FIELD(0x54, C32_ODF_MASK, 16), 89 CLKGEN_FIELD(0x54, C32_ODF_MASK, 22) }, 90 .odf_gate = { CLKGEN_FIELD(0x54, 0x1, 0), 91 CLKGEN_FIELD(0x54, 0x1, 1), 92 CLKGEN_FIELD(0x54, 0x1, 2), 93 CLKGEN_FIELD(0x54, 0x1, 3) }, 94 .ops = &stm_pll3200c32_ops, 95 }; 96 97 static const struct clkgen_pll_data st_pll3200c32_a1x_1 = { 98 .pdn_status = CLKGEN_FIELD(0xC, 0x1, 31), 99 .locked_status = CLKGEN_FIELD(0x10, 0x1, 31), 100 .ndiv = CLKGEN_FIELD(0xC, C32_NDIV_MASK, 0x0), 101 .idf = CLKGEN_FIELD(0x10, C32_IDF_MASK, 0x0), 102 .num_odfs = 4, 103 .odf = { CLKGEN_FIELD(0x58, C32_ODF_MASK, 4), 104 CLKGEN_FIELD(0x58, C32_ODF_MASK, 10), 105 CLKGEN_FIELD(0x58, C32_ODF_MASK, 16), 106 CLKGEN_FIELD(0x58, C32_ODF_MASK, 22) }, 107 .odf_gate = { CLKGEN_FIELD(0x58, 0x1, 0), 108 CLKGEN_FIELD(0x58, 0x1, 1), 109 CLKGEN_FIELD(0x58, 0x1, 2), 110 CLKGEN_FIELD(0x58, 0x1, 3) }, 111 .ops = &stm_pll3200c32_ops, 112 }; 113 114 /* 415 specific */ 115 static const struct clkgen_pll_data st_pll3200c32_a9_415 = { 116 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), 117 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0), 118 .ndiv = CLKGEN_FIELD(0x0, C32_NDIV_MASK, 9), 119 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 22), 120 .num_odfs = 1, 121 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 3) }, 122 .odf_gate = { CLKGEN_FIELD(0x0, 0x1, 28) }, 123 .ops = &stm_pll3200c32_ops, 124 }; 125 126 static const struct clkgen_pll_data st_pll3200c32_ddr_415 = { 127 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), 128 .locked_status = CLKGEN_FIELD(0x100, 0x1, 0), 129 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), 130 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25), 131 .num_odfs = 2, 132 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8), 133 CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) }, 134 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28), 135 CLKGEN_FIELD(0x4, 0x1, 29) }, 136 .ops = &stm_pll3200c32_ops, 137 }; 138 139 static const struct clkgen_pll_data st_pll1200c32_gpu_415 = { 140 .pdn_status = CLKGEN_FIELD(0x144, 0x1, 3), 141 .locked_status = CLKGEN_FIELD(0x168, 0x1, 0), 142 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3), 143 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0), 144 .num_odfs = 0, 145 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) }, 146 .ops = &st_pll1200c32_ops, 147 }; 148 149 /* 416 specific */ 150 static const struct clkgen_pll_data st_pll3200c32_a9_416 = { 151 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), 152 .locked_status = CLKGEN_FIELD(0x6C, 0x1, 0), 153 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), 154 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25), 155 .num_odfs = 1, 156 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8) }, 157 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28) }, 158 .ops = &stm_pll3200c32_ops, 159 }; 160 161 static const struct clkgen_pll_data st_pll3200c32_ddr_416 = { 162 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 0), 163 .locked_status = CLKGEN_FIELD(0x10C, 0x1, 0), 164 .ndiv = CLKGEN_FIELD(0x8, C32_NDIV_MASK, 0), 165 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 25), 166 .num_odfs = 2, 167 .odf = { CLKGEN_FIELD(0x8, C32_ODF_MASK, 8), 168 CLKGEN_FIELD(0x8, C32_ODF_MASK, 14) }, 169 .odf_gate = { CLKGEN_FIELD(0x4, 0x1, 28), 170 CLKGEN_FIELD(0x4, 0x1, 29) }, 171 .ops = &stm_pll3200c32_ops, 172 }; 173 174 static const struct clkgen_pll_data st_pll1200c32_gpu_416 = { 175 .pdn_status = CLKGEN_FIELD(0x8E4, 0x1, 3), 176 .locked_status = CLKGEN_FIELD(0x90C, 0x1, 0), 177 .ldf = CLKGEN_FIELD(0x0, C32_LDF_MASK, 3), 178 .idf = CLKGEN_FIELD(0x0, C32_IDF_MASK, 0), 179 .num_odfs = 0, 180 .odf = { CLKGEN_FIELD(0x0, C32_ODF_MASK, 10) }, 181 .ops = &st_pll1200c32_ops, 182 }; 183 184 static const struct clkgen_pll_data st_pll3200c32_407_a0 = { 185 /* 407 A0 */ 186 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), 187 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24), 188 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16), 189 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0), 190 .num_odfs = 1, 191 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) }, 192 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) }, 193 .ops = &stm_pll3200c32_ops, 194 }; 195 196 static const struct clkgen_pll_data st_pll3200c32_cx_0 = { 197 /* 407 C0 PLL0 */ 198 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), 199 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24), 200 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16), 201 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0), 202 .num_odfs = 1, 203 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) }, 204 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) }, 205 .ops = &stm_pll3200c32_ops, 206 }; 207 208 static const struct clkgen_pll_data st_pll3200c32_cx_1 = { 209 /* 407 C0 PLL1 */ 210 .pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8), 211 .locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24), 212 .ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16), 213 .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0), 214 .num_odfs = 1, 215 .odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) }, 216 .odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) }, 217 .ops = &stm_pll3200c32_ops, 218 }; 219 220 static const struct clkgen_pll_data st_pll3200c32_407_a9 = { 221 /* 407 A9 */ 222 .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0), 223 .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0), 224 .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0), 225 .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25), 226 .num_odfs = 1, 227 .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) }, 228 .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) }, 229 .ops = &stm_pll3200c32_ops, 230 }; 231 232 /** 233 * DOC: Clock Generated by PLL, rate set and enabled by bootloader 234 * 235 * Traits of this clock: 236 * prepare - clk_(un)prepare only ensures parent is (un)prepared 237 * enable - clk_enable/disable only ensures parent is enabled 238 * rate - rate is fixed. No clk_set_rate support 239 * parent - fixed parent. No clk_set_parent support 240 */ 241 242 /** 243 * PLL clock that is integrated in the ClockGenA instances on the STiH415 244 * and STiH416. 245 * 246 * @hw: handle between common and hardware-specific interfaces. 247 * @type: PLL instance type. 248 * @regs_base: base of the PLL configuration register(s). 249 * 250 */ 251 struct clkgen_pll { 252 struct clk_hw hw; 253 struct clkgen_pll_data *data; 254 void __iomem *regs_base; 255 }; 256 257 #define to_clkgen_pll(_hw) container_of(_hw, struct clkgen_pll, hw) 258 259 static int clkgen_pll_is_locked(struct clk_hw *hw) 260 { 261 struct clkgen_pll *pll = to_clkgen_pll(hw); 262 u32 locked = CLKGEN_READ(pll, locked_status); 263 264 return !!locked; 265 } 266 267 static int clkgen_pll_is_enabled(struct clk_hw *hw) 268 { 269 struct clkgen_pll *pll = to_clkgen_pll(hw); 270 u32 poweroff = CLKGEN_READ(pll, pdn_status); 271 return !poweroff; 272 } 273 274 static unsigned long recalc_stm_pll800c65(struct clk_hw *hw, 275 unsigned long parent_rate) 276 { 277 struct clkgen_pll *pll = to_clkgen_pll(hw); 278 unsigned long mdiv, ndiv, pdiv; 279 unsigned long rate; 280 uint64_t res; 281 282 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw)) 283 return 0; 284 285 pdiv = CLKGEN_READ(pll, pdiv); 286 mdiv = CLKGEN_READ(pll, mdiv); 287 ndiv = CLKGEN_READ(pll, ndiv); 288 289 if (!mdiv) 290 mdiv++; /* mdiv=0 or 1 => MDIV=1 */ 291 292 res = (uint64_t)2 * (uint64_t)parent_rate * (uint64_t)ndiv; 293 rate = (unsigned long)div64_u64(res, mdiv * (1 << pdiv)); 294 295 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 296 297 return rate; 298 299 } 300 301 static unsigned long recalc_stm_pll1600c65(struct clk_hw *hw, 302 unsigned long parent_rate) 303 { 304 struct clkgen_pll *pll = to_clkgen_pll(hw); 305 unsigned long mdiv, ndiv; 306 unsigned long rate; 307 308 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw)) 309 return 0; 310 311 mdiv = CLKGEN_READ(pll, mdiv); 312 ndiv = CLKGEN_READ(pll, ndiv); 313 314 if (!mdiv) 315 mdiv = 1; 316 317 /* Note: input is divided by 1000 to avoid overflow */ 318 rate = ((2 * (parent_rate / 1000) * ndiv) / mdiv) * 1000; 319 320 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 321 322 return rate; 323 } 324 325 static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw, 326 unsigned long parent_rate) 327 { 328 struct clkgen_pll *pll = to_clkgen_pll(hw); 329 unsigned long ndiv, idf; 330 unsigned long rate = 0; 331 332 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw)) 333 return 0; 334 335 ndiv = CLKGEN_READ(pll, ndiv); 336 idf = CLKGEN_READ(pll, idf); 337 338 if (idf) 339 /* Note: input is divided to avoid overflow */ 340 rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000; 341 342 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 343 344 return rate; 345 } 346 347 static unsigned long recalc_stm_pll1200c32(struct clk_hw *hw, 348 unsigned long parent_rate) 349 { 350 struct clkgen_pll *pll = to_clkgen_pll(hw); 351 unsigned long odf, ldf, idf; 352 unsigned long rate; 353 354 if (!clkgen_pll_is_enabled(hw) || !clkgen_pll_is_locked(hw)) 355 return 0; 356 357 odf = CLKGEN_READ(pll, odf[0]); 358 ldf = CLKGEN_READ(pll, ldf); 359 idf = CLKGEN_READ(pll, idf); 360 361 if (!idf) /* idf==0 means 1 */ 362 idf = 1; 363 if (!odf) /* odf==0 means 1 */ 364 odf = 1; 365 366 /* Note: input is divided by 1000 to avoid overflow */ 367 rate = (((parent_rate / 1000) * ldf) / (odf * idf)) * 1000; 368 369 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 370 371 return rate; 372 } 373 374 static const struct clk_ops st_pll1600c65_ops = { 375 .is_enabled = clkgen_pll_is_enabled, 376 .recalc_rate = recalc_stm_pll1600c65, 377 }; 378 379 static const struct clk_ops st_pll800c65_ops = { 380 .is_enabled = clkgen_pll_is_enabled, 381 .recalc_rate = recalc_stm_pll800c65, 382 }; 383 384 static const struct clk_ops stm_pll3200c32_ops = { 385 .is_enabled = clkgen_pll_is_enabled, 386 .recalc_rate = recalc_stm_pll3200c32, 387 }; 388 389 static const struct clk_ops st_pll1200c32_ops = { 390 .is_enabled = clkgen_pll_is_enabled, 391 .recalc_rate = recalc_stm_pll1200c32, 392 }; 393 394 static struct clk * __init clkgen_pll_register(const char *parent_name, 395 struct clkgen_pll_data *pll_data, 396 void __iomem *reg, 397 const char *clk_name) 398 { 399 struct clkgen_pll *pll; 400 struct clk *clk; 401 struct clk_init_data init; 402 403 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 404 if (!pll) 405 return ERR_PTR(-ENOMEM); 406 407 init.name = clk_name; 408 init.ops = pll_data->ops; 409 410 init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE; 411 init.parent_names = &parent_name; 412 init.num_parents = 1; 413 414 pll->data = pll_data; 415 pll->regs_base = reg; 416 pll->hw.init = &init; 417 418 clk = clk_register(NULL, &pll->hw); 419 if (IS_ERR(clk)) { 420 kfree(pll); 421 return clk; 422 } 423 424 pr_debug("%s: parent %s rate %lu\n", 425 __clk_get_name(clk), 426 __clk_get_name(clk_get_parent(clk)), 427 clk_get_rate(clk)); 428 429 return clk; 430 } 431 432 static struct clk * __init clkgen_c65_lsdiv_register(const char *parent_name, 433 const char *clk_name) 434 { 435 struct clk *clk; 436 437 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, 1, 2); 438 if (IS_ERR(clk)) 439 return clk; 440 441 pr_debug("%s: parent %s rate %lu\n", 442 __clk_get_name(clk), 443 __clk_get_name(clk_get_parent(clk)), 444 clk_get_rate(clk)); 445 return clk; 446 } 447 448 static void __iomem * __init clkgen_get_register_base( 449 struct device_node *np) 450 { 451 struct device_node *pnode; 452 void __iomem *reg = NULL; 453 454 pnode = of_get_parent(np); 455 if (!pnode) 456 return NULL; 457 458 reg = of_iomap(pnode, 0); 459 460 of_node_put(pnode); 461 return reg; 462 } 463 464 #define CLKGENAx_PLL0_OFFSET 0x0 465 #define CLKGENAx_PLL1_OFFSET 0x4 466 467 static void __init clkgena_c65_pll_setup(struct device_node *np) 468 { 469 const int num_pll_outputs = 3; 470 struct clk_onecell_data *clk_data; 471 const char *parent_name; 472 void __iomem *reg; 473 const char *clk_name; 474 475 parent_name = of_clk_get_parent_name(np, 0); 476 if (!parent_name) 477 return; 478 479 reg = clkgen_get_register_base(np); 480 if (!reg) 481 return; 482 483 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 484 if (!clk_data) 485 return; 486 487 clk_data->clk_num = num_pll_outputs; 488 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), 489 GFP_KERNEL); 490 491 if (!clk_data->clks) 492 goto err; 493 494 if (of_property_read_string_index(np, "clock-output-names", 495 0, &clk_name)) 496 goto err; 497 498 /* 499 * PLL0 HS (high speed) output 500 */ 501 clk_data->clks[0] = clkgen_pll_register(parent_name, 502 (struct clkgen_pll_data *) &st_pll1600c65_ax, 503 reg + CLKGENAx_PLL0_OFFSET, clk_name); 504 505 if (IS_ERR(clk_data->clks[0])) 506 goto err; 507 508 if (of_property_read_string_index(np, "clock-output-names", 509 1, &clk_name)) 510 goto err; 511 512 /* 513 * PLL0 LS (low speed) output, which is a fixed divide by 2 of the 514 * high speed output. 515 */ 516 clk_data->clks[1] = clkgen_c65_lsdiv_register(__clk_get_name 517 (clk_data->clks[0]), 518 clk_name); 519 520 if (IS_ERR(clk_data->clks[1])) 521 goto err; 522 523 if (of_property_read_string_index(np, "clock-output-names", 524 2, &clk_name)) 525 goto err; 526 527 /* 528 * PLL1 output 529 */ 530 clk_data->clks[2] = clkgen_pll_register(parent_name, 531 (struct clkgen_pll_data *) &st_pll800c65_ax, 532 reg + CLKGENAx_PLL1_OFFSET, clk_name); 533 534 if (IS_ERR(clk_data->clks[2])) 535 goto err; 536 537 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 538 return; 539 540 err: 541 kfree(clk_data->clks); 542 kfree(clk_data); 543 } 544 CLK_OF_DECLARE(clkgena_c65_plls, 545 "st,clkgena-plls-c65", clkgena_c65_pll_setup); 546 547 static struct clk * __init clkgen_odf_register(const char *parent_name, 548 void __iomem *reg, 549 struct clkgen_pll_data *pll_data, 550 int odf, 551 spinlock_t *odf_lock, 552 const char *odf_name) 553 { 554 struct clk *clk; 555 unsigned long flags; 556 struct clk_gate *gate; 557 struct clk_divider *div; 558 559 flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; 560 561 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 562 if (!gate) 563 return ERR_PTR(-ENOMEM); 564 565 gate->flags = CLK_GATE_SET_TO_DISABLE; 566 gate->reg = reg + pll_data->odf_gate[odf].offset; 567 gate->bit_idx = pll_data->odf_gate[odf].shift; 568 gate->lock = odf_lock; 569 570 div = kzalloc(sizeof(*div), GFP_KERNEL); 571 if (!div) { 572 kfree(gate); 573 return ERR_PTR(-ENOMEM); 574 } 575 576 div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; 577 div->reg = reg + pll_data->odf[odf].offset; 578 div->shift = pll_data->odf[odf].shift; 579 div->width = fls(pll_data->odf[odf].mask); 580 div->lock = odf_lock; 581 582 clk = clk_register_composite(NULL, odf_name, &parent_name, 1, 583 NULL, NULL, 584 &div->hw, &clk_divider_ops, 585 &gate->hw, &clk_gate_ops, 586 flags); 587 if (IS_ERR(clk)) 588 return clk; 589 590 pr_debug("%s: parent %s rate %lu\n", 591 __clk_get_name(clk), 592 __clk_get_name(clk_get_parent(clk)), 593 clk_get_rate(clk)); 594 return clk; 595 } 596 597 static const struct of_device_id c32_pll_of_match[] = { 598 { 599 .compatible = "st,plls-c32-a1x-0", 600 .data = &st_pll3200c32_a1x_0, 601 }, 602 { 603 .compatible = "st,plls-c32-a1x-1", 604 .data = &st_pll3200c32_a1x_1, 605 }, 606 { 607 .compatible = "st,stih415-plls-c32-a9", 608 .data = &st_pll3200c32_a9_415, 609 }, 610 { 611 .compatible = "st,stih415-plls-c32-ddr", 612 .data = &st_pll3200c32_ddr_415, 613 }, 614 { 615 .compatible = "st,stih416-plls-c32-a9", 616 .data = &st_pll3200c32_a9_416, 617 }, 618 { 619 .compatible = "st,stih416-plls-c32-ddr", 620 .data = &st_pll3200c32_ddr_416, 621 }, 622 { 623 .compatible = "st,stih407-plls-c32-a0", 624 .data = &st_pll3200c32_407_a0, 625 }, 626 { 627 .compatible = "st,plls-c32-cx_0", 628 .data = &st_pll3200c32_cx_0, 629 }, 630 { 631 .compatible = "st,plls-c32-cx_1", 632 .data = &st_pll3200c32_cx_1, 633 }, 634 { 635 .compatible = "st,stih407-plls-c32-a9", 636 .data = &st_pll3200c32_407_a9, 637 }, 638 {} 639 }; 640 641 static void __init clkgen_c32_pll_setup(struct device_node *np) 642 { 643 const struct of_device_id *match; 644 struct clk *clk; 645 const char *parent_name, *pll_name; 646 void __iomem *pll_base; 647 int num_odfs, odf; 648 struct clk_onecell_data *clk_data; 649 struct clkgen_pll_data *data; 650 651 match = of_match_node(c32_pll_of_match, np); 652 if (!match) { 653 pr_err("%s: No matching data\n", __func__); 654 return; 655 } 656 657 data = (struct clkgen_pll_data *) match->data; 658 659 parent_name = of_clk_get_parent_name(np, 0); 660 if (!parent_name) 661 return; 662 663 pll_base = clkgen_get_register_base(np); 664 if (!pll_base) 665 return; 666 667 clk = clkgen_pll_register(parent_name, data, pll_base, np->name); 668 if (IS_ERR(clk)) 669 return; 670 671 pll_name = __clk_get_name(clk); 672 673 num_odfs = data->num_odfs; 674 675 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 676 if (!clk_data) 677 return; 678 679 clk_data->clk_num = num_odfs; 680 clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *), 681 GFP_KERNEL); 682 683 if (!clk_data->clks) 684 goto err; 685 686 for (odf = 0; odf < num_odfs; odf++) { 687 struct clk *clk; 688 const char *clk_name; 689 690 if (of_property_read_string_index(np, "clock-output-names", 691 odf, &clk_name)) 692 return; 693 694 clk = clkgen_odf_register(pll_name, pll_base, data, 695 odf, &clkgena_c32_odf_lock, clk_name); 696 if (IS_ERR(clk)) 697 goto err; 698 699 clk_data->clks[odf] = clk; 700 } 701 702 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 703 return; 704 705 err: 706 kfree(pll_name); 707 kfree(clk_data->clks); 708 kfree(clk_data); 709 } 710 CLK_OF_DECLARE(clkgen_c32_pll, "st,clkgen-plls-c32", clkgen_c32_pll_setup); 711 712 static const struct of_device_id c32_gpu_pll_of_match[] = { 713 { 714 .compatible = "st,stih415-gpu-pll-c32", 715 .data = &st_pll1200c32_gpu_415, 716 }, 717 { 718 .compatible = "st,stih416-gpu-pll-c32", 719 .data = &st_pll1200c32_gpu_416, 720 }, 721 {} 722 }; 723 724 static void __init clkgengpu_c32_pll_setup(struct device_node *np) 725 { 726 const struct of_device_id *match; 727 struct clk *clk; 728 const char *parent_name; 729 void __iomem *reg; 730 const char *clk_name; 731 struct clkgen_pll_data *data; 732 733 match = of_match_node(c32_gpu_pll_of_match, np); 734 if (!match) { 735 pr_err("%s: No matching data\n", __func__); 736 return; 737 } 738 739 data = (struct clkgen_pll_data *)match->data; 740 741 parent_name = of_clk_get_parent_name(np, 0); 742 if (!parent_name) 743 return; 744 745 reg = clkgen_get_register_base(np); 746 if (!reg) 747 return; 748 749 if (of_property_read_string_index(np, "clock-output-names", 750 0, &clk_name)) 751 return; 752 753 /* 754 * PLL 1200MHz output 755 */ 756 clk = clkgen_pll_register(parent_name, data, reg, clk_name); 757 758 if (!IS_ERR(clk)) 759 of_clk_add_provider(np, of_clk_src_simple_get, clk); 760 761 return; 762 } 763 CLK_OF_DECLARE(clkgengpu_c32_pll, 764 "st,clkgengpu-pll-c32", clkgengpu_c32_pll_setup); 765