1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Unisoc UMS512 clock driver 4 * 5 * Copyright (C) 2022 Unisoc, Inc. 6 * Author: Xiaolong Zhang <xiaolong.zhang@unisoc.com> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 16 #include <dt-bindings/clock/sprd,ums512-clk.h> 17 18 #include "common.h" 19 #include "composite.h" 20 #include "div.h" 21 #include "gate.h" 22 #include "mux.h" 23 #include "pll.h" 24 25 #define UMS512_MUX_FLAG \ 26 (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT) 27 28 /* pll gate clock */ 29 /* some pll clocks configure CLK_IGNORE_UNUSED because hw dvfs does not call 30 * clock interface. hw dvfs can not gate the pll clock. 31 */ 32 static CLK_FIXED_FACTOR_FW_NAME(clk_26m_aud, "clk-26m-aud", "ext-26m", 1, 1, 0); 33 static CLK_FIXED_FACTOR_FW_NAME(clk_13m, "clk-13m", "ext-26m", 2, 1, 0); 34 static CLK_FIXED_FACTOR_FW_NAME(clk_6m5, "clk-6m5", "ext-26m", 4, 1, 0); 35 static CLK_FIXED_FACTOR_FW_NAME(clk_4m3, "clk-4m3", "ext-26m", 6, 1, 0); 36 static CLK_FIXED_FACTOR_FW_NAME(clk_2m, "clk-2m", "ext-26m", 13, 1, 0); 37 static CLK_FIXED_FACTOR_FW_NAME(clk_1m, "clk-1m", "ext-26m", 26, 1, 0); 38 static CLK_FIXED_FACTOR_FW_NAME(clk_250k, "clk-250k", "ext-26m", 104, 1, 0); 39 static CLK_FIXED_FACTOR_FW_NAME(rco_25m, "rco-25m", "rco-100m", 4, 1, 0); 40 static CLK_FIXED_FACTOR_FW_NAME(rco_4m, "rco-4m", "rco-100m", 25, 1, 0); 41 static CLK_FIXED_FACTOR_FW_NAME(rco_2m, "rco-2m", "rco-100m", 50, 1, 0); 42 static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x8c, 43 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 44 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98, 45 0x1000, BIT(0), 0, 0, 240); 46 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x9c, 47 0x1000, BIT(0), 0, 0, 240); 48 static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0xa0, 49 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 50 static SPRD_PLL_SC_GATE_CLK_FW_NAME(twpll_gate, "twpll-gate", "ext-26m", 0xa4, 51 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 52 static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8, 53 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 54 static SPRD_PLL_SC_GATE_CLK_FW_NAME(rpll_gate, "rpll-gate", "ext-26m", 0xac, 55 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 56 static SPRD_PLL_SC_GATE_CLK_FW_NAME(cppll_gate, "cppll-gate", "ext-26m", 0xe4, 57 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 58 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x190, 59 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 60 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x194, 61 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 62 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x198, 63 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240); 64 65 static struct sprd_clk_common *ums512_pmu_gate_clks[] = { 66 /* address base is 0x327e0000 */ 67 &isppll_gate.common, 68 &dpll0_gate.common, 69 &dpll1_gate.common, 70 &lpll_gate.common, 71 &twpll_gate.common, 72 &gpll_gate.common, 73 &rpll_gate.common, 74 &cppll_gate.common, 75 &mpll0_gate.common, 76 &mpll1_gate.common, 77 &mpll2_gate.common, 78 }; 79 80 static struct clk_hw_onecell_data ums512_pmu_gate_hws = { 81 .hws = { 82 [CLK_26M_AUD] = &clk_26m_aud.hw, 83 [CLK_13M] = &clk_13m.hw, 84 [CLK_6M5] = &clk_6m5.hw, 85 [CLK_4M3] = &clk_4m3.hw, 86 [CLK_2M] = &clk_2m.hw, 87 [CLK_1M] = &clk_1m.hw, 88 [CLK_250K] = &clk_250k.hw, 89 [CLK_RCO_25M] = &rco_25m.hw, 90 [CLK_RCO_4M] = &rco_4m.hw, 91 [CLK_RCO_2M] = &rco_2m.hw, 92 [CLK_ISPPLL_GATE] = &isppll_gate.common.hw, 93 [CLK_DPLL0_GATE] = &dpll0_gate.common.hw, 94 [CLK_DPLL1_GATE] = &dpll1_gate.common.hw, 95 [CLK_LPLL_GATE] = &lpll_gate.common.hw, 96 [CLK_TWPLL_GATE] = &twpll_gate.common.hw, 97 [CLK_GPLL_GATE] = &gpll_gate.common.hw, 98 [CLK_RPLL_GATE] = &rpll_gate.common.hw, 99 [CLK_CPPLL_GATE] = &cppll_gate.common.hw, 100 [CLK_MPLL0_GATE] = &mpll0_gate.common.hw, 101 [CLK_MPLL1_GATE] = &mpll1_gate.common.hw, 102 [CLK_MPLL2_GATE] = &mpll2_gate.common.hw, 103 }, 104 .num = CLK_PMU_GATE_NUM, 105 }; 106 107 static struct sprd_clk_desc ums512_pmu_gate_desc = { 108 .clk_clks = ums512_pmu_gate_clks, 109 .num_clk_clks = ARRAY_SIZE(ums512_pmu_gate_clks), 110 .hw_clks = &ums512_pmu_gate_hws, 111 }; 112 113 /* pll clock at g0 */ 114 static const u64 itable_dpll0[7] = { 6, 0, 0, 115 1173000000ULL, 1475000000ULL, 116 1855000000ULL, 1866000000ULL }; 117 118 static struct clk_bit_field f_dpll0[PLL_FACT_MAX] = { 119 { .shift = 18, .width = 1 }, /* lock_done */ 120 { .shift = 0, .width = 1 }, /* div_s */ 121 { .shift = 67, .width = 1 }, /* mod_en */ 122 { .shift = 1, .width = 1 }, /* sdm_en */ 123 { .shift = 0, .width = 0 }, /* refin */ 124 { .shift = 4, .width = 3 }, /* icp */ 125 { .shift = 7, .width = 11 }, /* n */ 126 { .shift = 55, .width = 7 }, /* nint */ 127 { .shift = 32, .width = 23}, /* kint */ 128 { .shift = 0, .width = 0 }, /* prediv */ 129 { .shift = 0, .width = 0 }, /* postdiv */ 130 }; 131 static SPRD_PLL_HW(dpll0, "dpll0", &dpll0_gate.common.hw, 0x4, 3, 132 itable_dpll0, f_dpll0, 240, 1000, 1000, 0, 0); 133 static CLK_FIXED_FACTOR_HW(dpll0_58m31, "dpll0-58m31", &dpll0.common.hw, 134 32, 1, 0); 135 136 static struct sprd_clk_common *ums512_g0_pll_clks[] = { 137 /* address base is 0x32390000 */ 138 &dpll0.common, 139 }; 140 141 static struct clk_hw_onecell_data ums512_g0_pll_hws = { 142 .hws = { 143 [CLK_DPLL0] = &dpll0.common.hw, 144 [CLK_DPLL0_58M31] = &dpll0_58m31.hw, 145 }, 146 .num = CLK_ANLG_PHY_G0_NUM, 147 }; 148 149 static struct sprd_clk_desc ums512_g0_pll_desc = { 150 .clk_clks = ums512_g0_pll_clks, 151 .num_clk_clks = ARRAY_SIZE(ums512_g0_pll_clks), 152 .hw_clks = &ums512_g0_pll_hws, 153 }; 154 155 /* pll clock at g2 */ 156 static const u64 itable_mpll[8] = { 7, 0, 157 1400000000ULL, 1600000000ULL, 158 1800000000ULL, 2000000000ULL, 159 2200000000ULL, 2500000000ULL }; 160 161 static struct clk_bit_field f_mpll[PLL_FACT_MAX] = { 162 { .shift = 17, .width = 1 }, /* lock_done */ 163 { .shift = 0, .width = 1 }, /* div_s */ 164 { .shift = 67, .width = 1 }, /* mod_en */ 165 { .shift = 1, .width = 1 }, /* sdm_en */ 166 { .shift = 0, .width = 0 }, /* refin */ 167 { .shift = 2, .width = 3 }, /* icp */ 168 { .shift = 5, .width = 11 }, /* n */ 169 { .shift = 55, .width = 7 }, /* nint */ 170 { .shift = 32, .width = 23}, /* kint */ 171 { .shift = 0, .width = 0 }, /* prediv */ 172 { .shift = 77, .width = 1 }, /* postdiv */ 173 }; 174 static SPRD_PLL_HW(mpll1, "mpll1", &mpll1_gate.common.hw, 0x0, 3, 175 itable_mpll, f_mpll, 240, 1000, 1000, 1, 1200000000); 176 static CLK_FIXED_FACTOR_HW(mpll1_63m38, "mpll1-63m38", &mpll1.common.hw, 177 32, 1, 0); 178 179 static struct sprd_clk_common *ums512_g2_pll_clks[] = { 180 /* address base is 0x323B0000 */ 181 &mpll1.common, 182 }; 183 184 static struct clk_hw_onecell_data ums512_g2_pll_hws = { 185 .hws = { 186 [CLK_MPLL1] = &mpll1.common.hw, 187 [CLK_MPLL1_63M38] = &mpll1_63m38.hw, 188 }, 189 .num = CLK_ANLG_PHY_G2_NUM, 190 }; 191 192 static struct sprd_clk_desc ums512_g2_pll_desc = { 193 .clk_clks = ums512_g2_pll_clks, 194 .num_clk_clks = ARRAY_SIZE(ums512_g2_pll_clks), 195 .hw_clks = &ums512_g2_pll_hws, 196 }; 197 198 /* pll at g3 */ 199 static const u64 itable[8] = { 7, 0, 0, 200 900000000ULL, 1100000000ULL, 201 1300000000ULL, 1500000000ULL, 202 1600000000ULL }; 203 204 static struct clk_bit_field f_pll[PLL_FACT_MAX] = { 205 { .shift = 18, .width = 1 }, /* lock_done */ 206 { .shift = 0, .width = 1 }, /* div_s */ 207 { .shift = 67, .width = 1 }, /* mod_en */ 208 { .shift = 1, .width = 1 }, /* sdm_en */ 209 { .shift = 0, .width = 0 }, /* refin */ 210 { .shift = 2, .width = 3 }, /* icp */ 211 { .shift = 5, .width = 11 }, /* n */ 212 { .shift = 55, .width = 7 }, /* nint */ 213 { .shift = 32, .width = 23}, /* kint */ 214 { .shift = 0, .width = 0 }, /* prediv */ 215 { .shift = 77, .width = 1 }, /* postdiv */ 216 }; 217 218 static SPRD_PLL_FW_NAME(rpll, "rpll", "ext-26m", 0x0, 3, 219 itable, f_pll, 240, 1000, 1000, 1, 750000000); 220 221 static SPRD_SC_GATE_CLK_FW_NAME(audio_gate, "audio-gate", "ext-26m", 0x24, 222 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); 223 224 static struct clk_bit_field f_mpll2[PLL_FACT_MAX] = { 225 { .shift = 16, .width = 1 }, /* lock_done */ 226 { .shift = 0, .width = 1 }, /* div_s */ 227 { .shift = 67, .width = 1 }, /* mod_en */ 228 { .shift = 1, .width = 1 }, /* sdm_en */ 229 { .shift = 0, .width = 0 }, /* refin */ 230 { .shift = 2, .width = 3 }, /* icp */ 231 { .shift = 5, .width = 11 }, /* n */ 232 { .shift = 55, .width = 7 }, /* nint */ 233 { .shift = 32, .width = 23}, /* kint */ 234 { .shift = 0, .width = 0 }, /* prediv */ 235 { .shift = 77, .width = 1 }, /* postdiv */ 236 }; 237 static SPRD_PLL_HW(mpll0, "mpll0", &mpll0_gate.common.hw, 0x54, 3, 238 itable_mpll, f_mpll, 240, 1000, 1000, 1, 1200000000); 239 static CLK_FIXED_FACTOR_HW(mpll0_56m88, "mpll0-56m88", &mpll0.common.hw, 240 32, 1, 0); 241 242 static const u64 itable_mpll2[6] = { 5, 243 1200000000ULL, 1400000000ULL, 244 1600000000ULL, 1800000000ULL, 245 2000000000ULL }; 246 247 static SPRD_PLL_HW(mpll2, "mpll2", &mpll2_gate.common.hw, 0x9c, 3, 248 itable_mpll2, f_mpll2, 240, 1000, 1000, 1, 1000000000); 249 static CLK_FIXED_FACTOR_HW(mpll2_47m13, "mpll2-47m13", &mpll2.common.hw, 250 32, 1, 0); 251 252 static struct sprd_clk_common *ums512_g3_pll_clks[] = { 253 /* address base is 0x323c0000 */ 254 &rpll.common, 255 &audio_gate.common, 256 &mpll0.common, 257 &mpll2.common, 258 }; 259 260 static struct clk_hw_onecell_data ums512_g3_pll_hws = { 261 .hws = { 262 [CLK_RPLL] = &rpll.common.hw, 263 [CLK_AUDIO_GATE] = &audio_gate.common.hw, 264 [CLK_MPLL0] = &mpll0.common.hw, 265 [CLK_MPLL0_56M88] = &mpll0_56m88.hw, 266 [CLK_MPLL2] = &mpll2.common.hw, 267 [CLK_MPLL2_47M13] = &mpll2_47m13.hw, 268 }, 269 .num = CLK_ANLG_PHY_G3_NUM, 270 }; 271 272 static struct sprd_clk_desc ums512_g3_pll_desc = { 273 .clk_clks = ums512_g3_pll_clks, 274 .num_clk_clks = ARRAY_SIZE(ums512_g3_pll_clks), 275 .hw_clks = &ums512_g3_pll_hws, 276 }; 277 278 /* pll clock at gc */ 279 static SPRD_PLL_FW_NAME(twpll, "twpll", "ext-26m", 0x0, 3, 280 itable, f_pll, 240, 1000, 1000, 1, 750000000); 281 static CLK_FIXED_FACTOR_HW(twpll_768m, "twpll-768m", &twpll.common.hw, 282 2, 1, 0); 283 static CLK_FIXED_FACTOR_HW(twpll_384m, "twpll-384m", &twpll.common.hw, 284 4, 1, 0); 285 static CLK_FIXED_FACTOR_HW(twpll_192m, "twpll-192m", &twpll.common.hw, 286 8, 1, 0); 287 static CLK_FIXED_FACTOR_HW(twpll_96m, "twpll-96m", &twpll.common.hw, 288 16, 1, 0); 289 static CLK_FIXED_FACTOR_HW(twpll_48m, "twpll-48m", &twpll.common.hw, 290 32, 1, 0); 291 static CLK_FIXED_FACTOR_HW(twpll_24m, "twpll-24m", &twpll.common.hw, 292 64, 1, 0); 293 static CLK_FIXED_FACTOR_HW(twpll_12m, "twpll-12m", &twpll.common.hw, 294 128, 1, 0); 295 static CLK_FIXED_FACTOR_HW(twpll_512m, "twpll-512m", &twpll.common.hw, 296 3, 1, 0); 297 static CLK_FIXED_FACTOR_HW(twpll_256m, "twpll-256m", &twpll.common.hw, 298 6, 1, 0); 299 static CLK_FIXED_FACTOR_HW(twpll_128m, "twpll-128m", &twpll.common.hw, 300 12, 1, 0); 301 static CLK_FIXED_FACTOR_HW(twpll_64m, "twpll-64m", &twpll.common.hw, 302 24, 1, 0); 303 static CLK_FIXED_FACTOR_HW(twpll_307m2, "twpll-307m2", &twpll.common.hw, 304 5, 1, 0); 305 static CLK_FIXED_FACTOR_HW(twpll_219m4, "twpll-219m4", &twpll.common.hw, 306 7, 1, 0); 307 static CLK_FIXED_FACTOR_HW(twpll_170m6, "twpll-170m6", &twpll.common.hw, 308 9, 1, 0); 309 static CLK_FIXED_FACTOR_HW(twpll_153m6, "twpll-153m6", &twpll.common.hw, 310 10, 1, 0); 311 static CLK_FIXED_FACTOR_HW(twpll_76m8, "twpll-76m8", &twpll.common.hw, 312 20, 1, 0); 313 static CLK_FIXED_FACTOR_HW(twpll_51m2, "twpll-51m2", &twpll.common.hw, 314 30, 1, 0); 315 static CLK_FIXED_FACTOR_HW(twpll_38m4, "twpll-38m4", &twpll.common.hw, 316 40, 1, 0); 317 static CLK_FIXED_FACTOR_HW(twpll_19m2, "twpll-19m2", &twpll.common.hw, 318 80, 1, 0); 319 static CLK_FIXED_FACTOR_HW(twpll_12m29, "twpll-12m29", &twpll.common.hw, 320 125, 1, 0); 321 322 static SPRD_PLL_FW_NAME(lpll, "lpll", "ext-26m", 0x18, 3, 323 itable, f_pll, 240, 1000, 1000, 1, 750000000); 324 static CLK_FIXED_FACTOR_HW(lpll_614m4, "lpll-614m4", &lpll.common.hw, 325 2, 1, 0); 326 static CLK_FIXED_FACTOR_HW(lpll_409m6, "lpll-409m6", &lpll.common.hw, 327 3, 1, 0); 328 static CLK_FIXED_FACTOR_HW(lpll_245m76, "lpll-245m76", &lpll.common.hw, 329 5, 1, 0); 330 static CLK_FIXED_FACTOR_HW(lpll_30m72, "lpll-30m72", &lpll.common.hw, 331 40, 1, 0); 332 333 static SPRD_PLL_FW_NAME(isppll, "isppll", "ext-26m", 0x30, 3, 334 itable, f_pll, 240, 1000, 1000, 1, 750000000); 335 static CLK_FIXED_FACTOR_HW(isppll_468m, "isppll-468m", &isppll.common.hw, 336 2, 1, 0); 337 static CLK_FIXED_FACTOR_HW(isppll_78m, "isppll-78m", &isppll.common.hw, 338 12, 1, 0); 339 340 static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x48, 3, 341 itable, f_pll, 240, 1000, 1000, 1, 750000000); 342 static CLK_FIXED_FACTOR_HW(gpll_40m, "gpll-40m", &gpll.common.hw, 343 20, 1, 0); 344 345 static SPRD_PLL_HW(cppll, "cppll", &cppll_gate.common.hw, 0x60, 3, 346 itable, f_pll, 240, 1000, 1000, 1, 750000000); 347 static CLK_FIXED_FACTOR_HW(cppll_39m32, "cppll-39m32", &cppll.common.hw, 348 26, 1, 0); 349 350 static struct sprd_clk_common *ums512_gc_pll_clks[] = { 351 /* address base is 0x323e0000 */ 352 &twpll.common, 353 &lpll.common, 354 &isppll.common, 355 &gpll.common, 356 &cppll.common, 357 }; 358 359 static struct clk_hw_onecell_data ums512_gc_pll_hws = { 360 .hws = { 361 [CLK_TWPLL] = &twpll.common.hw, 362 [CLK_TWPLL_768M] = &twpll_768m.hw, 363 [CLK_TWPLL_384M] = &twpll_384m.hw, 364 [CLK_TWPLL_192M] = &twpll_192m.hw, 365 [CLK_TWPLL_96M] = &twpll_96m.hw, 366 [CLK_TWPLL_48M] = &twpll_48m.hw, 367 [CLK_TWPLL_24M] = &twpll_24m.hw, 368 [CLK_TWPLL_12M] = &twpll_12m.hw, 369 [CLK_TWPLL_512M] = &twpll_512m.hw, 370 [CLK_TWPLL_256M] = &twpll_256m.hw, 371 [CLK_TWPLL_128M] = &twpll_128m.hw, 372 [CLK_TWPLL_64M] = &twpll_64m.hw, 373 [CLK_TWPLL_307M2] = &twpll_307m2.hw, 374 [CLK_TWPLL_219M4] = &twpll_219m4.hw, 375 [CLK_TWPLL_170M6] = &twpll_170m6.hw, 376 [CLK_TWPLL_153M6] = &twpll_153m6.hw, 377 [CLK_TWPLL_76M8] = &twpll_76m8.hw, 378 [CLK_TWPLL_51M2] = &twpll_51m2.hw, 379 [CLK_TWPLL_38M4] = &twpll_38m4.hw, 380 [CLK_TWPLL_19M2] = &twpll_19m2.hw, 381 [CLK_TWPLL_12M29] = &twpll_12m29.hw, 382 [CLK_LPLL] = &lpll.common.hw, 383 [CLK_LPLL_614M4] = &lpll_614m4.hw, 384 [CLK_LPLL_409M6] = &lpll_409m6.hw, 385 [CLK_LPLL_245M76] = &lpll_245m76.hw, 386 [CLK_LPLL_30M72] = &lpll_30m72.hw, 387 [CLK_ISPPLL] = &isppll.common.hw, 388 [CLK_ISPPLL_468M] = &isppll_468m.hw, 389 [CLK_ISPPLL_78M] = &isppll_78m.hw, 390 [CLK_GPLL] = &gpll.common.hw, 391 [CLK_GPLL_40M] = &gpll_40m.hw, 392 [CLK_CPPLL] = &cppll.common.hw, 393 [CLK_CPPLL_39M32] = &cppll_39m32.hw, 394 }, 395 .num = CLK_ANLG_PHY_GC_NUM, 396 }; 397 398 static struct sprd_clk_desc ums512_gc_pll_desc = { 399 .clk_clks = ums512_gc_pll_clks, 400 .num_clk_clks = ARRAY_SIZE(ums512_gc_pll_clks), 401 .hw_clks = &ums512_gc_pll_hws, 402 }; 403 404 /* ap ahb gates */ 405 static SPRD_SC_GATE_CLK_FW_NAME(dsi_eb, "dsi-eb", "ext-26m", 406 0x0, 0x1000, BIT(0), 0, 0); 407 static SPRD_SC_GATE_CLK_FW_NAME(dispc_eb, "dispc-eb", "ext-26m", 408 0x0, 0x1000, BIT(1), 0, 0); 409 static SPRD_SC_GATE_CLK_FW_NAME(vsp_eb, "vsp-eb", "ext-26m", 410 0x0, 0x1000, BIT(2), 0, 0); 411 static SPRD_SC_GATE_CLK_FW_NAME(vdma_eb, "vdma-eb", "ext-26m", 412 0x0, 0x1000, BIT(3), 0, 0); 413 static SPRD_SC_GATE_CLK_FW_NAME(dma_pub_eb, "dma-pub-eb", "ext-26m", 414 0x0, 0x1000, BIT(4), 0, 0); 415 static SPRD_SC_GATE_CLK_FW_NAME(dma_sec_eb, "dma-sec-eb", "ext-26m", 416 0x0, 0x1000, BIT(5), 0, 0); 417 static SPRD_SC_GATE_CLK_FW_NAME(ipi_eb, "ipi-eb", "ext-26m", 418 0x0, 0x1000, BIT(6), 0, 0); 419 static SPRD_SC_GATE_CLK_FW_NAME(ahb_ckg_eb, "ahb-ckg-eb", "ext-26m", 420 0x0, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); 421 static SPRD_SC_GATE_CLK_FW_NAME(bm_clk_eb, "bm-clk-eb", "ext-26m", 422 0x0, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); 423 424 static struct sprd_clk_common *ums512_apahb_gate[] = { 425 /* address base is 0x20100000 */ 426 &dsi_eb.common, 427 &dispc_eb.common, 428 &vsp_eb.common, 429 &vdma_eb.common, 430 &dma_pub_eb.common, 431 &dma_sec_eb.common, 432 &ipi_eb.common, 433 &ahb_ckg_eb.common, 434 &bm_clk_eb.common, 435 }; 436 437 static struct clk_hw_onecell_data ums512_apahb_gate_hws = { 438 .hws = { 439 [CLK_DSI_EB] = &dsi_eb.common.hw, 440 [CLK_DISPC_EB] = &dispc_eb.common.hw, 441 [CLK_VSP_EB] = &vsp_eb.common.hw, 442 [CLK_VDMA_EB] = &vdma_eb.common.hw, 443 [CLK_DMA_PUB_EB] = &dma_pub_eb.common.hw, 444 [CLK_DMA_SEC_EB] = &dma_sec_eb.common.hw, 445 [CLK_IPI_EB] = &ipi_eb.common.hw, 446 [CLK_AHB_CKG_EB] = &ahb_ckg_eb.common.hw, 447 [CLK_BM_CLK_EB] = &bm_clk_eb.common.hw, 448 }, 449 .num = CLK_AP_AHB_GATE_NUM, 450 }; 451 452 static struct sprd_clk_desc ums512_apahb_gate_desc = { 453 .clk_clks = ums512_apahb_gate, 454 .num_clk_clks = ARRAY_SIZE(ums512_apahb_gate), 455 .hw_clks = &ums512_apahb_gate_hws, 456 }; 457 458 /* ap clks */ 459 static const struct clk_parent_data ap_apb_parents[] = { 460 { .fw_name = "ext-26m" }, 461 { .hw = &twpll_64m.hw }, 462 { .hw = &twpll_96m.hw }, 463 { .hw = &twpll_128m.hw }, 464 }; 465 static SPRD_MUX_CLK_DATA(ap_apb_clk, "ap-apb-clk", ap_apb_parents, 466 0x20, 0, 2, UMS512_MUX_FLAG); 467 468 static const struct clk_parent_data ipi_parents[] = { 469 { .fw_name = "ext-26m" }, 470 { .hw = &twpll_64m.hw }, 471 { .hw = &twpll_96m.hw }, 472 { .hw = &twpll_128m.hw }, 473 }; 474 static SPRD_MUX_CLK_DATA(ipi_clk, "ipi-clk", ipi_parents, 475 0x24, 0, 2, UMS512_MUX_FLAG); 476 477 static const struct clk_parent_data ap_uart_parents[] = { 478 { .fw_name = "ext-26m" }, 479 { .hw = &twpll_48m.hw }, 480 { .hw = &twpll_51m2.hw }, 481 { .hw = &twpll_96m.hw }, 482 }; 483 static SPRD_COMP_CLK_DATA(ap_uart0_clk, "ap-uart0-clk", ap_uart_parents, 484 0x28, 0, 2, 8, 3, 0); 485 static SPRD_COMP_CLK_DATA(ap_uart1_clk, "ap-uart1-clk", ap_uart_parents, 486 0x2c, 0, 2, 8, 3, 0); 487 static SPRD_COMP_CLK_DATA(ap_uart2_clk, "ap-uart2-clk", ap_uart_parents, 488 0x30, 0, 2, 8, 3, 0); 489 490 static const struct clk_parent_data i2c_parents[] = { 491 { .fw_name = "ext-26m" }, 492 { .hw = &twpll_48m.hw }, 493 { .hw = &twpll_51m2.hw }, 494 { .hw = &twpll_153m6.hw }, 495 }; 496 static SPRD_COMP_CLK_DATA(ap_i2c0_clk, "ap-i2c0-clk", i2c_parents, 497 0x34, 0, 2, 8, 3, 0); 498 static SPRD_COMP_CLK_DATA(ap_i2c1_clk, "ap-i2c1-clk", i2c_parents, 499 0x38, 0, 2, 8, 3, 0); 500 static SPRD_COMP_CLK_DATA(ap_i2c2_clk, "ap-i2c2-clk", i2c_parents, 501 0x3c, 0, 2, 8, 3, 0); 502 static SPRD_COMP_CLK_DATA(ap_i2c3_clk, "ap-i2c3-clk", i2c_parents, 503 0x40, 0, 2, 8, 3, 0); 504 static SPRD_COMP_CLK_DATA(ap_i2c4_clk, "ap-i2c4-clk", i2c_parents, 505 0x44, 0, 2, 8, 3, 0); 506 507 static const struct clk_parent_data spi_parents[] = { 508 { .fw_name = "ext-26m" }, 509 { .hw = &twpll_128m.hw }, 510 { .hw = &twpll_153m6.hw }, 511 { .hw = &twpll_192m.hw }, 512 }; 513 static SPRD_COMP_CLK_DATA(ap_spi0_clk, "ap-spi0-clk", spi_parents, 514 0x48, 0, 2, 8, 3, 0); 515 static SPRD_COMP_CLK_DATA(ap_spi1_clk, "ap-spi1-clk", spi_parents, 516 0x4c, 0, 2, 8, 3, 0); 517 static SPRD_COMP_CLK_DATA(ap_spi2_clk, "ap-spi2-clk", spi_parents, 518 0x50, 0, 2, 8, 3, 0); 519 static SPRD_COMP_CLK_DATA(ap_spi3_clk, "ap-spi3-clk", spi_parents, 520 0x54, 0, 2, 8, 3, 0); 521 522 static const struct clk_parent_data iis_parents[] = { 523 { .fw_name = "ext-26m" }, 524 { .hw = &twpll_128m.hw }, 525 { .hw = &twpll_153m6.hw }, 526 }; 527 static SPRD_COMP_CLK_DATA(ap_iis0_clk, "ap-iis0-clk", iis_parents, 528 0x58, 0, 2, 8, 3, 0); 529 static SPRD_COMP_CLK_DATA(ap_iis1_clk, "ap-iis1-clk", iis_parents, 530 0x5c, 0, 2, 8, 3, 0); 531 static SPRD_COMP_CLK_DATA(ap_iis2_clk, "ap-iis2-clk", iis_parents, 532 0x60, 0, 2, 8, 3, 0); 533 534 static const struct clk_parent_data sim_parents[] = { 535 { .fw_name = "ext-26m" }, 536 { .hw = &twpll_51m2.hw }, 537 { .hw = &twpll_64m.hw }, 538 { .hw = &twpll_96m.hw }, 539 { .hw = &twpll_128m.hw }, 540 }; 541 static SPRD_COMP_CLK_DATA(ap_sim_clk, "ap-sim-clk", sim_parents, 542 0x64, 0, 3, 8, 3, 0); 543 544 static const struct clk_parent_data ap_ce_parents[] = { 545 { .fw_name = "ext-26m" }, 546 { .hw = &twpll_96m.hw }, 547 { .hw = &twpll_192m.hw }, 548 { .hw = &twpll_256m.hw }, 549 }; 550 static SPRD_MUX_CLK_DATA(ap_ce_clk, "ap-ce-clk", ap_ce_parents, 551 0x68, 0, 2, UMS512_MUX_FLAG); 552 553 static const struct clk_parent_data sdio_parents[] = { 554 { .hw = &clk_1m.hw }, 555 { .fw_name = "ext-26m" }, 556 { .hw = &twpll_307m2.hw }, 557 { .hw = &twpll_384m.hw }, 558 { .hw = &rpll.common.hw }, 559 { .hw = &lpll_409m6.hw }, 560 }; 561 static SPRD_MUX_CLK_DATA(sdio0_2x_clk, "sdio0-2x", sdio_parents, 562 0x80, 0, 3, UMS512_MUX_FLAG); 563 static SPRD_MUX_CLK_DATA(sdio1_2x_clk, "sdio1-2x", sdio_parents, 564 0x88, 0, 3, UMS512_MUX_FLAG); 565 static SPRD_MUX_CLK_DATA(emmc_2x_clk, "emmc-2x", sdio_parents, 566 0x90, 0, 3, UMS512_MUX_FLAG); 567 568 static const struct clk_parent_data vsp_parents[] = { 569 { .hw = &twpll_256m.hw }, 570 { .hw = &twpll_307m2.hw }, 571 { .hw = &twpll_384m.hw }, 572 }; 573 static SPRD_MUX_CLK_DATA(vsp_clk, "vsp-clk", vsp_parents, 574 0x98, 0, 2, UMS512_MUX_FLAG); 575 576 static const struct clk_parent_data dispc0_parents[] = { 577 { .hw = &twpll_153m6.hw }, 578 { .hw = &twpll_192m.hw }, 579 { .hw = &twpll_256m.hw }, 580 { .hw = &twpll_307m2.hw }, 581 { .hw = &twpll_384m.hw }, 582 }; 583 static SPRD_MUX_CLK_DATA(dispc0_clk, "dispc0-clk", dispc0_parents, 584 0x9c, 0, 3, UMS512_MUX_FLAG); 585 586 static const struct clk_parent_data dispc0_dpi_parents[] = { 587 { .hw = &twpll_96m.hw }, 588 { .hw = &twpll_128m.hw }, 589 { .hw = &twpll_153m6.hw }, 590 { .hw = &twpll_192m.hw }, 591 }; 592 static SPRD_COMP_CLK_DATA(dispc0_dpi_clk, "dispc0-dpi-clk", dispc0_dpi_parents, 593 0xa0, 0, 3, 8, 4, 0); 594 595 static const struct clk_parent_data dsi_apb_parents[] = { 596 { .hw = &twpll_96m.hw }, 597 { .hw = &twpll_128m.hw }, 598 { .hw = &twpll_153m6.hw }, 599 { .hw = &twpll_192m.hw }, 600 }; 601 static SPRD_MUX_CLK_DATA(dsi_apb_clk, "dsi-apb-clk", dsi_apb_parents, 602 0xa4, 0, 2, UMS512_MUX_FLAG); 603 604 static SPRD_GATE_CLK_FW_NAME(dsi_rxesc, "dsi-rxesc", "ext-26m", 605 0xa8, BIT(16), 0, 0); 606 607 static SPRD_GATE_CLK_FW_NAME(dsi_lanebyte, "dsi-lanebyte", "ext-26m", 608 0xac, BIT(16), 0, 0); 609 610 static const struct clk_parent_data vdsp_parents[] = { 611 { .hw = &twpll_256m.hw }, 612 { .hw = &twpll_384m.hw }, 613 { .hw = &twpll_512m.hw }, 614 { .hw = &lpll_614m4.hw }, 615 { .hw = &twpll_768m.hw }, 616 { .hw = &isppll.common.hw }, 617 }; 618 static SPRD_MUX_CLK_DATA(vdsp_clk, "vdsp-clk", vdsp_parents, 619 0xb0, 0, 3, UMS512_MUX_FLAG); 620 static SPRD_DIV_CLK_HW(vdsp_m_clk, "vdsp-m-clk", &vdsp_clk.common.hw, 621 0xb4, 8, 2, 0); 622 623 static struct sprd_clk_common *ums512_ap_clks[] = { 624 /* address base is 0x20200000 */ 625 &ap_apb_clk.common, 626 &ipi_clk.common, 627 &ap_uart0_clk.common, 628 &ap_uart1_clk.common, 629 &ap_uart2_clk.common, 630 &ap_i2c0_clk.common, 631 &ap_i2c1_clk.common, 632 &ap_i2c2_clk.common, 633 &ap_i2c3_clk.common, 634 &ap_i2c4_clk.common, 635 &ap_spi0_clk.common, 636 &ap_spi1_clk.common, 637 &ap_spi2_clk.common, 638 &ap_spi3_clk.common, 639 &ap_iis0_clk.common, 640 &ap_iis1_clk.common, 641 &ap_iis2_clk.common, 642 &ap_sim_clk.common, 643 &ap_ce_clk.common, 644 &sdio0_2x_clk.common, 645 &sdio1_2x_clk.common, 646 &emmc_2x_clk.common, 647 &vsp_clk.common, 648 &dispc0_clk.common, 649 &dispc0_dpi_clk.common, 650 &dsi_apb_clk.common, 651 &dsi_rxesc.common, 652 &dsi_lanebyte.common, 653 &vdsp_clk.common, 654 &vdsp_m_clk.common, 655 656 }; 657 658 static struct clk_hw_onecell_data ums512_ap_clk_hws = { 659 .hws = { 660 [CLK_AP_APB] = &ap_apb_clk.common.hw, 661 [CLK_IPI] = &ipi_clk.common.hw, 662 [CLK_AP_UART0] = &ap_uart0_clk.common.hw, 663 [CLK_AP_UART1] = &ap_uart1_clk.common.hw, 664 [CLK_AP_UART2] = &ap_uart2_clk.common.hw, 665 [CLK_AP_I2C0] = &ap_i2c0_clk.common.hw, 666 [CLK_AP_I2C1] = &ap_i2c1_clk.common.hw, 667 [CLK_AP_I2C2] = &ap_i2c2_clk.common.hw, 668 [CLK_AP_I2C3] = &ap_i2c3_clk.common.hw, 669 [CLK_AP_I2C4] = &ap_i2c4_clk.common.hw, 670 [CLK_AP_SPI0] = &ap_spi0_clk.common.hw, 671 [CLK_AP_SPI1] = &ap_spi1_clk.common.hw, 672 [CLK_AP_SPI2] = &ap_spi2_clk.common.hw, 673 [CLK_AP_SPI3] = &ap_spi3_clk.common.hw, 674 [CLK_AP_IIS0] = &ap_iis0_clk.common.hw, 675 [CLK_AP_IIS1] = &ap_iis1_clk.common.hw, 676 [CLK_AP_IIS2] = &ap_iis2_clk.common.hw, 677 [CLK_AP_SIM] = &ap_sim_clk.common.hw, 678 [CLK_AP_CE] = &ap_ce_clk.common.hw, 679 [CLK_SDIO0_2X] = &sdio0_2x_clk.common.hw, 680 [CLK_SDIO1_2X] = &sdio1_2x_clk.common.hw, 681 [CLK_EMMC_2X] = &emmc_2x_clk.common.hw, 682 [CLK_VSP] = &vsp_clk.common.hw, 683 [CLK_DISPC0] = &dispc0_clk.common.hw, 684 [CLK_DISPC0_DPI] = &dispc0_dpi_clk.common.hw, 685 [CLK_DSI_APB] = &dsi_apb_clk.common.hw, 686 [CLK_DSI_RXESC] = &dsi_rxesc.common.hw, 687 [CLK_DSI_LANEBYTE] = &dsi_lanebyte.common.hw, 688 [CLK_VDSP] = &vdsp_clk.common.hw, 689 [CLK_VDSP_M] = &vdsp_m_clk.common.hw, 690 }, 691 .num = CLK_AP_CLK_NUM, 692 }; 693 694 static struct sprd_clk_desc ums512_ap_clk_desc = { 695 .clk_clks = ums512_ap_clks, 696 .num_clk_clks = ARRAY_SIZE(ums512_ap_clks), 697 .hw_clks = &ums512_ap_clk_hws, 698 }; 699 700 /* aon apb clks */ 701 static const struct clk_parent_data aon_apb_parents[] = { 702 { .hw = &rco_4m.hw }, 703 { .fw_name = "ext-4m" }, 704 { .hw = &clk_13m.hw }, 705 { .hw = &rco_25m.hw }, 706 { .fw_name = "ext-26m" }, 707 { .hw = &twpll_96m.hw }, 708 { .fw_name = "rco-100m" }, 709 { .hw = &twpll_128m.hw }, 710 }; 711 static SPRD_COMP_CLK_DATA(aon_apb_clk, "aon-apb-clk", aon_apb_parents, 712 0x220, 0, 3, 8, 2, 0); 713 714 715 static const struct clk_parent_data adi_parents[] = { 716 { .hw = &rco_4m.hw }, 717 { .fw_name = "ext-26m" }, 718 { .hw = &rco_25m.hw }, 719 { .hw = &twpll_38m4.hw }, 720 { .hw = &twpll_51m2.hw }, 721 }; 722 static SPRD_MUX_CLK_DATA(adi_clk, "adi-clk", adi_parents, 723 0x224, 0, 3, UMS512_MUX_FLAG); 724 725 static const struct clk_parent_data aux_parents[] = { 726 { .fw_name = "ext-32k" }, 727 { .fw_name = "ext-26m" }, 728 { .hw = &clk_26m_aud.hw }, 729 { .hw = &rco_25m.hw }, 730 { .hw = &cppll_39m32.hw }, 731 { .hw = &mpll0_56m88.hw }, 732 { .hw = &mpll1_63m38.hw }, 733 { .hw = &mpll2_47m13.hw }, 734 { .hw = &dpll0_58m31.hw }, 735 { .hw = &gpll_40m.hw }, 736 { .hw = &twpll_48m.hw }, 737 }; 738 static const struct clk_parent_data aux1_parents[] = { 739 { .fw_name = "ext-32k" }, 740 { .fw_name = "ext-26m" }, 741 { .hw = &clk_26m_aud.hw }, 742 { .hw = &rco_25m.hw }, 743 { .hw = &cppll_39m32.hw }, 744 { .hw = &mpll0_56m88.hw }, 745 { .hw = &mpll1_63m38.hw }, 746 { .hw = &mpll2_47m13.hw }, 747 { .hw = &dpll0_58m31.hw }, 748 { .hw = &gpll_40m.hw }, 749 { .hw = &twpll_19m2.hw }, 750 { .hw = &lpll_30m72.hw }, 751 { .hw = &rpll.common.hw }, 752 { .hw = &twpll_12m29.hw }, 753 754 }; 755 static SPRD_COMP_CLK_DATA(aux0_clk, "aux0-clk", aux_parents, 756 0x228, 0, 5, 8, 4, 0); 757 static SPRD_COMP_CLK_DATA(aux1_clk, "aux1-clk", aux1_parents, 758 0x22c, 0, 5, 8, 4, 0); 759 static SPRD_COMP_CLK_DATA(aux2_clk, "aux2-clk", aux_parents, 760 0x230, 0, 5, 8, 4, 0); 761 static SPRD_COMP_CLK_DATA(probe_clk, "probe-clk", aux_parents, 762 0x234, 0, 5, 8, 4, 0); 763 764 static const struct clk_parent_data pwm_parents[] = { 765 { .fw_name = "ext-32k" }, 766 { .fw_name = "ext-26m" }, 767 { .hw = &rco_4m.hw }, 768 { .hw = &rco_25m.hw }, 769 { .hw = &twpll_48m.hw }, 770 }; 771 static SPRD_MUX_CLK_DATA(pwm0_clk, "pwm0-clk", pwm_parents, 772 0x238, 0, 3, UMS512_MUX_FLAG); 773 static SPRD_MUX_CLK_DATA(pwm1_clk, "pwm1-clk", pwm_parents, 774 0x23c, 0, 3, UMS512_MUX_FLAG); 775 static SPRD_MUX_CLK_DATA(pwm2_clk, "pwm2-clk", pwm_parents, 776 0x240, 0, 3, UMS512_MUX_FLAG); 777 static SPRD_MUX_CLK_DATA(pwm3_clk, "pwm3-clk", pwm_parents, 778 0x244, 0, 3, UMS512_MUX_FLAG); 779 780 static const struct clk_parent_data efuse_parents[] = { 781 { .hw = &rco_25m.hw }, 782 { .fw_name = "ext-26m" }, 783 }; 784 static SPRD_MUX_CLK_DATA(efuse_clk, "efuse-clk", efuse_parents, 785 0x248, 0, 1, UMS512_MUX_FLAG); 786 787 static const struct clk_parent_data uart_parents[] = { 788 { .hw = &rco_4m.hw }, 789 { .fw_name = "ext-26m" }, 790 { .hw = &twpll_48m.hw }, 791 { .hw = &twpll_51m2.hw }, 792 { .hw = &twpll_96m.hw }, 793 { .fw_name = "rco-100m" }, 794 { .hw = &twpll_128m.hw }, 795 }; 796 static SPRD_MUX_CLK_DATA(uart0_clk, "uart0-clk", uart_parents, 797 0x24c, 0, 3, UMS512_MUX_FLAG); 798 static SPRD_MUX_CLK_DATA(uart1_clk, "uart1-clk", uart_parents, 799 0x250, 0, 3, UMS512_MUX_FLAG); 800 801 static const struct clk_parent_data thm_parents[] = { 802 { .fw_name = "ext-32k" }, 803 { .hw = &clk_250k.hw }, 804 }; 805 static SPRD_MUX_CLK_DATA(thm0_clk, "thm0-clk", thm_parents, 806 0x260, 0, 1, UMS512_MUX_FLAG); 807 static SPRD_MUX_CLK_DATA(thm1_clk, "thm1-clk", thm_parents, 808 0x264, 0, 1, UMS512_MUX_FLAG); 809 static SPRD_MUX_CLK_DATA(thm2_clk, "thm2-clk", thm_parents, 810 0x268, 0, 1, UMS512_MUX_FLAG); 811 static SPRD_MUX_CLK_DATA(thm3_clk, "thm3-clk", thm_parents, 812 0x26c, 0, 1, UMS512_MUX_FLAG); 813 814 static const struct clk_parent_data aon_i2c_parents[] = { 815 { .hw = &rco_4m.hw }, 816 { .fw_name = "ext-26m" }, 817 { .hw = &twpll_48m.hw }, 818 { .hw = &twpll_51m2.hw }, 819 { .fw_name = "rco-100m" }, 820 { .hw = &twpll_153m6.hw }, 821 }; 822 static SPRD_MUX_CLK_DATA(aon_i2c_clk, "aon-i2c-clk", aon_i2c_parents, 823 0x27c, 0, 3, UMS512_MUX_FLAG); 824 825 static const struct clk_parent_data aon_iis_parents[] = { 826 { .fw_name = "ext-26m" }, 827 { .hw = &twpll_128m.hw }, 828 { .hw = &twpll_153m6.hw }, 829 }; 830 static SPRD_MUX_CLK_DATA(aon_iis_clk, "aon-iis-clk", aon_iis_parents, 831 0x280, 0, 2, UMS512_MUX_FLAG); 832 833 static const struct clk_parent_data scc_parents[] = { 834 { .fw_name = "ext-26m" }, 835 { .hw = &twpll_48m.hw }, 836 { .hw = &twpll_51m2.hw }, 837 { .hw = &twpll_96m.hw }, 838 }; 839 static SPRD_MUX_CLK_DATA(scc_clk, "scc-clk", scc_parents, 840 0x284, 0, 2, UMS512_MUX_FLAG); 841 842 static const struct clk_parent_data apcpu_dap_parents[] = { 843 { .fw_name = "ext-26m" }, 844 { .hw = &rco_4m.hw }, 845 { .hw = &twpll_76m8.hw }, 846 { .fw_name = "rco-100m" }, 847 { .hw = &twpll_128m.hw }, 848 { .hw = &twpll_153m6.hw }, 849 }; 850 static SPRD_MUX_CLK_DATA(apcpu_dap_clk, "apcpu-dap-clk", apcpu_dap_parents, 851 0x288, 0, 3, UMS512_MUX_FLAG); 852 853 static SPRD_GATE_CLK_FW_NAME(apcpu_dap_mtck, "apcpu-dap-mtck", "ext-26m", 854 0x28c, BIT(16), 0, 0); 855 856 static const struct clk_parent_data apcpu_ts_parents[] = { 857 { .fw_name = "ext-32m" }, 858 { .fw_name = "ext-26m" }, 859 { .hw = &twpll_128m.hw }, 860 { .hw = &twpll_153m6.hw }, 861 }; 862 static SPRD_MUX_CLK_DATA(apcpu_ts_clk, "apcpu-ts-clk", apcpu_ts_parents, 863 0x290, 0, 2, UMS512_MUX_FLAG); 864 865 static const struct clk_parent_data debug_ts_parents[] = { 866 { .fw_name = "ext-26m" }, 867 { .hw = &twpll_76m8.hw }, 868 { .hw = &twpll_128m.hw }, 869 { .hw = &twpll_192m.hw }, 870 }; 871 static SPRD_MUX_CLK_DATA(debug_ts_clk, "debug-ts-clk", debug_ts_parents, 872 0x294, 0, 2, UMS512_MUX_FLAG); 873 874 static SPRD_GATE_CLK_FW_NAME(dsi_test_s, "dsi-test-s", "ext-26m", 875 0x298, BIT(16), 0, 0); 876 877 static const struct clk_parent_data djtag_tck_parents[] = { 878 { .hw = &rco_4m.hw }, 879 { .fw_name = "ext-26m" }, 880 }; 881 static SPRD_MUX_CLK_DATA(djtag_tck_clk, "djtag-tck-clk", djtag_tck_parents, 882 0x2b4, 0, 1, UMS512_MUX_FLAG); 883 884 static SPRD_GATE_CLK_FW_NAME(djtag_tck_hw, "djtag-tck-hw", "ext-26m", 885 0x2b8, BIT(16), 0, 0); 886 887 static const struct clk_parent_data aon_tmr_parents[] = { 888 { .hw = &rco_4m.hw }, 889 { .hw = &rco_25m.hw }, 890 { .fw_name = "ext-26m" }, 891 }; 892 static SPRD_MUX_CLK_DATA(aon_tmr_clk, "aon-tmr-clk", aon_tmr_parents, 893 0x2c0, 0, 2, UMS512_MUX_FLAG); 894 895 static const struct clk_parent_data aon_pmu_parents[] = { 896 { .fw_name = "ext-32k" }, 897 { .hw = &rco_4m.hw }, 898 { .fw_name = "ext-4m" }, 899 }; 900 static SPRD_MUX_CLK_DATA(aon_pmu_clk, "aon-pmu-clk", aon_pmu_parents, 901 0x2c8, 0, 2, UMS512_MUX_FLAG); 902 903 static const struct clk_parent_data debounce_parents[] = { 904 { .fw_name = "ext-32k" }, 905 { .hw = &rco_4m.hw }, 906 { .hw = &rco_25m.hw }, 907 { .fw_name = "ext-26m" }, 908 }; 909 static SPRD_MUX_CLK_DATA(debounce_clk, "debounce-clk", debounce_parents, 910 0x2cc, 0, 2, UMS512_MUX_FLAG); 911 912 static const struct clk_parent_data apcpu_pmu_parents[] = { 913 { .fw_name = "ext-26m" }, 914 { .hw = &twpll_76m8.hw }, 915 { .fw_name = "rco-100m" }, 916 { .hw = &twpll_128m.hw }, 917 }; 918 static SPRD_MUX_CLK_DATA(apcpu_pmu_clk, "apcpu-pmu-clk", apcpu_pmu_parents, 919 0x2d0, 0, 2, UMS512_MUX_FLAG); 920 921 static const struct clk_parent_data top_dvfs_parents[] = { 922 { .fw_name = "ext-26m" }, 923 { .hw = &twpll_96m.hw }, 924 { .fw_name = "rco-100m" }, 925 { .hw = &twpll_128m.hw }, 926 }; 927 static SPRD_MUX_CLK_DATA(top_dvfs_clk, "top-dvfs-clk", top_dvfs_parents, 928 0x2d8, 0, 2, UMS512_MUX_FLAG); 929 930 static SPRD_GATE_CLK_FW_NAME(otg_utmi, "otg-utmi", "ext-26m", 0x2dc, 931 BIT(16), 0, 0); 932 933 static const struct clk_parent_data otg_ref_parents[] = { 934 { .hw = &twpll_12m.hw }, 935 { .fw_name = "ext-26m" }, 936 }; 937 static SPRD_MUX_CLK_DATA(otg_ref_clk, "otg-ref-clk", otg_ref_parents, 938 0x2e0, 0, 1, UMS512_MUX_FLAG); 939 940 static const struct clk_parent_data cssys_parents[] = { 941 { .hw = &rco_25m.hw }, 942 { .fw_name = "ext-26m" }, 943 { .fw_name = "rco-100m" }, 944 { .hw = &twpll_153m6.hw }, 945 { .hw = &twpll_384m.hw }, 946 { .hw = &twpll_512m.hw }, 947 }; 948 static SPRD_COMP_CLK_DATA(cssys_clk, "cssys-clk", cssys_parents, 949 0x2e4, 0, 3, 8, 2, 0); 950 static SPRD_DIV_CLK_HW(cssys_pub_clk, "cssys-pub-clk", &cssys_clk.common.hw, 951 0x2e8, 8, 2, 0); 952 static SPRD_DIV_CLK_HW(cssys_apb_clk, "cssys-apb-clk", &cssys_clk.common.hw, 953 0x2ec, 8, 3, 0); 954 955 static const struct clk_parent_data ap_axi_parents[] = { 956 { .fw_name = "ext-26m" }, 957 { .hw = &twpll_76m8.hw }, 958 { .hw = &twpll_128m.hw }, 959 { .hw = &twpll_256m.hw }, 960 }; 961 static SPRD_MUX_CLK_DATA(ap_axi_clk, "ap-axi-clk", ap_axi_parents, 962 0x2f0, 0, 2, UMS512_MUX_FLAG); 963 964 static const struct clk_parent_data ap_mm_parents[] = { 965 { .fw_name = "ext-26m" }, 966 { .hw = &twpll_96m.hw }, 967 { .hw = &twpll_128m.hw }, 968 { .hw = &twpll_153m6.hw }, 969 }; 970 static SPRD_MUX_CLK_DATA(ap_mm_clk, "ap-mm-clk", ap_mm_parents, 971 0x2f4, 0, 2, UMS512_MUX_FLAG); 972 973 static const struct clk_parent_data sdio2_2x_parents[] = { 974 { .hw = &clk_1m.hw }, 975 { .fw_name = "ext-26m" }, 976 { .hw = &twpll_307m2.hw }, 977 { .hw = &twpll_384m.hw }, 978 { .hw = &rpll.common.hw }, 979 { .hw = &lpll_409m6.hw }, 980 }; 981 static SPRD_MUX_CLK_DATA(sdio2_2x_clk, "sdio2-2x-clk", sdio2_2x_parents, 982 0x2f8, 0, 3, UMS512_MUX_FLAG); 983 984 static const struct clk_parent_data analog_io_apb_parents[] = { 985 { .fw_name = "ext-26m" }, 986 { .hw = &twpll_48m.hw }, 987 }; 988 static SPRD_COMP_CLK_DATA(analog_io_apb, "analog-io-apb", analog_io_apb_parents, 989 0x300, 0, 1, 8, 2, 0); 990 991 static const struct clk_parent_data dmc_ref_parents[] = { 992 { .hw = &clk_6m5.hw }, 993 { .hw = &clk_13m.hw }, 994 { .fw_name = "ext-26m" }, 995 }; 996 static SPRD_MUX_CLK_DATA(dmc_ref_clk, "dmc-ref-clk", dmc_ref_parents, 997 0x304, 0, 2, UMS512_MUX_FLAG); 998 999 static const struct clk_parent_data emc_parents[] = { 1000 { .fw_name = "ext-26m" }, 1001 { .hw = &twpll_384m.hw }, 1002 { .hw = &twpll_512m.hw }, 1003 { .hw = &twpll_768m.hw }, 1004 }; 1005 static SPRD_MUX_CLK_DATA(emc_clk, "emc-clk", emc_parents, 1006 0x30c, 0, 2, UMS512_MUX_FLAG); 1007 1008 static const struct clk_parent_data usb_parents[] = { 1009 { .hw = &rco_25m.hw }, 1010 { .fw_name = "ext-26m" }, 1011 { .hw = &twpll_192m.hw }, 1012 { .hw = &twpll_96m.hw }, 1013 { .fw_name = "rco-100m" }, 1014 { .hw = &twpll_128m.hw }, 1015 }; 1016 static SPRD_COMP_CLK_DATA(usb_clk, "usb-clk", usb_parents, 1017 0x310, 0, 3, 8, 2, 0); 1018 1019 static const struct clk_parent_data pmu_26m_parents[] = { 1020 { .hw = &rco_25m.hw }, 1021 { .fw_name = "ext-26m" }, 1022 }; 1023 static SPRD_MUX_CLK_DATA(pmu_26m_clk, "26m-pmu-clk", pmu_26m_parents, 1024 0x318, 0, 1, UMS512_MUX_FLAG); 1025 1026 static struct sprd_clk_common *ums512_aon_apb[] = { 1027 /* address base is 0x32080200 */ 1028 &aon_apb_clk.common, 1029 &adi_clk.common, 1030 &aux0_clk.common, 1031 &aux1_clk.common, 1032 &aux2_clk.common, 1033 &probe_clk.common, 1034 &pwm0_clk.common, 1035 &pwm1_clk.common, 1036 &pwm2_clk.common, 1037 &pwm3_clk.common, 1038 &efuse_clk.common, 1039 &uart0_clk.common, 1040 &uart1_clk.common, 1041 &thm0_clk.common, 1042 &thm1_clk.common, 1043 &thm2_clk.common, 1044 &thm3_clk.common, 1045 &aon_i2c_clk.common, 1046 &aon_iis_clk.common, 1047 &scc_clk.common, 1048 &apcpu_dap_clk.common, 1049 &apcpu_dap_mtck.common, 1050 &apcpu_ts_clk.common, 1051 &debug_ts_clk.common, 1052 &dsi_test_s.common, 1053 &djtag_tck_clk.common, 1054 &djtag_tck_hw.common, 1055 &aon_tmr_clk.common, 1056 &aon_pmu_clk.common, 1057 &debounce_clk.common, 1058 &apcpu_pmu_clk.common, 1059 &top_dvfs_clk.common, 1060 &otg_utmi.common, 1061 &otg_ref_clk.common, 1062 &cssys_clk.common, 1063 &cssys_pub_clk.common, 1064 &cssys_apb_clk.common, 1065 &ap_axi_clk.common, 1066 &ap_mm_clk.common, 1067 &sdio2_2x_clk.common, 1068 &analog_io_apb.common, 1069 &dmc_ref_clk.common, 1070 &emc_clk.common, 1071 &usb_clk.common, 1072 &pmu_26m_clk.common, 1073 }; 1074 1075 static struct clk_hw_onecell_data ums512_aon_apb_hws = { 1076 .hws = { 1077 [CLK_AON_APB] = &aon_apb_clk.common.hw, 1078 [CLK_ADI] = &adi_clk.common.hw, 1079 [CLK_AUX0] = &aux0_clk.common.hw, 1080 [CLK_AUX1] = &aux1_clk.common.hw, 1081 [CLK_AUX2] = &aux2_clk.common.hw, 1082 [CLK_PROBE] = &probe_clk.common.hw, 1083 [CLK_PWM0] = &pwm0_clk.common.hw, 1084 [CLK_PWM1] = &pwm1_clk.common.hw, 1085 [CLK_PWM2] = &pwm2_clk.common.hw, 1086 [CLK_PWM3] = &pwm3_clk.common.hw, 1087 [CLK_EFUSE] = &efuse_clk.common.hw, 1088 [CLK_UART0] = &uart0_clk.common.hw, 1089 [CLK_UART1] = &uart1_clk.common.hw, 1090 [CLK_THM0] = &thm0_clk.common.hw, 1091 [CLK_THM1] = &thm1_clk.common.hw, 1092 [CLK_THM2] = &thm2_clk.common.hw, 1093 [CLK_THM3] = &thm3_clk.common.hw, 1094 [CLK_AON_I2C] = &aon_i2c_clk.common.hw, 1095 [CLK_AON_IIS] = &aon_iis_clk.common.hw, 1096 [CLK_SCC] = &scc_clk.common.hw, 1097 [CLK_APCPU_DAP] = &apcpu_dap_clk.common.hw, 1098 [CLK_APCPU_DAP_MTCK] = &apcpu_dap_mtck.common.hw, 1099 [CLK_APCPU_TS] = &apcpu_ts_clk.common.hw, 1100 [CLK_DEBUG_TS] = &debug_ts_clk.common.hw, 1101 [CLK_DSI_TEST_S] = &dsi_test_s.common.hw, 1102 [CLK_DJTAG_TCK] = &djtag_tck_clk.common.hw, 1103 [CLK_DJTAG_TCK_HW] = &djtag_tck_hw.common.hw, 1104 [CLK_AON_TMR] = &aon_tmr_clk.common.hw, 1105 [CLK_AON_PMU] = &aon_pmu_clk.common.hw, 1106 [CLK_DEBOUNCE] = &debounce_clk.common.hw, 1107 [CLK_APCPU_PMU] = &apcpu_pmu_clk.common.hw, 1108 [CLK_TOP_DVFS] = &top_dvfs_clk.common.hw, 1109 [CLK_OTG_UTMI] = &otg_utmi.common.hw, 1110 [CLK_OTG_REF] = &otg_ref_clk.common.hw, 1111 [CLK_CSSYS] = &cssys_clk.common.hw, 1112 [CLK_CSSYS_PUB] = &cssys_pub_clk.common.hw, 1113 [CLK_CSSYS_APB] = &cssys_apb_clk.common.hw, 1114 [CLK_AP_AXI] = &ap_axi_clk.common.hw, 1115 [CLK_AP_MM] = &ap_mm_clk.common.hw, 1116 [CLK_SDIO2_2X] = &sdio2_2x_clk.common.hw, 1117 [CLK_ANALOG_IO_APB] = &analog_io_apb.common.hw, 1118 [CLK_DMC_REF_CLK] = &dmc_ref_clk.common.hw, 1119 [CLK_EMC] = &emc_clk.common.hw, 1120 [CLK_USB] = &usb_clk.common.hw, 1121 [CLK_26M_PMU] = &pmu_26m_clk.common.hw, 1122 }, 1123 .num = CLK_AON_APB_NUM, 1124 }; 1125 1126 static struct sprd_clk_desc ums512_aon_apb_desc = { 1127 .clk_clks = ums512_aon_apb, 1128 .num_clk_clks = ARRAY_SIZE(ums512_aon_apb), 1129 .hw_clks = &ums512_aon_apb_hws, 1130 }; 1131 1132 /* aon apb gates */ 1133 static SPRD_SC_GATE_CLK_FW_NAME(rc100m_cal_eb, "rc100m-cal-eb", "ext-26m", 1134 0x0, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); 1135 static SPRD_SC_GATE_CLK_FW_NAME(djtag_tck_eb, "djtag-tck-eb", "ext-26m", 1136 0x0, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 1137 static SPRD_SC_GATE_CLK_FW_NAME(djtag_eb, "djtag-eb", "ext-26m", 1138 0x0, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); 1139 static SPRD_SC_GATE_CLK_FW_NAME(aux0_eb, "aux0-eb", "ext-26m", 1140 0x0, 0x1000, BIT(4), 0, 0); 1141 static SPRD_SC_GATE_CLK_FW_NAME(aux1_eb, "aux1-eb", "ext-26m", 1142 0x0, 0x1000, BIT(5), 0, 0); 1143 static SPRD_SC_GATE_CLK_FW_NAME(aux2_eb, "aux2-eb", "ext-26m", 1144 0x0, 0x1000, BIT(6), 0, 0); 1145 static SPRD_SC_GATE_CLK_FW_NAME(probe_eb, "probe-eb", "ext-26m", 1146 0x0, 0x1000, BIT(7), 0, 0); 1147 static SPRD_SC_GATE_CLK_FW_NAME(mm_eb, "mm-eb", "ext-26m", 1148 0x0, 0x1000, BIT(9), 0, 0); 1149 static SPRD_SC_GATE_CLK_FW_NAME(gpu_eb, "gpu-eb", "ext-26m", 1150 0x0, 0x1000, BIT(11), 0, 0); 1151 static SPRD_SC_GATE_CLK_FW_NAME(mspi_eb, "mspi-eb", "ext-26m", 1152 0x0, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 1153 static SPRD_SC_GATE_CLK_FW_NAME(apcpu_dap_eb, "apcpu-dap-eb", "ext-26m", 1154 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); 1155 static SPRD_SC_GATE_CLK_FW_NAME(aon_cssys_eb, "aon-cssys-eb", "ext-26m", 1156 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); 1157 static SPRD_SC_GATE_CLK_FW_NAME(cssys_apb_eb, "cssys-apb-eb", "ext-26m", 1158 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); 1159 static SPRD_SC_GATE_CLK_FW_NAME(cssys_pub_eb, "cssys-pub-eb", "ext-26m", 1160 0x0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 1161 static SPRD_SC_GATE_CLK_FW_NAME(sdphy_cfg_eb, "sdphy-cfg-eb", "ext-26m", 1162 0x0, 0x1000, BIT(19), 0, 0); 1163 static SPRD_SC_GATE_CLK_FW_NAME(sdphy_ref_eb, "sdphy-ref-eb", "ext-26m", 1164 0x0, 0x1000, BIT(20), 0, 0); 1165 static SPRD_SC_GATE_CLK_FW_NAME(efuse_eb, "efuse-eb", "ext-26m", 1166 0x4, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); 1167 static SPRD_SC_GATE_CLK_FW_NAME(gpio_eb, "gpio-eb", "ext-26m", 1168 0x4, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); 1169 static SPRD_SC_GATE_CLK_FW_NAME(mbox_eb, "mbox-eb", "ext-26m", 1170 0x4, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 1171 static SPRD_SC_GATE_CLK_FW_NAME(kpd_eb, "kpd-eb", "ext-26m", 1172 0x4, 0x1000, BIT(3), 0, 0); 1173 static SPRD_SC_GATE_CLK_FW_NAME(aon_syst_eb, "aon-syst-eb", "ext-26m", 1174 0x4, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); 1175 static SPRD_SC_GATE_CLK_FW_NAME(ap_syst_eb, "ap-syst-eb", "ext-26m", 1176 0x4, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); 1177 static SPRD_SC_GATE_CLK_FW_NAME(aon_tmr_eb, "aon-tmr-eb", "ext-26m", 1178 0x4, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); 1179 static SPRD_SC_GATE_CLK_FW_NAME(otg_utmi_eb, "otg-utmi-eb", "ext-26m", 1180 0x4, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); 1181 static SPRD_SC_GATE_CLK_FW_NAME(otg_phy_eb, "otg-phy-eb", "ext-26m", 1182 0x4, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); 1183 static SPRD_SC_GATE_CLK_FW_NAME(splk_eb, "splk-eb", "ext-26m", 1184 0x4, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); 1185 static SPRD_SC_GATE_CLK_FW_NAME(pin_eb, "pin-eb", "ext-26m", 1186 0x4, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); 1187 static SPRD_SC_GATE_CLK_FW_NAME(ana_eb, "ana-eb", "ext-26m", 1188 0x4, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 1189 static SPRD_SC_GATE_CLK_FW_NAME(apcpu_ts0_eb, "apcpu-ts0-eb", "ext-26m", 1190 0x4, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 1191 static SPRD_SC_GATE_CLK_FW_NAME(apb_busmon_eb, "apb-busmon-eb", "ext-26m", 1192 0x4, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); 1193 static SPRD_SC_GATE_CLK_FW_NAME(aon_iis_eb, "aon-iis-eb", "ext-26m", 1194 0x4, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); 1195 static SPRD_SC_GATE_CLK_FW_NAME(scc_eb, "scc-eb", "ext-26m", 1196 0x4, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); 1197 static SPRD_SC_GATE_CLK_FW_NAME(thm0_eb, "thm0-eb", "ext-26m", 1198 0x8, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); 1199 static SPRD_SC_GATE_CLK_FW_NAME(thm1_eb, "thm1-eb", "ext-26m", 1200 0x8, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); 1201 static SPRD_SC_GATE_CLK_FW_NAME(thm2_eb, "thm2-eb", "ext-26m", 1202 0x8, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 1203 static SPRD_SC_GATE_CLK_FW_NAME(asim_top_eb, "asim-top", "ext-26m", 1204 0x8, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); 1205 static SPRD_SC_GATE_CLK_FW_NAME(i2c_eb, "i2c-eb", "ext-26m", 1206 0x8, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); 1207 static SPRD_SC_GATE_CLK_FW_NAME(pmu_eb, "pmu-eb", "ext-26m", 1208 0x8, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); 1209 static SPRD_SC_GATE_CLK_FW_NAME(adi_eb, "adi-eb", "ext-26m", 1210 0x8, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); 1211 static SPRD_SC_GATE_CLK_FW_NAME(eic_eb, "eic-eb", "ext-26m", 1212 0x8, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); 1213 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc0_eb, "ap-intc0-eb", "ext-26m", 1214 0x8, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); 1215 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc1_eb, "ap-intc1-eb", "ext-26m", 1216 0x8, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 1217 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc2_eb, "ap-intc2-eb", "ext-26m", 1218 0x8, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); 1219 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc3_eb, "ap-intc3-eb", "ext-26m", 1220 0x8, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); 1221 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc4_eb, "ap-intc4-eb", "ext-26m", 1222 0x8, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); 1223 static SPRD_SC_GATE_CLK_FW_NAME(ap_intc5_eb, "ap-intc5-eb", "ext-26m", 1224 0x8, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); 1225 static SPRD_SC_GATE_CLK_FW_NAME(audcp_intc_eb, "audcp-intc-eb", "ext-26m", 1226 0x8, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 1227 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr0_eb, "ap-tmr0-eb", "ext-26m", 1228 0x8, 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); 1229 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr1_eb, "ap-tmr1-eb", "ext-26m", 1230 0x8, 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); 1231 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr2_eb, "ap-tmr2-eb", "ext-26m", 1232 0x8, 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); 1233 static SPRD_SC_GATE_CLK_FW_NAME(pwm0_eb, "pwm0-eb", "ext-26m", 1234 0x8, 0x1000, BIT(25), 0, 0); 1235 static SPRD_SC_GATE_CLK_FW_NAME(pwm1_eb, "pwm1-eb", "ext-26m", 1236 0x8, 0x1000, BIT(26), 0, 0); 1237 static SPRD_SC_GATE_CLK_FW_NAME(pwm2_eb, "pwm2-eb", "ext-26m", 1238 0x8, 0x1000, BIT(27), 0, 0); 1239 static SPRD_SC_GATE_CLK_FW_NAME(pwm3_eb, "pwm3-eb", "ext-26m", 1240 0x8, 0x1000, BIT(28), 0, 0); 1241 static SPRD_SC_GATE_CLK_FW_NAME(ap_wdg_eb, "ap-wdg-eb", "ext-26m", 1242 0x8, 0x1000, BIT(29), 0, 0); 1243 static SPRD_SC_GATE_CLK_FW_NAME(apcpu_wdg_eb, "apcpu-wdg-eb", "ext-26m", 1244 0x8, 0x1000, BIT(30), 0, 0); 1245 static SPRD_SC_GATE_CLK_FW_NAME(serdes_eb, "serdes-eb", "ext-26m", 1246 0x8, 0x1000, BIT(31), 0, 0); 1247 static SPRD_SC_GATE_CLK_FW_NAME(arch_rtc_eb, "arch-rtc-eb", "ext-26m", 1248 0x18, 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); 1249 static SPRD_SC_GATE_CLK_FW_NAME(kpd_rtc_eb, "kpd-rtc-eb", "ext-26m", 1250 0x18, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); 1251 static SPRD_SC_GATE_CLK_FW_NAME(aon_syst_rtc_eb, "aon-syst-rtc-eb", "ext-26m", 1252 0x18, 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 1253 static SPRD_SC_GATE_CLK_FW_NAME(ap_syst_rtc_eb, "ap-syst-rtc-eb", "ext-26m", 1254 0x18, 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); 1255 static SPRD_SC_GATE_CLK_FW_NAME(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", "ext-26m", 1256 0x18, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); 1257 static SPRD_SC_GATE_CLK_FW_NAME(eic_rtc_eb, "eic-rtc-eb", "ext-26m", 1258 0x18, 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); 1259 static SPRD_SC_GATE_CLK_FW_NAME(eic_rtcdv5_eb, "eic-rtcdv5-eb", "ext-26m", 1260 0x18, 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); 1261 static SPRD_SC_GATE_CLK_FW_NAME(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", "ext-26m", 1262 0x18, 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); 1263 static SPRD_SC_GATE_CLK_FW_NAME(ac_wdg_rtc_eb, "ac-wdg-rtc-eb", "ext-26m", 1264 0x18, 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); 1265 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", "ext-26m", 1266 0x18, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); 1267 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", "ext-26m", 1268 0x18, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); 1269 static SPRD_SC_GATE_CLK_FW_NAME(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", "ext-26m", 1270 0x18, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); 1271 static SPRD_SC_GATE_CLK_FW_NAME(dcxo_lc_rtc_eb, "dcxo-lc-rtc-eb", "ext-26m", 1272 0x18, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 1273 static SPRD_SC_GATE_CLK_FW_NAME(bb_cal_rtc_eb, "bb-cal-rtc-eb", "ext-26m", 1274 0x18, 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); 1275 static SPRD_SC_GATE_CLK_FW_NAME(ap_emmc_rtc_eb, "ap-emmc-rtc-eb", "ext-26m", 1276 0x18, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); 1277 static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio0_rtc_eb, "ap-sdio0-rtc-eb", "ext-26m", 1278 0x18, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); 1279 static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio1_rtc_eb, "ap-sdio1-rtc-eb", "ext-26m", 1280 0x18, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); 1281 static SPRD_SC_GATE_CLK_FW_NAME(ap_sdio2_rtc_eb, "ap-sdio2-rtc-eb", "ext-26m", 1282 0x18, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 1283 static SPRD_SC_GATE_CLK_FW_NAME(dsi_csi_test_eb, "dsi-csi-test-eb", "ext-26m", 1284 0x138, 0x1000, BIT(8), 0, 0); 1285 static SPRD_SC_GATE_CLK_FW_NAME(djtag_tck_en, "djtag-tck-en", "ext-26m", 1286 0x138, 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); 1287 static SPRD_SC_GATE_CLK_FW_NAME(dphy_ref_eb, "dphy-ref-eb", "ext-26m", 1288 0x138, 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); 1289 static SPRD_SC_GATE_CLK_FW_NAME(dmc_ref_eb, "dmc-ref-eb", "ext-26m", 1290 0x138, 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); 1291 static SPRD_SC_GATE_CLK_FW_NAME(otg_ref_eb, "otg-ref-eb", "ext-26m", 1292 0x138, 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 1293 static SPRD_SC_GATE_CLK_FW_NAME(tsen_eb, "tsen-eb", "ext-26m", 1294 0x138, 0x1000, BIT(13), 0, 0); 1295 static SPRD_SC_GATE_CLK_FW_NAME(tmr_eb, "tmr-eb", "ext-26m", 1296 0x138, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); 1297 static SPRD_SC_GATE_CLK_FW_NAME(rc100m_ref_eb, "rc100m-ref-eb", "ext-26m", 1298 0x138, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); 1299 static SPRD_SC_GATE_CLK_FW_NAME(rc100m_fdk_eb, "rc100m-fdk-eb", "ext-26m", 1300 0x138, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); 1301 static SPRD_SC_GATE_CLK_FW_NAME(debounce_eb, "debounce-eb", "ext-26m", 1302 0x138, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 1303 static SPRD_SC_GATE_CLK_FW_NAME(det_32k_eb, "det-32k-eb", "ext-26m", 1304 0x138, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); 1305 static SPRD_SC_GATE_CLK_FW_NAME(top_cssys_en, "top-cssys-en", "ext-26m", 1306 0x13c, 0x1000, BIT(0), 0, 0); 1307 static SPRD_SC_GATE_CLK_FW_NAME(ap_axi_en, "ap-axi-en", "ext-26m", 1308 0x13c, 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); 1309 static SPRD_SC_GATE_CLK_FW_NAME(sdio0_2x_en, "sdio0-2x-en", "ext-26m", 1310 0x13c, 0x1000, BIT(2), 0, 0); 1311 static SPRD_SC_GATE_CLK_FW_NAME(sdio0_1x_en, "sdio0-1x-en", "ext-26m", 1312 0x13c, 0x1000, BIT(3), 0, 0); 1313 static SPRD_SC_GATE_CLK_FW_NAME(sdio1_2x_en, "sdio1-2x-en", "ext-26m", 1314 0x13c, 0x1000, BIT(4), 0, 0); 1315 static SPRD_SC_GATE_CLK_FW_NAME(sdio1_1x_en, "sdio1-1x-en", "ext-26m", 1316 0x13c, 0x1000, BIT(5), 0, 0); 1317 static SPRD_SC_GATE_CLK_FW_NAME(sdio2_2x_en, "sdio2-2x-en", "ext-26m", 1318 0x13c, 0x1000, BIT(6), 0, 0); 1319 static SPRD_SC_GATE_CLK_FW_NAME(sdio2_1x_en, "sdio2-1x-en", "ext-26m", 1320 0x13c, 0x1000, BIT(7), 0, 0); 1321 static SPRD_SC_GATE_CLK_FW_NAME(emmc_2x_en, "emmc-2x-en", "ext-26m", 1322 0x13c, 0x1000, BIT(8), 0, 0); 1323 static SPRD_SC_GATE_CLK_FW_NAME(emmc_1x_en, "emmc-1x-en", "ext-26m", 1324 0x13c, 0x1000, BIT(9), 0, 0); 1325 static SPRD_SC_GATE_CLK_FW_NAME(pll_test_en, "pll-test-en", "ext-26m", 1326 0x13c, 0x1000, BIT(14), 0, 0); 1327 static SPRD_SC_GATE_CLK_FW_NAME(cphy_cfg_en, "cphy-cfg-en", "ext-26m", 1328 0x13c, 0x1000, BIT(15), 0, 0); 1329 static SPRD_SC_GATE_CLK_FW_NAME(debug_ts_en, "debug-ts-en", "ext-26m", 1330 0x13c, 0x1000, BIT(18), 0, 0); 1331 static SPRD_SC_GATE_CLK_FW_NAME(access_aud_en, "access-aud-en", 1332 "ext-26m", 0x14c, 0x1000, BIT(0), 0, 0); 1333 1334 static struct sprd_clk_common *ums512_aon_gate[] = { 1335 /* address base is 0x327d0000 */ 1336 &rc100m_cal_eb.common, 1337 &djtag_tck_eb.common, 1338 &djtag_eb.common, 1339 &aux0_eb.common, 1340 &aux1_eb.common, 1341 &aux2_eb.common, 1342 &probe_eb.common, 1343 &mm_eb.common, 1344 &gpu_eb.common, 1345 &mspi_eb.common, 1346 &apcpu_dap_eb.common, 1347 &aon_cssys_eb.common, 1348 &cssys_apb_eb.common, 1349 &cssys_pub_eb.common, 1350 &sdphy_cfg_eb.common, 1351 &sdphy_ref_eb.common, 1352 &efuse_eb.common, 1353 &gpio_eb.common, 1354 &mbox_eb.common, 1355 &kpd_eb.common, 1356 &aon_syst_eb.common, 1357 &ap_syst_eb.common, 1358 &aon_tmr_eb.common, 1359 &otg_utmi_eb.common, 1360 &otg_phy_eb.common, 1361 &splk_eb.common, 1362 &pin_eb.common, 1363 &ana_eb.common, 1364 &apcpu_ts0_eb.common, 1365 &apb_busmon_eb.common, 1366 &aon_iis_eb.common, 1367 &scc_eb.common, 1368 &thm0_eb.common, 1369 &thm1_eb.common, 1370 &thm2_eb.common, 1371 &asim_top_eb.common, 1372 &i2c_eb.common, 1373 &pmu_eb.common, 1374 &adi_eb.common, 1375 &eic_eb.common, 1376 &ap_intc0_eb.common, 1377 &ap_intc1_eb.common, 1378 &ap_intc2_eb.common, 1379 &ap_intc3_eb.common, 1380 &ap_intc4_eb.common, 1381 &ap_intc5_eb.common, 1382 &audcp_intc_eb.common, 1383 &ap_tmr0_eb.common, 1384 &ap_tmr1_eb.common, 1385 &ap_tmr2_eb.common, 1386 &pwm0_eb.common, 1387 &pwm1_eb.common, 1388 &pwm2_eb.common, 1389 &pwm3_eb.common, 1390 &ap_wdg_eb.common, 1391 &apcpu_wdg_eb.common, 1392 &serdes_eb.common, 1393 &arch_rtc_eb.common, 1394 &kpd_rtc_eb.common, 1395 &aon_syst_rtc_eb.common, 1396 &ap_syst_rtc_eb.common, 1397 &aon_tmr_rtc_eb.common, 1398 &eic_rtc_eb.common, 1399 &eic_rtcdv5_eb.common, 1400 &ap_wdg_rtc_eb.common, 1401 &ac_wdg_rtc_eb.common, 1402 &ap_tmr0_rtc_eb.common, 1403 &ap_tmr1_rtc_eb.common, 1404 &ap_tmr2_rtc_eb.common, 1405 &dcxo_lc_rtc_eb.common, 1406 &bb_cal_rtc_eb.common, 1407 &ap_emmc_rtc_eb.common, 1408 &ap_sdio0_rtc_eb.common, 1409 &ap_sdio1_rtc_eb.common, 1410 &ap_sdio2_rtc_eb.common, 1411 &dsi_csi_test_eb.common, 1412 &djtag_tck_en.common, 1413 &dphy_ref_eb.common, 1414 &dmc_ref_eb.common, 1415 &otg_ref_eb.common, 1416 &tsen_eb.common, 1417 &tmr_eb.common, 1418 &rc100m_ref_eb.common, 1419 &rc100m_fdk_eb.common, 1420 &debounce_eb.common, 1421 &det_32k_eb.common, 1422 &top_cssys_en.common, 1423 &ap_axi_en.common, 1424 &sdio0_2x_en.common, 1425 &sdio0_1x_en.common, 1426 &sdio1_2x_en.common, 1427 &sdio1_1x_en.common, 1428 &sdio2_2x_en.common, 1429 &sdio2_1x_en.common, 1430 &emmc_2x_en.common, 1431 &emmc_1x_en.common, 1432 &pll_test_en.common, 1433 &cphy_cfg_en.common, 1434 &debug_ts_en.common, 1435 &access_aud_en.common, 1436 }; 1437 1438 static struct clk_hw_onecell_data ums512_aon_gate_hws = { 1439 .hws = { 1440 [CLK_RC100M_CAL_EB] = &rc100m_cal_eb.common.hw, 1441 [CLK_DJTAG_TCK_EB] = &djtag_tck_eb.common.hw, 1442 [CLK_DJTAG_EB] = &djtag_eb.common.hw, 1443 [CLK_AUX0_EB] = &aux0_eb.common.hw, 1444 [CLK_AUX1_EB] = &aux1_eb.common.hw, 1445 [CLK_AUX2_EB] = &aux2_eb.common.hw, 1446 [CLK_PROBE_EB] = &probe_eb.common.hw, 1447 [CLK_MM_EB] = &mm_eb.common.hw, 1448 [CLK_GPU_EB] = &gpu_eb.common.hw, 1449 [CLK_MSPI_EB] = &mspi_eb.common.hw, 1450 [CLK_APCPU_DAP_EB] = &apcpu_dap_eb.common.hw, 1451 [CLK_AON_CSSYS_EB] = &aon_cssys_eb.common.hw, 1452 [CLK_CSSYS_APB_EB] = &cssys_apb_eb.common.hw, 1453 [CLK_CSSYS_PUB_EB] = &cssys_pub_eb.common.hw, 1454 [CLK_SDPHY_CFG_EB] = &sdphy_cfg_eb.common.hw, 1455 [CLK_SDPHY_REF_EB] = &sdphy_ref_eb.common.hw, 1456 [CLK_EFUSE_EB] = &efuse_eb.common.hw, 1457 [CLK_GPIO_EB] = &gpio_eb.common.hw, 1458 [CLK_MBOX_EB] = &mbox_eb.common.hw, 1459 [CLK_KPD_EB] = &kpd_eb.common.hw, 1460 [CLK_AON_SYST_EB] = &aon_syst_eb.common.hw, 1461 [CLK_AP_SYST_EB] = &ap_syst_eb.common.hw, 1462 [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw, 1463 [CLK_OTG_UTMI_EB] = &otg_utmi_eb.common.hw, 1464 [CLK_OTG_PHY_EB] = &otg_phy_eb.common.hw, 1465 [CLK_SPLK_EB] = &splk_eb.common.hw, 1466 [CLK_PIN_EB] = &pin_eb.common.hw, 1467 [CLK_ANA_EB] = &ana_eb.common.hw, 1468 [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw, 1469 [CLK_APB_BUSMON_EB] = &apb_busmon_eb.common.hw, 1470 [CLK_AON_IIS_EB] = &aon_iis_eb.common.hw, 1471 [CLK_SCC_EB] = &scc_eb.common.hw, 1472 [CLK_THM0_EB] = &thm0_eb.common.hw, 1473 [CLK_THM1_EB] = &thm1_eb.common.hw, 1474 [CLK_THM2_EB] = &thm2_eb.common.hw, 1475 [CLK_ASIM_TOP_EB] = &asim_top_eb.common.hw, 1476 [CLK_I2C_EB] = &i2c_eb.common.hw, 1477 [CLK_PMU_EB] = &pmu_eb.common.hw, 1478 [CLK_ADI_EB] = &adi_eb.common.hw, 1479 [CLK_EIC_EB] = &eic_eb.common.hw, 1480 [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw, 1481 [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw, 1482 [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw, 1483 [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw, 1484 [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw, 1485 [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw, 1486 [CLK_AUDCP_INTC_EB] = &audcp_intc_eb.common.hw, 1487 [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw, 1488 [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw, 1489 [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw, 1490 [CLK_PWM0_EB] = &pwm0_eb.common.hw, 1491 [CLK_PWM1_EB] = &pwm1_eb.common.hw, 1492 [CLK_PWM2_EB] = &pwm2_eb.common.hw, 1493 [CLK_PWM3_EB] = &pwm3_eb.common.hw, 1494 [CLK_AP_WDG_EB] = &ap_wdg_eb.common.hw, 1495 [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw, 1496 [CLK_SERDES_EB] = &serdes_eb.common.hw, 1497 [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw, 1498 [CLK_KPD_RTC_EB] = &kpd_rtc_eb.common.hw, 1499 [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw, 1500 [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw, 1501 [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw, 1502 [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw, 1503 [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw, 1504 [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw, 1505 [CLK_AC_WDG_RTC_EB] = &ac_wdg_rtc_eb.common.hw, 1506 [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw, 1507 [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw, 1508 [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw, 1509 [CLK_DCXO_LC_RTC_EB] = &dcxo_lc_rtc_eb.common.hw, 1510 [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw, 1511 [CLK_AP_EMMC_RTC_EB] = &ap_emmc_rtc_eb.common.hw, 1512 [CLK_AP_SDIO0_RTC_EB] = &ap_sdio0_rtc_eb.common.hw, 1513 [CLK_AP_SDIO1_RTC_EB] = &ap_sdio1_rtc_eb.common.hw, 1514 [CLK_AP_SDIO2_RTC_EB] = &ap_sdio2_rtc_eb.common.hw, 1515 [CLK_DSI_CSI_TEST_EB] = &dsi_csi_test_eb.common.hw, 1516 [CLK_DJTAG_TCK_EN] = &djtag_tck_en.common.hw, 1517 [CLK_DPHY_REF_EB] = &dphy_ref_eb.common.hw, 1518 [CLK_DMC_REF_EB] = &dmc_ref_eb.common.hw, 1519 [CLK_OTG_REF_EB] = &otg_ref_eb.common.hw, 1520 [CLK_TSEN_EB] = &tsen_eb.common.hw, 1521 [CLK_TMR_EB] = &tmr_eb.common.hw, 1522 [CLK_RC100M_REF_EB] = &rc100m_ref_eb.common.hw, 1523 [CLK_RC100M_FDK_EB] = &rc100m_fdk_eb.common.hw, 1524 [CLK_DEBOUNCE_EB] = &debounce_eb.common.hw, 1525 [CLK_DET_32K_EB] = &det_32k_eb.common.hw, 1526 [CLK_TOP_CSSYS_EB] = &top_cssys_en.common.hw, 1527 [CLK_AP_AXI_EN] = &ap_axi_en.common.hw, 1528 [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw, 1529 [CLK_SDIO0_1X_EN] = &sdio0_1x_en.common.hw, 1530 [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw, 1531 [CLK_SDIO1_1X_EN] = &sdio1_1x_en.common.hw, 1532 [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw, 1533 [CLK_SDIO2_1X_EN] = &sdio2_1x_en.common.hw, 1534 [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw, 1535 [CLK_EMMC_1X_EN] = &emmc_1x_en.common.hw, 1536 [CLK_PLL_TEST_EN] = &pll_test_en.common.hw, 1537 [CLK_CPHY_CFG_EN] = &cphy_cfg_en.common.hw, 1538 [CLK_DEBUG_TS_EN] = &debug_ts_en.common.hw, 1539 [CLK_ACCESS_AUD_EN] = &access_aud_en.common.hw, 1540 }, 1541 .num = CLK_AON_APB_GATE_NUM, 1542 }; 1543 1544 static struct sprd_clk_desc ums512_aon_gate_desc = { 1545 .clk_clks = ums512_aon_gate, 1546 .num_clk_clks = ARRAY_SIZE(ums512_aon_gate), 1547 .hw_clks = &ums512_aon_gate_hws, 1548 }; 1549 1550 /* audcp apb gates */ 1551 /* Audcp apb clocks configure CLK_IGNORE_UNUSED because these clocks may be 1552 * controlled by audcp sys at the same time. It may cause an exception if 1553 * kernel gates these clock. 1554 */ 1555 static SPRD_SC_GATE_CLK_HW(audcp_wdg_eb, "audcp-wdg-eb", 1556 &access_aud_en.common.hw, 0x0, 0x100, BIT(1), 1557 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1558 static SPRD_SC_GATE_CLK_HW(audcp_rtc_wdg_eb, "audcp-rtc-wdg-eb", 1559 &access_aud_en.common.hw, 0x0, 0x100, BIT(2), 1560 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1561 static SPRD_SC_GATE_CLK_HW(audcp_tmr0_eb, "audcp-tmr0-eb", 1562 &access_aud_en.common.hw, 0x0, 0x100, BIT(5), 1563 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1564 static SPRD_SC_GATE_CLK_HW(audcp_tmr1_eb, "audcp-tmr1-eb", 1565 &access_aud_en.common.hw, 0x0, 0x100, BIT(6), 1566 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1567 1568 static struct sprd_clk_common *ums512_audcpapb_gate[] = { 1569 /* address base is 0x3350d000 */ 1570 &audcp_wdg_eb.common, 1571 &audcp_rtc_wdg_eb.common, 1572 &audcp_tmr0_eb.common, 1573 &audcp_tmr1_eb.common, 1574 }; 1575 1576 static struct clk_hw_onecell_data ums512_audcpapb_gate_hws = { 1577 .hws = { 1578 [CLK_AUDCP_WDG_EB] = &audcp_wdg_eb.common.hw, 1579 [CLK_AUDCP_RTC_WDG_EB] = &audcp_rtc_wdg_eb.common.hw, 1580 [CLK_AUDCP_TMR0_EB] = &audcp_tmr0_eb.common.hw, 1581 [CLK_AUDCP_TMR1_EB] = &audcp_tmr1_eb.common.hw, 1582 }, 1583 .num = CLK_AUDCP_APB_GATE_NUM, 1584 }; 1585 1586 static const struct sprd_clk_desc ums512_audcpapb_gate_desc = { 1587 .clk_clks = ums512_audcpapb_gate, 1588 .num_clk_clks = ARRAY_SIZE(ums512_audcpapb_gate), 1589 .hw_clks = &ums512_audcpapb_gate_hws, 1590 }; 1591 1592 /* audcp ahb gates */ 1593 /* Audcp aphb clocks configure CLK_IGNORE_UNUSED because these clocks may be 1594 * controlled by audcp sys at the same time. It may cause an exception if 1595 * kernel gates these clock. 1596 */ 1597 static SPRD_SC_GATE_CLK_HW(audcp_iis0_eb, "audcp-iis0-eb", 1598 &access_aud_en.common.hw, 0x0, 0x100, BIT(0), 1599 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1600 static SPRD_SC_GATE_CLK_HW(audcp_iis1_eb, "audcp-iis1-eb", 1601 &access_aud_en.common.hw, 0x0, 0x100, BIT(1), 1602 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1603 static SPRD_SC_GATE_CLK_HW(audcp_iis2_eb, "audcp-iis2-eb", 1604 &access_aud_en.common.hw, 0x0, 0x100, BIT(2), 1605 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1606 static SPRD_SC_GATE_CLK_HW(audcp_uart_eb, "audcp-uart-eb", 1607 &access_aud_en.common.hw, 0x0, 0x100, BIT(4), 1608 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1609 static SPRD_SC_GATE_CLK_HW(audcp_dma_cp_eb, "audcp-dma-cp-eb", 1610 &access_aud_en.common.hw, 0x0, 0x100, BIT(5), 1611 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1612 static SPRD_SC_GATE_CLK_HW(audcp_dma_ap_eb, "audcp-dma-ap-eb", 1613 &access_aud_en.common.hw, 0x0, 0x100, BIT(6), 1614 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1615 static SPRD_SC_GATE_CLK_HW(audcp_src48k_eb, "audcp-src48k-eb", 1616 &access_aud_en.common.hw, 0x0, 0x100, BIT(10), 1617 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1618 static SPRD_SC_GATE_CLK_HW(audcp_mcdt_eb, "audcp-mcdt-eb", 1619 &access_aud_en.common.hw, 0x0, 0x100, BIT(12), 1620 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1621 static SPRD_SC_GATE_CLK_HW(audcp_vbcifd_eb, "audcp-vbcifd-eb", 1622 &access_aud_en.common.hw, 0x0, 0x100, BIT(13), 1623 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1624 static SPRD_SC_GATE_CLK_HW(audcp_vbc_eb, "audcp-vbc-eb", 1625 &access_aud_en.common.hw, 0x0, 0x100, BIT(14), 1626 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1627 static SPRD_SC_GATE_CLK_HW(audcp_splk_eb, "audcp-splk-eb", 1628 &access_aud_en.common.hw, 0x0, 0x100, BIT(15), 1629 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1630 static SPRD_SC_GATE_CLK_HW(audcp_icu_eb, "audcp-icu-eb", 1631 &access_aud_en.common.hw, 0x0, 0x100, BIT(16), 1632 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1633 static SPRD_SC_GATE_CLK_HW(dma_ap_ashb_eb, "dma-ap-ashb-eb", 1634 &access_aud_en.common.hw, 0x0, 0x100, BIT(17), 1635 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1636 static SPRD_SC_GATE_CLK_HW(dma_cp_ashb_eb, "dma-cp-ashb-eb", 1637 &access_aud_en.common.hw, 0x0, 0x100, BIT(18), 1638 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1639 static SPRD_SC_GATE_CLK_HW(audcp_aud_eb, "audcp-aud-eb", 1640 &access_aud_en.common.hw, 0x0, 0x100, BIT(19), 1641 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1642 static SPRD_SC_GATE_CLK_HW(audcp_vbc_24m_eb, "audcp-vbc-24m-eb", 1643 &access_aud_en.common.hw, 0x0, 0x100, BIT(21), 1644 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1645 static SPRD_SC_GATE_CLK_HW(audcp_tmr_26m_eb, "audcp-tmr-26m-eb", 1646 &access_aud_en.common.hw, 0x0, 0x100, BIT(22), 1647 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1648 static SPRD_SC_GATE_CLK_HW(audcp_dvfs_ashb_eb, "audcp-dvfs-ashb-eb", 1649 &access_aud_en.common.hw, 0x0, 0x100, BIT(23), 1650 CLK_IGNORE_UNUSED, SPRD_GATE_NON_AON); 1651 1652 static struct sprd_clk_common *ums512_audcpahb_gate[] = { 1653 /* address base is 0x335e0000 */ 1654 &audcp_iis0_eb.common, 1655 &audcp_iis1_eb.common, 1656 &audcp_iis2_eb.common, 1657 &audcp_uart_eb.common, 1658 &audcp_dma_cp_eb.common, 1659 &audcp_dma_ap_eb.common, 1660 &audcp_src48k_eb.common, 1661 &audcp_mcdt_eb.common, 1662 &audcp_vbcifd_eb.common, 1663 &audcp_vbc_eb.common, 1664 &audcp_splk_eb.common, 1665 &audcp_icu_eb.common, 1666 &dma_ap_ashb_eb.common, 1667 &dma_cp_ashb_eb.common, 1668 &audcp_aud_eb.common, 1669 &audcp_vbc_24m_eb.common, 1670 &audcp_tmr_26m_eb.common, 1671 &audcp_dvfs_ashb_eb.common, 1672 }; 1673 1674 static struct clk_hw_onecell_data ums512_audcpahb_gate_hws = { 1675 .hws = { 1676 [CLK_AUDCP_IIS0_EB] = &audcp_iis0_eb.common.hw, 1677 [CLK_AUDCP_IIS1_EB] = &audcp_iis1_eb.common.hw, 1678 [CLK_AUDCP_IIS2_EB] = &audcp_iis2_eb.common.hw, 1679 [CLK_AUDCP_UART_EB] = &audcp_uart_eb.common.hw, 1680 [CLK_AUDCP_DMA_CP_EB] = &audcp_dma_cp_eb.common.hw, 1681 [CLK_AUDCP_DMA_AP_EB] = &audcp_dma_ap_eb.common.hw, 1682 [CLK_AUDCP_SRC48K_EB] = &audcp_src48k_eb.common.hw, 1683 [CLK_AUDCP_MCDT_EB] = &audcp_mcdt_eb.common.hw, 1684 [CLK_AUDCP_VBCIFD_EB] = &audcp_vbcifd_eb.common.hw, 1685 [CLK_AUDCP_VBC_EB] = &audcp_vbc_eb.common.hw, 1686 [CLK_AUDCP_SPLK_EB] = &audcp_splk_eb.common.hw, 1687 [CLK_AUDCP_ICU_EB] = &audcp_icu_eb.common.hw, 1688 [CLK_AUDCP_DMA_AP_ASHB_EB] = &dma_ap_ashb_eb.common.hw, 1689 [CLK_AUDCP_DMA_CP_ASHB_EB] = &dma_cp_ashb_eb.common.hw, 1690 [CLK_AUDCP_AUD_EB] = &audcp_aud_eb.common.hw, 1691 [CLK_AUDCP_VBC_24M_EB] = &audcp_vbc_24m_eb.common.hw, 1692 [CLK_AUDCP_TMR_26M_EB] = &audcp_tmr_26m_eb.common.hw, 1693 [CLK_AUDCP_DVFS_ASHB_EB] = &audcp_dvfs_ashb_eb.common.hw, 1694 }, 1695 .num = CLK_AUDCP_AHB_GATE_NUM, 1696 }; 1697 1698 static const struct sprd_clk_desc ums512_audcpahb_gate_desc = { 1699 .clk_clks = ums512_audcpahb_gate, 1700 .num_clk_clks = ARRAY_SIZE(ums512_audcpahb_gate), 1701 .hw_clks = &ums512_audcpahb_gate_hws, 1702 }; 1703 1704 /* gpu clocks */ 1705 static SPRD_GATE_CLK_HW(gpu_core_gate, "gpu-core-gate", &gpu_eb.common.hw, 1706 0x4, BIT(0), 0, 0); 1707 1708 static const struct clk_parent_data gpu_parents[] = { 1709 { .fw_name = "ext-26m" }, 1710 { .hw = &twpll_384m.hw }, 1711 { .hw = &twpll_512m.hw }, 1712 { .hw = &lpll_614m4.hw }, 1713 { .hw = &twpll_768m.hw }, 1714 { .hw = &gpll.common.hw }, 1715 }; 1716 1717 static SPRD_COMP_CLK_DATA(gpu_core_clk, "gpu-core-clk", gpu_parents, 1718 0x4, 4, 3, 8, 3, 0); 1719 1720 static SPRD_GATE_CLK_HW(gpu_mem_gate, "gpu-mem-gate", &gpu_eb.common.hw, 1721 0x8, BIT(0), 0, 0); 1722 1723 static SPRD_COMP_CLK_DATA(gpu_mem_clk, "gpu-mem-clk", gpu_parents, 1724 0x8, 4, 3, 8, 3, 0); 1725 1726 static SPRD_GATE_CLK_HW(gpu_sys_gate, "gpu-sys-gate", &gpu_eb.common.hw, 1727 0xc, BIT(0), 0, 0); 1728 1729 static SPRD_DIV_CLK_HW(gpu_sys_clk, "gpu-sys-clk", &gpu_eb.common.hw, 1730 0xc, 4, 3, 0); 1731 1732 static struct sprd_clk_common *ums512_gpu_clk[] = { 1733 /* address base is 0x60100000 */ 1734 &gpu_core_gate.common, 1735 &gpu_core_clk.common, 1736 &gpu_mem_gate.common, 1737 &gpu_mem_clk.common, 1738 &gpu_sys_gate.common, 1739 &gpu_sys_clk.common, 1740 }; 1741 1742 static struct clk_hw_onecell_data ums512_gpu_clk_hws = { 1743 .hws = { 1744 [CLK_GPU_CORE_EB] = &gpu_core_gate.common.hw, 1745 [CLK_GPU_CORE] = &gpu_core_clk.common.hw, 1746 [CLK_GPU_MEM_EB] = &gpu_mem_gate.common.hw, 1747 [CLK_GPU_MEM] = &gpu_mem_clk.common.hw, 1748 [CLK_GPU_SYS_EB] = &gpu_sys_gate.common.hw, 1749 [CLK_GPU_SYS] = &gpu_sys_clk.common.hw, 1750 }, 1751 .num = CLK_GPU_CLK_NUM, 1752 }; 1753 1754 static struct sprd_clk_desc ums512_gpu_clk_desc = { 1755 .clk_clks = ums512_gpu_clk, 1756 .num_clk_clks = ARRAY_SIZE(ums512_gpu_clk), 1757 .hw_clks = &ums512_gpu_clk_hws, 1758 }; 1759 1760 /* mm clocks */ 1761 static const struct clk_parent_data mm_ahb_parents[] = { 1762 { .fw_name = "ext-26m" }, 1763 { .hw = &twpll_96m.hw }, 1764 { .hw = &twpll_128m.hw }, 1765 { .hw = &twpll_153m6.hw }, 1766 }; 1767 static SPRD_MUX_CLK_DATA(mm_ahb_clk, "mm-ahb-clk", mm_ahb_parents, 1768 0x20, 0, 2, UMS512_MUX_FLAG); 1769 1770 static const struct clk_parent_data mm_mtx_parents[] = { 1771 { .hw = &twpll_76m8.hw }, 1772 { .hw = &twpll_128m.hw }, 1773 { .hw = &twpll_256m.hw }, 1774 { .hw = &twpll_307m2.hw }, 1775 { .hw = &twpll_384m.hw }, 1776 { .hw = &isppll_468m.hw }, 1777 { .hw = &twpll_512m.hw }, 1778 }; 1779 static SPRD_MUX_CLK_DATA(mm_mtx_clk, "mm-mtx-clk", mm_mtx_parents, 1780 0x24, 0, 3, UMS512_MUX_FLAG); 1781 1782 static const struct clk_parent_data sensor_parents[] = { 1783 { .fw_name = "ext-26m" }, 1784 { .hw = &twpll_48m.hw }, 1785 { .hw = &twpll_76m8.hw }, 1786 { .hw = &twpll_96m.hw }, 1787 }; 1788 static SPRD_COMP_CLK_DATA(sensor0_clk, "sensor0-clk", sensor_parents, 1789 0x28, 0, 2, 8, 3, 0); 1790 static SPRD_COMP_CLK_DATA(sensor1_clk, "sensor1-clk", sensor_parents, 1791 0x2c, 0, 2, 8, 3, 0); 1792 static SPRD_COMP_CLK_DATA(sensor2_clk, "sensor2-clk", sensor_parents, 1793 0x30, 0, 2, 8, 3, 0); 1794 1795 static const struct clk_parent_data cpp_parents[] = { 1796 { .hw = &twpll_76m8.hw }, 1797 { .hw = &twpll_128m.hw }, 1798 { .hw = &twpll_256m.hw }, 1799 { .hw = &twpll_384m.hw }, 1800 }; 1801 static SPRD_MUX_CLK_DATA(cpp_clk, "cpp-clk", cpp_parents, 1802 0x34, 0, 2, UMS512_MUX_FLAG); 1803 1804 static const struct clk_parent_data jpg_parents[] = { 1805 { .hw = &twpll_76m8.hw }, 1806 { .hw = &twpll_128m.hw }, 1807 { .hw = &twpll_256m.hw }, 1808 { .hw = &twpll_384m.hw }, 1809 }; 1810 static SPRD_MUX_CLK_DATA(jpg_clk, "jpg-clk", jpg_parents, 1811 0x38, 0, 2, UMS512_MUX_FLAG); 1812 1813 static const struct clk_parent_data fd_parents[] = { 1814 { .hw = &twpll_76m8.hw }, 1815 { .hw = &twpll_192m.hw }, 1816 { .hw = &twpll_307m2.hw }, 1817 { .hw = &twpll_384m.hw }, 1818 }; 1819 static SPRD_MUX_CLK_DATA(fd_clk, "fd-clk", fd_parents, 1820 0x3c, 0, 2, UMS512_MUX_FLAG); 1821 1822 static const struct clk_parent_data dcam_if_parents[] = { 1823 { .hw = &twpll_192m.hw }, 1824 { .hw = &twpll_256m.hw }, 1825 { .hw = &twpll_307m2.hw }, 1826 { .hw = &twpll_384m.hw }, 1827 { .hw = &isppll_468m.hw }, 1828 }; 1829 static SPRD_MUX_CLK_DATA(dcam_if_clk, "dcam-if-clk", dcam_if_parents, 1830 0x40, 0, 3, UMS512_MUX_FLAG); 1831 1832 static const struct clk_parent_data dcam_axi_parents[] = { 1833 { .hw = &twpll_256m.hw }, 1834 { .hw = &twpll_307m2.hw }, 1835 { .hw = &twpll_384m.hw }, 1836 { .hw = &isppll_468m.hw }, 1837 }; 1838 static SPRD_MUX_CLK_DATA(dcam_axi_clk, "dcam-axi-clk", dcam_axi_parents, 1839 0x44, 0, 2, UMS512_MUX_FLAG); 1840 1841 static const struct clk_parent_data isp_parents[] = { 1842 { .hw = &twpll_256m.hw }, 1843 { .hw = &twpll_307m2.hw }, 1844 { .hw = &twpll_384m.hw }, 1845 { .hw = &isppll_468m.hw }, 1846 { .hw = &twpll_512m.hw }, 1847 }; 1848 static SPRD_MUX_CLK_DATA(isp_clk, "isp-clk", isp_parents, 1849 0x48, 0, 3, UMS512_MUX_FLAG); 1850 1851 static SPRD_GATE_CLK_HW(mipi_csi0, "mipi-csi0", &mm_eb.common.hw, 1852 0x4c, BIT(16), CLK_IGNORE_UNUSED, 0); 1853 1854 static SPRD_GATE_CLK_HW(mipi_csi1, "mipi-csi1", &mm_eb.common.hw, 1855 0x50, BIT(16), CLK_IGNORE_UNUSED, 0); 1856 1857 static SPRD_GATE_CLK_HW(mipi_csi2, "mipi-csi2", &mm_eb.common.hw, 1858 0x54, BIT(16), CLK_IGNORE_UNUSED, 0); 1859 1860 static struct sprd_clk_common *ums512_mm_clk[] = { 1861 /* address base is 0x62100000 */ 1862 &mm_ahb_clk.common, 1863 &mm_mtx_clk.common, 1864 &sensor0_clk.common, 1865 &sensor1_clk.common, 1866 &sensor2_clk.common, 1867 &cpp_clk.common, 1868 &jpg_clk.common, 1869 &fd_clk.common, 1870 &dcam_if_clk.common, 1871 &dcam_axi_clk.common, 1872 &isp_clk.common, 1873 &mipi_csi0.common, 1874 &mipi_csi1.common, 1875 &mipi_csi2.common, 1876 }; 1877 1878 static struct clk_hw_onecell_data ums512_mm_clk_hws = { 1879 .hws = { 1880 [CLK_MM_AHB] = &mm_ahb_clk.common.hw, 1881 [CLK_MM_MTX] = &mm_mtx_clk.common.hw, 1882 [CLK_SENSOR0] = &sensor0_clk.common.hw, 1883 [CLK_SENSOR1] = &sensor1_clk.common.hw, 1884 [CLK_SENSOR2] = &sensor2_clk.common.hw, 1885 [CLK_CPP] = &cpp_clk.common.hw, 1886 [CLK_JPG] = &jpg_clk.common.hw, 1887 [CLK_FD] = &fd_clk.common.hw, 1888 [CLK_DCAM_IF] = &dcam_if_clk.common.hw, 1889 [CLK_DCAM_AXI] = &dcam_axi_clk.common.hw, 1890 [CLK_ISP] = &isp_clk.common.hw, 1891 [CLK_MIPI_CSI0] = &mipi_csi0.common.hw, 1892 [CLK_MIPI_CSI1] = &mipi_csi1.common.hw, 1893 [CLK_MIPI_CSI2] = &mipi_csi2.common.hw, 1894 }, 1895 .num = CLK_MM_CLK_NUM, 1896 }; 1897 1898 static struct sprd_clk_desc ums512_mm_clk_desc = { 1899 .clk_clks = ums512_mm_clk, 1900 .num_clk_clks = ARRAY_SIZE(ums512_mm_clk), 1901 .hw_clks = &ums512_mm_clk_hws, 1902 }; 1903 1904 /* mm gate clocks */ 1905 static SPRD_SC_GATE_CLK_HW(mm_cpp_eb, "mm-cpp-eb", &mm_eb.common.hw, 1906 0x0, 0x1000, BIT(0), 0, 0); 1907 static SPRD_SC_GATE_CLK_HW(mm_jpg_eb, "mm-jpg-eb", &mm_eb.common.hw, 1908 0x0, 0x1000, BIT(1), 0, 0); 1909 static SPRD_SC_GATE_CLK_HW(mm_dcam_eb, "mm-dcam-eb", &mm_eb.common.hw, 1910 0x0, 0x1000, BIT(2), 0, 0); 1911 static SPRD_SC_GATE_CLK_HW(mm_isp_eb, "mm-isp-eb", &mm_eb.common.hw, 1912 0x0, 0x1000, BIT(3), 0, 0); 1913 static SPRD_SC_GATE_CLK_HW(mm_csi2_eb, "mm-csi2-eb", &mm_eb.common.hw, 1914 0x0, 0x1000, BIT(4), 0, 0); 1915 static SPRD_SC_GATE_CLK_HW(mm_csi1_eb, "mm-csi1-eb", &mm_eb.common.hw, 1916 0x0, 0x1000, BIT(5), 0, 0); 1917 static SPRD_SC_GATE_CLK_HW(mm_csi0_eb, "mm-csi0-eb", &mm_eb.common.hw, 1918 0x0, 0x1000, BIT(6), 0, 0); 1919 static SPRD_SC_GATE_CLK_HW(mm_ckg_eb, "mm-ckg-eb", &mm_eb.common.hw, 1920 0x0, 0x1000, BIT(7), 0, 0); 1921 static SPRD_SC_GATE_CLK_HW(mm_isp_ahb_eb, "mm-isp-ahb-eb", &mm_eb.common.hw, 1922 0x0, 0x1000, BIT(8), 0, 0); 1923 static SPRD_SC_GATE_CLK_HW(mm_dvfs_eb, "mm-dvfs-eb", &mm_eb.common.hw, 1924 0x0, 0x1000, BIT(9), 0, 0); 1925 static SPRD_SC_GATE_CLK_HW(mm_fd_eb, "mm-fd-eb", &mm_eb.common.hw, 1926 0x0, 0x1000, BIT(10), 0, 0); 1927 static SPRD_SC_GATE_CLK_HW(mm_sensor2_en, "mm-sensor2-en", &mm_eb.common.hw, 1928 0x8, 0x1000, BIT(0), 0, 0); 1929 static SPRD_SC_GATE_CLK_HW(mm_sensor1_en, "mm-sensor1-en", &mm_eb.common.hw, 1930 0x8, 0x1000, BIT(1), 0, 0); 1931 static SPRD_SC_GATE_CLK_HW(mm_sensor0_en, "mm-sensor0-en", &mm_eb.common.hw, 1932 0x8, 0x1000, BIT(2), 0, 0); 1933 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi2_en, "mm-mipi-csi2-en", &mm_eb.common.hw, 1934 0x8, 0x1000, BIT(3), 0, 0); 1935 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi1_en, "mm-mipi-csi1-en", &mm_eb.common.hw, 1936 0x8, 0x1000, BIT(4), 0, 0); 1937 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi0_en, "mm-mipi-csi0-en", &mm_eb.common.hw, 1938 0x8, 0x1000, BIT(5), 0, 0); 1939 static SPRD_SC_GATE_CLK_HW(mm_dcam_axi_en, "mm-dcam-axi-en", &mm_eb.common.hw, 1940 0x8, 0x1000, BIT(6), 0, 0); 1941 static SPRD_SC_GATE_CLK_HW(mm_isp_axi_en, "mm-isp-axi-en", &mm_eb.common.hw, 1942 0x8, 0x1000, BIT(7), 0, 0); 1943 static SPRD_SC_GATE_CLK_HW(mm_cphy_en, "mm-cphy-en", &mm_eb.common.hw, 1944 0x8, 0x1000, BIT(8), 0, 0); 1945 1946 static struct sprd_clk_common *ums512_mm_gate_clk[] = { 1947 /* address base is 0x62200000 */ 1948 &mm_cpp_eb.common, 1949 &mm_jpg_eb.common, 1950 &mm_dcam_eb.common, 1951 &mm_isp_eb.common, 1952 &mm_csi2_eb.common, 1953 &mm_csi1_eb.common, 1954 &mm_csi0_eb.common, 1955 &mm_ckg_eb.common, 1956 &mm_isp_ahb_eb.common, 1957 &mm_dvfs_eb.common, 1958 &mm_fd_eb.common, 1959 &mm_sensor2_en.common, 1960 &mm_sensor1_en.common, 1961 &mm_sensor0_en.common, 1962 &mm_mipi_csi2_en.common, 1963 &mm_mipi_csi1_en.common, 1964 &mm_mipi_csi0_en.common, 1965 &mm_dcam_axi_en.common, 1966 &mm_isp_axi_en.common, 1967 &mm_cphy_en.common, 1968 }; 1969 1970 static struct clk_hw_onecell_data ums512_mm_gate_clk_hws = { 1971 .hws = { 1972 [CLK_MM_CPP_EB] = &mm_cpp_eb.common.hw, 1973 [CLK_MM_JPG_EB] = &mm_jpg_eb.common.hw, 1974 [CLK_MM_DCAM_EB] = &mm_dcam_eb.common.hw, 1975 [CLK_MM_ISP_EB] = &mm_isp_eb.common.hw, 1976 [CLK_MM_CSI2_EB] = &mm_csi2_eb.common.hw, 1977 [CLK_MM_CSI1_EB] = &mm_csi1_eb.common.hw, 1978 [CLK_MM_CSI0_EB] = &mm_csi0_eb.common.hw, 1979 [CLK_MM_CKG_EB] = &mm_ckg_eb.common.hw, 1980 [CLK_ISP_AHB_EB] = &mm_isp_ahb_eb.common.hw, 1981 [CLK_MM_DVFS_EB] = &mm_dvfs_eb.common.hw, 1982 [CLK_MM_FD_EB] = &mm_fd_eb.common.hw, 1983 [CLK_MM_SENSOR2_EB] = &mm_sensor2_en.common.hw, 1984 [CLK_MM_SENSOR1_EB] = &mm_sensor1_en.common.hw, 1985 [CLK_MM_SENSOR0_EB] = &mm_sensor0_en.common.hw, 1986 [CLK_MM_MIPI_CSI2_EB] = &mm_mipi_csi2_en.common.hw, 1987 [CLK_MM_MIPI_CSI1_EB] = &mm_mipi_csi1_en.common.hw, 1988 [CLK_MM_MIPI_CSI0_EB] = &mm_mipi_csi0_en.common.hw, 1989 [CLK_DCAM_AXI_EB] = &mm_dcam_axi_en.common.hw, 1990 [CLK_ISP_AXI_EB] = &mm_isp_axi_en.common.hw, 1991 [CLK_MM_CPHY_EB] = &mm_cphy_en.common.hw, 1992 }, 1993 .num = CLK_MM_GATE_CLK_NUM, 1994 }; 1995 1996 static struct sprd_clk_desc ums512_mm_gate_clk_desc = { 1997 .clk_clks = ums512_mm_gate_clk, 1998 .num_clk_clks = ARRAY_SIZE(ums512_mm_gate_clk), 1999 .hw_clks = &ums512_mm_gate_clk_hws, 2000 }; 2001 2002 /* ap apb gates */ 2003 static SPRD_SC_GATE_CLK_FW_NAME(sim0_eb, "sim0-eb", "ext-26m", 2004 0x0, 0x1000, BIT(0), 0, 0); 2005 static SPRD_SC_GATE_CLK_FW_NAME(iis0_eb, "iis0-eb", "ext-26m", 2006 0x0, 0x1000, BIT(1), 0, 0); 2007 static SPRD_SC_GATE_CLK_FW_NAME(iis1_eb, "iis1-eb", "ext-26m", 2008 0x0, 0x1000, BIT(2), 0, 0); 2009 static SPRD_SC_GATE_CLK_FW_NAME(iis2_eb, "iis2-eb", "ext-26m", 2010 0x0, 0x1000, BIT(3), 0, 0); 2011 static SPRD_SC_GATE_CLK_FW_NAME(apb_reg_eb, "apb-reg-eb", "ext-26m", 2012 0x0, 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); 2013 static SPRD_SC_GATE_CLK_FW_NAME(spi0_eb, "spi0-eb", "ext-26m", 2014 0x0, 0x1000, BIT(5), 0, 0); 2015 static SPRD_SC_GATE_CLK_FW_NAME(spi1_eb, "spi1-eb", "ext-26m", 2016 0x0, 0x1000, BIT(6), 0, 0); 2017 static SPRD_SC_GATE_CLK_FW_NAME(spi2_eb, "spi2-eb", "ext-26m", 2018 0x0, 0x1000, BIT(7), 0, 0); 2019 static SPRD_SC_GATE_CLK_FW_NAME(spi3_eb, "spi3-eb", "ext-26m", 2020 0x0, 0x1000, BIT(8), 0, 0); 2021 static SPRD_SC_GATE_CLK_FW_NAME(i2c0_eb, "i2c0-eb", "ext-26m", 2022 0x0, 0x1000, BIT(9), 0, 0); 2023 static SPRD_SC_GATE_CLK_FW_NAME(i2c1_eb, "i2c1-eb", "ext-26m", 2024 0x0, 0x1000, BIT(10), 0, 0); 2025 static SPRD_SC_GATE_CLK_FW_NAME(i2c2_eb, "i2c2-eb", "ext-26m", 2026 0x0, 0x1000, BIT(11), 0, 0); 2027 static SPRD_SC_GATE_CLK_FW_NAME(i2c3_eb, "i2c3-eb", "ext-26m", 2028 0x0, 0x1000, BIT(12), 0, 0); 2029 static SPRD_SC_GATE_CLK_FW_NAME(i2c4_eb, "i2c4-eb", "ext-26m", 2030 0x0, 0x1000, BIT(13), 0, 0); 2031 static SPRD_SC_GATE_CLK_FW_NAME(uart0_eb, "uart0-eb", "ext-26m", 2032 0x0, 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); 2033 static SPRD_SC_GATE_CLK_FW_NAME(uart1_eb, "uart1-eb", "ext-26m", 2034 0x0, 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); 2035 static SPRD_SC_GATE_CLK_FW_NAME(uart2_eb, "uart2-eb", "ext-26m", 2036 0x0, 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); 2037 static SPRD_SC_GATE_CLK_FW_NAME(sim0_32k_eb, "sim0-32k-eb", "ext-26m", 2038 0x0, 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 2039 static SPRD_SC_GATE_CLK_FW_NAME(spi0_lfin_eb, "spi0-lfin-eb", "ext-26m", 2040 0x0, 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); 2041 static SPRD_SC_GATE_CLK_FW_NAME(spi1_lfin_eb, "spi1-lfin-eb", "ext-26m", 2042 0x0, 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); 2043 static SPRD_SC_GATE_CLK_FW_NAME(spi2_lfin_eb, "spi2-lfin-eb", "ext-26m", 2044 0x0, 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); 2045 static SPRD_SC_GATE_CLK_FW_NAME(spi3_lfin_eb, "spi3-lfin-eb", "ext-26m", 2046 0x0, 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); 2047 static SPRD_SC_GATE_CLK_FW_NAME(sdio0_eb, "sdio0-eb", "ext-26m", 2048 0x0, 0x1000, BIT(22), 0, 0); 2049 static SPRD_SC_GATE_CLK_FW_NAME(sdio1_eb, "sdio1-eb", "ext-26m", 2050 0x0, 0x1000, BIT(23), 0, 0); 2051 static SPRD_SC_GATE_CLK_FW_NAME(sdio2_eb, "sdio2-eb", "ext-26m", 2052 0x0, 0x1000, BIT(24), 0, 0); 2053 static SPRD_SC_GATE_CLK_FW_NAME(emmc_eb, "emmc-eb", "ext-26m", 2054 0x0, 0x1000, BIT(25), 0, 0); 2055 static SPRD_SC_GATE_CLK_FW_NAME(sdio0_32k_eb, "sdio0-32k-eb", "ext-26m", 2056 0x0, 0x1000, BIT(26), 0, 0); 2057 static SPRD_SC_GATE_CLK_FW_NAME(sdio1_32k_eb, "sdio1-32k-eb", "ext-26m", 2058 0x0, 0x1000, BIT(27), 0, 0); 2059 static SPRD_SC_GATE_CLK_FW_NAME(sdio2_32k_eb, "sdio2-32k-eb", "ext-26m", 2060 0x0, 0x1000, BIT(28), 0, 0); 2061 static SPRD_SC_GATE_CLK_FW_NAME(emmc_32k_eb, "emmc-32k-eb", "ext-26m", 2062 0x0, 0x1000, BIT(29), 0, 0); 2063 2064 static struct sprd_clk_common *ums512_apapb_gate[] = { 2065 /* address base is 0x71000000 */ 2066 &sim0_eb.common, 2067 &iis0_eb.common, 2068 &iis1_eb.common, 2069 &iis2_eb.common, 2070 &apb_reg_eb.common, 2071 &spi0_eb.common, 2072 &spi1_eb.common, 2073 &spi2_eb.common, 2074 &spi3_eb.common, 2075 &i2c0_eb.common, 2076 &i2c1_eb.common, 2077 &i2c2_eb.common, 2078 &i2c3_eb.common, 2079 &i2c4_eb.common, 2080 &uart0_eb.common, 2081 &uart1_eb.common, 2082 &uart2_eb.common, 2083 &sim0_32k_eb.common, 2084 &spi0_lfin_eb.common, 2085 &spi1_lfin_eb.common, 2086 &spi2_lfin_eb.common, 2087 &spi3_lfin_eb.common, 2088 &sdio0_eb.common, 2089 &sdio1_eb.common, 2090 &sdio2_eb.common, 2091 &emmc_eb.common, 2092 &sdio0_32k_eb.common, 2093 &sdio1_32k_eb.common, 2094 &sdio2_32k_eb.common, 2095 &emmc_32k_eb.common, 2096 }; 2097 2098 static struct clk_hw_onecell_data ums512_apapb_gate_hws = { 2099 .hws = { 2100 [CLK_SIM0_EB] = &sim0_eb.common.hw, 2101 [CLK_IIS0_EB] = &iis0_eb.common.hw, 2102 [CLK_IIS1_EB] = &iis1_eb.common.hw, 2103 [CLK_IIS2_EB] = &iis2_eb.common.hw, 2104 [CLK_APB_REG_EB] = &apb_reg_eb.common.hw, 2105 [CLK_SPI0_EB] = &spi0_eb.common.hw, 2106 [CLK_SPI1_EB] = &spi1_eb.common.hw, 2107 [CLK_SPI2_EB] = &spi2_eb.common.hw, 2108 [CLK_SPI3_EB] = &spi3_eb.common.hw, 2109 [CLK_I2C0_EB] = &i2c0_eb.common.hw, 2110 [CLK_I2C1_EB] = &i2c1_eb.common.hw, 2111 [CLK_I2C2_EB] = &i2c2_eb.common.hw, 2112 [CLK_I2C3_EB] = &i2c3_eb.common.hw, 2113 [CLK_I2C4_EB] = &i2c4_eb.common.hw, 2114 [CLK_UART0_EB] = &uart0_eb.common.hw, 2115 [CLK_UART1_EB] = &uart1_eb.common.hw, 2116 [CLK_UART2_EB] = &uart2_eb.common.hw, 2117 [CLK_SIM0_32K_EB] = &sim0_32k_eb.common.hw, 2118 [CLK_SPI0_LFIN_EB] = &spi0_lfin_eb.common.hw, 2119 [CLK_SPI1_LFIN_EB] = &spi1_lfin_eb.common.hw, 2120 [CLK_SPI2_LFIN_EB] = &spi2_lfin_eb.common.hw, 2121 [CLK_SPI3_LFIN_EB] = &spi3_lfin_eb.common.hw, 2122 [CLK_SDIO0_EB] = &sdio0_eb.common.hw, 2123 [CLK_SDIO1_EB] = &sdio1_eb.common.hw, 2124 [CLK_SDIO2_EB] = &sdio2_eb.common.hw, 2125 [CLK_EMMC_EB] = &emmc_eb.common.hw, 2126 [CLK_SDIO0_32K_EB] = &sdio0_32k_eb.common.hw, 2127 [CLK_SDIO1_32K_EB] = &sdio1_32k_eb.common.hw, 2128 [CLK_SDIO2_32K_EB] = &sdio2_32k_eb.common.hw, 2129 [CLK_EMMC_32K_EB] = &emmc_32k_eb.common.hw, 2130 }, 2131 .num = CLK_AP_APB_GATE_NUM, 2132 }; 2133 2134 static struct sprd_clk_desc ums512_apapb_gate_desc = { 2135 .clk_clks = ums512_apapb_gate, 2136 .num_clk_clks = ARRAY_SIZE(ums512_apapb_gate), 2137 .hw_clks = &ums512_apapb_gate_hws, 2138 }; 2139 2140 static const struct of_device_id sprd_ums512_clk_ids[] = { 2141 { .compatible = "sprd,ums512-pmu-gate", /* 0x327e0000 */ 2142 .data = &ums512_pmu_gate_desc }, 2143 { .compatible = "sprd,ums512-g0-pll", /* 0x32390000 */ 2144 .data = &ums512_g0_pll_desc }, 2145 { .compatible = "sprd,ums512-g2-pll", /* 0x323b0000 */ 2146 .data = &ums512_g2_pll_desc }, 2147 { .compatible = "sprd,ums512-g3-pll", /* 0x323c0000 */ 2148 .data = &ums512_g3_pll_desc }, 2149 { .compatible = "sprd,ums512-gc-pll", /* 0x323e0000 */ 2150 .data = &ums512_gc_pll_desc }, 2151 { .compatible = "sprd,ums512-apahb-gate", /* 0x20100000 */ 2152 .data = &ums512_apahb_gate_desc }, 2153 { .compatible = "sprd,ums512-ap-clk", /* 0x20200000 */ 2154 .data = &ums512_ap_clk_desc }, 2155 { .compatible = "sprd,ums512-aonapb-clk", /* 0x32080200 */ 2156 .data = &ums512_aon_apb_desc }, 2157 { .compatible = "sprd,ums512-aon-gate", /* 0x327d0000 */ 2158 .data = &ums512_aon_gate_desc }, 2159 { .compatible = "sprd,ums512-audcpapb-gate", /* 0x3350d000 */ 2160 .data = &ums512_audcpapb_gate_desc }, 2161 { .compatible = "sprd,ums512-audcpahb-gate", /* 0x335e0000 */ 2162 .data = &ums512_audcpahb_gate_desc }, 2163 { .compatible = "sprd,ums512-gpu-clk", /* 0x60100000 */ 2164 .data = &ums512_gpu_clk_desc }, 2165 { .compatible = "sprd,ums512-mm-clk", /* 0x62100000 */ 2166 .data = &ums512_mm_clk_desc }, 2167 { .compatible = "sprd,ums512-mm-gate-clk", /* 0x62200000 */ 2168 .data = &ums512_mm_gate_clk_desc }, 2169 { .compatible = "sprd,ums512-apapb-gate", /* 0x71000000 */ 2170 .data = &ums512_apapb_gate_desc }, 2171 { } 2172 }; 2173 MODULE_DEVICE_TABLE(of, sprd_ums512_clk_ids); 2174 2175 static int ums512_clk_probe(struct platform_device *pdev) 2176 { 2177 const struct sprd_clk_desc *desc; 2178 int ret; 2179 2180 desc = device_get_match_data(&pdev->dev); 2181 if (!desc) 2182 return -ENODEV; 2183 2184 ret = sprd_clk_regmap_init(pdev, desc); 2185 if (ret) 2186 return ret; 2187 2188 return sprd_clk_probe(&pdev->dev, desc->hw_clks); 2189 } 2190 2191 static struct platform_driver ums512_clk_driver = { 2192 .probe = ums512_clk_probe, 2193 .driver = { 2194 .name = "ums512-clk", 2195 .of_match_table = sprd_ums512_clk_ids, 2196 }, 2197 }; 2198 module_platform_driver(ums512_clk_driver); 2199 2200 MODULE_DESCRIPTION("Unisoc UMS512 Clock Driver"); 2201 MODULE_LICENSE("GPL"); 2202