1 /* 2 * arch/arm/mach-spear13xx/spear1340_clock.c 3 * 4 * SPEAr1340 machine clock framework source file 5 * 6 * Copyright (C) 2012 ST Microelectronics 7 * Viresh Kumar <viresh.linux@gmail.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/of_platform.h> 19 #include <linux/spinlock_types.h> 20 #include <mach/spear.h> 21 #include "clk.h" 22 23 /* Clock Configuration Registers */ 24 #define SPEAR1340_SYS_CLK_CTRL (VA_MISC_BASE + 0x200) 25 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27 26 #define SPEAR1340_HCLK_SRC_SEL_MASK 1 27 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23 28 #define SPEAR1340_SCLK_SRC_SEL_MASK 3 29 30 /* PLL related registers and bit values */ 31 #define SPEAR1340_PLL_CFG (VA_MISC_BASE + 0x210) 32 /* PLL_CFG bit values */ 33 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1 34 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31 35 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29 36 #define SPEAR1340_GEN_SYNT_CLK_MASK 2 37 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27 38 #define SPEAR1340_PLL_CLK_MASK 2 39 #define SPEAR1340_PLL3_CLK_SHIFT 24 40 #define SPEAR1340_PLL2_CLK_SHIFT 22 41 #define SPEAR1340_PLL1_CLK_SHIFT 20 42 43 #define SPEAR1340_PLL1_CTR (VA_MISC_BASE + 0x214) 44 #define SPEAR1340_PLL1_FRQ (VA_MISC_BASE + 0x218) 45 #define SPEAR1340_PLL2_CTR (VA_MISC_BASE + 0x220) 46 #define SPEAR1340_PLL2_FRQ (VA_MISC_BASE + 0x224) 47 #define SPEAR1340_PLL3_CTR (VA_MISC_BASE + 0x22C) 48 #define SPEAR1340_PLL3_FRQ (VA_MISC_BASE + 0x230) 49 #define SPEAR1340_PLL4_CTR (VA_MISC_BASE + 0x238) 50 #define SPEAR1340_PLL4_FRQ (VA_MISC_BASE + 0x23C) 51 #define SPEAR1340_PERIP_CLK_CFG (VA_MISC_BASE + 0x244) 52 /* PERIP_CLK_CFG bit values */ 53 #define SPEAR1340_SPDIF_CLK_MASK 1 54 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15 55 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14 56 #define SPEAR1340_GPT3_CLK_SHIFT 13 57 #define SPEAR1340_GPT2_CLK_SHIFT 12 58 #define SPEAR1340_GPT_CLK_MASK 1 59 #define SPEAR1340_GPT1_CLK_SHIFT 9 60 #define SPEAR1340_GPT0_CLK_SHIFT 8 61 #define SPEAR1340_UART_CLK_MASK 2 62 #define SPEAR1340_UART1_CLK_SHIFT 6 63 #define SPEAR1340_UART0_CLK_SHIFT 4 64 #define SPEAR1340_CLCD_CLK_MASK 2 65 #define SPEAR1340_CLCD_CLK_SHIFT 2 66 #define SPEAR1340_C3_CLK_MASK 1 67 #define SPEAR1340_C3_CLK_SHIFT 1 68 69 #define SPEAR1340_GMAC_CLK_CFG (VA_MISC_BASE + 0x248) 70 #define SPEAR1340_GMAC_PHY_CLK_MASK 1 71 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2 72 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2 73 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0 74 75 #define SPEAR1340_I2S_CLK_CFG (VA_MISC_BASE + 0x24C) 76 /* I2S_CLK_CFG register mask */ 77 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F 78 #define SPEAR1340_I2S_SCLK_X_SHIFT 27 79 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F 80 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22 81 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21 82 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20 83 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF 84 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12 85 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF 86 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4 87 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3 88 #define SPEAR1340_I2S_REF_SEL_MASK 1 89 #define SPEAR1340_I2S_REF_SHIFT 2 90 #define SPEAR1340_I2S_SRC_CLK_MASK 2 91 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0 92 93 #define SPEAR1340_C3_CLK_SYNT (VA_MISC_BASE + 0x250) 94 #define SPEAR1340_UART0_CLK_SYNT (VA_MISC_BASE + 0x254) 95 #define SPEAR1340_UART1_CLK_SYNT (VA_MISC_BASE + 0x258) 96 #define SPEAR1340_GMAC_CLK_SYNT (VA_MISC_BASE + 0x25C) 97 #define SPEAR1340_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x260) 98 #define SPEAR1340_CFXD_CLK_SYNT (VA_MISC_BASE + 0x264) 99 #define SPEAR1340_ADC_CLK_SYNT (VA_MISC_BASE + 0x270) 100 #define SPEAR1340_AMBA_CLK_SYNT (VA_MISC_BASE + 0x274) 101 #define SPEAR1340_CLCD_CLK_SYNT (VA_MISC_BASE + 0x27C) 102 #define SPEAR1340_SYS_CLK_SYNT (VA_MISC_BASE + 0x284) 103 #define SPEAR1340_GEN_CLK_SYNT0 (VA_MISC_BASE + 0x28C) 104 #define SPEAR1340_GEN_CLK_SYNT1 (VA_MISC_BASE + 0x294) 105 #define SPEAR1340_GEN_CLK_SYNT2 (VA_MISC_BASE + 0x29C) 106 #define SPEAR1340_GEN_CLK_SYNT3 (VA_MISC_BASE + 0x304) 107 #define SPEAR1340_PERIP1_CLK_ENB (VA_MISC_BASE + 0x30C) 108 #define SPEAR1340_RTC_CLK_ENB 31 109 #define SPEAR1340_ADC_CLK_ENB 30 110 #define SPEAR1340_C3_CLK_ENB 29 111 #define SPEAR1340_CLCD_CLK_ENB 27 112 #define SPEAR1340_DMA_CLK_ENB 25 113 #define SPEAR1340_GPIO1_CLK_ENB 24 114 #define SPEAR1340_GPIO0_CLK_ENB 23 115 #define SPEAR1340_GPT1_CLK_ENB 22 116 #define SPEAR1340_GPT0_CLK_ENB 21 117 #define SPEAR1340_I2S_PLAY_CLK_ENB 20 118 #define SPEAR1340_I2S_REC_CLK_ENB 19 119 #define SPEAR1340_I2C0_CLK_ENB 18 120 #define SPEAR1340_SSP_CLK_ENB 17 121 #define SPEAR1340_UART0_CLK_ENB 15 122 #define SPEAR1340_PCIE_SATA_CLK_ENB 12 123 #define SPEAR1340_UOC_CLK_ENB 11 124 #define SPEAR1340_UHC1_CLK_ENB 10 125 #define SPEAR1340_UHC0_CLK_ENB 9 126 #define SPEAR1340_GMAC_CLK_ENB 8 127 #define SPEAR1340_CFXD_CLK_ENB 7 128 #define SPEAR1340_SDHCI_CLK_ENB 6 129 #define SPEAR1340_SMI_CLK_ENB 5 130 #define SPEAR1340_FSMC_CLK_ENB 4 131 #define SPEAR1340_SYSRAM0_CLK_ENB 3 132 #define SPEAR1340_SYSRAM1_CLK_ENB 2 133 #define SPEAR1340_SYSROM_CLK_ENB 1 134 #define SPEAR1340_BUS_CLK_ENB 0 135 136 #define SPEAR1340_PERIP2_CLK_ENB (VA_MISC_BASE + 0x310) 137 #define SPEAR1340_THSENS_CLK_ENB 8 138 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7 139 #define SPEAR1340_ACP_CLK_ENB 6 140 #define SPEAR1340_GPT3_CLK_ENB 5 141 #define SPEAR1340_GPT2_CLK_ENB 4 142 #define SPEAR1340_KBD_CLK_ENB 3 143 #define SPEAR1340_CPU_DBG_CLK_ENB 2 144 #define SPEAR1340_DDR_CORE_CLK_ENB 1 145 #define SPEAR1340_DDR_CTRL_CLK_ENB 0 146 147 #define SPEAR1340_PERIP3_CLK_ENB (VA_MISC_BASE + 0x314) 148 #define SPEAR1340_PLGPIO_CLK_ENB 18 149 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16 150 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15 151 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13 152 #define SPEAR1340_SPDIF_IN_CLK_ENB 12 153 #define SPEAR1340_VIDEO_IN_CLK_ENB 11 154 #define SPEAR1340_CAM0_CLK_ENB 10 155 #define SPEAR1340_CAM1_CLK_ENB 9 156 #define SPEAR1340_CAM2_CLK_ENB 8 157 #define SPEAR1340_CAM3_CLK_ENB 7 158 #define SPEAR1340_MALI_CLK_ENB 6 159 #define SPEAR1340_CEC0_CLK_ENB 5 160 #define SPEAR1340_CEC1_CLK_ENB 4 161 #define SPEAR1340_PWM_CLK_ENB 3 162 #define SPEAR1340_I2C1_CLK_ENB 2 163 #define SPEAR1340_UART1_CLK_ENB 1 164 165 static DEFINE_SPINLOCK(_lock); 166 167 /* pll rate configuration table, in ascending order of rates */ 168 static struct pll_rate_tbl pll_rtbl[] = { 169 /* PCLK 24MHz */ 170 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */ 171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */ 172 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */ 173 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ 174 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */ 175 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */ 176 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 177 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */ 178 }; 179 180 /* vco-pll4 rate configuration table, in ascending order of rates */ 181 static struct pll_rate_tbl pll4_rtbl[] = { 182 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */ 183 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */ 184 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */ 185 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 186 }; 187 188 /* 189 * All below entries generate 166 MHz for 190 * different values of vco1div2 191 */ 192 static struct frac_rate_tbl amba_synth_rtbl[] = { 193 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */ 194 {.div = 0x06062}, /* for vco1div2 = 500 MHz */ 195 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */ 196 {.div = 0x04000}, /* for vco1div2 = 332 MHz */ 197 {.div = 0x03031}, /* for vco1div2 = 250 MHz */ 198 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */ 199 }; 200 201 /* 202 * Synthesizer Clock derived from vcodiv2. This clock is one of the 203 * possible clocks to feed cpu directly. 204 * We can program this synthesizer to make cpu run on different clock 205 * frequencies. 206 * Following table provides configuration values to let cpu run on 200, 207 * 250, 332, 400 or 500 MHz considering different possibilites of input 208 * (vco1div2) clock. 209 * 210 * -------------------------------------------------------------------- 211 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div 212 * -------------------------------------------------------------------- 213 * 400 200 100 0x04000 214 * 400 250 125 0x03333 215 * 400 332 166 0x0268D 216 * 400 400 200 0x02000 217 * -------------------------------------------------------------------- 218 * 500 200 100 0x05000 219 * 500 250 125 0x04000 220 * 500 332 166 0x03031 221 * 500 400 200 0x02800 222 * 500 500 250 0x02000 223 * -------------------------------------------------------------------- 224 * 600 200 100 0x06000 225 * 600 250 125 0x04CCE 226 * 600 332 166 0x039D5 227 * 600 400 200 0x03000 228 * 600 500 250 0x02666 229 * -------------------------------------------------------------------- 230 * 664 200 100 0x06a38 231 * 664 250 125 0x054FD 232 * 664 332 166 0x04000 233 * 664 400 200 0x0351E 234 * 664 500 250 0x02A7E 235 * -------------------------------------------------------------------- 236 * 800 200 100 0x08000 237 * 800 250 125 0x06666 238 * 800 332 166 0x04D18 239 * 800 400 200 0x04000 240 * 800 500 250 0x03333 241 * -------------------------------------------------------------------- 242 * sys rate configuration table is in descending order of divisor. 243 */ 244 static struct frac_rate_tbl sys_synth_rtbl[] = { 245 {.div = 0x08000}, 246 {.div = 0x06a38}, 247 {.div = 0x06666}, 248 {.div = 0x06000}, 249 {.div = 0x054FD}, 250 {.div = 0x05000}, 251 {.div = 0x04D18}, 252 {.div = 0x04CCE}, 253 {.div = 0x04000}, 254 {.div = 0x039D5}, 255 {.div = 0x0351E}, 256 {.div = 0x03333}, 257 {.div = 0x03031}, 258 {.div = 0x03000}, 259 {.div = 0x02A7E}, 260 {.div = 0x02800}, 261 {.div = 0x0268D}, 262 {.div = 0x02666}, 263 {.div = 0x02000}, 264 }; 265 266 /* aux rate configuration table, in ascending order of rates */ 267 static struct aux_rate_tbl aux_rtbl[] = { 268 /* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */ 269 {.xscale = 5, .yscale = 122, .eq = 0}, 270 /* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */ 271 {.xscale = 10, .yscale = 204, .eq = 0}, 272 /* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */ 273 {.xscale = 4, .yscale = 25, .eq = 0}, 274 /* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */ 275 {.xscale = 4, .yscale = 21, .eq = 0}, 276 /* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */ 277 {.xscale = 5, .yscale = 18, .eq = 0}, 278 /* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */ 279 {.xscale = 2, .yscale = 6, .eq = 0}, 280 /* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */ 281 {.xscale = 5, .yscale = 12, .eq = 0}, 282 /* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */ 283 {.xscale = 2, .yscale = 4, .eq = 0}, 284 /* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */ 285 {.xscale = 5, .yscale = 18, .eq = 1}, 286 /* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */ 287 {.xscale = 1, .yscale = 3, .eq = 1}, 288 /* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */ 289 {.xscale = 5, .yscale = 12, .eq = 1}, 290 /* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */ 291 {.xscale = 1, .yscale = 2, .eq = 1}, 292 }; 293 294 /* gmac rate configuration table, in ascending order of rates */ 295 static struct aux_rate_tbl gmac_rtbl[] = { 296 /* For gmac phy input clk */ 297 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ 298 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ 299 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ 300 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ 301 }; 302 303 /* clcd rate configuration table, in ascending order of rates */ 304 static struct frac_rate_tbl clcd_rtbl[] = { 305 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/ 306 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/ 307 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 308 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 309 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 310 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ 311 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */ 312 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/ 313 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ 314 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/ 315 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/ 316 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 317 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 318 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ 319 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/ 320 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ 321 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/ 322 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 323 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/ 324 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/ 325 }; 326 327 /* i2s prescaler1 masks */ 328 static struct aux_clk_masks i2s_prs1_masks = { 329 .eq_sel_mask = AUX_EQ_SEL_MASK, 330 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT, 331 .eq1_mask = AUX_EQ1_SEL, 332 .eq2_mask = AUX_EQ2_SEL, 333 .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK, 334 .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT, 335 .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK, 336 .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT, 337 }; 338 339 /* i2s sclk (bit clock) syynthesizers masks */ 340 static struct aux_clk_masks i2s_sclk_masks = { 341 .eq_sel_mask = AUX_EQ_SEL_MASK, 342 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT, 343 .eq1_mask = AUX_EQ1_SEL, 344 .eq2_mask = AUX_EQ2_SEL, 345 .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK, 346 .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT, 347 .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK, 348 .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT, 349 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB, 350 }; 351 352 /* i2s prs1 aux rate configuration table, in ascending order of rates */ 353 static struct aux_rate_tbl i2s_prs1_rtbl[] = { 354 /* For parent clk = 49.152 MHz */ 355 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */ 356 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */ 357 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */ 358 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */ 359 360 /* 361 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz 362 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz 363 */ 364 {.xscale = 1, .yscale = 3, .eq = 0}, 365 366 /* For parent clk = 49.152 MHz */ 367 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/ 368 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/ 369 }; 370 371 /* i2s sclk aux rate configuration table, in ascending order of rates */ 372 static struct aux_rate_tbl i2s_sclk_rtbl[] = { 373 /* For sclk = ref_clk * x/2/y */ 374 {.xscale = 1, .yscale = 4, .eq = 0}, 375 {.xscale = 1, .yscale = 2, .eq = 0}, 376 }; 377 378 /* adc rate configuration table, in ascending order of rates */ 379 /* possible adc range is 2.5 MHz to 20 MHz. */ 380 static struct aux_rate_tbl adc_rtbl[] = { 381 /* For ahb = 166.67 MHz */ 382 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ 383 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ 384 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ 385 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ 386 }; 387 388 /* General synth rate configuration table, in ascending order of rates */ 389 static struct frac_rate_tbl gen_rtbl[] = { 390 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/ 391 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/ 392 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/ 393 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/ 394 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/ 395 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/ 396 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/ 397 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/ 398 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/ 399 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/ 400 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/ 401 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/ 402 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/ 403 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/ 404 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/ 405 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/ 406 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/ 407 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/ 408 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/ 409 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/ 410 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/ 411 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/ 412 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/ 413 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/ 414 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/ 415 }; 416 417 /* clock parents */ 418 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 419 static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk", 420 "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", }; 421 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", }; 422 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 423 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk", 424 "uart0_syn_gclk", }; 425 static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk", 426 "uart1_syn_gclk", }; 427 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", }; 428 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk", 429 "osc_25m_clk", }; 430 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", }; 431 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; 432 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", }; 433 static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk", 434 "i2s_src_pad_clk", }; 435 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", }; 436 static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", }; 437 static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", }; 438 439 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 440 "pll3_clk", }; 441 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk", 442 "pll2_clk", }; 443 444 void __init spear1340_clk_init(void) 445 { 446 struct clk *clk, *clk1; 447 448 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 449 32000); 450 clk_register_clkdev(clk, "osc_32k_clk", NULL); 451 452 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, 453 24000000); 454 clk_register_clkdev(clk, "osc_24m_clk", NULL); 455 456 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, 457 25000000); 458 clk_register_clkdev(clk, "osc_25m_clk", NULL); 459 460 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, 461 125000000); 462 clk_register_clkdev(clk, "gmii_pad_clk", NULL); 463 464 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 465 CLK_IS_ROOT, 12288000); 466 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); 467 468 /* clock derived from 32 KHz osc clk */ 469 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 470 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0, 471 &_lock); 472 clk_register_clkdev(clk, NULL, "e0580000.rtc"); 473 474 /* clock derived from 24 or 25 MHz osc clk */ 475 /* vco-pll */ 476 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 477 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 478 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 479 &_lock); 480 clk_register_clkdev(clk, "vco1_mclk", NULL); 481 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, 482 SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl, 483 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 484 clk_register_clkdev(clk, "vco1_clk", NULL); 485 clk_register_clkdev(clk1, "pll1_clk", NULL); 486 487 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 488 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 489 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 490 &_lock); 491 clk_register_clkdev(clk, "vco2_mclk", NULL); 492 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, 493 SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl, 494 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 495 clk_register_clkdev(clk, "vco2_clk", NULL); 496 clk_register_clkdev(clk1, "pll2_clk", NULL); 497 498 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 499 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 500 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 501 &_lock); 502 clk_register_clkdev(clk, "vco3_mclk", NULL); 503 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, 504 SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl, 505 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 506 clk_register_clkdev(clk, "vco3_clk", NULL); 507 clk_register_clkdev(clk1, "pll3_clk", NULL); 508 509 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 510 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl, 511 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); 512 clk_register_clkdev(clk, "vco4_clk", NULL); 513 clk_register_clkdev(clk1, "pll4_clk", NULL); 514 515 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 516 48000000); 517 clk_register_clkdev(clk, "pll5_clk", NULL); 518 519 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 520 25000000); 521 clk_register_clkdev(clk, "pll6_clk", NULL); 522 523 /* vco div n clocks */ 524 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 525 2); 526 clk_register_clkdev(clk, "vco1div2_clk", NULL); 527 528 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 529 4); 530 clk_register_clkdev(clk, "vco1div4_clk", NULL); 531 532 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 533 2); 534 clk_register_clkdev(clk, "vco2div2_clk", NULL); 535 536 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 537 2); 538 clk_register_clkdev(clk, "vco3div2_clk", NULL); 539 540 /* peripherals */ 541 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 542 128); 543 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, 544 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0, 545 &_lock); 546 clk_register_clkdev(clk, NULL, "e07008c4.thermal"); 547 548 /* clock derived from pll4 clk */ 549 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 550 1); 551 clk_register_clkdev(clk, "ddr_clk", NULL); 552 553 /* clock derived from pll1 clk */ 554 clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0, 555 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl, 556 ARRAY_SIZE(sys_synth_rtbl), &_lock); 557 clk_register_clkdev(clk, "sys_syn_clk", NULL); 558 559 clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0, 560 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl, 561 ARRAY_SIZE(amba_synth_rtbl), &_lock); 562 clk_register_clkdev(clk, "amba_syn_clk", NULL); 563 564 clk = clk_register_mux(NULL, "sys_mclk", sys_parents, 565 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL, 566 SPEAR1340_SCLK_SRC_SEL_SHIFT, 567 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock); 568 clk_register_clkdev(clk, "sys_mclk", NULL); 569 570 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1, 571 2); 572 clk_register_clkdev(clk, "cpu_clk", NULL); 573 574 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1, 575 3); 576 clk_register_clkdev(clk, "cpu_div3_clk", NULL); 577 578 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 579 2); 580 clk_register_clkdev(clk, NULL, "ec800620.wdt"); 581 582 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, 583 2); 584 clk_register_clkdev(clk, NULL, "smp_twd"); 585 586 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, 587 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL, 588 SPEAR1340_HCLK_SRC_SEL_SHIFT, 589 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock); 590 clk_register_clkdev(clk, "ahb_clk", NULL); 591 592 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 593 2); 594 clk_register_clkdev(clk, "apb_clk", NULL); 595 596 /* gpt clocks */ 597 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 598 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 599 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 600 &_lock); 601 clk_register_clkdev(clk, "gpt0_mclk", NULL); 602 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 603 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0, 604 &_lock); 605 clk_register_clkdev(clk, NULL, "gpt0"); 606 607 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 608 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 609 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 610 &_lock); 611 clk_register_clkdev(clk, "gpt1_mclk", NULL); 612 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 613 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0, 614 &_lock); 615 clk_register_clkdev(clk, NULL, "gpt1"); 616 617 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 618 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 619 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 620 &_lock); 621 clk_register_clkdev(clk, "gpt2_mclk", NULL); 622 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 623 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0, 624 &_lock); 625 clk_register_clkdev(clk, NULL, "gpt2"); 626 627 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 628 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 629 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 630 &_lock); 631 clk_register_clkdev(clk, "gpt3_mclk", NULL); 632 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 633 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0, 634 &_lock); 635 clk_register_clkdev(clk, NULL, "gpt3"); 636 637 /* others */ 638 clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk", 639 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL, 640 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 641 clk_register_clkdev(clk, "uart0_syn_clk", NULL); 642 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL); 643 644 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 645 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 646 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT, 647 SPEAR1340_UART_CLK_MASK, 0, &_lock); 648 clk_register_clkdev(clk, "uart0_mclk", NULL); 649 650 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 651 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, 652 SPEAR1340_UART0_CLK_ENB, 0, &_lock); 653 clk_register_clkdev(clk, NULL, "e0000000.serial"); 654 655 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk", 656 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL, 657 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 658 clk_register_clkdev(clk, "uart1_syn_clk", NULL); 659 clk_register_clkdev(clk1, "uart1_syn_gclk", NULL); 660 661 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents, 662 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG, 663 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, 664 &_lock); 665 clk_register_clkdev(clk, "uart1_mclk", NULL); 666 667 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 668 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0, 669 &_lock); 670 clk_register_clkdev(clk, NULL, "b4100000.serial"); 671 672 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", 673 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL, 674 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 675 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); 676 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); 677 678 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 679 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, 680 SPEAR1340_SDHCI_CLK_ENB, 0, &_lock); 681 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 682 683 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 684 0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl, 685 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 686 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); 687 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); 688 689 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 690 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, 691 SPEAR1340_CFXD_CLK_ENB, 0, &_lock); 692 clk_register_clkdev(clk, NULL, "b2800000.cf"); 693 clk_register_clkdev(clk, NULL, "arasan_xd"); 694 695 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0, 696 SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl, 697 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 698 clk_register_clkdev(clk, "c3_syn_clk", NULL); 699 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 700 701 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 702 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, 703 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT, 704 SPEAR1340_C3_CLK_MASK, 0, &_lock); 705 clk_register_clkdev(clk, "c3_mclk", NULL); 706 707 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT, 708 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0, 709 &_lock); 710 clk_register_clkdev(clk, NULL, "e1800000.c3"); 711 712 /* gmac */ 713 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 714 ARRAY_SIZE(gmac_phy_input_parents), 0, 715 SPEAR1340_GMAC_CLK_CFG, 716 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT, 717 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 718 clk_register_clkdev(clk, "phy_input_mclk", NULL); 719 720 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 721 0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl, 722 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); 723 clk_register_clkdev(clk, "phy_syn_clk", NULL); 724 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 725 726 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 727 ARRAY_SIZE(gmac_phy_parents), 0, 728 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT, 729 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock); 730 clk_register_clkdev(clk, "stmmacphy.0", NULL); 731 732 /* clcd */ 733 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 734 ARRAY_SIZE(clcd_synth_parents), 0, 735 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT, 736 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock); 737 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 738 739 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, 740 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl, 741 ARRAY_SIZE(clcd_rtbl), &_lock); 742 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 743 744 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 745 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, 746 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, 747 SPEAR1340_CLCD_CLK_MASK, 0, &_lock); 748 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 749 750 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, 751 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0, 752 &_lock); 753 clk_register_clkdev(clk, NULL, "e1000000.clcd"); 754 755 /* i2s */ 756 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 757 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG, 758 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK, 759 0, &_lock); 760 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 761 762 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 763 CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG, 764 &i2s_prs1_masks, i2s_prs1_rtbl, 765 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 766 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 767 768 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 769 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 770 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT, 771 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock); 772 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 773 774 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, 775 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB, 776 0, &_lock); 777 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 778 779 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk", 780 0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks, 781 i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock, 782 &clk1); 783 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 784 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); 785 786 /* clock derived from ahb clk */ 787 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, 788 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0, 789 &_lock); 790 clk_register_clkdev(clk, NULL, "e0280000.i2c"); 791 792 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0, 793 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0, 794 &_lock); 795 clk_register_clkdev(clk, NULL, "b4000000.i2c"); 796 797 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, 798 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0, 799 &_lock); 800 clk_register_clkdev(clk, NULL, "ea800000.dma"); 801 clk_register_clkdev(clk, NULL, "eb000000.dma"); 802 803 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, 804 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0, 805 &_lock); 806 clk_register_clkdev(clk, NULL, "e2000000.eth"); 807 808 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, 809 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0, 810 &_lock); 811 clk_register_clkdev(clk, NULL, "b0000000.flash"); 812 813 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, 814 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0, 815 &_lock); 816 clk_register_clkdev(clk, NULL, "ea000000.flash"); 817 818 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, 819 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0, 820 &_lock); 821 clk_register_clkdev(clk, NULL, "e4000000.ohci"); 822 clk_register_clkdev(clk, NULL, "e4800000.ehci"); 823 824 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, 825 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0, 826 &_lock); 827 clk_register_clkdev(clk, NULL, "e5000000.ohci"); 828 clk_register_clkdev(clk, NULL, "e5800000.ehci"); 829 830 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, 831 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0, 832 &_lock); 833 clk_register_clkdev(clk, NULL, "e3800000.otg"); 834 835 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0, 836 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB, 837 0, &_lock); 838 clk_register_clkdev(clk, NULL, "dw_pcie"); 839 clk_register_clkdev(clk, NULL, "b1000000.ahci"); 840 841 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 842 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0, 843 &_lock); 844 clk_register_clkdev(clk, "sysram0_clk", NULL); 845 846 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, 847 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0, 848 &_lock); 849 clk_register_clkdev(clk, "sysram1_clk", NULL); 850 851 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 852 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl, 853 ARRAY_SIZE(adc_rtbl), &_lock, &clk1); 854 clk_register_clkdev(clk, "adc_syn_clk", NULL); 855 clk_register_clkdev(clk1, "adc_syn_gclk", NULL); 856 857 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 858 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, 859 SPEAR1340_ADC_CLK_ENB, 0, &_lock); 860 clk_register_clkdev(clk, NULL, "e0080000.adc"); 861 862 /* clock derived from apb clk */ 863 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0, 864 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0, 865 &_lock); 866 clk_register_clkdev(clk, NULL, "e0100000.spi"); 867 868 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, 869 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0, 870 &_lock); 871 clk_register_clkdev(clk, NULL, "e0600000.gpio"); 872 873 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, 874 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0, 875 &_lock); 876 clk_register_clkdev(clk, NULL, "e0680000.gpio"); 877 878 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0, 879 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0, 880 &_lock); 881 clk_register_clkdev(clk, NULL, "b2400000.i2s-play"); 882 883 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0, 884 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0, 885 &_lock); 886 clk_register_clkdev(clk, NULL, "b2000000.i2s-rec"); 887 888 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, 889 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0, 890 &_lock); 891 clk_register_clkdev(clk, NULL, "e0300000.kbd"); 892 893 /* RAS clks */ 894 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 895 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG, 896 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT, 897 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 898 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL); 899 900 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 901 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG, 902 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT, 903 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 904 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL); 905 906 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0, 907 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 908 &_lock); 909 clk_register_clkdev(clk, "gen_syn0_clk", NULL); 910 911 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0, 912 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 913 &_lock); 914 clk_register_clkdev(clk, "gen_syn1_clk", NULL); 915 916 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0, 917 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 918 &_lock); 919 clk_register_clkdev(clk, "gen_syn2_clk", NULL); 920 921 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0, 922 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 923 &_lock); 924 clk_register_clkdev(clk, "gen_syn3_clk", NULL); 925 926 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", 927 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, 928 SPEAR1340_MALI_CLK_ENB, 0, &_lock); 929 clk_register_clkdev(clk, NULL, "mali"); 930 931 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, 932 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0, 933 &_lock); 934 clk_register_clkdev(clk, NULL, "spear_cec.0"); 935 936 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0, 937 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0, 938 &_lock); 939 clk_register_clkdev(clk, NULL, "spear_cec.1"); 940 941 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, 942 ARRAY_SIZE(spdif_out_parents), CLK_SET_RATE_PARENT, 943 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, 944 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 945 clk_register_clkdev(clk, "spdif_out_mclk", NULL); 946 947 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", 948 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, 949 SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock); 950 clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); 951 952 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, 953 ARRAY_SIZE(spdif_in_parents), CLK_SET_RATE_PARENT, 954 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, 955 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 956 clk_register_clkdev(clk, "spdif_in_mclk", NULL); 957 958 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", 959 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, 960 SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock); 961 clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); 962 963 clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0, 964 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0, 965 &_lock); 966 clk_register_clkdev(clk, NULL, "acp_clk"); 967 968 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0, 969 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0, 970 &_lock); 971 clk_register_clkdev(clk, NULL, "e2800000.gpio"); 972 973 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0, 974 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB, 975 0, &_lock); 976 clk_register_clkdev(clk, NULL, "video_dec"); 977 978 clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mclk", 0, 979 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB, 980 0, &_lock); 981 clk_register_clkdev(clk, NULL, "video_enc"); 982 983 clk = clk_register_gate(NULL, "video_in_clk", "video_in_mclk", 0, 984 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0, 985 &_lock); 986 clk_register_clkdev(clk, NULL, "spear_vip"); 987 988 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0, 989 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0, 990 &_lock); 991 clk_register_clkdev(clk, NULL, "d0200000.cam0"); 992 993 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0, 994 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0, 995 &_lock); 996 clk_register_clkdev(clk, NULL, "d0300000.cam1"); 997 998 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0, 999 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0, 1000 &_lock); 1001 clk_register_clkdev(clk, NULL, "d0400000.cam2"); 1002 1003 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0, 1004 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0, 1005 &_lock); 1006 clk_register_clkdev(clk, NULL, "d0500000.cam3"); 1007 1008 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0, 1009 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0, 1010 &_lock); 1011 clk_register_clkdev(clk, NULL, "e0180000.pwm"); 1012 } 1013