1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * arch/arm/mach-spear13xx/spear1340_clock.c 4 * 5 * SPEAr1340 machine clock framework source file 6 * 7 * Copyright (C) 2012 ST Microelectronics 8 * Viresh Kumar <vireshk@kernel.org> 9 */ 10 11 #include <linux/clkdev.h> 12 #include <linux/clk/spear.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/of_platform.h> 16 #include <linux/spinlock_types.h> 17 #include "clk.h" 18 19 /* Clock Configuration Registers */ 20 #define SPEAR1340_SYS_CLK_CTRL (misc_base + 0x200) 21 #define SPEAR1340_HCLK_SRC_SEL_SHIFT 27 22 #define SPEAR1340_HCLK_SRC_SEL_MASK 1 23 #define SPEAR1340_SCLK_SRC_SEL_SHIFT 23 24 #define SPEAR1340_SCLK_SRC_SEL_MASK 3 25 26 /* PLL related registers and bit values */ 27 #define SPEAR1340_PLL_CFG (misc_base + 0x210) 28 /* PLL_CFG bit values */ 29 #define SPEAR1340_CLCD_SYNT_CLK_MASK 1 30 #define SPEAR1340_CLCD_SYNT_CLK_SHIFT 31 31 #define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT 29 32 #define SPEAR1340_GEN_SYNT_CLK_MASK 2 33 #define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT 27 34 #define SPEAR1340_PLL_CLK_MASK 2 35 #define SPEAR1340_PLL3_CLK_SHIFT 24 36 #define SPEAR1340_PLL2_CLK_SHIFT 22 37 #define SPEAR1340_PLL1_CLK_SHIFT 20 38 39 #define SPEAR1340_PLL1_CTR (misc_base + 0x214) 40 #define SPEAR1340_PLL1_FRQ (misc_base + 0x218) 41 #define SPEAR1340_PLL2_CTR (misc_base + 0x220) 42 #define SPEAR1340_PLL2_FRQ (misc_base + 0x224) 43 #define SPEAR1340_PLL3_CTR (misc_base + 0x22C) 44 #define SPEAR1340_PLL3_FRQ (misc_base + 0x230) 45 #define SPEAR1340_PLL4_CTR (misc_base + 0x238) 46 #define SPEAR1340_PLL4_FRQ (misc_base + 0x23C) 47 #define SPEAR1340_PERIP_CLK_CFG (misc_base + 0x244) 48 /* PERIP_CLK_CFG bit values */ 49 #define SPEAR1340_SPDIF_CLK_MASK 1 50 #define SPEAR1340_SPDIF_OUT_CLK_SHIFT 15 51 #define SPEAR1340_SPDIF_IN_CLK_SHIFT 14 52 #define SPEAR1340_GPT3_CLK_SHIFT 13 53 #define SPEAR1340_GPT2_CLK_SHIFT 12 54 #define SPEAR1340_GPT_CLK_MASK 1 55 #define SPEAR1340_GPT1_CLK_SHIFT 9 56 #define SPEAR1340_GPT0_CLK_SHIFT 8 57 #define SPEAR1340_UART_CLK_MASK 2 58 #define SPEAR1340_UART1_CLK_SHIFT 6 59 #define SPEAR1340_UART0_CLK_SHIFT 4 60 #define SPEAR1340_CLCD_CLK_MASK 2 61 #define SPEAR1340_CLCD_CLK_SHIFT 2 62 #define SPEAR1340_C3_CLK_MASK 1 63 #define SPEAR1340_C3_CLK_SHIFT 1 64 65 #define SPEAR1340_GMAC_CLK_CFG (misc_base + 0x248) 66 #define SPEAR1340_GMAC_PHY_CLK_MASK 1 67 #define SPEAR1340_GMAC_PHY_CLK_SHIFT 2 68 #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK 2 69 #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT 0 70 71 #define SPEAR1340_I2S_CLK_CFG (misc_base + 0x24C) 72 /* I2S_CLK_CFG register mask */ 73 #define SPEAR1340_I2S_SCLK_X_MASK 0x1F 74 #define SPEAR1340_I2S_SCLK_X_SHIFT 27 75 #define SPEAR1340_I2S_SCLK_Y_MASK 0x1F 76 #define SPEAR1340_I2S_SCLK_Y_SHIFT 22 77 #define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT 21 78 #define SPEAR1340_I2S_SCLK_SYNTH_ENB 20 79 #define SPEAR1340_I2S_PRS1_CLK_X_MASK 0xFF 80 #define SPEAR1340_I2S_PRS1_CLK_X_SHIFT 12 81 #define SPEAR1340_I2S_PRS1_CLK_Y_MASK 0xFF 82 #define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT 4 83 #define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT 3 84 #define SPEAR1340_I2S_REF_SEL_MASK 1 85 #define SPEAR1340_I2S_REF_SHIFT 2 86 #define SPEAR1340_I2S_SRC_CLK_MASK 2 87 #define SPEAR1340_I2S_SRC_CLK_SHIFT 0 88 89 #define SPEAR1340_C3_CLK_SYNT (misc_base + 0x250) 90 #define SPEAR1340_UART0_CLK_SYNT (misc_base + 0x254) 91 #define SPEAR1340_UART1_CLK_SYNT (misc_base + 0x258) 92 #define SPEAR1340_GMAC_CLK_SYNT (misc_base + 0x25C) 93 #define SPEAR1340_SDHCI_CLK_SYNT (misc_base + 0x260) 94 #define SPEAR1340_CFXD_CLK_SYNT (misc_base + 0x264) 95 #define SPEAR1340_ADC_CLK_SYNT (misc_base + 0x270) 96 #define SPEAR1340_AMBA_CLK_SYNT (misc_base + 0x274) 97 #define SPEAR1340_CLCD_CLK_SYNT (misc_base + 0x27C) 98 #define SPEAR1340_SYS_CLK_SYNT (misc_base + 0x284) 99 #define SPEAR1340_GEN_CLK_SYNT0 (misc_base + 0x28C) 100 #define SPEAR1340_GEN_CLK_SYNT1 (misc_base + 0x294) 101 #define SPEAR1340_GEN_CLK_SYNT2 (misc_base + 0x29C) 102 #define SPEAR1340_GEN_CLK_SYNT3 (misc_base + 0x304) 103 #define SPEAR1340_PERIP1_CLK_ENB (misc_base + 0x30C) 104 #define SPEAR1340_RTC_CLK_ENB 31 105 #define SPEAR1340_ADC_CLK_ENB 30 106 #define SPEAR1340_C3_CLK_ENB 29 107 #define SPEAR1340_CLCD_CLK_ENB 27 108 #define SPEAR1340_DMA_CLK_ENB 25 109 #define SPEAR1340_GPIO1_CLK_ENB 24 110 #define SPEAR1340_GPIO0_CLK_ENB 23 111 #define SPEAR1340_GPT1_CLK_ENB 22 112 #define SPEAR1340_GPT0_CLK_ENB 21 113 #define SPEAR1340_I2S_PLAY_CLK_ENB 20 114 #define SPEAR1340_I2S_REC_CLK_ENB 19 115 #define SPEAR1340_I2C0_CLK_ENB 18 116 #define SPEAR1340_SSP_CLK_ENB 17 117 #define SPEAR1340_UART0_CLK_ENB 15 118 #define SPEAR1340_PCIE_SATA_CLK_ENB 12 119 #define SPEAR1340_UOC_CLK_ENB 11 120 #define SPEAR1340_UHC1_CLK_ENB 10 121 #define SPEAR1340_UHC0_CLK_ENB 9 122 #define SPEAR1340_GMAC_CLK_ENB 8 123 #define SPEAR1340_CFXD_CLK_ENB 7 124 #define SPEAR1340_SDHCI_CLK_ENB 6 125 #define SPEAR1340_SMI_CLK_ENB 5 126 #define SPEAR1340_FSMC_CLK_ENB 4 127 #define SPEAR1340_SYSRAM0_CLK_ENB 3 128 #define SPEAR1340_SYSRAM1_CLK_ENB 2 129 #define SPEAR1340_SYSROM_CLK_ENB 1 130 #define SPEAR1340_BUS_CLK_ENB 0 131 132 #define SPEAR1340_PERIP2_CLK_ENB (misc_base + 0x310) 133 #define SPEAR1340_THSENS_CLK_ENB 8 134 #define SPEAR1340_I2S_REF_PAD_CLK_ENB 7 135 #define SPEAR1340_ACP_CLK_ENB 6 136 #define SPEAR1340_GPT3_CLK_ENB 5 137 #define SPEAR1340_GPT2_CLK_ENB 4 138 #define SPEAR1340_KBD_CLK_ENB 3 139 #define SPEAR1340_CPU_DBG_CLK_ENB 2 140 #define SPEAR1340_DDR_CORE_CLK_ENB 1 141 #define SPEAR1340_DDR_CTRL_CLK_ENB 0 142 143 #define SPEAR1340_PERIP3_CLK_ENB (misc_base + 0x314) 144 #define SPEAR1340_PLGPIO_CLK_ENB 18 145 #define SPEAR1340_VIDEO_DEC_CLK_ENB 16 146 #define SPEAR1340_VIDEO_ENC_CLK_ENB 15 147 #define SPEAR1340_SPDIF_OUT_CLK_ENB 13 148 #define SPEAR1340_SPDIF_IN_CLK_ENB 12 149 #define SPEAR1340_VIDEO_IN_CLK_ENB 11 150 #define SPEAR1340_CAM0_CLK_ENB 10 151 #define SPEAR1340_CAM1_CLK_ENB 9 152 #define SPEAR1340_CAM2_CLK_ENB 8 153 #define SPEAR1340_CAM3_CLK_ENB 7 154 #define SPEAR1340_MALI_CLK_ENB 6 155 #define SPEAR1340_CEC0_CLK_ENB 5 156 #define SPEAR1340_CEC1_CLK_ENB 4 157 #define SPEAR1340_PWM_CLK_ENB 3 158 #define SPEAR1340_I2C1_CLK_ENB 2 159 #define SPEAR1340_UART1_CLK_ENB 1 160 161 static DEFINE_SPINLOCK(_lock); 162 163 /* pll rate configuration table, in ascending order of rates */ 164 static struct pll_rate_tbl pll_rtbl[] = { 165 /* PCLK 24MHz */ 166 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */ 167 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */ 168 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */ 169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ 170 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */ 171 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */ 172 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 173 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */ 174 }; 175 176 /* vco-pll4 rate configuration table, in ascending order of rates */ 177 static struct pll_rate_tbl pll4_rtbl[] = { 178 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */ 179 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */ 180 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */ 181 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 182 }; 183 184 /* 185 * All below entries generate 166 MHz for 186 * different values of vco1div2 187 */ 188 static struct frac_rate_tbl amba_synth_rtbl[] = { 189 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */ 190 {.div = 0x06062}, /* for vco1div2 = 500 MHz */ 191 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */ 192 {.div = 0x04000}, /* for vco1div2 = 332 MHz */ 193 {.div = 0x03031}, /* for vco1div2 = 250 MHz */ 194 {.div = 0x0268D}, /* for vco1div2 = 200 MHz */ 195 }; 196 197 /* 198 * Synthesizer Clock derived from vcodiv2. This clock is one of the 199 * possible clocks to feed cpu directly. 200 * We can program this synthesizer to make cpu run on different clock 201 * frequencies. 202 * Following table provides configuration values to let cpu run on 200, 203 * 250, 332, 400 or 500 MHz considering different possibilites of input 204 * (vco1div2) clock. 205 * 206 * -------------------------------------------------------------------- 207 * vco1div2(Mhz) fout(Mhz) cpuclk = fout/2 div 208 * -------------------------------------------------------------------- 209 * 400 200 100 0x04000 210 * 400 250 125 0x03333 211 * 400 332 166 0x0268D 212 * 400 400 200 0x02000 213 * -------------------------------------------------------------------- 214 * 500 200 100 0x05000 215 * 500 250 125 0x04000 216 * 500 332 166 0x03031 217 * 500 400 200 0x02800 218 * 500 500 250 0x02000 219 * -------------------------------------------------------------------- 220 * 600 200 100 0x06000 221 * 600 250 125 0x04CCE 222 * 600 332 166 0x039D5 223 * 600 400 200 0x03000 224 * 600 500 250 0x02666 225 * -------------------------------------------------------------------- 226 * 664 200 100 0x06a38 227 * 664 250 125 0x054FD 228 * 664 332 166 0x04000 229 * 664 400 200 0x0351E 230 * 664 500 250 0x02A7E 231 * -------------------------------------------------------------------- 232 * 800 200 100 0x08000 233 * 800 250 125 0x06666 234 * 800 332 166 0x04D18 235 * 800 400 200 0x04000 236 * 800 500 250 0x03333 237 * -------------------------------------------------------------------- 238 * sys rate configuration table is in descending order of divisor. 239 */ 240 static struct frac_rate_tbl sys_synth_rtbl[] = { 241 {.div = 0x08000}, 242 {.div = 0x06a38}, 243 {.div = 0x06666}, 244 {.div = 0x06000}, 245 {.div = 0x054FD}, 246 {.div = 0x05000}, 247 {.div = 0x04D18}, 248 {.div = 0x04CCE}, 249 {.div = 0x04000}, 250 {.div = 0x039D5}, 251 {.div = 0x0351E}, 252 {.div = 0x03333}, 253 {.div = 0x03031}, 254 {.div = 0x03000}, 255 {.div = 0x02A7E}, 256 {.div = 0x02800}, 257 {.div = 0x0268D}, 258 {.div = 0x02666}, 259 {.div = 0x02000}, 260 }; 261 262 /* aux rate configuration table, in ascending order of rates */ 263 static struct aux_rate_tbl aux_rtbl[] = { 264 /* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */ 265 {.xscale = 5, .yscale = 122, .eq = 0}, 266 /* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */ 267 {.xscale = 10, .yscale = 204, .eq = 0}, 268 /* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */ 269 {.xscale = 4, .yscale = 25, .eq = 0}, 270 /* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */ 271 {.xscale = 4, .yscale = 21, .eq = 0}, 272 /* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */ 273 {.xscale = 5, .yscale = 18, .eq = 0}, 274 /* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */ 275 {.xscale = 2, .yscale = 6, .eq = 0}, 276 /* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */ 277 {.xscale = 5, .yscale = 12, .eq = 0}, 278 /* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */ 279 {.xscale = 2, .yscale = 4, .eq = 0}, 280 /* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */ 281 {.xscale = 5, .yscale = 18, .eq = 1}, 282 /* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */ 283 {.xscale = 1, .yscale = 3, .eq = 1}, 284 /* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */ 285 {.xscale = 5, .yscale = 12, .eq = 1}, 286 /* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */ 287 {.xscale = 1, .yscale = 2, .eq = 1}, 288 }; 289 290 /* gmac rate configuration table, in ascending order of rates */ 291 static struct aux_rate_tbl gmac_rtbl[] = { 292 /* For gmac phy input clk */ 293 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ 294 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ 295 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ 296 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ 297 }; 298 299 /* clcd rate configuration table, in ascending order of rates */ 300 static struct frac_rate_tbl clcd_rtbl[] = { 301 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/ 302 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/ 303 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 304 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 305 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 306 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ 307 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */ 308 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/ 309 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ 310 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/ 311 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/ 312 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 313 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 314 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ 315 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/ 316 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ 317 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/ 318 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 319 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/ 320 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/ 321 }; 322 323 /* i2s prescaler1 masks */ 324 static const struct aux_clk_masks i2s_prs1_masks = { 325 .eq_sel_mask = AUX_EQ_SEL_MASK, 326 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT, 327 .eq1_mask = AUX_EQ1_SEL, 328 .eq2_mask = AUX_EQ2_SEL, 329 .xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK, 330 .xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT, 331 .yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK, 332 .yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT, 333 }; 334 335 /* i2s sclk (bit clock) syynthesizers masks */ 336 static const struct aux_clk_masks i2s_sclk_masks = { 337 .eq_sel_mask = AUX_EQ_SEL_MASK, 338 .eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT, 339 .eq1_mask = AUX_EQ1_SEL, 340 .eq2_mask = AUX_EQ2_SEL, 341 .xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK, 342 .xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT, 343 .yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK, 344 .yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT, 345 .enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB, 346 }; 347 348 /* i2s prs1 aux rate configuration table, in ascending order of rates */ 349 static struct aux_rate_tbl i2s_prs1_rtbl[] = { 350 /* For parent clk = 49.152 MHz */ 351 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */ 352 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */ 353 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */ 354 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */ 355 356 /* 357 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz 358 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz 359 */ 360 {.xscale = 1, .yscale = 3, .eq = 0}, 361 362 /* For parent clk = 49.152 MHz */ 363 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/ 364 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/ 365 }; 366 367 /* i2s sclk aux rate configuration table, in ascending order of rates */ 368 static struct aux_rate_tbl i2s_sclk_rtbl[] = { 369 /* For sclk = ref_clk * x/2/y */ 370 {.xscale = 1, .yscale = 4, .eq = 0}, 371 {.xscale = 1, .yscale = 2, .eq = 0}, 372 }; 373 374 /* adc rate configuration table, in ascending order of rates */ 375 /* possible adc range is 2.5 MHz to 20 MHz. */ 376 static struct aux_rate_tbl adc_rtbl[] = { 377 /* For ahb = 166.67 MHz */ 378 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ 379 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ 380 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ 381 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ 382 }; 383 384 /* General synth rate configuration table, in ascending order of rates */ 385 static struct frac_rate_tbl gen_rtbl[] = { 386 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/ 387 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/ 388 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/ 389 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/ 390 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/ 391 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/ 392 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/ 393 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/ 394 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/ 395 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/ 396 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/ 397 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/ 398 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/ 399 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/ 400 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/ 401 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/ 402 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/ 403 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/ 404 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/ 405 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/ 406 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/ 407 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/ 408 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/ 409 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/ 410 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/ 411 }; 412 413 /* clock parents */ 414 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 415 static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk", 416 "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", }; 417 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", }; 418 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 419 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk", 420 "uart0_syn_gclk", }; 421 static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk", 422 "uart1_syn_gclk", }; 423 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", }; 424 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk", 425 "osc_25m_clk", }; 426 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", }; 427 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; 428 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", }; 429 static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk", 430 "i2s_src_pad_clk", }; 431 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", }; 432 static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", }; 433 static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", }; 434 435 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 436 "pll3_clk", }; 437 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk", 438 "pll2_clk", }; 439 440 void __init spear1340_clk_init(void __iomem *misc_base) 441 { 442 struct clk *clk, *clk1; 443 444 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); 445 clk_register_clkdev(clk, "osc_32k_clk", NULL); 446 447 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); 448 clk_register_clkdev(clk, "osc_24m_clk", NULL); 449 450 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); 451 clk_register_clkdev(clk, "osc_25m_clk", NULL); 452 453 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); 454 clk_register_clkdev(clk, "gmii_pad_clk", NULL); 455 456 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, 457 12288000); 458 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); 459 460 /* clock derived from 32 KHz osc clk */ 461 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 462 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0, 463 &_lock); 464 clk_register_clkdev(clk, NULL, "e0580000.rtc"); 465 466 /* clock derived from 24 or 25 MHz osc clk */ 467 /* vco-pll */ 468 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 469 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 470 SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT, 471 SPEAR1340_PLL_CLK_MASK, 0, &_lock); 472 clk_register_clkdev(clk, "vco1_mclk", NULL); 473 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, 474 SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl, 475 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 476 clk_register_clkdev(clk, "vco1_clk", NULL); 477 clk_register_clkdev(clk1, "pll1_clk", NULL); 478 479 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 480 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 481 SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT, 482 SPEAR1340_PLL_CLK_MASK, 0, &_lock); 483 clk_register_clkdev(clk, "vco2_mclk", NULL); 484 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, 485 SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl, 486 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 487 clk_register_clkdev(clk, "vco2_clk", NULL); 488 clk_register_clkdev(clk1, "pll2_clk", NULL); 489 490 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 491 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT, 492 SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT, 493 SPEAR1340_PLL_CLK_MASK, 0, &_lock); 494 clk_register_clkdev(clk, "vco3_mclk", NULL); 495 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, 496 SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl, 497 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 498 clk_register_clkdev(clk, "vco3_clk", NULL); 499 clk_register_clkdev(clk1, "pll3_clk", NULL); 500 501 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 502 0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl, 503 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); 504 clk_register_clkdev(clk, "vco4_clk", NULL); 505 clk_register_clkdev(clk1, "pll4_clk", NULL); 506 507 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 508 48000000); 509 clk_register_clkdev(clk, "pll5_clk", NULL); 510 511 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 512 25000000); 513 clk_register_clkdev(clk, "pll6_clk", NULL); 514 515 /* vco div n clocks */ 516 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 517 2); 518 clk_register_clkdev(clk, "vco1div2_clk", NULL); 519 520 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 521 4); 522 clk_register_clkdev(clk, "vco1div4_clk", NULL); 523 524 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 525 2); 526 clk_register_clkdev(clk, "vco2div2_clk", NULL); 527 528 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 529 2); 530 clk_register_clkdev(clk, "vco3div2_clk", NULL); 531 532 /* peripherals */ 533 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 534 128); 535 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, 536 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0, 537 &_lock); 538 clk_register_clkdev(clk, NULL, "e07008c4.thermal"); 539 540 /* clock derived from pll4 clk */ 541 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 542 1); 543 clk_register_clkdev(clk, "ddr_clk", NULL); 544 545 /* clock derived from pll1 clk */ 546 clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0, 547 SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl, 548 ARRAY_SIZE(sys_synth_rtbl), &_lock); 549 clk_register_clkdev(clk, "sys_syn_clk", NULL); 550 551 clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0, 552 SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl, 553 ARRAY_SIZE(amba_synth_rtbl), &_lock); 554 clk_register_clkdev(clk, "amba_syn_clk", NULL); 555 556 clk = clk_register_mux(NULL, "sys_mclk", sys_parents, 557 ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT, 558 SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT, 559 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock); 560 clk_register_clkdev(clk, "sys_mclk", NULL); 561 562 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1, 563 2); 564 clk_register_clkdev(clk, "cpu_clk", NULL); 565 566 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1, 567 3); 568 clk_register_clkdev(clk, "cpu_div3_clk", NULL); 569 570 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 571 2); 572 clk_register_clkdev(clk, NULL, "ec800620.wdt"); 573 574 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, 575 2); 576 clk_register_clkdev(clk, NULL, "smp_twd"); 577 578 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, 579 ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT, 580 SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT, 581 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock); 582 clk_register_clkdev(clk, "ahb_clk", NULL); 583 584 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, 585 2); 586 clk_register_clkdev(clk, "apb_clk", NULL); 587 588 /* gpt clocks */ 589 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 590 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 591 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT, 592 SPEAR1340_GPT_CLK_MASK, 0, &_lock); 593 clk_register_clkdev(clk, "gpt0_mclk", NULL); 594 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 595 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0, 596 &_lock); 597 clk_register_clkdev(clk, NULL, "gpt0"); 598 599 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 600 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 601 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT, 602 SPEAR1340_GPT_CLK_MASK, 0, &_lock); 603 clk_register_clkdev(clk, "gpt1_mclk", NULL); 604 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 605 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0, 606 &_lock); 607 clk_register_clkdev(clk, NULL, "gpt1"); 608 609 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 610 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 611 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT, 612 SPEAR1340_GPT_CLK_MASK, 0, &_lock); 613 clk_register_clkdev(clk, "gpt2_mclk", NULL); 614 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 615 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0, 616 &_lock); 617 clk_register_clkdev(clk, NULL, "gpt2"); 618 619 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 620 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT, 621 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT, 622 SPEAR1340_GPT_CLK_MASK, 0, &_lock); 623 clk_register_clkdev(clk, "gpt3_mclk", NULL); 624 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 625 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0, 626 &_lock); 627 clk_register_clkdev(clk, NULL, "gpt3"); 628 629 /* others */ 630 clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk", 631 "vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL, 632 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 633 clk_register_clkdev(clk, "uart0_syn_clk", NULL); 634 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL); 635 636 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 637 ARRAY_SIZE(uart0_parents), 638 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 639 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT, 640 SPEAR1340_UART_CLK_MASK, 0, &_lock); 641 clk_register_clkdev(clk, "uart0_mclk", NULL); 642 643 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 644 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, 645 SPEAR1340_UART0_CLK_ENB, 0, &_lock); 646 clk_register_clkdev(clk, NULL, "e0000000.serial"); 647 648 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk", 649 "vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL, 650 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 651 clk_register_clkdev(clk, "uart1_syn_clk", NULL); 652 clk_register_clkdev(clk1, "uart1_syn_gclk", NULL); 653 654 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents, 655 ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT, 656 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT, 657 SPEAR1340_UART_CLK_MASK, 0, &_lock); 658 clk_register_clkdev(clk, "uart1_mclk", NULL); 659 660 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 661 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0, 662 &_lock); 663 clk_register_clkdev(clk, NULL, "b4100000.serial"); 664 665 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", 666 "vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL, 667 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 668 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); 669 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); 670 671 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 672 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, 673 SPEAR1340_SDHCI_CLK_ENB, 0, &_lock); 674 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 675 676 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 677 0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl, 678 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 679 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); 680 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); 681 682 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 683 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, 684 SPEAR1340_CFXD_CLK_ENB, 0, &_lock); 685 clk_register_clkdev(clk, NULL, "b2800000.cf"); 686 clk_register_clkdev(clk, NULL, "arasan_xd"); 687 688 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0, 689 SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl, 690 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 691 clk_register_clkdev(clk, "c3_syn_clk", NULL); 692 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 693 694 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 695 ARRAY_SIZE(c3_parents), 696 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 697 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT, 698 SPEAR1340_C3_CLK_MASK, 0, &_lock); 699 clk_register_clkdev(clk, "c3_mclk", NULL); 700 701 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT, 702 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0, 703 &_lock); 704 clk_register_clkdev(clk, NULL, "e1800000.c3"); 705 706 /* gmac */ 707 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 708 ARRAY_SIZE(gmac_phy_input_parents), 709 CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG, 710 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT, 711 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 712 clk_register_clkdev(clk, "phy_input_mclk", NULL); 713 714 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 715 0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl, 716 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); 717 clk_register_clkdev(clk, "phy_syn_clk", NULL); 718 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 719 720 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 721 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT, 722 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT, 723 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock); 724 clk_register_clkdev(clk, "stmmacphy.0", NULL); 725 726 /* clcd */ 727 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 728 ARRAY_SIZE(clcd_synth_parents), 729 CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT, 730 SPEAR1340_CLCD_SYNT_CLK_SHIFT, 731 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock); 732 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 733 734 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, 735 SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl, 736 ARRAY_SIZE(clcd_rtbl), &_lock); 737 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 738 739 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 740 ARRAY_SIZE(clcd_pixel_parents), 741 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 742 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, 743 SPEAR1340_CLCD_CLK_MASK, 0, &_lock); 744 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 745 746 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, 747 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0, 748 &_lock); 749 clk_register_clkdev(clk, NULL, "e1000000.clcd"); 750 751 /* i2s */ 752 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 753 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT, 754 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT, 755 SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock); 756 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 757 758 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 759 CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG, 760 &i2s_prs1_masks, i2s_prs1_rtbl, 761 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 762 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 763 764 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 765 ARRAY_SIZE(i2s_ref_parents), 766 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 767 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT, 768 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock); 769 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 770 771 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, 772 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB, 773 0, &_lock); 774 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 775 776 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk", 777 0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks, 778 i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock, 779 &clk1); 780 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 781 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); 782 783 /* clock derived from ahb clk */ 784 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, 785 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0, 786 &_lock); 787 clk_register_clkdev(clk, NULL, "e0280000.i2c"); 788 789 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0, 790 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0, 791 &_lock); 792 clk_register_clkdev(clk, NULL, "b4000000.i2c"); 793 794 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, 795 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0, 796 &_lock); 797 clk_register_clkdev(clk, NULL, "ea800000.dma"); 798 clk_register_clkdev(clk, NULL, "eb000000.dma"); 799 800 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, 801 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0, 802 &_lock); 803 clk_register_clkdev(clk, NULL, "e2000000.eth"); 804 805 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, 806 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0, 807 &_lock); 808 clk_register_clkdev(clk, NULL, "b0000000.flash"); 809 810 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, 811 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0, 812 &_lock); 813 clk_register_clkdev(clk, NULL, "ea000000.flash"); 814 815 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, 816 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0, 817 &_lock); 818 clk_register_clkdev(clk, NULL, "e4000000.ohci"); 819 clk_register_clkdev(clk, NULL, "e4800000.ehci"); 820 821 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, 822 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0, 823 &_lock); 824 clk_register_clkdev(clk, NULL, "e5000000.ohci"); 825 clk_register_clkdev(clk, NULL, "e5800000.ehci"); 826 827 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, 828 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0, 829 &_lock); 830 clk_register_clkdev(clk, NULL, "e3800000.otg"); 831 832 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0, 833 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB, 834 0, &_lock); 835 clk_register_clkdev(clk, NULL, "b1000000.pcie"); 836 clk_register_clkdev(clk, NULL, "b1000000.ahci"); 837 838 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 839 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0, 840 &_lock); 841 clk_register_clkdev(clk, "sysram0_clk", NULL); 842 843 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, 844 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0, 845 &_lock); 846 clk_register_clkdev(clk, "sysram1_clk", NULL); 847 848 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 849 0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl, 850 ARRAY_SIZE(adc_rtbl), &_lock, &clk1); 851 clk_register_clkdev(clk, "adc_syn_clk", NULL); 852 clk_register_clkdev(clk1, "adc_syn_gclk", NULL); 853 854 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 855 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB, 856 SPEAR1340_ADC_CLK_ENB, 0, &_lock); 857 clk_register_clkdev(clk, NULL, "e0080000.adc"); 858 859 /* clock derived from apb clk */ 860 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0, 861 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0, 862 &_lock); 863 clk_register_clkdev(clk, NULL, "e0100000.spi"); 864 865 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, 866 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0, 867 &_lock); 868 clk_register_clkdev(clk, NULL, "e0600000.gpio"); 869 870 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, 871 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0, 872 &_lock); 873 clk_register_clkdev(clk, NULL, "e0680000.gpio"); 874 875 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0, 876 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0, 877 &_lock); 878 clk_register_clkdev(clk, NULL, "b2400000.i2s-play"); 879 880 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0, 881 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0, 882 &_lock); 883 clk_register_clkdev(clk, NULL, "b2000000.i2s-rec"); 884 885 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, 886 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0, 887 &_lock); 888 clk_register_clkdev(clk, NULL, "e0300000.kbd"); 889 890 /* RAS clks */ 891 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 892 ARRAY_SIZE(gen_synth0_1_parents), 893 CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG, 894 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT, 895 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 896 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL); 897 898 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 899 ARRAY_SIZE(gen_synth2_3_parents), 900 CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG, 901 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT, 902 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 903 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL); 904 905 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0, 906 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 907 &_lock); 908 clk_register_clkdev(clk, "gen_syn0_clk", NULL); 909 910 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0, 911 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 912 &_lock); 913 clk_register_clkdev(clk, "gen_syn1_clk", NULL); 914 915 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0, 916 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 917 &_lock); 918 clk_register_clkdev(clk, "gen_syn2_clk", NULL); 919 920 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0, 921 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 922 &_lock); 923 clk_register_clkdev(clk, "gen_syn3_clk", NULL); 924 925 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", 926 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, 927 SPEAR1340_MALI_CLK_ENB, 0, &_lock); 928 clk_register_clkdev(clk, NULL, "mali"); 929 930 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, 931 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0, 932 &_lock); 933 clk_register_clkdev(clk, NULL, "spear_cec.0"); 934 935 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0, 936 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0, 937 &_lock); 938 clk_register_clkdev(clk, NULL, "spear_cec.1"); 939 940 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, 941 ARRAY_SIZE(spdif_out_parents), 942 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 943 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, 944 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 945 clk_register_clkdev(clk, "spdif_out_mclk", NULL); 946 947 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", 948 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, 949 SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock); 950 clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); 951 952 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, 953 ARRAY_SIZE(spdif_in_parents), 954 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 955 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, 956 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 957 clk_register_clkdev(clk, "spdif_in_mclk", NULL); 958 959 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", 960 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB, 961 SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock); 962 clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); 963 964 clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0, 965 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0, 966 &_lock); 967 clk_register_clkdev(clk, NULL, "acp_clk"); 968 969 clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0, 970 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0, 971 &_lock); 972 clk_register_clkdev(clk, NULL, "e2800000.gpio"); 973 974 clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0, 975 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB, 976 0, &_lock); 977 clk_register_clkdev(clk, NULL, "video_dec"); 978 979 clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0, 980 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB, 981 0, &_lock); 982 clk_register_clkdev(clk, NULL, "video_enc"); 983 984 clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0, 985 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0, 986 &_lock); 987 clk_register_clkdev(clk, NULL, "spear_vip"); 988 989 clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0, 990 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0, 991 &_lock); 992 clk_register_clkdev(clk, NULL, "d0200000.cam0"); 993 994 clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0, 995 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0, 996 &_lock); 997 clk_register_clkdev(clk, NULL, "d0300000.cam1"); 998 999 clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0, 1000 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0, 1001 &_lock); 1002 clk_register_clkdev(clk, NULL, "d0400000.cam2"); 1003 1004 clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0, 1005 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0, 1006 &_lock); 1007 clk_register_clkdev(clk, NULL, "d0500000.cam3"); 1008 1009 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0, 1010 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0, 1011 &_lock); 1012 clk_register_clkdev(clk, NULL, "e0180000.pwm"); 1013 } 1014