1 /* 2 * arch/arm/mach-spear13xx/spear1310_clock.c 3 * 4 * SPEAr1310 machine clock framework source file 5 * 6 * Copyright (C) 2012 ST Microelectronics 7 * Viresh Kumar <viresh.linux@gmail.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 #include <linux/of_platform.h> 19 #include <linux/spinlock_types.h> 20 #include <mach/spear.h> 21 #include "clk.h" 22 23 /* PLL related registers and bit values */ 24 #define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210) 25 /* PLL_CFG bit values */ 26 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1 27 #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31 28 #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2 29 #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29 30 #define SPEAR1310_RAS_SYNT_CLK_MASK 2 31 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27 32 #define SPEAR1310_PLL_CLK_MASK 2 33 #define SPEAR1310_PLL3_CLK_SHIFT 24 34 #define SPEAR1310_PLL2_CLK_SHIFT 22 35 #define SPEAR1310_PLL1_CLK_SHIFT 20 36 37 #define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214) 38 #define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218) 39 #define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220) 40 #define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224) 41 #define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C) 42 #define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230) 43 #define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238) 44 #define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C) 45 #define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244) 46 /* PERIP_CLK_CFG bit values */ 47 #define SPEAR1310_GPT_OSC24_VAL 0 48 #define SPEAR1310_GPT_APB_VAL 1 49 #define SPEAR1310_GPT_CLK_MASK 1 50 #define SPEAR1310_GPT3_CLK_SHIFT 11 51 #define SPEAR1310_GPT2_CLK_SHIFT 10 52 #define SPEAR1310_GPT1_CLK_SHIFT 9 53 #define SPEAR1310_GPT0_CLK_SHIFT 8 54 #define SPEAR1310_UART_CLK_PLL5_VAL 0 55 #define SPEAR1310_UART_CLK_OSC24_VAL 1 56 #define SPEAR1310_UART_CLK_SYNT_VAL 2 57 #define SPEAR1310_UART_CLK_MASK 2 58 #define SPEAR1310_UART_CLK_SHIFT 4 59 60 #define SPEAR1310_AUX_CLK_PLL5_VAL 0 61 #define SPEAR1310_AUX_CLK_SYNT_VAL 1 62 #define SPEAR1310_CLCD_CLK_MASK 2 63 #define SPEAR1310_CLCD_CLK_SHIFT 2 64 #define SPEAR1310_C3_CLK_MASK 1 65 #define SPEAR1310_C3_CLK_SHIFT 1 66 67 #define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248) 68 #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3 69 #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4 70 #define SPEAR1310_GMAC_PHY_CLK_MASK 1 71 #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3 72 #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2 73 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1 74 75 #define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C) 76 /* I2S_CLK_CFG register mask */ 77 #define SPEAR1310_I2S_SCLK_X_MASK 0x1F 78 #define SPEAR1310_I2S_SCLK_X_SHIFT 27 79 #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F 80 #define SPEAR1310_I2S_SCLK_Y_SHIFT 22 81 #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21 82 #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20 83 #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF 84 #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12 85 #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF 86 #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4 87 #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3 88 #define SPEAR1310_I2S_REF_SEL_MASK 1 89 #define SPEAR1310_I2S_REF_SHIFT 2 90 #define SPEAR1310_I2S_SRC_CLK_MASK 2 91 #define SPEAR1310_I2S_SRC_CLK_SHIFT 0 92 93 #define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250) 94 #define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254) 95 #define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258) 96 #define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C) 97 #define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260) 98 #define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264) 99 #define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268) 100 #define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270) 101 #define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280) 102 #define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288) 103 #define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290) 104 #define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298) 105 /* Check Fractional synthesizer reg masks */ 106 107 #define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300) 108 /* PERIP1_CLK_ENB register masks */ 109 #define SPEAR1310_RTC_CLK_ENB 31 110 #define SPEAR1310_ADC_CLK_ENB 30 111 #define SPEAR1310_C3_CLK_ENB 29 112 #define SPEAR1310_JPEG_CLK_ENB 28 113 #define SPEAR1310_CLCD_CLK_ENB 27 114 #define SPEAR1310_DMA_CLK_ENB 25 115 #define SPEAR1310_GPIO1_CLK_ENB 24 116 #define SPEAR1310_GPIO0_CLK_ENB 23 117 #define SPEAR1310_GPT1_CLK_ENB 22 118 #define SPEAR1310_GPT0_CLK_ENB 21 119 #define SPEAR1310_I2S0_CLK_ENB 20 120 #define SPEAR1310_I2S1_CLK_ENB 19 121 #define SPEAR1310_I2C0_CLK_ENB 18 122 #define SPEAR1310_SSP_CLK_ENB 17 123 #define SPEAR1310_UART_CLK_ENB 15 124 #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14 125 #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13 126 #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12 127 #define SPEAR1310_UOC_CLK_ENB 11 128 #define SPEAR1310_UHC1_CLK_ENB 10 129 #define SPEAR1310_UHC0_CLK_ENB 9 130 #define SPEAR1310_GMAC_CLK_ENB 8 131 #define SPEAR1310_CFXD_CLK_ENB 7 132 #define SPEAR1310_SDHCI_CLK_ENB 6 133 #define SPEAR1310_SMI_CLK_ENB 5 134 #define SPEAR1310_FSMC_CLK_ENB 4 135 #define SPEAR1310_SYSRAM0_CLK_ENB 3 136 #define SPEAR1310_SYSRAM1_CLK_ENB 2 137 #define SPEAR1310_SYSROM_CLK_ENB 1 138 #define SPEAR1310_BUS_CLK_ENB 0 139 140 #define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304) 141 /* PERIP2_CLK_ENB register masks */ 142 #define SPEAR1310_THSENS_CLK_ENB 8 143 #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7 144 #define SPEAR1310_ACP_CLK_ENB 6 145 #define SPEAR1310_GPT3_CLK_ENB 5 146 #define SPEAR1310_GPT2_CLK_ENB 4 147 #define SPEAR1310_KBD_CLK_ENB 3 148 #define SPEAR1310_CPU_DBG_CLK_ENB 2 149 #define SPEAR1310_DDR_CORE_CLK_ENB 1 150 #define SPEAR1310_DDR_CTRL_CLK_ENB 0 151 152 #define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310) 153 /* RAS_CLK_ENB register masks */ 154 #define SPEAR1310_SYNT3_CLK_ENB 17 155 #define SPEAR1310_SYNT2_CLK_ENB 16 156 #define SPEAR1310_SYNT1_CLK_ENB 15 157 #define SPEAR1310_SYNT0_CLK_ENB 14 158 #define SPEAR1310_PCLK3_CLK_ENB 13 159 #define SPEAR1310_PCLK2_CLK_ENB 12 160 #define SPEAR1310_PCLK1_CLK_ENB 11 161 #define SPEAR1310_PCLK0_CLK_ENB 10 162 #define SPEAR1310_PLL3_CLK_ENB 9 163 #define SPEAR1310_PLL2_CLK_ENB 8 164 #define SPEAR1310_C125M_PAD_CLK_ENB 7 165 #define SPEAR1310_C30M_CLK_ENB 6 166 #define SPEAR1310_C48M_CLK_ENB 5 167 #define SPEAR1310_OSC_25M_CLK_ENB 4 168 #define SPEAR1310_OSC_32K_CLK_ENB 3 169 #define SPEAR1310_OSC_24M_CLK_ENB 2 170 #define SPEAR1310_PCLK_CLK_ENB 1 171 #define SPEAR1310_ACLK_CLK_ENB 0 172 173 /* RAS Area Control Register */ 174 #define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000) 175 #define SPEAR1310_SSP1_CLK_MASK 3 176 #define SPEAR1310_SSP1_CLK_SHIFT 26 177 #define SPEAR1310_TDM_CLK_MASK 1 178 #define SPEAR1310_TDM2_CLK_SHIFT 24 179 #define SPEAR1310_TDM1_CLK_SHIFT 23 180 #define SPEAR1310_I2C_CLK_MASK 1 181 #define SPEAR1310_I2C7_CLK_SHIFT 22 182 #define SPEAR1310_I2C6_CLK_SHIFT 21 183 #define SPEAR1310_I2C5_CLK_SHIFT 20 184 #define SPEAR1310_I2C4_CLK_SHIFT 19 185 #define SPEAR1310_I2C3_CLK_SHIFT 18 186 #define SPEAR1310_I2C2_CLK_SHIFT 17 187 #define SPEAR1310_I2C1_CLK_SHIFT 16 188 #define SPEAR1310_GPT64_CLK_MASK 1 189 #define SPEAR1310_GPT64_CLK_SHIFT 15 190 #define SPEAR1310_RAS_UART_CLK_MASK 1 191 #define SPEAR1310_UART5_CLK_SHIFT 14 192 #define SPEAR1310_UART4_CLK_SHIFT 13 193 #define SPEAR1310_UART3_CLK_SHIFT 12 194 #define SPEAR1310_UART2_CLK_SHIFT 11 195 #define SPEAR1310_UART1_CLK_SHIFT 10 196 #define SPEAR1310_PCI_CLK_MASK 1 197 #define SPEAR1310_PCI_CLK_SHIFT 0 198 199 #define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004) 200 #define SPEAR1310_PHY_CLK_MASK 0x3 201 #define SPEAR1310_RMII_PHY_CLK_SHIFT 0 202 #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2 203 204 #define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148) 205 #define SPEAR1310_CAN1_CLK_ENB 25 206 #define SPEAR1310_CAN0_CLK_ENB 24 207 #define SPEAR1310_GPT64_CLK_ENB 23 208 #define SPEAR1310_SSP1_CLK_ENB 22 209 #define SPEAR1310_I2C7_CLK_ENB 21 210 #define SPEAR1310_I2C6_CLK_ENB 20 211 #define SPEAR1310_I2C5_CLK_ENB 19 212 #define SPEAR1310_I2C4_CLK_ENB 18 213 #define SPEAR1310_I2C3_CLK_ENB 17 214 #define SPEAR1310_I2C2_CLK_ENB 16 215 #define SPEAR1310_I2C1_CLK_ENB 15 216 #define SPEAR1310_UART5_CLK_ENB 14 217 #define SPEAR1310_UART4_CLK_ENB 13 218 #define SPEAR1310_UART3_CLK_ENB 12 219 #define SPEAR1310_UART2_CLK_ENB 11 220 #define SPEAR1310_UART1_CLK_ENB 10 221 #define SPEAR1310_RS485_1_CLK_ENB 9 222 #define SPEAR1310_RS485_0_CLK_ENB 8 223 #define SPEAR1310_TDM2_CLK_ENB 7 224 #define SPEAR1310_TDM1_CLK_ENB 6 225 #define SPEAR1310_PCI_CLK_ENB 5 226 #define SPEAR1310_GMII_CLK_ENB 4 227 #define SPEAR1310_MII2_CLK_ENB 3 228 #define SPEAR1310_MII1_CLK_ENB 2 229 #define SPEAR1310_MII0_CLK_ENB 1 230 #define SPEAR1310_ESRAM_CLK_ENB 0 231 232 static DEFINE_SPINLOCK(_lock); 233 234 /* pll rate configuration table, in ascending order of rates */ 235 static struct pll_rate_tbl pll_rtbl[] = { 236 /* PCLK 24MHz */ 237 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */ 238 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */ 239 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */ 240 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ 241 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */ 242 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */ 243 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 244 }; 245 246 /* vco-pll4 rate configuration table, in ascending order of rates */ 247 static struct pll_rate_tbl pll4_rtbl[] = { 248 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */ 249 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */ 250 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */ 251 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 252 }; 253 254 /* aux rate configuration table, in ascending order of rates */ 255 static struct aux_rate_tbl aux_rtbl[] = { 256 /* For VCO1div2 = 500 MHz */ 257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */ 258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */ 259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */ 260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */ 261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */ 262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */ 263 }; 264 265 /* gmac rate configuration table, in ascending order of rates */ 266 static struct aux_rate_tbl gmac_rtbl[] = { 267 /* For gmac phy input clk */ 268 {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ 269 {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ 270 {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ 271 {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ 272 }; 273 274 /* clcd rate configuration table, in ascending order of rates */ 275 static struct frac_rate_tbl clcd_rtbl[] = { 276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ 280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ 281 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 282 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 283 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ 284 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ 285 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 286 }; 287 288 /* i2s prescaler1 masks */ 289 static struct aux_clk_masks i2s_prs1_masks = { 290 .eq_sel_mask = AUX_EQ_SEL_MASK, 291 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT, 292 .eq1_mask = AUX_EQ1_SEL, 293 .eq2_mask = AUX_EQ2_SEL, 294 .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK, 295 .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT, 296 .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK, 297 .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT, 298 }; 299 300 /* i2s sclk (bit clock) syynthesizers masks */ 301 static struct aux_clk_masks i2s_sclk_masks = { 302 .eq_sel_mask = AUX_EQ_SEL_MASK, 303 .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT, 304 .eq1_mask = AUX_EQ1_SEL, 305 .eq2_mask = AUX_EQ2_SEL, 306 .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK, 307 .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT, 308 .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK, 309 .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT, 310 .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB, 311 }; 312 313 /* i2s prs1 aux rate configuration table, in ascending order of rates */ 314 static struct aux_rate_tbl i2s_prs1_rtbl[] = { 315 /* For parent clk = 49.152 MHz */ 316 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */ 317 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */ 318 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */ 319 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */ 320 321 /* 322 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz 323 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz 324 */ 325 {.xscale = 1, .yscale = 3, .eq = 0}, 326 327 /* For parent clk = 49.152 MHz */ 328 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/ 329 330 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */ 331 }; 332 333 /* i2s sclk aux rate configuration table, in ascending order of rates */ 334 static struct aux_rate_tbl i2s_sclk_rtbl[] = { 335 /* For i2s_ref_clk = 12.288MHz */ 336 {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */ 337 {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */ 338 }; 339 340 /* adc rate configuration table, in ascending order of rates */ 341 /* possible adc range is 2.5 MHz to 20 MHz. */ 342 static struct aux_rate_tbl adc_rtbl[] = { 343 /* For ahb = 166.67 MHz */ 344 {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ 345 {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ 346 {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ 347 {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ 348 }; 349 350 /* General synth rate configuration table, in ascending order of rates */ 351 static struct frac_rate_tbl gen_rtbl[] = { 352 /* For vco1div4 = 250 MHz */ 353 {.div = 0x14000}, /* 25 MHz */ 354 {.div = 0x0A000}, /* 50 MHz */ 355 {.div = 0x05000}, /* 100 MHz */ 356 {.div = 0x02000}, /* 250 MHz */ 357 }; 358 359 /* clock parents */ 360 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 361 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 362 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", }; 363 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", }; 364 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk", 365 "osc_25m_clk", }; 366 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", }; 367 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; 368 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", }; 369 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk", 370 "i2s_src_pad_clk", }; 371 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", }; 372 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 373 "pll3_clk", }; 374 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", 375 "pll2_clk", }; 376 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none", 377 "ras_pll2_clk", "ras_syn0_clk", }; 378 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk", 379 "ras_pll2_clk", "ras_syn0_clk", }; 380 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; 381 static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", }; 382 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk", 383 "ras_plclk0_clk", }; 384 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", }; 385 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; 386 387 void __init spear1310_clk_init(void) 388 { 389 struct clk *clk, *clk1; 390 391 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); 392 clk_register_clkdev(clk, "apb_pclk", NULL); 393 394 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 395 32000); 396 clk_register_clkdev(clk, "osc_32k_clk", NULL); 397 398 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, 399 24000000); 400 clk_register_clkdev(clk, "osc_24m_clk", NULL); 401 402 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, 403 25000000); 404 clk_register_clkdev(clk, "osc_25m_clk", NULL); 405 406 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, 407 125000000); 408 clk_register_clkdev(clk, "gmii_pad_clk", NULL); 409 410 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 411 CLK_IS_ROOT, 12288000); 412 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); 413 414 /* clock derived from 32 KHz osc clk */ 415 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 416 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, 417 &_lock); 418 clk_register_clkdev(clk, NULL, "e0580000.rtc"); 419 420 /* clock derived from 24 or 25 MHz osc clk */ 421 /* vco-pll */ 422 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 423 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 424 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 425 &_lock); 426 clk_register_clkdev(clk, "vco1_mclk", NULL); 427 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 428 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, 429 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 430 clk_register_clkdev(clk, "vco1_clk", NULL); 431 clk_register_clkdev(clk1, "pll1_clk", NULL); 432 433 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 434 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 435 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 436 &_lock); 437 clk_register_clkdev(clk, "vco2_mclk", NULL); 438 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 439 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, 440 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 441 clk_register_clkdev(clk, "vco2_clk", NULL); 442 clk_register_clkdev(clk1, "pll2_clk", NULL); 443 444 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 445 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 446 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 447 &_lock); 448 clk_register_clkdev(clk, "vco3_mclk", NULL); 449 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 450 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, 451 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 452 clk_register_clkdev(clk, "vco3_clk", NULL); 453 clk_register_clkdev(clk1, "pll3_clk", NULL); 454 455 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 456 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl, 457 ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); 458 clk_register_clkdev(clk, "vco4_clk", NULL); 459 clk_register_clkdev(clk1, "pll4_clk", NULL); 460 461 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 462 48000000); 463 clk_register_clkdev(clk, "pll5_clk", NULL); 464 465 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 466 25000000); 467 clk_register_clkdev(clk, "pll6_clk", NULL); 468 469 /* vco div n clocks */ 470 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 471 2); 472 clk_register_clkdev(clk, "vco1div2_clk", NULL); 473 474 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 475 4); 476 clk_register_clkdev(clk, "vco1div4_clk", NULL); 477 478 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 479 2); 480 clk_register_clkdev(clk, "vco2div2_clk", NULL); 481 482 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 483 2); 484 clk_register_clkdev(clk, "vco3div2_clk", NULL); 485 486 /* peripherals */ 487 clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 488 128); 489 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, 490 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0, 491 &_lock); 492 clk_register_clkdev(clk, NULL, "spear_thermal"); 493 494 /* clock derived from pll4 clk */ 495 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 496 1); 497 clk_register_clkdev(clk, "ddr_clk", NULL); 498 499 /* clock derived from pll1 clk */ 500 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 501 CLK_SET_RATE_PARENT, 1, 2); 502 clk_register_clkdev(clk, "cpu_clk", NULL); 503 504 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 505 2); 506 clk_register_clkdev(clk, NULL, "ec800620.wdt"); 507 508 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, 509 2); 510 clk_register_clkdev(clk, NULL, "smp_twd"); 511 512 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, 513 6); 514 clk_register_clkdev(clk, "ahb_clk", NULL); 515 516 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, 517 12); 518 clk_register_clkdev(clk, "apb_clk", NULL); 519 520 /* gpt clocks */ 521 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 522 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 523 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 524 &_lock); 525 clk_register_clkdev(clk, "gpt0_mclk", NULL); 526 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 527 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, 528 &_lock); 529 clk_register_clkdev(clk, NULL, "gpt0"); 530 531 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 532 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 533 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 534 &_lock); 535 clk_register_clkdev(clk, "gpt1_mclk", NULL); 536 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 537 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, 538 &_lock); 539 clk_register_clkdev(clk, NULL, "gpt1"); 540 541 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 542 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 543 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 544 &_lock); 545 clk_register_clkdev(clk, "gpt2_mclk", NULL); 546 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 547 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, 548 &_lock); 549 clk_register_clkdev(clk, NULL, "gpt2"); 550 551 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 552 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 553 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 554 &_lock); 555 clk_register_clkdev(clk, "gpt3_mclk", NULL); 556 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 557 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, 558 &_lock); 559 clk_register_clkdev(clk, NULL, "gpt3"); 560 561 /* others */ 562 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", 563 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl, 564 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 565 clk_register_clkdev(clk, "uart_syn_clk", NULL); 566 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 567 568 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 569 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 570 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, 571 SPEAR1310_UART_CLK_MASK, 0, &_lock); 572 clk_register_clkdev(clk, "uart0_mclk", NULL); 573 574 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 575 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 576 SPEAR1310_UART_CLK_ENB, 0, &_lock); 577 clk_register_clkdev(clk, NULL, "e0000000.serial"); 578 579 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", 580 "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL, 581 aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 582 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); 583 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); 584 585 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 586 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 587 SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); 588 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 589 590 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 591 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl, 592 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 593 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); 594 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); 595 596 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 597 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 598 SPEAR1310_CFXD_CLK_ENB, 0, &_lock); 599 clk_register_clkdev(clk, NULL, "b2800000.cf"); 600 clk_register_clkdev(clk, NULL, "arasan_xd"); 601 602 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 603 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl, 604 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 605 clk_register_clkdev(clk, "c3_syn_clk", NULL); 606 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 607 608 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 609 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, 610 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, 611 SPEAR1310_C3_CLK_MASK, 0, &_lock); 612 clk_register_clkdev(clk, "c3_mclk", NULL); 613 614 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, 615 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0, 616 &_lock); 617 clk_register_clkdev(clk, NULL, "c3"); 618 619 /* gmac */ 620 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 621 ARRAY_SIZE(gmac_phy_input_parents), 0, 622 SPEAR1310_GMAC_CLK_CFG, 623 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, 624 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 625 clk_register_clkdev(clk, "phy_input_mclk", NULL); 626 627 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 628 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl, 629 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); 630 clk_register_clkdev(clk, "phy_syn_clk", NULL); 631 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 632 633 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 634 ARRAY_SIZE(gmac_phy_parents), 0, 635 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, 636 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); 637 clk_register_clkdev(clk, "stmmacphy.0", NULL); 638 639 /* clcd */ 640 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 641 ARRAY_SIZE(clcd_synth_parents), 0, 642 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT, 643 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); 644 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 645 646 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, 647 SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl, 648 ARRAY_SIZE(clcd_rtbl), &_lock); 649 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 650 651 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 652 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, 653 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, 654 SPEAR1310_CLCD_CLK_MASK, 0, &_lock); 655 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 656 657 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, 658 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, 659 &_lock); 660 clk_register_clkdev(clk, NULL, "e1000000.clcd"); 661 662 /* i2s */ 663 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 664 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG, 665 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK, 666 0, &_lock); 667 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 668 669 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, 670 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, 671 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 672 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 673 674 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 675 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 676 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, 677 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); 678 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 679 680 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, 681 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, 682 0, &_lock); 683 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 684 685 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", 686 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG, 687 &i2s_sclk_masks, i2s_sclk_rtbl, 688 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); 689 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 690 clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); 691 692 /* clock derived from ahb clk */ 693 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, 694 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0, 695 &_lock); 696 clk_register_clkdev(clk, NULL, "e0280000.i2c"); 697 698 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, 699 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0, 700 &_lock); 701 clk_register_clkdev(clk, NULL, "ea800000.dma"); 702 clk_register_clkdev(clk, NULL, "eb000000.dma"); 703 704 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, 705 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0, 706 &_lock); 707 clk_register_clkdev(clk, NULL, "b2000000.jpeg"); 708 709 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, 710 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0, 711 &_lock); 712 clk_register_clkdev(clk, NULL, "e2000000.eth"); 713 714 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, 715 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0, 716 &_lock); 717 clk_register_clkdev(clk, NULL, "b0000000.flash"); 718 719 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, 720 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0, 721 &_lock); 722 clk_register_clkdev(clk, NULL, "ea000000.flash"); 723 724 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, 725 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, 726 &_lock); 727 clk_register_clkdev(clk, NULL, "e4000000.ohci"); 728 clk_register_clkdev(clk, NULL, "e4800000.ehci"); 729 730 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, 731 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, 732 &_lock); 733 clk_register_clkdev(clk, NULL, "e5000000.ohci"); 734 clk_register_clkdev(clk, NULL, "e5800000.ehci"); 735 736 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, 737 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, 738 &_lock); 739 clk_register_clkdev(clk, NULL, "e3800000.otg"); 740 741 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, 742 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 743 0, &_lock); 744 clk_register_clkdev(clk, NULL, "dw_pcie.0"); 745 clk_register_clkdev(clk, NULL, "b1000000.ahci"); 746 747 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, 748 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 749 0, &_lock); 750 clk_register_clkdev(clk, NULL, "dw_pcie.1"); 751 clk_register_clkdev(clk, NULL, "b1800000.ahci"); 752 753 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, 754 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 755 0, &_lock); 756 clk_register_clkdev(clk, NULL, "dw_pcie.2"); 757 clk_register_clkdev(clk, NULL, "b4000000.ahci"); 758 759 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 760 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, 761 &_lock); 762 clk_register_clkdev(clk, "sysram0_clk", NULL); 763 764 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, 765 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0, 766 &_lock); 767 clk_register_clkdev(clk, "sysram1_clk", NULL); 768 769 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 770 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl, 771 ARRAY_SIZE(adc_rtbl), &_lock, &clk1); 772 clk_register_clkdev(clk, "adc_syn_clk", NULL); 773 clk_register_clkdev(clk1, "adc_syn_gclk", NULL); 774 775 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 776 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 777 SPEAR1310_ADC_CLK_ENB, 0, &_lock); 778 clk_register_clkdev(clk, NULL, "e0080000.adc"); 779 780 /* clock derived from apb clk */ 781 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, 782 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0, 783 &_lock); 784 clk_register_clkdev(clk, NULL, "e0100000.spi"); 785 786 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, 787 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0, 788 &_lock); 789 clk_register_clkdev(clk, NULL, "e0600000.gpio"); 790 791 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, 792 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0, 793 &_lock); 794 clk_register_clkdev(clk, NULL, "e0680000.gpio"); 795 796 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, 797 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0, 798 &_lock); 799 clk_register_clkdev(clk, NULL, "e0180000.i2s"); 800 801 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, 802 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0, 803 &_lock); 804 clk_register_clkdev(clk, NULL, "e0200000.i2s"); 805 806 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, 807 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0, 808 &_lock); 809 clk_register_clkdev(clk, NULL, "e0300000.kbd"); 810 811 /* RAS clks */ 812 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 813 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG, 814 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, 815 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 816 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); 817 818 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 819 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG, 820 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, 821 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 822 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); 823 824 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, 825 SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 826 &_lock); 827 clk_register_clkdev(clk, "gen_syn0_clk", NULL); 828 829 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, 830 SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 831 &_lock); 832 clk_register_clkdev(clk, "gen_syn1_clk", NULL); 833 834 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, 835 SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 836 &_lock); 837 clk_register_clkdev(clk, "gen_syn2_clk", NULL); 838 839 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, 840 SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 841 &_lock); 842 clk_register_clkdev(clk, "gen_syn3_clk", NULL); 843 844 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, 845 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0, 846 &_lock); 847 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); 848 849 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, 850 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0, 851 &_lock); 852 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); 853 854 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, 855 SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0, 856 &_lock); 857 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); 858 859 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, 860 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0, 861 &_lock); 862 clk_register_clkdev(clk, "ras_pll2_clk", NULL); 863 864 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, 865 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0, 866 &_lock); 867 clk_register_clkdev(clk, "ras_pll3_clk", NULL); 868 869 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, 870 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0, 871 &_lock); 872 clk_register_clkdev(clk, "ras_tx125_clk", NULL); 873 874 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, 875 30000000); 876 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, 877 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0, 878 &_lock); 879 clk_register_clkdev(clk, "ras_30m_clk", NULL); 880 881 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, 882 48000000); 883 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, 884 SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0, 885 &_lock); 886 clk_register_clkdev(clk, "ras_48m_clk", NULL); 887 888 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, 889 SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0, 890 &_lock); 891 clk_register_clkdev(clk, "ras_ahb_clk", NULL); 892 893 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, 894 SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0, 895 &_lock); 896 clk_register_clkdev(clk, "ras_apb_clk", NULL); 897 898 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT, 899 50000000); 900 901 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT, 902 50000000); 903 904 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, 905 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0, 906 &_lock); 907 clk_register_clkdev(clk, NULL, "c_can_platform.0"); 908 909 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, 910 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0, 911 &_lock); 912 clk_register_clkdev(clk, NULL, "c_can_platform.1"); 913 914 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, 915 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0, 916 &_lock); 917 clk_register_clkdev(clk, NULL, "5c400000.eth"); 918 919 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, 920 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0, 921 &_lock); 922 clk_register_clkdev(clk, NULL, "5c500000.eth"); 923 924 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, 925 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0, 926 &_lock); 927 clk_register_clkdev(clk, NULL, "5c600000.eth"); 928 929 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, 930 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0, 931 &_lock); 932 clk_register_clkdev(clk, NULL, "5c700000.eth"); 933 934 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", 935 smii_rgmii_phy_parents, 936 ARRAY_SIZE(smii_rgmii_phy_parents), 0, 937 SPEAR1310_RAS_CTRL_REG1, 938 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, 939 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 940 clk_register_clkdev(clk, "stmmacphy.1", NULL); 941 clk_register_clkdev(clk, "stmmacphy.2", NULL); 942 clk_register_clkdev(clk, "stmmacphy.4", NULL); 943 944 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, 945 ARRAY_SIZE(rmii_phy_parents), 0, 946 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, 947 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 948 clk_register_clkdev(clk, "stmmacphy.3", NULL); 949 950 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, 951 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 952 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 953 0, &_lock); 954 clk_register_clkdev(clk, "uart1_mclk", NULL); 955 956 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 957 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0, 958 &_lock); 959 clk_register_clkdev(clk, NULL, "5c800000.serial"); 960 961 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, 962 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 963 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 964 0, &_lock); 965 clk_register_clkdev(clk, "uart2_mclk", NULL); 966 967 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, 968 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0, 969 &_lock); 970 clk_register_clkdev(clk, NULL, "5c900000.serial"); 971 972 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, 973 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 974 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 975 0, &_lock); 976 clk_register_clkdev(clk, "uart3_mclk", NULL); 977 978 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, 979 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0, 980 &_lock); 981 clk_register_clkdev(clk, NULL, "5ca00000.serial"); 982 983 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, 984 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 985 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 986 0, &_lock); 987 clk_register_clkdev(clk, "uart4_mclk", NULL); 988 989 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, 990 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0, 991 &_lock); 992 clk_register_clkdev(clk, NULL, "5cb00000.serial"); 993 994 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, 995 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 996 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 997 0, &_lock); 998 clk_register_clkdev(clk, "uart5_mclk", NULL); 999 1000 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, 1001 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0, 1002 &_lock); 1003 clk_register_clkdev(clk, NULL, "5cc00000.serial"); 1004 1005 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, 1006 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1007 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1008 &_lock); 1009 clk_register_clkdev(clk, "i2c1_mclk", NULL); 1010 1011 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, 1012 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0, 1013 &_lock); 1014 clk_register_clkdev(clk, NULL, "5cd00000.i2c"); 1015 1016 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, 1017 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1018 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1019 &_lock); 1020 clk_register_clkdev(clk, "i2c2_mclk", NULL); 1021 1022 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, 1023 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0, 1024 &_lock); 1025 clk_register_clkdev(clk, NULL, "5ce00000.i2c"); 1026 1027 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, 1028 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1029 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1030 &_lock); 1031 clk_register_clkdev(clk, "i2c3_mclk", NULL); 1032 1033 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, 1034 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0, 1035 &_lock); 1036 clk_register_clkdev(clk, NULL, "5cf00000.i2c"); 1037 1038 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, 1039 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1040 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1041 &_lock); 1042 clk_register_clkdev(clk, "i2c4_mclk", NULL); 1043 1044 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, 1045 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0, 1046 &_lock); 1047 clk_register_clkdev(clk, NULL, "5d000000.i2c"); 1048 1049 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, 1050 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1051 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1052 &_lock); 1053 clk_register_clkdev(clk, "i2c5_mclk", NULL); 1054 1055 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, 1056 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0, 1057 &_lock); 1058 clk_register_clkdev(clk, NULL, "5d100000.i2c"); 1059 1060 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, 1061 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1062 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1063 &_lock); 1064 clk_register_clkdev(clk, "i2c6_mclk", NULL); 1065 1066 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, 1067 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0, 1068 &_lock); 1069 clk_register_clkdev(clk, NULL, "5d200000.i2c"); 1070 1071 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, 1072 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1073 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1074 &_lock); 1075 clk_register_clkdev(clk, "i2c7_mclk", NULL); 1076 1077 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, 1078 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0, 1079 &_lock); 1080 clk_register_clkdev(clk, NULL, "5d300000.i2c"); 1081 1082 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, 1083 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1084 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0, 1085 &_lock); 1086 clk_register_clkdev(clk, "ssp1_mclk", NULL); 1087 1088 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, 1089 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0, 1090 &_lock); 1091 clk_register_clkdev(clk, NULL, "5d400000.spi"); 1092 1093 clk = clk_register_mux(NULL, "pci_mclk", pci_parents, 1094 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1095 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0, 1096 &_lock); 1097 clk_register_clkdev(clk, "pci_mclk", NULL); 1098 1099 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, 1100 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0, 1101 &_lock); 1102 clk_register_clkdev(clk, NULL, "pci"); 1103 1104 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, 1105 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1106 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 1107 &_lock); 1108 clk_register_clkdev(clk, "tdm1_mclk", NULL); 1109 1110 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, 1111 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0, 1112 &_lock); 1113 clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); 1114 1115 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, 1116 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1117 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 1118 &_lock); 1119 clk_register_clkdev(clk, "tdm2_mclk", NULL); 1120 1121 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, 1122 SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0, 1123 &_lock); 1124 clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); 1125 } 1126