10b928af1SViresh Kumar /* 20b928af1SViresh Kumar * arch/arm/mach-spear13xx/spear1310_clock.c 30b928af1SViresh Kumar * 40b928af1SViresh Kumar * SPEAr1310 machine clock framework source file 50b928af1SViresh Kumar * 60b928af1SViresh Kumar * Copyright (C) 2012 ST Microelectronics 710d8935fSViresh Kumar * Viresh Kumar <viresh.linux@gmail.com> 80b928af1SViresh Kumar * 90b928af1SViresh Kumar * This file is licensed under the terms of the GNU General Public 100b928af1SViresh Kumar * License version 2. This program is licensed "as is" without any 110b928af1SViresh Kumar * warranty of any kind, whether express or implied. 120b928af1SViresh Kumar */ 130b928af1SViresh Kumar 140b928af1SViresh Kumar #include <linux/clk.h> 150b928af1SViresh Kumar #include <linux/clkdev.h> 160b928af1SViresh Kumar #include <linux/err.h> 170b928af1SViresh Kumar #include <linux/io.h> 180b928af1SViresh Kumar #include <linux/of_platform.h> 190b928af1SViresh Kumar #include <linux/spinlock_types.h> 200b928af1SViresh Kumar #include <mach/spear.h> 210b928af1SViresh Kumar #include "clk.h" 220b928af1SViresh Kumar 230b928af1SViresh Kumar /* PLL related registers and bit values */ 240b928af1SViresh Kumar #define SPEAR1310_PLL_CFG (VA_MISC_BASE + 0x210) 250b928af1SViresh Kumar /* PLL_CFG bit values */ 260b928af1SViresh Kumar #define SPEAR1310_CLCD_SYNT_CLK_MASK 1 270b928af1SViresh Kumar #define SPEAR1310_CLCD_SYNT_CLK_SHIFT 31 280b928af1SViresh Kumar #define SPEAR1310_RAS_SYNT2_3_CLK_MASK 2 290b928af1SViresh Kumar #define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT 29 300b928af1SViresh Kumar #define SPEAR1310_RAS_SYNT_CLK_MASK 2 310b928af1SViresh Kumar #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27 320b928af1SViresh Kumar #define SPEAR1310_PLL_CLK_MASK 2 330b928af1SViresh Kumar #define SPEAR1310_PLL3_CLK_SHIFT 24 340b928af1SViresh Kumar #define SPEAR1310_PLL2_CLK_SHIFT 22 350b928af1SViresh Kumar #define SPEAR1310_PLL1_CLK_SHIFT 20 360b928af1SViresh Kumar 370b928af1SViresh Kumar #define SPEAR1310_PLL1_CTR (VA_MISC_BASE + 0x214) 380b928af1SViresh Kumar #define SPEAR1310_PLL1_FRQ (VA_MISC_BASE + 0x218) 390b928af1SViresh Kumar #define SPEAR1310_PLL2_CTR (VA_MISC_BASE + 0x220) 400b928af1SViresh Kumar #define SPEAR1310_PLL2_FRQ (VA_MISC_BASE + 0x224) 410b928af1SViresh Kumar #define SPEAR1310_PLL3_CTR (VA_MISC_BASE + 0x22C) 420b928af1SViresh Kumar #define SPEAR1310_PLL3_FRQ (VA_MISC_BASE + 0x230) 430b928af1SViresh Kumar #define SPEAR1310_PLL4_CTR (VA_MISC_BASE + 0x238) 440b928af1SViresh Kumar #define SPEAR1310_PLL4_FRQ (VA_MISC_BASE + 0x23C) 450b928af1SViresh Kumar #define SPEAR1310_PERIP_CLK_CFG (VA_MISC_BASE + 0x244) 460b928af1SViresh Kumar /* PERIP_CLK_CFG bit values */ 470b928af1SViresh Kumar #define SPEAR1310_GPT_OSC24_VAL 0 480b928af1SViresh Kumar #define SPEAR1310_GPT_APB_VAL 1 490b928af1SViresh Kumar #define SPEAR1310_GPT_CLK_MASK 1 500b928af1SViresh Kumar #define SPEAR1310_GPT3_CLK_SHIFT 11 510b928af1SViresh Kumar #define SPEAR1310_GPT2_CLK_SHIFT 10 520b928af1SViresh Kumar #define SPEAR1310_GPT1_CLK_SHIFT 9 530b928af1SViresh Kumar #define SPEAR1310_GPT0_CLK_SHIFT 8 540b928af1SViresh Kumar #define SPEAR1310_UART_CLK_PLL5_VAL 0 550b928af1SViresh Kumar #define SPEAR1310_UART_CLK_OSC24_VAL 1 560b928af1SViresh Kumar #define SPEAR1310_UART_CLK_SYNT_VAL 2 570b928af1SViresh Kumar #define SPEAR1310_UART_CLK_MASK 2 580b928af1SViresh Kumar #define SPEAR1310_UART_CLK_SHIFT 4 590b928af1SViresh Kumar 600b928af1SViresh Kumar #define SPEAR1310_AUX_CLK_PLL5_VAL 0 610b928af1SViresh Kumar #define SPEAR1310_AUX_CLK_SYNT_VAL 1 620b928af1SViresh Kumar #define SPEAR1310_CLCD_CLK_MASK 2 630b928af1SViresh Kumar #define SPEAR1310_CLCD_CLK_SHIFT 2 640b928af1SViresh Kumar #define SPEAR1310_C3_CLK_MASK 1 650b928af1SViresh Kumar #define SPEAR1310_C3_CLK_SHIFT 1 660b928af1SViresh Kumar 670b928af1SViresh Kumar #define SPEAR1310_GMAC_CLK_CFG (VA_MISC_BASE + 0x248) 680b928af1SViresh Kumar #define SPEAR1310_GMAC_PHY_IF_SEL_MASK 3 690b928af1SViresh Kumar #define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT 4 700b928af1SViresh Kumar #define SPEAR1310_GMAC_PHY_CLK_MASK 1 710b928af1SViresh Kumar #define SPEAR1310_GMAC_PHY_CLK_SHIFT 3 720b928af1SViresh Kumar #define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK 2 730b928af1SViresh Kumar #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1 740b928af1SViresh Kumar 750b928af1SViresh Kumar #define SPEAR1310_I2S_CLK_CFG (VA_MISC_BASE + 0x24C) 760b928af1SViresh Kumar /* I2S_CLK_CFG register mask */ 770b928af1SViresh Kumar #define SPEAR1310_I2S_SCLK_X_MASK 0x1F 780b928af1SViresh Kumar #define SPEAR1310_I2S_SCLK_X_SHIFT 27 790b928af1SViresh Kumar #define SPEAR1310_I2S_SCLK_Y_MASK 0x1F 800b928af1SViresh Kumar #define SPEAR1310_I2S_SCLK_Y_SHIFT 22 810b928af1SViresh Kumar #define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT 21 820b928af1SViresh Kumar #define SPEAR1310_I2S_SCLK_SYNTH_ENB 20 830b928af1SViresh Kumar #define SPEAR1310_I2S_PRS1_CLK_X_MASK 0xFF 840b928af1SViresh Kumar #define SPEAR1310_I2S_PRS1_CLK_X_SHIFT 12 850b928af1SViresh Kumar #define SPEAR1310_I2S_PRS1_CLK_Y_MASK 0xFF 860b928af1SViresh Kumar #define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT 4 870b928af1SViresh Kumar #define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT 3 880b928af1SViresh Kumar #define SPEAR1310_I2S_REF_SEL_MASK 1 890b928af1SViresh Kumar #define SPEAR1310_I2S_REF_SHIFT 2 900b928af1SViresh Kumar #define SPEAR1310_I2S_SRC_CLK_MASK 2 910b928af1SViresh Kumar #define SPEAR1310_I2S_SRC_CLK_SHIFT 0 920b928af1SViresh Kumar 930b928af1SViresh Kumar #define SPEAR1310_C3_CLK_SYNT (VA_MISC_BASE + 0x250) 940b928af1SViresh Kumar #define SPEAR1310_UART_CLK_SYNT (VA_MISC_BASE + 0x254) 950b928af1SViresh Kumar #define SPEAR1310_GMAC_CLK_SYNT (VA_MISC_BASE + 0x258) 960b928af1SViresh Kumar #define SPEAR1310_SDHCI_CLK_SYNT (VA_MISC_BASE + 0x25C) 970b928af1SViresh Kumar #define SPEAR1310_CFXD_CLK_SYNT (VA_MISC_BASE + 0x260) 980b928af1SViresh Kumar #define SPEAR1310_ADC_CLK_SYNT (VA_MISC_BASE + 0x264) 990b928af1SViresh Kumar #define SPEAR1310_AMBA_CLK_SYNT (VA_MISC_BASE + 0x268) 1000b928af1SViresh Kumar #define SPEAR1310_CLCD_CLK_SYNT (VA_MISC_BASE + 0x270) 1010b928af1SViresh Kumar #define SPEAR1310_RAS_CLK_SYNT0 (VA_MISC_BASE + 0x280) 1020b928af1SViresh Kumar #define SPEAR1310_RAS_CLK_SYNT1 (VA_MISC_BASE + 0x288) 1030b928af1SViresh Kumar #define SPEAR1310_RAS_CLK_SYNT2 (VA_MISC_BASE + 0x290) 1040b928af1SViresh Kumar #define SPEAR1310_RAS_CLK_SYNT3 (VA_MISC_BASE + 0x298) 1050b928af1SViresh Kumar /* Check Fractional synthesizer reg masks */ 1060b928af1SViresh Kumar 1070b928af1SViresh Kumar #define SPEAR1310_PERIP1_CLK_ENB (VA_MISC_BASE + 0x300) 1080b928af1SViresh Kumar /* PERIP1_CLK_ENB register masks */ 1090b928af1SViresh Kumar #define SPEAR1310_RTC_CLK_ENB 31 1100b928af1SViresh Kumar #define SPEAR1310_ADC_CLK_ENB 30 1110b928af1SViresh Kumar #define SPEAR1310_C3_CLK_ENB 29 1120b928af1SViresh Kumar #define SPEAR1310_JPEG_CLK_ENB 28 1130b928af1SViresh Kumar #define SPEAR1310_CLCD_CLK_ENB 27 1140b928af1SViresh Kumar #define SPEAR1310_DMA_CLK_ENB 25 1150b928af1SViresh Kumar #define SPEAR1310_GPIO1_CLK_ENB 24 1160b928af1SViresh Kumar #define SPEAR1310_GPIO0_CLK_ENB 23 1170b928af1SViresh Kumar #define SPEAR1310_GPT1_CLK_ENB 22 1180b928af1SViresh Kumar #define SPEAR1310_GPT0_CLK_ENB 21 1190b928af1SViresh Kumar #define SPEAR1310_I2S0_CLK_ENB 20 1200b928af1SViresh Kumar #define SPEAR1310_I2S1_CLK_ENB 19 1210b928af1SViresh Kumar #define SPEAR1310_I2C0_CLK_ENB 18 1220b928af1SViresh Kumar #define SPEAR1310_SSP_CLK_ENB 17 1230b928af1SViresh Kumar #define SPEAR1310_UART_CLK_ENB 15 1240b928af1SViresh Kumar #define SPEAR1310_PCIE_SATA_2_CLK_ENB 14 1250b928af1SViresh Kumar #define SPEAR1310_PCIE_SATA_1_CLK_ENB 13 1260b928af1SViresh Kumar #define SPEAR1310_PCIE_SATA_0_CLK_ENB 12 1270b928af1SViresh Kumar #define SPEAR1310_UOC_CLK_ENB 11 1280b928af1SViresh Kumar #define SPEAR1310_UHC1_CLK_ENB 10 1290b928af1SViresh Kumar #define SPEAR1310_UHC0_CLK_ENB 9 1300b928af1SViresh Kumar #define SPEAR1310_GMAC_CLK_ENB 8 1310b928af1SViresh Kumar #define SPEAR1310_CFXD_CLK_ENB 7 1320b928af1SViresh Kumar #define SPEAR1310_SDHCI_CLK_ENB 6 1330b928af1SViresh Kumar #define SPEAR1310_SMI_CLK_ENB 5 1340b928af1SViresh Kumar #define SPEAR1310_FSMC_CLK_ENB 4 1350b928af1SViresh Kumar #define SPEAR1310_SYSRAM0_CLK_ENB 3 1360b928af1SViresh Kumar #define SPEAR1310_SYSRAM1_CLK_ENB 2 1370b928af1SViresh Kumar #define SPEAR1310_SYSROM_CLK_ENB 1 1380b928af1SViresh Kumar #define SPEAR1310_BUS_CLK_ENB 0 1390b928af1SViresh Kumar 1400b928af1SViresh Kumar #define SPEAR1310_PERIP2_CLK_ENB (VA_MISC_BASE + 0x304) 1410b928af1SViresh Kumar /* PERIP2_CLK_ENB register masks */ 1420b928af1SViresh Kumar #define SPEAR1310_THSENS_CLK_ENB 8 1430b928af1SViresh Kumar #define SPEAR1310_I2S_REF_PAD_CLK_ENB 7 1440b928af1SViresh Kumar #define SPEAR1310_ACP_CLK_ENB 6 1450b928af1SViresh Kumar #define SPEAR1310_GPT3_CLK_ENB 5 1460b928af1SViresh Kumar #define SPEAR1310_GPT2_CLK_ENB 4 1470b928af1SViresh Kumar #define SPEAR1310_KBD_CLK_ENB 3 1480b928af1SViresh Kumar #define SPEAR1310_CPU_DBG_CLK_ENB 2 1490b928af1SViresh Kumar #define SPEAR1310_DDR_CORE_CLK_ENB 1 1500b928af1SViresh Kumar #define SPEAR1310_DDR_CTRL_CLK_ENB 0 1510b928af1SViresh Kumar 1520b928af1SViresh Kumar #define SPEAR1310_RAS_CLK_ENB (VA_MISC_BASE + 0x310) 1530b928af1SViresh Kumar /* RAS_CLK_ENB register masks */ 1540b928af1SViresh Kumar #define SPEAR1310_SYNT3_CLK_ENB 17 1550b928af1SViresh Kumar #define SPEAR1310_SYNT2_CLK_ENB 16 1560b928af1SViresh Kumar #define SPEAR1310_SYNT1_CLK_ENB 15 1570b928af1SViresh Kumar #define SPEAR1310_SYNT0_CLK_ENB 14 1580b928af1SViresh Kumar #define SPEAR1310_PCLK3_CLK_ENB 13 1590b928af1SViresh Kumar #define SPEAR1310_PCLK2_CLK_ENB 12 1600b928af1SViresh Kumar #define SPEAR1310_PCLK1_CLK_ENB 11 1610b928af1SViresh Kumar #define SPEAR1310_PCLK0_CLK_ENB 10 1620b928af1SViresh Kumar #define SPEAR1310_PLL3_CLK_ENB 9 1630b928af1SViresh Kumar #define SPEAR1310_PLL2_CLK_ENB 8 1640b928af1SViresh Kumar #define SPEAR1310_C125M_PAD_CLK_ENB 7 1650b928af1SViresh Kumar #define SPEAR1310_C30M_CLK_ENB 6 1660b928af1SViresh Kumar #define SPEAR1310_C48M_CLK_ENB 5 1670b928af1SViresh Kumar #define SPEAR1310_OSC_25M_CLK_ENB 4 1680b928af1SViresh Kumar #define SPEAR1310_OSC_32K_CLK_ENB 3 1690b928af1SViresh Kumar #define SPEAR1310_OSC_24M_CLK_ENB 2 1700b928af1SViresh Kumar #define SPEAR1310_PCLK_CLK_ENB 1 1710b928af1SViresh Kumar #define SPEAR1310_ACLK_CLK_ENB 0 1720b928af1SViresh Kumar 1730b928af1SViresh Kumar /* RAS Area Control Register */ 1740b928af1SViresh Kumar #define SPEAR1310_RAS_CTRL_REG0 (VA_SPEAR1310_RAS_BASE + 0x000) 1750b928af1SViresh Kumar #define SPEAR1310_SSP1_CLK_MASK 3 1760b928af1SViresh Kumar #define SPEAR1310_SSP1_CLK_SHIFT 26 1770b928af1SViresh Kumar #define SPEAR1310_TDM_CLK_MASK 1 1780b928af1SViresh Kumar #define SPEAR1310_TDM2_CLK_SHIFT 24 1790b928af1SViresh Kumar #define SPEAR1310_TDM1_CLK_SHIFT 23 1800b928af1SViresh Kumar #define SPEAR1310_I2C_CLK_MASK 1 1810b928af1SViresh Kumar #define SPEAR1310_I2C7_CLK_SHIFT 22 1820b928af1SViresh Kumar #define SPEAR1310_I2C6_CLK_SHIFT 21 1830b928af1SViresh Kumar #define SPEAR1310_I2C5_CLK_SHIFT 20 1840b928af1SViresh Kumar #define SPEAR1310_I2C4_CLK_SHIFT 19 1850b928af1SViresh Kumar #define SPEAR1310_I2C3_CLK_SHIFT 18 1860b928af1SViresh Kumar #define SPEAR1310_I2C2_CLK_SHIFT 17 1870b928af1SViresh Kumar #define SPEAR1310_I2C1_CLK_SHIFT 16 1880b928af1SViresh Kumar #define SPEAR1310_GPT64_CLK_MASK 1 1890b928af1SViresh Kumar #define SPEAR1310_GPT64_CLK_SHIFT 15 1900b928af1SViresh Kumar #define SPEAR1310_RAS_UART_CLK_MASK 1 1910b928af1SViresh Kumar #define SPEAR1310_UART5_CLK_SHIFT 14 1920b928af1SViresh Kumar #define SPEAR1310_UART4_CLK_SHIFT 13 1930b928af1SViresh Kumar #define SPEAR1310_UART3_CLK_SHIFT 12 1940b928af1SViresh Kumar #define SPEAR1310_UART2_CLK_SHIFT 11 1950b928af1SViresh Kumar #define SPEAR1310_UART1_CLK_SHIFT 10 1960b928af1SViresh Kumar #define SPEAR1310_PCI_CLK_MASK 1 1970b928af1SViresh Kumar #define SPEAR1310_PCI_CLK_SHIFT 0 1980b928af1SViresh Kumar 1990b928af1SViresh Kumar #define SPEAR1310_RAS_CTRL_REG1 (VA_SPEAR1310_RAS_BASE + 0x004) 2000b928af1SViresh Kumar #define SPEAR1310_PHY_CLK_MASK 0x3 2010b928af1SViresh Kumar #define SPEAR1310_RMII_PHY_CLK_SHIFT 0 2020b928af1SViresh Kumar #define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT 2 2030b928af1SViresh Kumar 2040b928af1SViresh Kumar #define SPEAR1310_RAS_SW_CLK_CTRL (VA_SPEAR1310_RAS_BASE + 0x0148) 2050b928af1SViresh Kumar #define SPEAR1310_CAN1_CLK_ENB 25 2060b928af1SViresh Kumar #define SPEAR1310_CAN0_CLK_ENB 24 2070b928af1SViresh Kumar #define SPEAR1310_GPT64_CLK_ENB 23 2080b928af1SViresh Kumar #define SPEAR1310_SSP1_CLK_ENB 22 2090b928af1SViresh Kumar #define SPEAR1310_I2C7_CLK_ENB 21 2100b928af1SViresh Kumar #define SPEAR1310_I2C6_CLK_ENB 20 2110b928af1SViresh Kumar #define SPEAR1310_I2C5_CLK_ENB 19 2120b928af1SViresh Kumar #define SPEAR1310_I2C4_CLK_ENB 18 2130b928af1SViresh Kumar #define SPEAR1310_I2C3_CLK_ENB 17 2140b928af1SViresh Kumar #define SPEAR1310_I2C2_CLK_ENB 16 2150b928af1SViresh Kumar #define SPEAR1310_I2C1_CLK_ENB 15 2160b928af1SViresh Kumar #define SPEAR1310_UART5_CLK_ENB 14 2170b928af1SViresh Kumar #define SPEAR1310_UART4_CLK_ENB 13 2180b928af1SViresh Kumar #define SPEAR1310_UART3_CLK_ENB 12 2190b928af1SViresh Kumar #define SPEAR1310_UART2_CLK_ENB 11 2200b928af1SViresh Kumar #define SPEAR1310_UART1_CLK_ENB 10 2210b928af1SViresh Kumar #define SPEAR1310_RS485_1_CLK_ENB 9 2220b928af1SViresh Kumar #define SPEAR1310_RS485_0_CLK_ENB 8 2230b928af1SViresh Kumar #define SPEAR1310_TDM2_CLK_ENB 7 2240b928af1SViresh Kumar #define SPEAR1310_TDM1_CLK_ENB 6 2250b928af1SViresh Kumar #define SPEAR1310_PCI_CLK_ENB 5 2260b928af1SViresh Kumar #define SPEAR1310_GMII_CLK_ENB 4 2270b928af1SViresh Kumar #define SPEAR1310_MII2_CLK_ENB 3 2280b928af1SViresh Kumar #define SPEAR1310_MII1_CLK_ENB 2 2290b928af1SViresh Kumar #define SPEAR1310_MII0_CLK_ENB 1 2300b928af1SViresh Kumar #define SPEAR1310_ESRAM_CLK_ENB 0 2310b928af1SViresh Kumar 2320b928af1SViresh Kumar static DEFINE_SPINLOCK(_lock); 2330b928af1SViresh Kumar 2340b928af1SViresh Kumar /* pll rate configuration table, in ascending order of rates */ 2350b928af1SViresh Kumar static struct pll_rate_tbl pll_rtbl[] = { 2360b928af1SViresh Kumar /* PCLK 24MHz */ 2370b928af1SViresh Kumar {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */ 2380b928af1SViresh Kumar {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */ 2390b928af1SViresh Kumar {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */ 2400b928af1SViresh Kumar {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */ 2410b928af1SViresh Kumar {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */ 2420b928af1SViresh Kumar {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */ 2430b928af1SViresh Kumar {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 2440b928af1SViresh Kumar }; 2450b928af1SViresh Kumar 2460b928af1SViresh Kumar /* vco-pll4 rate configuration table, in ascending order of rates */ 2470b928af1SViresh Kumar static struct pll_rate_tbl pll4_rtbl[] = { 2480b928af1SViresh Kumar {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */ 2490b928af1SViresh Kumar {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */ 2500b928af1SViresh Kumar {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */ 2510b928af1SViresh Kumar {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */ 2520b928af1SViresh Kumar }; 2530b928af1SViresh Kumar 2540b928af1SViresh Kumar /* aux rate configuration table, in ascending order of rates */ 2550b928af1SViresh Kumar static struct aux_rate_tbl aux_rtbl[] = { 2560b928af1SViresh Kumar /* For VCO1div2 = 500 MHz */ 2570b928af1SViresh Kumar {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */ 2580b928af1SViresh Kumar {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */ 2590b928af1SViresh Kumar {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */ 2600b928af1SViresh Kumar {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */ 2610b928af1SViresh Kumar {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */ 2620b928af1SViresh Kumar {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */ 2630b928af1SViresh Kumar }; 2640b928af1SViresh Kumar 2650b928af1SViresh Kumar /* gmac rate configuration table, in ascending order of rates */ 2660b928af1SViresh Kumar static struct aux_rate_tbl gmac_rtbl[] = { 2670b928af1SViresh Kumar /* For gmac phy input clk */ 2680b928af1SViresh Kumar {.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */ 2690b928af1SViresh Kumar {.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */ 2700b928af1SViresh Kumar {.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */ 2710b928af1SViresh Kumar {.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */ 2720b928af1SViresh Kumar }; 2730b928af1SViresh Kumar 2740b928af1SViresh Kumar /* clcd rate configuration table, in ascending order of rates */ 2750b928af1SViresh Kumar static struct frac_rate_tbl clcd_rtbl[] = { 2760b928af1SViresh Kumar {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 2770b928af1SViresh Kumar {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 2780b928af1SViresh Kumar {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 2790b928af1SViresh Kumar {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ 2800b928af1SViresh Kumar {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ 2810b928af1SViresh Kumar {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 2820b928af1SViresh Kumar {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 2830b928af1SViresh Kumar {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ 2840b928af1SViresh Kumar {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ 2850b928af1SViresh Kumar {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 2860b928af1SViresh Kumar }; 2870b928af1SViresh Kumar 2880b928af1SViresh Kumar /* i2s prescaler1 masks */ 2890b928af1SViresh Kumar static struct aux_clk_masks i2s_prs1_masks = { 2900b928af1SViresh Kumar .eq_sel_mask = AUX_EQ_SEL_MASK, 2910b928af1SViresh Kumar .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT, 2920b928af1SViresh Kumar .eq1_mask = AUX_EQ1_SEL, 2930b928af1SViresh Kumar .eq2_mask = AUX_EQ2_SEL, 2940b928af1SViresh Kumar .xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK, 2950b928af1SViresh Kumar .xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT, 2960b928af1SViresh Kumar .yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK, 2970b928af1SViresh Kumar .yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT, 2980b928af1SViresh Kumar }; 2990b928af1SViresh Kumar 3000b928af1SViresh Kumar /* i2s sclk (bit clock) syynthesizers masks */ 3010b928af1SViresh Kumar static struct aux_clk_masks i2s_sclk_masks = { 3020b928af1SViresh Kumar .eq_sel_mask = AUX_EQ_SEL_MASK, 3030b928af1SViresh Kumar .eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT, 3040b928af1SViresh Kumar .eq1_mask = AUX_EQ1_SEL, 3050b928af1SViresh Kumar .eq2_mask = AUX_EQ2_SEL, 3060b928af1SViresh Kumar .xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK, 3070b928af1SViresh Kumar .xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT, 3080b928af1SViresh Kumar .yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK, 3090b928af1SViresh Kumar .yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT, 3100b928af1SViresh Kumar .enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB, 3110b928af1SViresh Kumar }; 3120b928af1SViresh Kumar 3130b928af1SViresh Kumar /* i2s prs1 aux rate configuration table, in ascending order of rates */ 3140b928af1SViresh Kumar static struct aux_rate_tbl i2s_prs1_rtbl[] = { 3150b928af1SViresh Kumar /* For parent clk = 49.152 MHz */ 3160b928af1SViresh Kumar {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */ 3170b928af1SViresh Kumar }; 3180b928af1SViresh Kumar 3190b928af1SViresh Kumar /* i2s sclk aux rate configuration table, in ascending order of rates */ 3200b928af1SViresh Kumar static struct aux_rate_tbl i2s_sclk_rtbl[] = { 3210b928af1SViresh Kumar /* For i2s_ref_clk = 12.288MHz */ 3220b928af1SViresh Kumar {.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */ 3230b928af1SViresh Kumar {.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */ 3240b928af1SViresh Kumar }; 3250b928af1SViresh Kumar 3260b928af1SViresh Kumar /* adc rate configuration table, in ascending order of rates */ 3270b928af1SViresh Kumar /* possible adc range is 2.5 MHz to 20 MHz. */ 3280b928af1SViresh Kumar static struct aux_rate_tbl adc_rtbl[] = { 3290b928af1SViresh Kumar /* For ahb = 166.67 MHz */ 3300b928af1SViresh Kumar {.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */ 3310b928af1SViresh Kumar {.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */ 3320b928af1SViresh Kumar {.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */ 3330b928af1SViresh Kumar {.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */ 3340b928af1SViresh Kumar }; 3350b928af1SViresh Kumar 3360b928af1SViresh Kumar /* General synth rate configuration table, in ascending order of rates */ 3370b928af1SViresh Kumar static struct frac_rate_tbl gen_rtbl[] = { 3380b928af1SViresh Kumar /* For vco1div4 = 250 MHz */ 3390b928af1SViresh Kumar {.div = 0x14000}, /* 25 MHz */ 3400b928af1SViresh Kumar {.div = 0x0A000}, /* 50 MHz */ 3410b928af1SViresh Kumar {.div = 0x05000}, /* 100 MHz */ 3420b928af1SViresh Kumar {.div = 0x02000}, /* 250 MHz */ 3430b928af1SViresh Kumar }; 3440b928af1SViresh Kumar 3450b928af1SViresh Kumar /* clock parents */ 3460b928af1SViresh Kumar static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 3470b928af1SViresh Kumar static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 348e28f1aa1SVipul Kumar Samar static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", }; 349e28f1aa1SVipul Kumar Samar static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", }; 350e28f1aa1SVipul Kumar Samar static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk", 3510b928af1SViresh Kumar "osc_25m_clk", }; 352e28f1aa1SVipul Kumar Samar static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", }; 3530b928af1SViresh Kumar static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", }; 354e28f1aa1SVipul Kumar Samar static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", }; 3550b928af1SViresh Kumar static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk", 3560b928af1SViresh Kumar "i2s_src_pad_clk", }; 357e28f1aa1SVipul Kumar Samar static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", }; 3580b928af1SViresh Kumar static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 3590b928af1SViresh Kumar "pll3_clk", }; 3600b928af1SViresh Kumar static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", 3610b928af1SViresh Kumar "pll2_clk", }; 3620b928af1SViresh Kumar static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none", 363e28f1aa1SVipul Kumar Samar "ras_pll2_clk", "ras_syn0_clk", }; 3640b928af1SViresh Kumar static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk", 365e28f1aa1SVipul Kumar Samar "ras_pll2_clk", "ras_syn0_clk", }; 366e28f1aa1SVipul Kumar Samar static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", }; 367e28f1aa1SVipul Kumar Samar static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", }; 368e28f1aa1SVipul Kumar Samar static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk", 3690b928af1SViresh Kumar "ras_plclk0_clk", }; 370e28f1aa1SVipul Kumar Samar static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", }; 371e28f1aa1SVipul Kumar Samar static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", }; 3720b928af1SViresh Kumar 3730b928af1SViresh Kumar void __init spear1310_clk_init(void) 3740b928af1SViresh Kumar { 3750b928af1SViresh Kumar struct clk *clk, *clk1; 3760b928af1SViresh Kumar 3770b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); 3780b928af1SViresh Kumar clk_register_clkdev(clk, "apb_pclk", NULL); 3790b928af1SViresh Kumar 3800b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 3810b928af1SViresh Kumar 32000); 3820b928af1SViresh Kumar clk_register_clkdev(clk, "osc_32k_clk", NULL); 3830b928af1SViresh Kumar 3840b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, 3850b928af1SViresh Kumar 24000000); 3860b928af1SViresh Kumar clk_register_clkdev(clk, "osc_24m_clk", NULL); 3870b928af1SViresh Kumar 3880b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, 3890b928af1SViresh Kumar 25000000); 3900b928af1SViresh Kumar clk_register_clkdev(clk, "osc_25m_clk", NULL); 3910b928af1SViresh Kumar 392e28f1aa1SVipul Kumar Samar clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, 393e28f1aa1SVipul Kumar Samar 125000000); 394e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gmii_pad_clk", NULL); 3950b928af1SViresh Kumar 3960b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 3970b928af1SViresh Kumar CLK_IS_ROOT, 12288000); 3980b928af1SViresh Kumar clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); 3990b928af1SViresh Kumar 4000b928af1SViresh Kumar /* clock derived from 32 KHz osc clk */ 4010b928af1SViresh Kumar clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 4020b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, 4030b928af1SViresh Kumar &_lock); 404df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e0580000.rtc"); 4050b928af1SViresh Kumar 4060b928af1SViresh Kumar /* clock derived from 24 or 25 MHz osc clk */ 4070b928af1SViresh Kumar /* vco-pll */ 408e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 4090b928af1SViresh Kumar ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 4100b928af1SViresh Kumar SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 4110b928af1SViresh Kumar &_lock); 412e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "vco1_mclk", NULL); 413e28f1aa1SVipul Kumar Samar clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 4140b928af1SViresh Kumar 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, 4150b928af1SViresh Kumar ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 4160b928af1SViresh Kumar clk_register_clkdev(clk, "vco1_clk", NULL); 4170b928af1SViresh Kumar clk_register_clkdev(clk1, "pll1_clk", NULL); 4180b928af1SViresh Kumar 419e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 4200b928af1SViresh Kumar ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 4210b928af1SViresh Kumar SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 4220b928af1SViresh Kumar &_lock); 423e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "vco2_mclk", NULL); 424e28f1aa1SVipul Kumar Samar clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 4250b928af1SViresh Kumar 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, 4260b928af1SViresh Kumar ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 4270b928af1SViresh Kumar clk_register_clkdev(clk, "vco2_clk", NULL); 4280b928af1SViresh Kumar clk_register_clkdev(clk1, "pll2_clk", NULL); 4290b928af1SViresh Kumar 430e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 4310b928af1SViresh Kumar ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 4320b928af1SViresh Kumar SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 4330b928af1SViresh Kumar &_lock); 434e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "vco3_mclk", NULL); 435e28f1aa1SVipul Kumar Samar clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 4360b928af1SViresh Kumar 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, 4370b928af1SViresh Kumar ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 4380b928af1SViresh Kumar clk_register_clkdev(clk, "vco3_clk", NULL); 4390b928af1SViresh Kumar clk_register_clkdev(clk1, "pll3_clk", NULL); 4400b928af1SViresh Kumar 4410b928af1SViresh Kumar clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", 4420b928af1SViresh Kumar 0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl, 4430b928af1SViresh Kumar ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL); 4440b928af1SViresh Kumar clk_register_clkdev(clk, "vco4_clk", NULL); 4450b928af1SViresh Kumar clk_register_clkdev(clk1, "pll4_clk", NULL); 4460b928af1SViresh Kumar 4470b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, 4480b928af1SViresh Kumar 48000000); 4490b928af1SViresh Kumar clk_register_clkdev(clk, "pll5_clk", NULL); 4500b928af1SViresh Kumar 4510b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, 4520b928af1SViresh Kumar 25000000); 4530b928af1SViresh Kumar clk_register_clkdev(clk, "pll6_clk", NULL); 4540b928af1SViresh Kumar 4550b928af1SViresh Kumar /* vco div n clocks */ 4560b928af1SViresh Kumar clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, 4570b928af1SViresh Kumar 2); 4580b928af1SViresh Kumar clk_register_clkdev(clk, "vco1div2_clk", NULL); 4590b928af1SViresh Kumar 4600b928af1SViresh Kumar clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, 4610b928af1SViresh Kumar 4); 4620b928af1SViresh Kumar clk_register_clkdev(clk, "vco1div4_clk", NULL); 4630b928af1SViresh Kumar 4640b928af1SViresh Kumar clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, 4650b928af1SViresh Kumar 2); 4660b928af1SViresh Kumar clk_register_clkdev(clk, "vco2div2_clk", NULL); 4670b928af1SViresh Kumar 4680b928af1SViresh Kumar clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, 4690b928af1SViresh Kumar 2); 4700b928af1SViresh Kumar clk_register_clkdev(clk, "vco3div2_clk", NULL); 4710b928af1SViresh Kumar 4720b928af1SViresh Kumar /* peripherals */ 4730b928af1SViresh Kumar clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1, 4740b928af1SViresh Kumar 128); 475e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, 4760b928af1SViresh Kumar SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0, 4770b928af1SViresh Kumar &_lock); 4780b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "spear_thermal"); 4790b928af1SViresh Kumar 4800b928af1SViresh Kumar /* clock derived from pll4 clk */ 4810b928af1SViresh Kumar clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 4820b928af1SViresh Kumar 1); 4830b928af1SViresh Kumar clk_register_clkdev(clk, "ddr_clk", NULL); 4840b928af1SViresh Kumar 4850b928af1SViresh Kumar /* clock derived from pll1 clk */ 486*12499792SVipul Kumar Samar clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 487*12499792SVipul Kumar Samar CLK_SET_RATE_PARENT, 1, 2); 4880b928af1SViresh Kumar clk_register_clkdev(clk, "cpu_clk", NULL); 4890b928af1SViresh Kumar 4900b928af1SViresh Kumar clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 4910b928af1SViresh Kumar 2); 4920b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "ec800620.wdt"); 4930b928af1SViresh Kumar 4940b928af1SViresh Kumar clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, 4950b928af1SViresh Kumar 6); 4960b928af1SViresh Kumar clk_register_clkdev(clk, "ahb_clk", NULL); 4970b928af1SViresh Kumar 4980b928af1SViresh Kumar clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, 4990b928af1SViresh Kumar 12); 5000b928af1SViresh Kumar clk_register_clkdev(clk, "apb_clk", NULL); 5010b928af1SViresh Kumar 5020b928af1SViresh Kumar /* gpt clocks */ 503e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 5040b928af1SViresh Kumar ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 5050b928af1SViresh Kumar SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 5060b928af1SViresh Kumar &_lock); 507e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gpt0_mclk", NULL); 508e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 5090b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, 5100b928af1SViresh Kumar &_lock); 5110b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "gpt0"); 5120b928af1SViresh Kumar 513e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 5140b928af1SViresh Kumar ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 5150b928af1SViresh Kumar SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 5160b928af1SViresh Kumar &_lock); 517e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gpt1_mclk", NULL); 518e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 5190b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, 5200b928af1SViresh Kumar &_lock); 5210b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "gpt1"); 5220b928af1SViresh Kumar 523e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 5240b928af1SViresh Kumar ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 5250b928af1SViresh Kumar SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 5260b928af1SViresh Kumar &_lock); 527e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gpt2_mclk", NULL); 528e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 5290b928af1SViresh Kumar SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, 5300b928af1SViresh Kumar &_lock); 5310b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "gpt2"); 5320b928af1SViresh Kumar 533e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 5340b928af1SViresh Kumar ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 5350b928af1SViresh Kumar SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 5360b928af1SViresh Kumar &_lock); 537e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gpt3_mclk", NULL); 538e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 5390b928af1SViresh Kumar SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, 5400b928af1SViresh Kumar &_lock); 5410b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "gpt3"); 5420b928af1SViresh Kumar 5430b928af1SViresh Kumar /* others */ 544e28f1aa1SVipul Kumar Samar clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", 545e28f1aa1SVipul Kumar Samar 0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl, 546e28f1aa1SVipul Kumar Samar ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 547e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "uart_syn_clk", NULL); 548e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 5490b928af1SViresh Kumar 550e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 551*12499792SVipul Kumar Samar ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 552*12499792SVipul Kumar Samar SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, 553*12499792SVipul Kumar Samar SPEAR1310_UART_CLK_MASK, 0, &_lock); 554e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "uart0_mclk", NULL); 5550b928af1SViresh Kumar 556*12499792SVipul Kumar Samar clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 557*12499792SVipul Kumar Samar CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 558*12499792SVipul Kumar Samar SPEAR1310_UART_CLK_ENB, 0, &_lock); 5590b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e0000000.serial"); 5600b928af1SViresh Kumar 561e28f1aa1SVipul Kumar Samar clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", 5620b928af1SViresh Kumar "vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL, 5630b928af1SViresh Kumar aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 564e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "sdhci_syn_clk", NULL); 565e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); 5660b928af1SViresh Kumar 567*12499792SVipul Kumar Samar clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 568*12499792SVipul Kumar Samar CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 569*12499792SVipul Kumar Samar SPEAR1310_SDHCI_CLK_ENB, 0, &_lock); 5700b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 5710b928af1SViresh Kumar 572e28f1aa1SVipul Kumar Samar clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 573e28f1aa1SVipul Kumar Samar 0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl, 574e28f1aa1SVipul Kumar Samar ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 575e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "cfxd_syn_clk", NULL); 576e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); 5770b928af1SViresh Kumar 578*12499792SVipul Kumar Samar clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 579*12499792SVipul Kumar Samar CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 580*12499792SVipul Kumar Samar SPEAR1310_CFXD_CLK_ENB, 0, &_lock); 5810b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "b2800000.cf"); 5820b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "arasan_xd"); 5830b928af1SViresh Kumar 584e28f1aa1SVipul Kumar Samar clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 585e28f1aa1SVipul Kumar Samar 0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl, 586e28f1aa1SVipul Kumar Samar ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 587e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "c3_syn_clk", NULL); 588e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 5890b928af1SViresh Kumar 590e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 591*12499792SVipul Kumar Samar ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, 592*12499792SVipul Kumar Samar SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, 593*12499792SVipul Kumar Samar SPEAR1310_C3_CLK_MASK, 0, &_lock); 594e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "c3_mclk", NULL); 5950b928af1SViresh Kumar 596e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, 5970b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0, 5980b928af1SViresh Kumar &_lock); 5990b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "c3"); 6000b928af1SViresh Kumar 6010b928af1SViresh Kumar /* gmac */ 602e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 6030b928af1SViresh Kumar ARRAY_SIZE(gmac_phy_input_parents), 0, 6040b928af1SViresh Kumar SPEAR1310_GMAC_CLK_CFG, 6050b928af1SViresh Kumar SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, 6060b928af1SViresh Kumar SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 607e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "phy_input_mclk", NULL); 6080b928af1SViresh Kumar 609e28f1aa1SVipul Kumar Samar clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", 610e28f1aa1SVipul Kumar Samar 0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl, 611e28f1aa1SVipul Kumar Samar ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); 612e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "phy_syn_clk", NULL); 613e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 6140b928af1SViresh Kumar 615e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 6160b928af1SViresh Kumar ARRAY_SIZE(gmac_phy_parents), 0, 6170b928af1SViresh Kumar SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, 6180b928af1SViresh Kumar SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); 619df2449abSRajeev Kumar clk_register_clkdev(clk, "stmmacphy.0", NULL); 6200b928af1SViresh Kumar 6210b928af1SViresh Kumar /* clcd */ 622e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 6230b928af1SViresh Kumar ARRAY_SIZE(clcd_synth_parents), 0, 6240b928af1SViresh Kumar SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT, 6250b928af1SViresh Kumar SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); 626e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 6270b928af1SViresh Kumar 628e28f1aa1SVipul Kumar Samar clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, 6290b928af1SViresh Kumar SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl, 6300b928af1SViresh Kumar ARRAY_SIZE(clcd_rtbl), &_lock); 631e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "clcd_syn_clk", NULL); 6320b928af1SViresh Kumar 633e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 634*12499792SVipul Kumar Samar ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, 6350b928af1SViresh Kumar SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, 6360b928af1SViresh Kumar SPEAR1310_CLCD_CLK_MASK, 0, &_lock); 637e0b9c210SShiraz Hashim clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 6380b928af1SViresh Kumar 639e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, 6400b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, 6410b928af1SViresh Kumar &_lock); 642df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e1000000.clcd"); 6430b928af1SViresh Kumar 6440b928af1SViresh Kumar /* i2s */ 645e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 6460b928af1SViresh Kumar ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG, 6470b928af1SViresh Kumar SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK, 6480b928af1SViresh Kumar 0, &_lock); 649e0b9c210SShiraz Hashim clk_register_clkdev(clk, "i2s_src_mclk", NULL); 6500b928af1SViresh Kumar 651e28f1aa1SVipul Kumar Samar clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, 6520b928af1SViresh Kumar SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, 6530b928af1SViresh Kumar ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 6540b928af1SViresh Kumar clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 6550b928af1SViresh Kumar 656e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 657*12499792SVipul Kumar Samar ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 658*12499792SVipul Kumar Samar SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, 659*12499792SVipul Kumar Samar SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); 660*12499792SVipul Kumar Samar clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 6610b928af1SViresh Kumar 662e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, 6630b928af1SViresh Kumar SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, 6640b928af1SViresh Kumar 0, &_lock); 6650b928af1SViresh Kumar clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 6660b928af1SViresh Kumar 667e28f1aa1SVipul Kumar Samar clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", 668463f9e20SShiraz Hashim "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG, 6690b928af1SViresh Kumar &i2s_sclk_masks, i2s_sclk_rtbl, 6700b928af1SViresh Kumar ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); 6710b928af1SViresh Kumar clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 672e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL); 6730b928af1SViresh Kumar 6740b928af1SViresh Kumar /* clock derived from ahb clk */ 6750b928af1SViresh Kumar clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, 6760b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0, 6770b928af1SViresh Kumar &_lock); 6780b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e0280000.i2c"); 6790b928af1SViresh Kumar 6800b928af1SViresh Kumar clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, 6810b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0, 6820b928af1SViresh Kumar &_lock); 6830b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "ea800000.dma"); 6840b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "eb000000.dma"); 6850b928af1SViresh Kumar 6860b928af1SViresh Kumar clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, 6870b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0, 6880b928af1SViresh Kumar &_lock); 6890b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "b2000000.jpeg"); 6900b928af1SViresh Kumar 6910b928af1SViresh Kumar clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, 6920b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0, 6930b928af1SViresh Kumar &_lock); 6940b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e2000000.eth"); 6950b928af1SViresh Kumar 6960b928af1SViresh Kumar clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, 6970b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0, 6980b928af1SViresh Kumar &_lock); 6990b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "b0000000.flash"); 7000b928af1SViresh Kumar 7010b928af1SViresh Kumar clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, 7020b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0, 7030b928af1SViresh Kumar &_lock); 7040b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "ea000000.flash"); 7050b928af1SViresh Kumar 7060b928af1SViresh Kumar clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, 7070b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, 7080b928af1SViresh Kumar &_lock); 709df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e4000000.ohci"); 710df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e4800000.ehci"); 7110b928af1SViresh Kumar 7120b928af1SViresh Kumar clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, 7130b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, 7140b928af1SViresh Kumar &_lock); 715df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e5000000.ohci"); 716df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e5800000.ehci"); 7170b928af1SViresh Kumar 7180b928af1SViresh Kumar clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, 7190b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, 7200b928af1SViresh Kumar &_lock); 721df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e3800000.otg"); 7220b928af1SViresh Kumar 7230b928af1SViresh Kumar clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, 7240b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 7250b928af1SViresh Kumar 0, &_lock); 7260b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "dw_pcie.0"); 727df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "b1000000.ahci"); 7280b928af1SViresh Kumar 7290b928af1SViresh Kumar clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, 7300b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 7310b928af1SViresh Kumar 0, &_lock); 7320b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "dw_pcie.1"); 733df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "b1800000.ahci"); 7340b928af1SViresh Kumar 7350b928af1SViresh Kumar clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, 7360b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 7370b928af1SViresh Kumar 0, &_lock); 7380b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "dw_pcie.2"); 739df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "b4000000.ahci"); 7400b928af1SViresh Kumar 7410b928af1SViresh Kumar clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 7420b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, 7430b928af1SViresh Kumar &_lock); 7440b928af1SViresh Kumar clk_register_clkdev(clk, "sysram0_clk", NULL); 7450b928af1SViresh Kumar 7460b928af1SViresh Kumar clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, 7470b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0, 7480b928af1SViresh Kumar &_lock); 7490b928af1SViresh Kumar clk_register_clkdev(clk, "sysram1_clk", NULL); 7500b928af1SViresh Kumar 751e28f1aa1SVipul Kumar Samar clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", 7520b928af1SViresh Kumar 0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl, 7530b928af1SViresh Kumar ARRAY_SIZE(adc_rtbl), &_lock, &clk1); 754e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "adc_syn_clk", NULL); 755e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk1, "adc_syn_gclk", NULL); 7560b928af1SViresh Kumar 757*12499792SVipul Kumar Samar clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 758*12499792SVipul Kumar Samar CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB, 759*12499792SVipul Kumar Samar SPEAR1310_ADC_CLK_ENB, 0, &_lock); 760df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e0080000.adc"); 7610b928af1SViresh Kumar 7620b928af1SViresh Kumar /* clock derived from apb clk */ 7630b928af1SViresh Kumar clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, 7640b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0, 7650b928af1SViresh Kumar &_lock); 7660b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e0100000.spi"); 7670b928af1SViresh Kumar 7680b928af1SViresh Kumar clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, 7690b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0, 7700b928af1SViresh Kumar &_lock); 7710b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e0600000.gpio"); 7720b928af1SViresh Kumar 7730b928af1SViresh Kumar clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, 7740b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0, 7750b928af1SViresh Kumar &_lock); 7760b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e0680000.gpio"); 7770b928af1SViresh Kumar 7780b928af1SViresh Kumar clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, 7790b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0, 7800b928af1SViresh Kumar &_lock); 7810b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e0180000.i2s"); 7820b928af1SViresh Kumar 7830b928af1SViresh Kumar clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, 7840b928af1SViresh Kumar SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0, 7850b928af1SViresh Kumar &_lock); 7860b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e0200000.i2s"); 7870b928af1SViresh Kumar 7880b928af1SViresh Kumar clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, 7890b928af1SViresh Kumar SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0, 7900b928af1SViresh Kumar &_lock); 7910b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "e0300000.kbd"); 7920b928af1SViresh Kumar 7930b928af1SViresh Kumar /* RAS clks */ 794e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 795e28f1aa1SVipul Kumar Samar ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG, 796e28f1aa1SVipul Kumar Samar SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, 7970b928af1SViresh Kumar SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 798e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); 7990b928af1SViresh Kumar 800e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 801e28f1aa1SVipul Kumar Samar ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG, 802e28f1aa1SVipul Kumar Samar SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, 8030b928af1SViresh Kumar SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 804e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); 8050b928af1SViresh Kumar 806e28f1aa1SVipul Kumar Samar clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, 8070b928af1SViresh Kumar SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 8080b928af1SViresh Kumar &_lock); 809e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gen_syn0_clk", NULL); 8100b928af1SViresh Kumar 811e28f1aa1SVipul Kumar Samar clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, 8120b928af1SViresh Kumar SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 8130b928af1SViresh Kumar &_lock); 814e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gen_syn1_clk", NULL); 8150b928af1SViresh Kumar 816e28f1aa1SVipul Kumar Samar clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, 8170b928af1SViresh Kumar SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 8180b928af1SViresh Kumar &_lock); 819e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gen_syn2_clk", NULL); 8200b928af1SViresh Kumar 821e28f1aa1SVipul Kumar Samar clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, 8220b928af1SViresh Kumar SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 8230b928af1SViresh Kumar &_lock); 824e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "gen_syn3_clk", NULL); 8250b928af1SViresh Kumar 8260b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, 8270b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0, 8280b928af1SViresh Kumar &_lock); 8290b928af1SViresh Kumar clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); 8300b928af1SViresh Kumar 8310b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, 8320b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0, 8330b928af1SViresh Kumar &_lock); 8340b928af1SViresh Kumar clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); 8350b928af1SViresh Kumar 8360b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, 8370b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0, 8380b928af1SViresh Kumar &_lock); 8390b928af1SViresh Kumar clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); 8400b928af1SViresh Kumar 8410b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, 8420b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0, 8430b928af1SViresh Kumar &_lock); 8440b928af1SViresh Kumar clk_register_clkdev(clk, "ras_pll2_clk", NULL); 8450b928af1SViresh Kumar 8460b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, 8470b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0, 8480b928af1SViresh Kumar &_lock); 8490b928af1SViresh Kumar clk_register_clkdev(clk, "ras_pll3_clk", NULL); 8500b928af1SViresh Kumar 851e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, 8520b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0, 8530b928af1SViresh Kumar &_lock); 8540b928af1SViresh Kumar clk_register_clkdev(clk, "ras_tx125_clk", NULL); 8550b928af1SViresh Kumar 8560b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, 8570b928af1SViresh Kumar 30000000); 8580b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, 8590b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0, 8600b928af1SViresh Kumar &_lock); 8610b928af1SViresh Kumar clk_register_clkdev(clk, "ras_30m_clk", NULL); 8620b928af1SViresh Kumar 8630b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, 8640b928af1SViresh Kumar 48000000); 8650b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, 8660b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0, 8670b928af1SViresh Kumar &_lock); 8680b928af1SViresh Kumar clk_register_clkdev(clk, "ras_48m_clk", NULL); 8690b928af1SViresh Kumar 8700b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, 8710b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0, 8720b928af1SViresh Kumar &_lock); 8730b928af1SViresh Kumar clk_register_clkdev(clk, "ras_ahb_clk", NULL); 8740b928af1SViresh Kumar 8750b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, 8760b928af1SViresh Kumar SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0, 8770b928af1SViresh Kumar &_lock); 8780b928af1SViresh Kumar clk_register_clkdev(clk, "ras_apb_clk", NULL); 8790b928af1SViresh Kumar 8800b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT, 8810b928af1SViresh Kumar 50000000); 8820b928af1SViresh Kumar 8830b928af1SViresh Kumar clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT, 8840b928af1SViresh Kumar 50000000); 8850b928af1SViresh Kumar 8860b928af1SViresh Kumar clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, 8870b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0, 8880b928af1SViresh Kumar &_lock); 8890b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "c_can_platform.0"); 8900b928af1SViresh Kumar 8910b928af1SViresh Kumar clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, 8920b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0, 8930b928af1SViresh Kumar &_lock); 8940b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "c_can_platform.1"); 8950b928af1SViresh Kumar 8960b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, 8970b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0, 8980b928af1SViresh Kumar &_lock); 8990b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5c400000.eth"); 9000b928af1SViresh Kumar 9010b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, 9020b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0, 9030b928af1SViresh Kumar &_lock); 9040b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5c500000.eth"); 9050b928af1SViresh Kumar 9060b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, 9070b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0, 9080b928af1SViresh Kumar &_lock); 9090b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5c600000.eth"); 9100b928af1SViresh Kumar 9110b928af1SViresh Kumar clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, 9120b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0, 9130b928af1SViresh Kumar &_lock); 9140b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5c700000.eth"); 9150b928af1SViresh Kumar 916e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", 9170b928af1SViresh Kumar smii_rgmii_phy_parents, 9180b928af1SViresh Kumar ARRAY_SIZE(smii_rgmii_phy_parents), 0, 9190b928af1SViresh Kumar SPEAR1310_RAS_CTRL_REG1, 9200b928af1SViresh Kumar SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, 9210b928af1SViresh Kumar SPEAR1310_PHY_CLK_MASK, 0, &_lock); 922df2449abSRajeev Kumar clk_register_clkdev(clk, "stmmacphy.1", NULL); 923df2449abSRajeev Kumar clk_register_clkdev(clk, "stmmacphy.2", NULL); 924df2449abSRajeev Kumar clk_register_clkdev(clk, "stmmacphy.4", NULL); 9250b928af1SViresh Kumar 926e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, 9270b928af1SViresh Kumar ARRAY_SIZE(rmii_phy_parents), 0, 9280b928af1SViresh Kumar SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, 9290b928af1SViresh Kumar SPEAR1310_PHY_CLK_MASK, 0, &_lock); 930df2449abSRajeev Kumar clk_register_clkdev(clk, "stmmacphy.3", NULL); 9310b928af1SViresh Kumar 932e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, 9330b928af1SViresh Kumar ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 9340b928af1SViresh Kumar SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 9350b928af1SViresh Kumar 0, &_lock); 936e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "uart1_mclk", NULL); 9370b928af1SViresh Kumar 938e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 9390b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0, 9400b928af1SViresh Kumar &_lock); 9410b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5c800000.serial"); 9420b928af1SViresh Kumar 943e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, 9440b928af1SViresh Kumar ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 9450b928af1SViresh Kumar SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 9460b928af1SViresh Kumar 0, &_lock); 947e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "uart2_mclk", NULL); 9480b928af1SViresh Kumar 949e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, 9500b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0, 9510b928af1SViresh Kumar &_lock); 9520b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5c900000.serial"); 9530b928af1SViresh Kumar 954e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, 9550b928af1SViresh Kumar ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 9560b928af1SViresh Kumar SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 9570b928af1SViresh Kumar 0, &_lock); 958e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "uart3_mclk", NULL); 9590b928af1SViresh Kumar 960e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, 9610b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0, 9620b928af1SViresh Kumar &_lock); 9630b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5ca00000.serial"); 9640b928af1SViresh Kumar 965e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, 9660b928af1SViresh Kumar ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 9670b928af1SViresh Kumar SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 9680b928af1SViresh Kumar 0, &_lock); 969e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "uart4_mclk", NULL); 9700b928af1SViresh Kumar 971e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, 9720b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0, 9730b928af1SViresh Kumar &_lock); 9740b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5cb00000.serial"); 9750b928af1SViresh Kumar 976e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, 9770b928af1SViresh Kumar ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 9780b928af1SViresh Kumar SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 9790b928af1SViresh Kumar 0, &_lock); 980e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "uart5_mclk", NULL); 9810b928af1SViresh Kumar 982e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, 9830b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0, 9840b928af1SViresh Kumar &_lock); 9850b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5cc00000.serial"); 9860b928af1SViresh Kumar 987e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, 9880b928af1SViresh Kumar ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 9890b928af1SViresh Kumar SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 9900b928af1SViresh Kumar &_lock); 991e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "i2c1_mclk", NULL); 9920b928af1SViresh Kumar 993e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, 9940b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0, 9950b928af1SViresh Kumar &_lock); 9960b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5cd00000.i2c"); 9970b928af1SViresh Kumar 998e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, 9990b928af1SViresh Kumar ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10000b928af1SViresh Kumar SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 10010b928af1SViresh Kumar &_lock); 1002e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "i2c2_mclk", NULL); 10030b928af1SViresh Kumar 1004e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, 10050b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0, 10060b928af1SViresh Kumar &_lock); 10070b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5ce00000.i2c"); 10080b928af1SViresh Kumar 1009e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, 10100b928af1SViresh Kumar ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10110b928af1SViresh Kumar SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 10120b928af1SViresh Kumar &_lock); 1013e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "i2c3_mclk", NULL); 10140b928af1SViresh Kumar 1015e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, 10160b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0, 10170b928af1SViresh Kumar &_lock); 10180b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5cf00000.i2c"); 10190b928af1SViresh Kumar 1020e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, 10210b928af1SViresh Kumar ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10220b928af1SViresh Kumar SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 10230b928af1SViresh Kumar &_lock); 1024e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "i2c4_mclk", NULL); 10250b928af1SViresh Kumar 1026e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, 10270b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0, 10280b928af1SViresh Kumar &_lock); 10290b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5d000000.i2c"); 10300b928af1SViresh Kumar 1031e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, 10320b928af1SViresh Kumar ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10330b928af1SViresh Kumar SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 10340b928af1SViresh Kumar &_lock); 1035e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "i2c5_mclk", NULL); 10360b928af1SViresh Kumar 1037e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, 10380b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0, 10390b928af1SViresh Kumar &_lock); 10400b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5d100000.i2c"); 10410b928af1SViresh Kumar 1042e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, 10430b928af1SViresh Kumar ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10440b928af1SViresh Kumar SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 10450b928af1SViresh Kumar &_lock); 1046e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "i2c6_mclk", NULL); 10470b928af1SViresh Kumar 1048e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, 10490b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0, 10500b928af1SViresh Kumar &_lock); 10510b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5d200000.i2c"); 10520b928af1SViresh Kumar 1053e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, 10540b928af1SViresh Kumar ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10550b928af1SViresh Kumar SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 10560b928af1SViresh Kumar &_lock); 1057e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "i2c7_mclk", NULL); 10580b928af1SViresh Kumar 1059e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, 10600b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0, 10610b928af1SViresh Kumar &_lock); 10620b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5d300000.i2c"); 10630b928af1SViresh Kumar 1064e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, 10650b928af1SViresh Kumar ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10660b928af1SViresh Kumar SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0, 10670b928af1SViresh Kumar &_lock); 1068e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "ssp1_mclk", NULL); 10690b928af1SViresh Kumar 1070e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, 10710b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0, 10720b928af1SViresh Kumar &_lock); 10730b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "5d400000.spi"); 10740b928af1SViresh Kumar 1075e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "pci_mclk", pci_parents, 10760b928af1SViresh Kumar ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10770b928af1SViresh Kumar SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0, 10780b928af1SViresh Kumar &_lock); 1079e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "pci_mclk", NULL); 10800b928af1SViresh Kumar 1081e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, 10820b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0, 10830b928af1SViresh Kumar &_lock); 10840b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "pci"); 10850b928af1SViresh Kumar 1086e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, 10870b928af1SViresh Kumar ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10880b928af1SViresh Kumar SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 10890b928af1SViresh Kumar &_lock); 1090e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "tdm1_mclk", NULL); 10910b928af1SViresh Kumar 1092e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, 10930b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0, 10940b928af1SViresh Kumar &_lock); 10950b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); 10960b928af1SViresh Kumar 1097e28f1aa1SVipul Kumar Samar clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, 10980b928af1SViresh Kumar ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 10990b928af1SViresh Kumar SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 11000b928af1SViresh Kumar &_lock); 1101e28f1aa1SVipul Kumar Samar clk_register_clkdev(clk, "tdm2_mclk", NULL); 11020b928af1SViresh Kumar 1103e28f1aa1SVipul Kumar Samar clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, 11040b928af1SViresh Kumar SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0, 11050b928af1SViresh Kumar &_lock); 11060b928af1SViresh Kumar clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); 11070b928af1SViresh Kumar } 1108