1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 SpacemiT Technology Co. Ltd 4 * Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org> 5 */ 6 7 #include <linux/array_size.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/minmax.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 15 #include "ccu_common.h" 16 #include "ccu_pll.h" 17 #include "ccu_mix.h" 18 #include "ccu_ddn.h" 19 20 #include <dt-bindings/clock/spacemit,k1-syscon.h> 21 22 /* APBS register offset */ 23 #define APBS_PLL1_SWCR1 0x100 24 #define APBS_PLL1_SWCR2 0x104 25 #define APBS_PLL1_SWCR3 0x108 26 #define APBS_PLL2_SWCR1 0x118 27 #define APBS_PLL2_SWCR2 0x11c 28 #define APBS_PLL2_SWCR3 0x120 29 #define APBS_PLL3_SWCR1 0x124 30 #define APBS_PLL3_SWCR2 0x128 31 #define APBS_PLL3_SWCR3 0x12c 32 33 /* MPMU register offset */ 34 #define MPMU_POSR 0x0010 35 #define POSR_PLL1_LOCK BIT(27) 36 #define POSR_PLL2_LOCK BIT(28) 37 #define POSR_PLL3_LOCK BIT(29) 38 #define MPMU_SUCCR 0x0014 39 #define MPMU_ISCCR 0x0044 40 #define MPMU_WDTPCR 0x0200 41 #define MPMU_RIPCCR 0x0210 42 #define MPMU_ACGR 0x1024 43 #define MPMU_APBCSCR 0x1050 44 #define MPMU_SUCCR_1 0x10b0 45 46 /* APBC register offset */ 47 #define APBC_UART1_CLK_RST 0x00 48 #define APBC_UART2_CLK_RST 0x04 49 #define APBC_GPIO_CLK_RST 0x08 50 #define APBC_PWM0_CLK_RST 0x0c 51 #define APBC_PWM1_CLK_RST 0x10 52 #define APBC_PWM2_CLK_RST 0x14 53 #define APBC_PWM3_CLK_RST 0x18 54 #define APBC_TWSI8_CLK_RST 0x20 55 #define APBC_UART3_CLK_RST 0x24 56 #define APBC_RTC_CLK_RST 0x28 57 #define APBC_TWSI0_CLK_RST 0x2c 58 #define APBC_TWSI1_CLK_RST 0x30 59 #define APBC_TIMERS1_CLK_RST 0x34 60 #define APBC_TWSI2_CLK_RST 0x38 61 #define APBC_AIB_CLK_RST 0x3c 62 #define APBC_TWSI4_CLK_RST 0x40 63 #define APBC_TIMERS2_CLK_RST 0x44 64 #define APBC_ONEWIRE_CLK_RST 0x48 65 #define APBC_TWSI5_CLK_RST 0x4c 66 #define APBC_DRO_CLK_RST 0x58 67 #define APBC_IR_CLK_RST 0x5c 68 #define APBC_TWSI6_CLK_RST 0x60 69 #define APBC_COUNTER_CLK_SEL 0x64 70 #define APBC_TWSI7_CLK_RST 0x68 71 #define APBC_TSEN_CLK_RST 0x6c 72 #define APBC_UART4_CLK_RST 0x70 73 #define APBC_UART5_CLK_RST 0x74 74 #define APBC_UART6_CLK_RST 0x78 75 #define APBC_SSP3_CLK_RST 0x7c 76 #define APBC_SSPA0_CLK_RST 0x80 77 #define APBC_SSPA1_CLK_RST 0x84 78 #define APBC_IPC_AP2AUD_CLK_RST 0x90 79 #define APBC_UART7_CLK_RST 0x94 80 #define APBC_UART8_CLK_RST 0x98 81 #define APBC_UART9_CLK_RST 0x9c 82 #define APBC_CAN0_CLK_RST 0xa0 83 #define APBC_PWM4_CLK_RST 0xa8 84 #define APBC_PWM5_CLK_RST 0xac 85 #define APBC_PWM6_CLK_RST 0xb0 86 #define APBC_PWM7_CLK_RST 0xb4 87 #define APBC_PWM8_CLK_RST 0xb8 88 #define APBC_PWM9_CLK_RST 0xbc 89 #define APBC_PWM10_CLK_RST 0xc0 90 #define APBC_PWM11_CLK_RST 0xc4 91 #define APBC_PWM12_CLK_RST 0xc8 92 #define APBC_PWM13_CLK_RST 0xcc 93 #define APBC_PWM14_CLK_RST 0xd0 94 #define APBC_PWM15_CLK_RST 0xd4 95 #define APBC_PWM16_CLK_RST 0xd8 96 #define APBC_PWM17_CLK_RST 0xdc 97 #define APBC_PWM18_CLK_RST 0xe0 98 #define APBC_PWM19_CLK_RST 0xe4 99 100 /* APMU register offset */ 101 #define APMU_JPG_CLK_RES_CTRL 0x020 102 #define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 103 #define APMU_ISP_CLK_RES_CTRL 0x038 104 #define APMU_LCD_CLK_RES_CTRL1 0x044 105 #define APMU_LCD_SPI_CLK_RES_CTRL 0x048 106 #define APMU_LCD_CLK_RES_CTRL2 0x04c 107 #define APMU_CCIC_CLK_RES_CTRL 0x050 108 #define APMU_SDH0_CLK_RES_CTRL 0x054 109 #define APMU_SDH1_CLK_RES_CTRL 0x058 110 #define APMU_USB_CLK_RES_CTRL 0x05c 111 #define APMU_QSPI_CLK_RES_CTRL 0x060 112 #define APMU_DMA_CLK_RES_CTRL 0x064 113 #define APMU_AES_CLK_RES_CTRL 0x068 114 #define APMU_VPU_CLK_RES_CTRL 0x0a4 115 #define APMU_GPU_CLK_RES_CTRL 0x0cc 116 #define APMU_SDH2_CLK_RES_CTRL 0x0e0 117 #define APMU_PMUA_MC_CTRL 0x0e8 118 #define APMU_PMU_CC2_AP 0x100 119 #define APMU_PMUA_EM_CLK_RES_CTRL 0x104 120 #define APMU_AUDIO_CLK_RES_CTRL 0x14c 121 #define APMU_HDMI_CLK_RES_CTRL 0x1b8 122 #define APMU_CCI550_CLK_CTRL 0x300 123 #define APMU_ACLK_CLK_CTRL 0x388 124 #define APMU_CPU_C0_CLK_CTRL 0x38C 125 #define APMU_CPU_C1_CLK_CTRL 0x390 126 #define APMU_PCIE_CLK_RES_CTRL_0 0x3cc 127 #define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 128 #define APMU_PCIE_CLK_RES_CTRL_2 0x3dc 129 #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 130 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec 131 132 struct spacemit_ccu_data { 133 struct clk_hw **hws; 134 size_t num; 135 }; 136 137 /* APBS clocks start, APBS region contains and only contains all PLL clocks */ 138 139 /* 140 * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for 141 * peripherals. 142 */ 143 static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { 144 CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), 145 }; 146 147 static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { 148 CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), 149 }; 150 151 static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { 152 CCU_PLL_RATE(1600000000UL, 0x0050cd61, 0x43eaaaab), 153 CCU_PLL_RATE(1800000000UL, 0x0050cd61, 0x4b000000), 154 CCU_PLL_RATE(2000000000UL, 0x0050dd62, 0x2aeaaaab), 155 CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), 156 CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), 157 CCU_PLL_RATE(3200000000UL, 0x0050dd67, 0x43eaaaab), 158 }; 159 160 CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK, 161 CLK_SET_RATE_GATE); 162 CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK, 163 CLK_SET_RATE_GATE); 164 CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK, 165 CLK_SET_RATE_GATE); 166 167 CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); 168 CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); 169 CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); 170 CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); 171 CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); 172 CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); 173 CCU_FACTOR_GATE_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1); 174 CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1); 175 CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1); 176 CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1); 177 CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(0), 64, 1); 178 CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(10), 10, 1); 179 CCU_FACTOR_GATE_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(11), 100, 1); 180 181 CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); 182 CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); 183 CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); 184 CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); 185 CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); 186 CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); 187 CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); 188 CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); 189 190 CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); 191 CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); 192 CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); 193 CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); 194 CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); 195 CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); 196 CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); 197 CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); 198 199 CCU_FACTOR_DEFINE(pll3_20, CCU_PARENT_HW(pll3_d8), 20, 1); 200 CCU_FACTOR_DEFINE(pll3_40, CCU_PARENT_HW(pll3_d8), 10, 1); 201 CCU_FACTOR_DEFINE(pll3_80, CCU_PARENT_HW(pll3_d8), 5, 1); 202 203 /* APBS clocks end */ 204 205 /* MPMU clocks start */ 206 CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); 207 208 CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); 209 210 CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); 211 212 CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); 213 CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); 214 CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); 215 CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); 216 CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); 217 CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); 218 CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); 219 CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); 220 CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); 221 222 CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); 223 CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); 224 CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); 225 226 CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); 227 CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); 228 229 CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); 230 CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); 231 232 CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); 233 CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); 234 CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); 235 236 CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); 237 238 CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); 239 240 CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); 241 CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 0); 242 CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 0); 243 244 CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); 245 246 CCU_FACTOR_GATE_DEFINE(i2s_sysclk, CCU_PARENT_HW(pll1_d16_153p6), MPMU_ISCCR, BIT(31), 50, 1); 247 CCU_FACTOR_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_sysclk), MPMU_ISCCR, BIT(29), 1, 1); 248 249 static const struct clk_parent_data apb_parents[] = { 250 CCU_PARENT_HW(pll1_d96_25p6), 251 CCU_PARENT_HW(pll1_d48_51p2), 252 CCU_PARENT_HW(pll1_d96_25p6), 253 CCU_PARENT_HW(pll1_d24_102p4), 254 }; 255 CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); 256 257 CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); 258 259 CCU_GATE_DEFINE(ripc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, 0x1, 0); 260 /* MPMU clocks end */ 261 262 /* APBC clocks start */ 263 static const struct clk_parent_data uart_clk_parents[] = { 264 CCU_PARENT_HW(pll1_m3d128_57p6), 265 CCU_PARENT_HW(slow_uart1_14p74), 266 CCU_PARENT_HW(slow_uart2_48), 267 }; 268 CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART1_CLK_RST, 4, 3, BIT(1), 0); 269 CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); 270 CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); 271 CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); 272 CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); 273 CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); 274 CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); 275 CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); 276 CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); 277 278 CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); 279 280 static const struct clk_parent_data pwm_parents[] = { 281 CCU_PARENT_HW(pll1_d192_12p8), 282 CCU_PARENT_NAME(osc), 283 }; 284 CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); 285 CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); 286 CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); 287 CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); 288 CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); 289 CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); 290 CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); 291 CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); 292 CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); 293 CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); 294 CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); 295 CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); 296 CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); 297 CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); 298 CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); 299 CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); 300 CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); 301 CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); 302 CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); 303 CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); 304 305 static const struct clk_parent_data ssp_parents[] = { 306 CCU_PARENT_HW(pll1_d384_6p4), 307 CCU_PARENT_HW(pll1_d192_12p8), 308 CCU_PARENT_HW(pll1_d96_25p6), 309 CCU_PARENT_HW(pll1_d48_51p2), 310 CCU_PARENT_HW(pll1_d768_3p2), 311 CCU_PARENT_HW(pll1_d1536_1p6), 312 CCU_PARENT_HW(pll1_d3072_0p8), 313 }; 314 CCU_MUX_GATE_DEFINE(ssp3_clk, ssp_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); 315 316 CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc), APBC_RTC_CLK_RST, 317 BIT(7) | BIT(1), 0); 318 319 static const struct clk_parent_data twsi_parents[] = { 320 CCU_PARENT_HW(pll1_d78_31p5), 321 CCU_PARENT_HW(pll1_d48_51p2), 322 CCU_PARENT_HW(pll1_d40_61p44), 323 }; 324 CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); 325 CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); 326 CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); 327 CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); 328 CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); 329 CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); 330 CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0); 331 /* 332 * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero. 333 * Combine functional and bus bits together as a gate to avoid sharing the 334 * write-only register between different clock hardwares. 335 */ 336 CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0); 337 338 static const struct clk_parent_data timer_parents[] = { 339 CCU_PARENT_HW(pll1_d192_12p8), 340 CCU_PARENT_NAME(osc), 341 CCU_PARENT_HW(pll1_d384_6p4), 342 CCU_PARENT_NAME(vctcxo_3m), 343 CCU_PARENT_NAME(vctcxo_1m), 344 }; 345 CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); 346 CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); 347 348 CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); 349 350 CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); 351 352 static const struct clk_parent_data sspa_parents[] = { 353 CCU_PARENT_HW(pll1_d384_6p4), 354 CCU_PARENT_HW(pll1_d192_12p8), 355 CCU_PARENT_HW(pll1_d96_25p6), 356 CCU_PARENT_HW(pll1_d48_51p2), 357 CCU_PARENT_HW(pll1_d768_3p2), 358 CCU_PARENT_HW(pll1_d1536_1p6), 359 CCU_PARENT_HW(pll1_d3072_0p8), 360 CCU_PARENT_HW(i2s_bclk), 361 }; 362 CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); 363 CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); 364 CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); 365 CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0); 366 CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); 367 CCU_GATE_DEFINE(ipc_ap2aud_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); 368 369 static const struct clk_parent_data can_parents[] = { 370 CCU_PARENT_HW(pll3_20), 371 CCU_PARENT_HW(pll3_40), 372 CCU_PARENT_HW(pll3_80), 373 }; 374 CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); 375 CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_CAN0_CLK_RST, BIT(0), 0); 376 377 CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART1_CLK_RST, BIT(0), 0); 378 CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); 379 CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); 380 CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); 381 CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); 382 CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); 383 CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); 384 CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); 385 CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); 386 387 CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); 388 389 CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); 390 CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); 391 CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); 392 CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); 393 CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); 394 CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); 395 CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); 396 CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); 397 CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); 398 CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); 399 CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); 400 CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); 401 CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); 402 CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); 403 CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); 404 CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); 405 CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); 406 CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); 407 CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); 408 CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); 409 410 CCU_GATE_DEFINE(ssp3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); 411 412 CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); 413 414 CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); 415 CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); 416 CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); 417 CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); 418 CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); 419 CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); 420 CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0); 421 /* Placeholder to workaround quirk of the register */ 422 CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1); 423 424 CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); 425 CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); 426 427 CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); 428 429 CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); 430 431 CCU_GATE_DEFINE(sspa0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); 432 CCU_GATE_DEFINE(sspa1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); 433 434 CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); 435 436 CCU_GATE_DEFINE(ipc_ap2aud_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); 437 /* APBC clocks end */ 438 439 /* APMU clocks start */ 440 static const struct clk_parent_data pmua_aclk_parents[] = { 441 CCU_PARENT_HW(pll1_d10_245p76), 442 CCU_PARENT_HW(pll1_d8_307p2), 443 }; 444 CCU_MUX_DIV_FC_DEFINE(pmua_aclk, pmua_aclk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); 445 446 static const struct clk_parent_data cci550_clk_parents[] = { 447 CCU_PARENT_HW(pll1_d5_491p52), 448 CCU_PARENT_HW(pll1_d4_614p4), 449 CCU_PARENT_HW(pll1_d3_819p2), 450 CCU_PARENT_HW(pll2_d3), 451 }; 452 CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 3, BIT(12), 0, 2, 453 CLK_IS_CRITICAL); 454 455 static const struct clk_parent_data cpu_c0_hi_clk_parents[] = { 456 CCU_PARENT_HW(pll3_d2), 457 CCU_PARENT_HW(pll3_d1), 458 }; 459 CCU_MUX_DEFINE(cpu_c0_hi_clk, cpu_c0_hi_clk_parents, APMU_CPU_C0_CLK_CTRL, 13, 1, 0); 460 static const struct clk_parent_data cpu_c0_clk_parents[] = { 461 CCU_PARENT_HW(pll1_d4_614p4), 462 CCU_PARENT_HW(pll1_d3_819p2), 463 CCU_PARENT_HW(pll1_d6_409p6), 464 CCU_PARENT_HW(pll1_d5_491p52), 465 CCU_PARENT_HW(pll1_d2_1228p8), 466 CCU_PARENT_HW(pll3_d3), 467 CCU_PARENT_HW(pll2_d3), 468 CCU_PARENT_HW(cpu_c0_hi_clk), 469 }; 470 CCU_MUX_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, BIT(12), 0, 3, 471 CLK_IS_CRITICAL); 472 CCU_DIV_DEFINE(cpu_c0_ace_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 6, 3, 473 CLK_IS_CRITICAL); 474 CCU_DIV_DEFINE(cpu_c0_tcm_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 9, 3, 475 CLK_IS_CRITICAL); 476 477 static const struct clk_parent_data cpu_c1_hi_clk_parents[] = { 478 CCU_PARENT_HW(pll3_d2), 479 CCU_PARENT_HW(pll3_d1), 480 }; 481 CCU_MUX_DEFINE(cpu_c1_hi_clk, cpu_c1_hi_clk_parents, APMU_CPU_C1_CLK_CTRL, 13, 1, 0); 482 static const struct clk_parent_data cpu_c1_clk_parents[] = { 483 CCU_PARENT_HW(pll1_d4_614p4), 484 CCU_PARENT_HW(pll1_d3_819p2), 485 CCU_PARENT_HW(pll1_d6_409p6), 486 CCU_PARENT_HW(pll1_d5_491p52), 487 CCU_PARENT_HW(pll1_d2_1228p8), 488 CCU_PARENT_HW(pll3_d3), 489 CCU_PARENT_HW(pll2_d3), 490 CCU_PARENT_HW(cpu_c1_hi_clk), 491 }; 492 CCU_MUX_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, BIT(12), 0, 3, 493 CLK_IS_CRITICAL); 494 CCU_DIV_DEFINE(cpu_c1_ace_clk, CCU_PARENT_HW(cpu_c1_core_clk), APMU_CPU_C1_CLK_CTRL, 6, 3, 495 CLK_IS_CRITICAL); 496 497 static const struct clk_parent_data jpg_parents[] = { 498 CCU_PARENT_HW(pll1_d4_614p4), 499 CCU_PARENT_HW(pll1_d6_409p6), 500 CCU_PARENT_HW(pll1_d5_491p52), 501 CCU_PARENT_HW(pll1_d3_819p2), 502 CCU_PARENT_HW(pll1_d2_1228p8), 503 CCU_PARENT_HW(pll2_d4), 504 CCU_PARENT_HW(pll2_d3), 505 }; 506 CCU_MUX_DIV_GATE_FC_DEFINE(jpg_clk, jpg_parents, APMU_JPG_CLK_RES_CTRL, 5, 3, BIT(15), 2, 3, 507 BIT(1), 0); 508 509 static const struct clk_parent_data ccic2phy_parents[] = { 510 CCU_PARENT_HW(pll1_d24_102p4), 511 CCU_PARENT_HW(pll1_d48_51p2_ap), 512 }; 513 CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); 514 515 static const struct clk_parent_data ccic3phy_parents[] = { 516 CCU_PARENT_HW(pll1_d24_102p4), 517 CCU_PARENT_HW(pll1_d48_51p2_ap), 518 }; 519 CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); 520 521 static const struct clk_parent_data csi_parents[] = { 522 CCU_PARENT_HW(pll1_d5_491p52), 523 CCU_PARENT_HW(pll1_d6_409p6), 524 CCU_PARENT_HW(pll1_d4_614p4), 525 CCU_PARENT_HW(pll1_d3_819p2), 526 CCU_PARENT_HW(pll2_d2), 527 CCU_PARENT_HW(pll2_d3), 528 CCU_PARENT_HW(pll2_d4), 529 CCU_PARENT_HW(pll1_d2_1228p8), 530 }; 531 CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), 532 16, 3, BIT(4), 0); 533 534 static const struct clk_parent_data camm_parents[] = { 535 CCU_PARENT_HW(pll1_d8_307p2), 536 CCU_PARENT_HW(pll2_d5), 537 CCU_PARENT_HW(pll1_d6_409p6), 538 CCU_PARENT_NAME(vctcxo_24m), 539 }; 540 CCU_MUX_DIV_GATE_DEFINE(camm0_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 541 BIT(28), 0); 542 CCU_MUX_DIV_GATE_DEFINE(camm1_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 543 BIT(6), 0); 544 CCU_MUX_DIV_GATE_DEFINE(camm2_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 545 BIT(3), 0); 546 547 static const struct clk_parent_data isp_cpp_parents[] = { 548 CCU_PARENT_HW(pll1_d8_307p2), 549 CCU_PARENT_HW(pll1_d6_409p6), 550 }; 551 CCU_MUX_DIV_GATE_DEFINE(isp_cpp_clk, isp_cpp_parents, APMU_ISP_CLK_RES_CTRL, 24, 2, 26, 1, 552 BIT(28), 0); 553 static const struct clk_parent_data isp_bus_parents[] = { 554 CCU_PARENT_HW(pll1_d6_409p6), 555 CCU_PARENT_HW(pll1_d5_491p52), 556 CCU_PARENT_HW(pll1_d8_307p2), 557 CCU_PARENT_HW(pll1_d10_245p76), 558 }; 559 CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), 560 21, 2, BIT(17), 0); 561 static const struct clk_parent_data isp_parents[] = { 562 CCU_PARENT_HW(pll1_d6_409p6), 563 CCU_PARENT_HW(pll1_d5_491p52), 564 CCU_PARENT_HW(pll1_d4_614p4), 565 CCU_PARENT_HW(pll1_d8_307p2), 566 }; 567 CCU_MUX_DIV_GATE_FC_DEFINE(isp_clk, isp_parents, APMU_ISP_CLK_RES_CTRL, 4, 3, BIT(7), 8, 2, 568 BIT(1), 0); 569 570 static const struct clk_parent_data dpumclk_parents[] = { 571 CCU_PARENT_HW(pll1_d6_409p6), 572 CCU_PARENT_HW(pll1_d5_491p52), 573 CCU_PARENT_HW(pll1_d4_614p4), 574 CCU_PARENT_HW(pll1_d8_307p2), 575 }; 576 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_mclk, dpumclk_parents, APMU_LCD_CLK_RES_CTRL2, 577 APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); 578 579 static const struct clk_parent_data dpuesc_parents[] = { 580 CCU_PARENT_HW(pll1_d48_51p2_ap), 581 CCU_PARENT_HW(pll1_d52_47p26), 582 CCU_PARENT_HW(pll1_d96_25p6), 583 CCU_PARENT_HW(pll1_d32_76p8), 584 }; 585 CCU_MUX_GATE_DEFINE(dpu_esc_clk, dpuesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); 586 587 static const struct clk_parent_data dpubit_parents[] = { 588 CCU_PARENT_HW(pll1_d3_819p2), 589 CCU_PARENT_HW(pll2_d2), 590 CCU_PARENT_HW(pll2_d3), 591 CCU_PARENT_HW(pll1_d2_1228p8), 592 CCU_PARENT_HW(pll2_d4), 593 CCU_PARENT_HW(pll2_d5), 594 CCU_PARENT_HW(pll2_d7), 595 CCU_PARENT_HW(pll2_d8), 596 }; 597 CCU_MUX_DIV_GATE_FC_DEFINE(dpu_bit_clk, dpubit_parents, APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(31), 598 20, 3, BIT(16), 0); 599 600 static const struct clk_parent_data dpupx_parents[] = { 601 CCU_PARENT_HW(pll1_d6_409p6), 602 CCU_PARENT_HW(pll1_d5_491p52), 603 CCU_PARENT_HW(pll1_d4_614p4), 604 CCU_PARENT_HW(pll1_d8_307p2), 605 CCU_PARENT_HW(pll2_d7), 606 CCU_PARENT_HW(pll2_d8), 607 }; 608 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_pxclk, dpupx_parents, APMU_LCD_CLK_RES_CTRL2, 609 APMU_LCD_CLK_RES_CTRL1, 17, 4, BIT(30), 21, 3, BIT(16), 0); 610 611 CCU_GATE_DEFINE(dpu_hclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_CLK_RES_CTRL1, 612 BIT(5), 0); 613 614 static const struct clk_parent_data dpu_spi_parents[] = { 615 CCU_PARENT_HW(pll1_d8_307p2), 616 CCU_PARENT_HW(pll1_d6_409p6), 617 CCU_PARENT_HW(pll1_d10_245p76), 618 CCU_PARENT_HW(pll1_d11_223p4), 619 CCU_PARENT_HW(pll1_d13_189), 620 CCU_PARENT_HW(pll1_d23_106p8), 621 CCU_PARENT_HW(pll2_d3), 622 CCU_PARENT_HW(pll2_d5), 623 }; 624 CCU_MUX_DIV_GATE_FC_DEFINE(dpu_spi_clk, dpu_spi_parents, APMU_LCD_SPI_CLK_RES_CTRL, 8, 3, 625 BIT(7), 12, 3, BIT(1), 0); 626 CCU_GATE_DEFINE(dpu_spi_hbus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(3), 0); 627 CCU_GATE_DEFINE(dpu_spi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(5), 0); 628 CCU_GATE_DEFINE(dpu_spi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(6), 0); 629 630 static const struct clk_parent_data v2d_parents[] = { 631 CCU_PARENT_HW(pll1_d5_491p52), 632 CCU_PARENT_HW(pll1_d6_409p6), 633 CCU_PARENT_HW(pll1_d8_307p2), 634 CCU_PARENT_HW(pll1_d4_614p4), 635 }; 636 CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, 637 BIT(8), 0); 638 639 static const struct clk_parent_data ccic_4x_parents[] = { 640 CCU_PARENT_HW(pll1_d5_491p52), 641 CCU_PARENT_HW(pll1_d6_409p6), 642 CCU_PARENT_HW(pll1_d4_614p4), 643 CCU_PARENT_HW(pll1_d3_819p2), 644 CCU_PARENT_HW(pll2_d2), 645 CCU_PARENT_HW(pll2_d3), 646 CCU_PARENT_HW(pll2_d4), 647 CCU_PARENT_HW(pll1_d2_1228p8), 648 }; 649 CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, 650 BIT(15), 23, 2, BIT(4), 0); 651 652 static const struct clk_parent_data ccic1phy_parents[] = { 653 CCU_PARENT_HW(pll1_d24_102p4), 654 CCU_PARENT_HW(pll1_d48_51p2_ap), 655 }; 656 CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); 657 658 CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); 659 static const struct clk_parent_data sdh01_parents[] = { 660 CCU_PARENT_HW(pll1_d6_409p6), 661 CCU_PARENT_HW(pll1_d4_614p4), 662 CCU_PARENT_HW(pll2_d8), 663 CCU_PARENT_HW(pll2_d5), 664 CCU_PARENT_HW(pll1_d11_223p4), 665 CCU_PARENT_HW(pll1_d13_189), 666 CCU_PARENT_HW(pll1_d23_106p8), 667 }; 668 CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 669 BIT(4), 0); 670 CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 671 BIT(4), 0); 672 static const struct clk_parent_data sdh2_parents[] = { 673 CCU_PARENT_HW(pll1_d6_409p6), 674 CCU_PARENT_HW(pll1_d4_614p4), 675 CCU_PARENT_HW(pll2_d8), 676 CCU_PARENT_HW(pll1_d3_819p2), 677 CCU_PARENT_HW(pll1_d11_223p4), 678 CCU_PARENT_HW(pll1_d13_189), 679 CCU_PARENT_HW(pll1_d23_106p8), 680 }; 681 CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 682 BIT(4), 0); 683 684 CCU_GATE_DEFINE(usb_axi_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); 685 CCU_GATE_DEFINE(usb_p1_aclk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(5), 0); 686 CCU_GATE_DEFINE(usb30_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); 687 688 static const struct clk_parent_data qspi_parents[] = { 689 CCU_PARENT_HW(pll1_d6_409p6), 690 CCU_PARENT_HW(pll2_d8), 691 CCU_PARENT_HW(pll1_d8_307p2), 692 CCU_PARENT_HW(pll1_d10_245p76), 693 CCU_PARENT_HW(pll1_d11_223p4), 694 CCU_PARENT_HW(pll1_d23_106p8), 695 CCU_PARENT_HW(pll1_d5_491p52), 696 CCU_PARENT_HW(pll1_d13_189), 697 }; 698 CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, BIT(12), 6, 3, 699 BIT(4), 0); 700 CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); 701 CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(pmua_aclk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); 702 703 static const struct clk_parent_data aes_parents[] = { 704 CCU_PARENT_HW(pll1_d12_204p8), 705 CCU_PARENT_HW(pll1_d24_102p4), 706 }; 707 CCU_MUX_GATE_DEFINE(aes_clk, aes_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); 708 709 static const struct clk_parent_data vpu_parents[] = { 710 CCU_PARENT_HW(pll1_d4_614p4), 711 CCU_PARENT_HW(pll1_d5_491p52), 712 CCU_PARENT_HW(pll1_d3_819p2), 713 CCU_PARENT_HW(pll1_d6_409p6), 714 CCU_PARENT_HW(pll3_d6), 715 CCU_PARENT_HW(pll2_d3), 716 CCU_PARENT_HW(pll2_d4), 717 CCU_PARENT_HW(pll2_d5), 718 }; 719 CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, BIT(21), 10, 3, 720 BIT(3), 0); 721 722 static const struct clk_parent_data gpu_parents[] = { 723 CCU_PARENT_HW(pll1_d4_614p4), 724 CCU_PARENT_HW(pll1_d5_491p52), 725 CCU_PARENT_HW(pll1_d3_819p2), 726 CCU_PARENT_HW(pll1_d6_409p6), 727 CCU_PARENT_HW(pll3_d6), 728 CCU_PARENT_HW(pll2_d3), 729 CCU_PARENT_HW(pll2_d4), 730 CCU_PARENT_HW(pll2_d5), 731 }; 732 CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, BIT(15), 18, 3, 733 BIT(4), 0); 734 735 static const struct clk_parent_data emmc_parents[] = { 736 CCU_PARENT_HW(pll1_d6_409p6), 737 CCU_PARENT_HW(pll1_d4_614p4), 738 CCU_PARENT_HW(pll1_d52_47p26), 739 CCU_PARENT_HW(pll1_d3_819p2), 740 }; 741 CCU_MUX_DIV_GATE_FC_DEFINE(emmc_clk, emmc_parents, APMU_PMUA_EM_CLK_RES_CTRL, 8, 3, BIT(11), 742 6, 2, BIT(4), 0); 743 CCU_DIV_GATE_DEFINE(emmc_x_clk, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMUA_EM_CLK_RES_CTRL, 12, 744 3, BIT(15), 0); 745 746 static const struct clk_parent_data audio_parents[] = { 747 CCU_PARENT_HW(pll1_aud_245p7), 748 CCU_PARENT_HW(pll1_d8_307p2), 749 CCU_PARENT_HW(pll1_d6_409p6), 750 }; 751 CCU_MUX_DIV_GATE_FC_DEFINE(audio_clk, audio_parents, APMU_AUDIO_CLK_RES_CTRL, 4, 3, BIT(15), 752 7, 3, BIT(12), 0); 753 754 static const struct clk_parent_data hdmi_parents[] = { 755 CCU_PARENT_HW(pll1_d6_409p6), 756 CCU_PARENT_HW(pll1_d5_491p52), 757 CCU_PARENT_HW(pll1_d4_614p4), 758 CCU_PARENT_HW(pll1_d8_307p2), 759 }; 760 CCU_MUX_DIV_GATE_FC_DEFINE(hdmi_mclk, hdmi_parents, APMU_HDMI_CLK_RES_CTRL, 1, 4, BIT(29), 5, 761 3, BIT(0), 0); 762 763 CCU_GATE_DEFINE(pcie0_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(2), 0); 764 CCU_GATE_DEFINE(pcie0_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(1), 0); 765 CCU_GATE_DEFINE(pcie0_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(0), 0); 766 767 CCU_GATE_DEFINE(pcie1_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(2), 0); 768 CCU_GATE_DEFINE(pcie1_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(1), 0); 769 CCU_GATE_DEFINE(pcie1_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(0), 0); 770 771 CCU_GATE_DEFINE(pcie2_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(2), 0); 772 CCU_GATE_DEFINE(pcie2_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(1), 0); 773 CCU_GATE_DEFINE(pcie2_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(0), 0); 774 775 CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); 776 CCU_GATE_DEFINE(emac0_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC0_CLK_RES_CTRL, BIT(15), 0); 777 CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); 778 CCU_GATE_DEFINE(emac1_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC1_CLK_RES_CTRL, BIT(15), 0); 779 780 CCU_GATE_DEFINE(emmc_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_PMUA_EM_CLK_RES_CTRL, BIT(3), 0); 781 /* APMU clocks end */ 782 783 static struct clk_hw *k1_ccu_pll_hws[] = { 784 [CLK_PLL1] = &pll1.common.hw, 785 [CLK_PLL2] = &pll2.common.hw, 786 [CLK_PLL3] = &pll3.common.hw, 787 [CLK_PLL1_D2] = &pll1_d2.common.hw, 788 [CLK_PLL1_D3] = &pll1_d3.common.hw, 789 [CLK_PLL1_D4] = &pll1_d4.common.hw, 790 [CLK_PLL1_D5] = &pll1_d5.common.hw, 791 [CLK_PLL1_D6] = &pll1_d6.common.hw, 792 [CLK_PLL1_D7] = &pll1_d7.common.hw, 793 [CLK_PLL1_D8] = &pll1_d8.common.hw, 794 [CLK_PLL1_D11] = &pll1_d11_223p4.common.hw, 795 [CLK_PLL1_D13] = &pll1_d13_189.common.hw, 796 [CLK_PLL1_D23] = &pll1_d23_106p8.common.hw, 797 [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, 798 [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, 799 [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, 800 [CLK_PLL2_D1] = &pll2_d1.common.hw, 801 [CLK_PLL2_D2] = &pll2_d2.common.hw, 802 [CLK_PLL2_D3] = &pll2_d3.common.hw, 803 [CLK_PLL2_D4] = &pll2_d4.common.hw, 804 [CLK_PLL2_D5] = &pll2_d5.common.hw, 805 [CLK_PLL2_D6] = &pll2_d6.common.hw, 806 [CLK_PLL2_D7] = &pll2_d7.common.hw, 807 [CLK_PLL2_D8] = &pll2_d8.common.hw, 808 [CLK_PLL3_D1] = &pll3_d1.common.hw, 809 [CLK_PLL3_D2] = &pll3_d2.common.hw, 810 [CLK_PLL3_D3] = &pll3_d3.common.hw, 811 [CLK_PLL3_D4] = &pll3_d4.common.hw, 812 [CLK_PLL3_D5] = &pll3_d5.common.hw, 813 [CLK_PLL3_D6] = &pll3_d6.common.hw, 814 [CLK_PLL3_D7] = &pll3_d7.common.hw, 815 [CLK_PLL3_D8] = &pll3_d8.common.hw, 816 [CLK_PLL3_80] = &pll3_80.common.hw, 817 [CLK_PLL3_40] = &pll3_40.common.hw, 818 [CLK_PLL3_20] = &pll3_20.common.hw, 819 }; 820 821 static const struct spacemit_ccu_data k1_ccu_pll_data = { 822 .hws = k1_ccu_pll_hws, 823 .num = ARRAY_SIZE(k1_ccu_pll_hws), 824 }; 825 826 static struct clk_hw *k1_ccu_mpmu_hws[] = { 827 [CLK_PLL1_307P2] = &pll1_d8_307p2.common.hw, 828 [CLK_PLL1_76P8] = &pll1_d32_76p8.common.hw, 829 [CLK_PLL1_61P44] = &pll1_d40_61p44.common.hw, 830 [CLK_PLL1_153P6] = &pll1_d16_153p6.common.hw, 831 [CLK_PLL1_102P4] = &pll1_d24_102p4.common.hw, 832 [CLK_PLL1_51P2] = &pll1_d48_51p2.common.hw, 833 [CLK_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, 834 [CLK_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, 835 [CLK_PLL1_25P6] = &pll1_d96_25p6.common.hw, 836 [CLK_PLL1_12P8] = &pll1_d192_12p8.common.hw, 837 [CLK_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, 838 [CLK_PLL1_6P4] = &pll1_d384_6p4.common.hw, 839 [CLK_PLL1_3P2] = &pll1_d768_3p2.common.hw, 840 [CLK_PLL1_1P6] = &pll1_d1536_1p6.common.hw, 841 [CLK_PLL1_0P8] = &pll1_d3072_0p8.common.hw, 842 [CLK_PLL1_409P6] = &pll1_d6_409p6.common.hw, 843 [CLK_PLL1_204P8] = &pll1_d12_204p8.common.hw, 844 [CLK_PLL1_491] = &pll1_d5_491p52.common.hw, 845 [CLK_PLL1_245P76] = &pll1_d10_245p76.common.hw, 846 [CLK_PLL1_614] = &pll1_d4_614p4.common.hw, 847 [CLK_PLL1_47P26] = &pll1_d52_47p26.common.hw, 848 [CLK_PLL1_31P5] = &pll1_d78_31p5.common.hw, 849 [CLK_PLL1_819] = &pll1_d3_819p2.common.hw, 850 [CLK_PLL1_1228] = &pll1_d2_1228p8.common.hw, 851 [CLK_SLOW_UART] = &slow_uart.common.hw, 852 [CLK_SLOW_UART1] = &slow_uart1_14p74.common.hw, 853 [CLK_SLOW_UART2] = &slow_uart2_48.common.hw, 854 [CLK_WDT] = &wdt_clk.common.hw, 855 [CLK_RIPC] = &ripc_clk.common.hw, 856 [CLK_I2S_SYSCLK] = &i2s_sysclk.common.hw, 857 [CLK_I2S_BCLK] = &i2s_bclk.common.hw, 858 [CLK_APB] = &apb_clk.common.hw, 859 [CLK_WDT_BUS] = &wdt_bus_clk.common.hw, 860 }; 861 862 static const struct spacemit_ccu_data k1_ccu_mpmu_data = { 863 .hws = k1_ccu_mpmu_hws, 864 .num = ARRAY_SIZE(k1_ccu_mpmu_hws), 865 }; 866 867 static struct clk_hw *k1_ccu_apbc_hws[] = { 868 [CLK_UART0] = &uart0_clk.common.hw, 869 [CLK_UART2] = &uart2_clk.common.hw, 870 [CLK_UART3] = &uart3_clk.common.hw, 871 [CLK_UART4] = &uart4_clk.common.hw, 872 [CLK_UART5] = &uart5_clk.common.hw, 873 [CLK_UART6] = &uart6_clk.common.hw, 874 [CLK_UART7] = &uart7_clk.common.hw, 875 [CLK_UART8] = &uart8_clk.common.hw, 876 [CLK_UART9] = &uart9_clk.common.hw, 877 [CLK_GPIO] = &gpio_clk.common.hw, 878 [CLK_PWM0] = &pwm0_clk.common.hw, 879 [CLK_PWM1] = &pwm1_clk.common.hw, 880 [CLK_PWM2] = &pwm2_clk.common.hw, 881 [CLK_PWM3] = &pwm3_clk.common.hw, 882 [CLK_PWM4] = &pwm4_clk.common.hw, 883 [CLK_PWM5] = &pwm5_clk.common.hw, 884 [CLK_PWM6] = &pwm6_clk.common.hw, 885 [CLK_PWM7] = &pwm7_clk.common.hw, 886 [CLK_PWM8] = &pwm8_clk.common.hw, 887 [CLK_PWM9] = &pwm9_clk.common.hw, 888 [CLK_PWM10] = &pwm10_clk.common.hw, 889 [CLK_PWM11] = &pwm11_clk.common.hw, 890 [CLK_PWM12] = &pwm12_clk.common.hw, 891 [CLK_PWM13] = &pwm13_clk.common.hw, 892 [CLK_PWM14] = &pwm14_clk.common.hw, 893 [CLK_PWM15] = &pwm15_clk.common.hw, 894 [CLK_PWM16] = &pwm16_clk.common.hw, 895 [CLK_PWM17] = &pwm17_clk.common.hw, 896 [CLK_PWM18] = &pwm18_clk.common.hw, 897 [CLK_PWM19] = &pwm19_clk.common.hw, 898 [CLK_SSP3] = &ssp3_clk.common.hw, 899 [CLK_RTC] = &rtc_clk.common.hw, 900 [CLK_TWSI0] = &twsi0_clk.common.hw, 901 [CLK_TWSI1] = &twsi1_clk.common.hw, 902 [CLK_TWSI2] = &twsi2_clk.common.hw, 903 [CLK_TWSI4] = &twsi4_clk.common.hw, 904 [CLK_TWSI5] = &twsi5_clk.common.hw, 905 [CLK_TWSI6] = &twsi6_clk.common.hw, 906 [CLK_TWSI7] = &twsi7_clk.common.hw, 907 [CLK_TWSI8] = &twsi8_clk.common.hw, 908 [CLK_TIMERS1] = &timers1_clk.common.hw, 909 [CLK_TIMERS2] = &timers2_clk.common.hw, 910 [CLK_AIB] = &aib_clk.common.hw, 911 [CLK_ONEWIRE] = &onewire_clk.common.hw, 912 [CLK_SSPA0] = &sspa0_clk.common.hw, 913 [CLK_SSPA1] = &sspa1_clk.common.hw, 914 [CLK_DRO] = &dro_clk.common.hw, 915 [CLK_IR] = &ir_clk.common.hw, 916 [CLK_TSEN] = &tsen_clk.common.hw, 917 [CLK_IPC_AP2AUD] = &ipc_ap2aud_clk.common.hw, 918 [CLK_CAN0] = &can0_clk.common.hw, 919 [CLK_CAN0_BUS] = &can0_bus_clk.common.hw, 920 [CLK_UART0_BUS] = &uart0_bus_clk.common.hw, 921 [CLK_UART2_BUS] = &uart2_bus_clk.common.hw, 922 [CLK_UART3_BUS] = &uart3_bus_clk.common.hw, 923 [CLK_UART4_BUS] = &uart4_bus_clk.common.hw, 924 [CLK_UART5_BUS] = &uart5_bus_clk.common.hw, 925 [CLK_UART6_BUS] = &uart6_bus_clk.common.hw, 926 [CLK_UART7_BUS] = &uart7_bus_clk.common.hw, 927 [CLK_UART8_BUS] = &uart8_bus_clk.common.hw, 928 [CLK_UART9_BUS] = &uart9_bus_clk.common.hw, 929 [CLK_GPIO_BUS] = &gpio_bus_clk.common.hw, 930 [CLK_PWM0_BUS] = &pwm0_bus_clk.common.hw, 931 [CLK_PWM1_BUS] = &pwm1_bus_clk.common.hw, 932 [CLK_PWM2_BUS] = &pwm2_bus_clk.common.hw, 933 [CLK_PWM3_BUS] = &pwm3_bus_clk.common.hw, 934 [CLK_PWM4_BUS] = &pwm4_bus_clk.common.hw, 935 [CLK_PWM5_BUS] = &pwm5_bus_clk.common.hw, 936 [CLK_PWM6_BUS] = &pwm6_bus_clk.common.hw, 937 [CLK_PWM7_BUS] = &pwm7_bus_clk.common.hw, 938 [CLK_PWM8_BUS] = &pwm8_bus_clk.common.hw, 939 [CLK_PWM9_BUS] = &pwm9_bus_clk.common.hw, 940 [CLK_PWM10_BUS] = &pwm10_bus_clk.common.hw, 941 [CLK_PWM11_BUS] = &pwm11_bus_clk.common.hw, 942 [CLK_PWM12_BUS] = &pwm12_bus_clk.common.hw, 943 [CLK_PWM13_BUS] = &pwm13_bus_clk.common.hw, 944 [CLK_PWM14_BUS] = &pwm14_bus_clk.common.hw, 945 [CLK_PWM15_BUS] = &pwm15_bus_clk.common.hw, 946 [CLK_PWM16_BUS] = &pwm16_bus_clk.common.hw, 947 [CLK_PWM17_BUS] = &pwm17_bus_clk.common.hw, 948 [CLK_PWM18_BUS] = &pwm18_bus_clk.common.hw, 949 [CLK_PWM19_BUS] = &pwm19_bus_clk.common.hw, 950 [CLK_SSP3_BUS] = &ssp3_bus_clk.common.hw, 951 [CLK_RTC_BUS] = &rtc_bus_clk.common.hw, 952 [CLK_TWSI0_BUS] = &twsi0_bus_clk.common.hw, 953 [CLK_TWSI1_BUS] = &twsi1_bus_clk.common.hw, 954 [CLK_TWSI2_BUS] = &twsi2_bus_clk.common.hw, 955 [CLK_TWSI4_BUS] = &twsi4_bus_clk.common.hw, 956 [CLK_TWSI5_BUS] = &twsi5_bus_clk.common.hw, 957 [CLK_TWSI6_BUS] = &twsi6_bus_clk.common.hw, 958 [CLK_TWSI7_BUS] = &twsi7_bus_clk.common.hw, 959 [CLK_TWSI8_BUS] = &twsi8_bus_clk.common.hw, 960 [CLK_TIMERS1_BUS] = &timers1_bus_clk.common.hw, 961 [CLK_TIMERS2_BUS] = &timers2_bus_clk.common.hw, 962 [CLK_AIB_BUS] = &aib_bus_clk.common.hw, 963 [CLK_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, 964 [CLK_SSPA0_BUS] = &sspa0_bus_clk.common.hw, 965 [CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw, 966 [CLK_TSEN_BUS] = &tsen_bus_clk.common.hw, 967 [CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw, 968 }; 969 970 static const struct spacemit_ccu_data k1_ccu_apbc_data = { 971 .hws = k1_ccu_apbc_hws, 972 .num = ARRAY_SIZE(k1_ccu_apbc_hws), 973 }; 974 975 static struct clk_hw *k1_ccu_apmu_hws[] = { 976 [CLK_CCI550] = &cci550_clk.common.hw, 977 [CLK_CPU_C0_HI] = &cpu_c0_hi_clk.common.hw, 978 [CLK_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, 979 [CLK_CPU_C0_ACE] = &cpu_c0_ace_clk.common.hw, 980 [CLK_CPU_C0_TCM] = &cpu_c0_tcm_clk.common.hw, 981 [CLK_CPU_C1_HI] = &cpu_c1_hi_clk.common.hw, 982 [CLK_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, 983 [CLK_CPU_C1_ACE] = &cpu_c1_ace_clk.common.hw, 984 [CLK_CCIC_4X] = &ccic_4x_clk.common.hw, 985 [CLK_CCIC1PHY] = &ccic1phy_clk.common.hw, 986 [CLK_SDH_AXI] = &sdh_axi_aclk.common.hw, 987 [CLK_SDH0] = &sdh0_clk.common.hw, 988 [CLK_SDH1] = &sdh1_clk.common.hw, 989 [CLK_SDH2] = &sdh2_clk.common.hw, 990 [CLK_USB_P1] = &usb_p1_aclk.common.hw, 991 [CLK_USB_AXI] = &usb_axi_clk.common.hw, 992 [CLK_USB30] = &usb30_clk.common.hw, 993 [CLK_QSPI] = &qspi_clk.common.hw, 994 [CLK_QSPI_BUS] = &qspi_bus_clk.common.hw, 995 [CLK_DMA] = &dma_clk.common.hw, 996 [CLK_AES] = &aes_clk.common.hw, 997 [CLK_VPU] = &vpu_clk.common.hw, 998 [CLK_GPU] = &gpu_clk.common.hw, 999 [CLK_EMMC] = &emmc_clk.common.hw, 1000 [CLK_EMMC_X] = &emmc_x_clk.common.hw, 1001 [CLK_AUDIO] = &audio_clk.common.hw, 1002 [CLK_HDMI] = &hdmi_mclk.common.hw, 1003 [CLK_PMUA_ACLK] = &pmua_aclk.common.hw, 1004 [CLK_PCIE0_MASTER] = &pcie0_master_clk.common.hw, 1005 [CLK_PCIE0_SLAVE] = &pcie0_slave_clk.common.hw, 1006 [CLK_PCIE0_DBI] = &pcie0_dbi_clk.common.hw, 1007 [CLK_PCIE1_MASTER] = &pcie1_master_clk.common.hw, 1008 [CLK_PCIE1_SLAVE] = &pcie1_slave_clk.common.hw, 1009 [CLK_PCIE1_DBI] = &pcie1_dbi_clk.common.hw, 1010 [CLK_PCIE2_MASTER] = &pcie2_master_clk.common.hw, 1011 [CLK_PCIE2_SLAVE] = &pcie2_slave_clk.common.hw, 1012 [CLK_PCIE2_DBI] = &pcie2_dbi_clk.common.hw, 1013 [CLK_EMAC0_BUS] = &emac0_bus_clk.common.hw, 1014 [CLK_EMAC0_PTP] = &emac0_ptp_clk.common.hw, 1015 [CLK_EMAC1_BUS] = &emac1_bus_clk.common.hw, 1016 [CLK_EMAC1_PTP] = &emac1_ptp_clk.common.hw, 1017 [CLK_JPG] = &jpg_clk.common.hw, 1018 [CLK_CCIC2PHY] = &ccic2phy_clk.common.hw, 1019 [CLK_CCIC3PHY] = &ccic3phy_clk.common.hw, 1020 [CLK_CSI] = &csi_clk.common.hw, 1021 [CLK_CAMM0] = &camm0_clk.common.hw, 1022 [CLK_CAMM1] = &camm1_clk.common.hw, 1023 [CLK_CAMM2] = &camm2_clk.common.hw, 1024 [CLK_ISP_CPP] = &isp_cpp_clk.common.hw, 1025 [CLK_ISP_BUS] = &isp_bus_clk.common.hw, 1026 [CLK_ISP] = &isp_clk.common.hw, 1027 [CLK_DPU_MCLK] = &dpu_mclk.common.hw, 1028 [CLK_DPU_ESC] = &dpu_esc_clk.common.hw, 1029 [CLK_DPU_BIT] = &dpu_bit_clk.common.hw, 1030 [CLK_DPU_PXCLK] = &dpu_pxclk.common.hw, 1031 [CLK_DPU_HCLK] = &dpu_hclk.common.hw, 1032 [CLK_DPU_SPI] = &dpu_spi_clk.common.hw, 1033 [CLK_DPU_SPI_HBUS] = &dpu_spi_hbus_clk.common.hw, 1034 [CLK_DPU_SPIBUS] = &dpu_spi_bus_clk.common.hw, 1035 [CLK_DPU_SPI_ACLK] = &dpu_spi_aclk.common.hw, 1036 [CLK_V2D] = &v2d_clk.common.hw, 1037 [CLK_EMMC_BUS] = &emmc_bus_clk.common.hw, 1038 }; 1039 1040 static const struct spacemit_ccu_data k1_ccu_apmu_data = { 1041 .hws = k1_ccu_apmu_hws, 1042 .num = ARRAY_SIZE(k1_ccu_apmu_hws), 1043 }; 1044 1045 static int spacemit_ccu_register(struct device *dev, 1046 struct regmap *regmap, 1047 struct regmap *lock_regmap, 1048 const struct spacemit_ccu_data *data) 1049 { 1050 struct clk_hw_onecell_data *clk_data; 1051 int i, ret; 1052 1053 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), 1054 GFP_KERNEL); 1055 if (!clk_data) 1056 return -ENOMEM; 1057 1058 for (i = 0; i < data->num; i++) { 1059 struct clk_hw *hw = data->hws[i]; 1060 struct ccu_common *common; 1061 const char *name; 1062 1063 if (!hw) { 1064 clk_data->hws[i] = ERR_PTR(-ENOENT); 1065 continue; 1066 } 1067 1068 name = hw->init->name; 1069 1070 common = hw_to_ccu_common(hw); 1071 common->regmap = regmap; 1072 common->lock_regmap = lock_regmap; 1073 1074 ret = devm_clk_hw_register(dev, hw); 1075 if (ret) { 1076 dev_err(dev, "Cannot register clock %d - %s\n", 1077 i, name); 1078 return ret; 1079 } 1080 1081 clk_data->hws[i] = hw; 1082 } 1083 1084 clk_data->num = data->num; 1085 1086 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); 1087 if (ret) 1088 dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); 1089 1090 return ret; 1091 } 1092 1093 static int k1_ccu_probe(struct platform_device *pdev) 1094 { 1095 struct regmap *base_regmap, *lock_regmap = NULL; 1096 struct device *dev = &pdev->dev; 1097 int ret; 1098 1099 base_regmap = device_node_to_regmap(dev->of_node); 1100 if (IS_ERR(base_regmap)) 1101 return dev_err_probe(dev, PTR_ERR(base_regmap), 1102 "failed to get regmap\n"); 1103 1104 /* 1105 * The lock status of PLLs locate in MPMU region, while PLLs themselves 1106 * are in APBS region. Reference to MPMU syscon is required to check PLL 1107 * status. 1108 */ 1109 if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) { 1110 struct device_node *mpmu = of_parse_phandle(dev->of_node, 1111 "spacemit,mpmu", 0); 1112 if (!mpmu) 1113 return dev_err_probe(dev, -ENODEV, 1114 "Cannot parse MPMU region\n"); 1115 1116 lock_regmap = device_node_to_regmap(mpmu); 1117 of_node_put(mpmu); 1118 1119 if (IS_ERR(lock_regmap)) 1120 return dev_err_probe(dev, PTR_ERR(lock_regmap), 1121 "failed to get lock regmap\n"); 1122 } 1123 1124 ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, 1125 of_device_get_match_data(dev)); 1126 if (ret) 1127 return dev_err_probe(dev, ret, "failed to register clocks\n"); 1128 1129 return 0; 1130 } 1131 1132 static const struct of_device_id of_k1_ccu_match[] = { 1133 { 1134 .compatible = "spacemit,k1-pll", 1135 .data = &k1_ccu_pll_data, 1136 }, 1137 { 1138 .compatible = "spacemit,k1-syscon-mpmu", 1139 .data = &k1_ccu_mpmu_data, 1140 }, 1141 { 1142 .compatible = "spacemit,k1-syscon-apbc", 1143 .data = &k1_ccu_apbc_data, 1144 }, 1145 { 1146 .compatible = "spacemit,k1-syscon-apmu", 1147 .data = &k1_ccu_apmu_data, 1148 }, 1149 { } 1150 }; 1151 MODULE_DEVICE_TABLE(of, of_k1_ccu_match); 1152 1153 static struct platform_driver k1_ccu_driver = { 1154 .driver = { 1155 .name = "spacemit,k1-ccu", 1156 .of_match_table = of_k1_ccu_match, 1157 }, 1158 .probe = k1_ccu_probe, 1159 }; 1160 module_platform_driver(k1_ccu_driver); 1161 1162 MODULE_DESCRIPTION("SpacemiT K1 CCU driver"); 1163 MODULE_AUTHOR("Haylen Chu <heylenay@4d2.org>"); 1164 MODULE_LICENSE("GPL"); 1165