1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 SpacemiT Technology Co. Ltd 4 * Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org> 5 */ 6 7 #include <linux/array_size.h> 8 #include <linux/clk-provider.h> 9 #include <linux/minmax.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <soc/spacemit/k1-syscon.h> 13 14 #include "ccu_common.h" 15 #include "ccu_pll.h" 16 #include "ccu_mix.h" 17 #include "ccu_ddn.h" 18 19 #include <dt-bindings/clock/spacemit,k1-syscon.h> 20 21 /* APBS clocks start, APBS region contains and only contains all PLL clocks */ 22 23 /* 24 * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for 25 * peripherals. 26 */ 27 static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { 28 CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), 29 }; 30 31 static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { 32 CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), 33 }; 34 35 static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { 36 CCU_PLL_RATE(1600000000UL, 0x0050cd61, 0x43eaaaab), 37 CCU_PLL_RATE(1800000000UL, 0x0050cd61, 0x4b000000), 38 CCU_PLL_RATE(2000000000UL, 0x0050dd62, 0x2aeaaaab), 39 CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), 40 CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), 41 CCU_PLL_RATE(3200000000UL, 0x0050dd67, 0x43eaaaab), 42 }; 43 44 CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK, 45 CLK_SET_RATE_GATE); 46 CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK, 47 CLK_SET_RATE_GATE); 48 CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK, 49 CLK_SET_RATE_GATE); 50 51 CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); 52 CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); 53 CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); 54 CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); 55 CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); 56 CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); 57 CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, 58 CLK_IS_CRITICAL); 59 CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1); 60 CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1); 61 CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1); 62 CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(0), 64, 1); 63 CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(10), 10, 1); 64 CCU_FACTOR_GATE_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(11), 100, 1); 65 66 CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); 67 CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); 68 CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); 69 CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); 70 CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); 71 CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); 72 CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); 73 CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); 74 75 CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); 76 CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); 77 CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); 78 CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); 79 CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); 80 CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); 81 CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); 82 CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); 83 84 CCU_FACTOR_DEFINE(pll3_20, CCU_PARENT_HW(pll3_d8), 20, 1); 85 CCU_FACTOR_DEFINE(pll3_40, CCU_PARENT_HW(pll3_d8), 10, 1); 86 CCU_FACTOR_DEFINE(pll3_80, CCU_PARENT_HW(pll3_d8), 5, 1); 87 88 /* APBS clocks end */ 89 90 /* MPMU clocks start */ 91 CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); 92 93 CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); 94 95 CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); 96 97 CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); 98 CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); 99 CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); 100 CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); 101 CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); 102 CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); 103 CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); 104 CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); 105 CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); 106 107 CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); 108 CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); 109 CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); 110 111 CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); 112 CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); 113 114 CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); 115 CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); 116 117 CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); 118 CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); 119 CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); 120 121 CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); 122 123 CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); 124 125 CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); 126 CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0); 127 CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0); 128 129 CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); 130 131 CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1); 132 133 static const struct clk_parent_data i2s_153p6_base_parents[] = { 134 CCU_PARENT_HW(i2s_153p6), 135 CCU_PARENT_HW(pll1_d8_307p2), 136 }; 137 CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0); 138 139 static const struct clk_parent_data i2s_sysclk_src_parents[] = { 140 CCU_PARENT_HW(pll1_d96_25p6), 141 CCU_PARENT_HW(i2s_153p6_base) 142 }; 143 CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR, 30, 1, BIT(31), 0); 144 145 CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR, 0, 15, 15, 12, 1, 0); 146 147 CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1); 148 /* 149 * Divider of i2s_bclk always implies a 1/2 factor, which is 150 * described by i2s_bclk_factor. 151 */ 152 CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR, 27, 2, BIT(29), 0); 153 154 static const struct clk_parent_data apb_parents[] = { 155 CCU_PARENT_HW(pll1_d96_25p6), 156 CCU_PARENT_HW(pll1_d48_51p2), 157 CCU_PARENT_HW(pll1_d96_25p6), 158 CCU_PARENT_HW(pll1_d24_102p4), 159 }; 160 CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); 161 162 CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); 163 164 CCU_GATE_DEFINE(ripc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, 0x1, 0); 165 /* MPMU clocks end */ 166 167 /* APBC clocks start */ 168 static const struct clk_parent_data uart_clk_parents[] = { 169 CCU_PARENT_HW(pll1_m3d128_57p6), 170 CCU_PARENT_HW(slow_uart1_14p74), 171 CCU_PARENT_HW(slow_uart2_48), 172 }; 173 CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART1_CLK_RST, 4, 3, BIT(1), 0); 174 CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); 175 CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); 176 CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); 177 CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); 178 CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); 179 CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); 180 CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); 181 CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); 182 183 CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); 184 185 static const struct clk_parent_data pwm_parents[] = { 186 CCU_PARENT_HW(pll1_d192_12p8), 187 CCU_PARENT_NAME(osc), 188 }; 189 CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); 190 CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); 191 CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); 192 CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); 193 CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); 194 CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); 195 CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); 196 CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); 197 CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); 198 CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); 199 CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); 200 CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); 201 CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); 202 CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); 203 CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); 204 CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); 205 CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); 206 CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); 207 CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); 208 CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); 209 210 static const struct clk_parent_data ssp_parents[] = { 211 CCU_PARENT_HW(pll1_d384_6p4), 212 CCU_PARENT_HW(pll1_d192_12p8), 213 CCU_PARENT_HW(pll1_d96_25p6), 214 CCU_PARENT_HW(pll1_d48_51p2), 215 CCU_PARENT_HW(pll1_d768_3p2), 216 CCU_PARENT_HW(pll1_d1536_1p6), 217 CCU_PARENT_HW(pll1_d3072_0p8), 218 }; 219 CCU_MUX_GATE_DEFINE(ssp3_clk, ssp_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); 220 221 CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc), APBC_RTC_CLK_RST, 222 BIT(7) | BIT(1), 0); 223 224 static const struct clk_parent_data twsi_parents[] = { 225 CCU_PARENT_HW(pll1_d78_31p5), 226 CCU_PARENT_HW(pll1_d48_51p2), 227 CCU_PARENT_HW(pll1_d40_61p44), 228 }; 229 CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); 230 CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); 231 CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); 232 CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); 233 CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); 234 CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); 235 CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0); 236 /* 237 * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero. 238 * Combine functional and bus bits together as a gate to avoid sharing the 239 * write-only register between different clock hardwares. 240 */ 241 CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0); 242 243 static const struct clk_parent_data timer_parents[] = { 244 CCU_PARENT_HW(pll1_d192_12p8), 245 CCU_PARENT_NAME(osc), 246 CCU_PARENT_HW(pll1_d384_6p4), 247 CCU_PARENT_NAME(vctcxo_3m), 248 CCU_PARENT_NAME(vctcxo_1m), 249 }; 250 CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); 251 CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); 252 253 CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); 254 255 CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); 256 257 /* 258 * When i2s_bclk is selected as the parent clock of sspa, 259 * the hardware requires bit3 to be set 260 */ 261 CCU_GATE_DEFINE(sspa0_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA0_CLK_RST, BIT(3), 0); 262 CCU_GATE_DEFINE(sspa1_i2s_bclk, CCU_PARENT_HW(i2s_bclk), APBC_SSPA1_CLK_RST, BIT(3), 0); 263 264 static const struct clk_parent_data sspa0_parents[] = { 265 CCU_PARENT_HW(pll1_d384_6p4), 266 CCU_PARENT_HW(pll1_d192_12p8), 267 CCU_PARENT_HW(pll1_d96_25p6), 268 CCU_PARENT_HW(pll1_d48_51p2), 269 CCU_PARENT_HW(pll1_d768_3p2), 270 CCU_PARENT_HW(pll1_d1536_1p6), 271 CCU_PARENT_HW(pll1_d3072_0p8), 272 CCU_PARENT_HW(sspa0_i2s_bclk), 273 }; 274 CCU_MUX_GATE_DEFINE(sspa0_clk, sspa0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); 275 276 static const struct clk_parent_data sspa1_parents[] = { 277 CCU_PARENT_HW(pll1_d384_6p4), 278 CCU_PARENT_HW(pll1_d192_12p8), 279 CCU_PARENT_HW(pll1_d96_25p6), 280 CCU_PARENT_HW(pll1_d48_51p2), 281 CCU_PARENT_HW(pll1_d768_3p2), 282 CCU_PARENT_HW(pll1_d1536_1p6), 283 CCU_PARENT_HW(pll1_d3072_0p8), 284 CCU_PARENT_HW(sspa1_i2s_bclk), 285 }; 286 CCU_MUX_GATE_DEFINE(sspa1_clk, sspa1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); 287 288 CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); 289 CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0); 290 CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); 291 CCU_GATE_DEFINE(ipc_ap2aud_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); 292 293 static const struct clk_parent_data can_parents[] = { 294 CCU_PARENT_HW(pll3_20), 295 CCU_PARENT_HW(pll3_40), 296 CCU_PARENT_HW(pll3_80), 297 }; 298 CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); 299 CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_CAN0_CLK_RST, BIT(0), 0); 300 301 CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART1_CLK_RST, BIT(0), 0); 302 CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); 303 CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); 304 CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); 305 CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); 306 CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); 307 CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); 308 CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); 309 CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); 310 311 CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); 312 313 CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); 314 CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); 315 CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); 316 CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); 317 CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); 318 CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); 319 CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); 320 CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); 321 CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); 322 CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); 323 CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); 324 CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); 325 CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); 326 CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); 327 CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); 328 CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); 329 CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); 330 CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); 331 CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); 332 CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); 333 334 CCU_GATE_DEFINE(ssp3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); 335 336 CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); 337 338 CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); 339 CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); 340 CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); 341 CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); 342 CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); 343 CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); 344 CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0); 345 /* Placeholder to workaround quirk of the register */ 346 CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1); 347 348 CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); 349 CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); 350 351 CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); 352 353 CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); 354 355 CCU_GATE_DEFINE(sspa0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); 356 CCU_GATE_DEFINE(sspa1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); 357 358 CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); 359 360 CCU_GATE_DEFINE(ipc_ap2aud_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); 361 /* APBC clocks end */ 362 363 /* APMU clocks start */ 364 static const struct clk_parent_data pmua_aclk_parents[] = { 365 CCU_PARENT_HW(pll1_d10_245p76), 366 CCU_PARENT_HW(pll1_d8_307p2), 367 }; 368 CCU_MUX_DIV_FC_DEFINE(pmua_aclk, pmua_aclk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); 369 370 static const struct clk_parent_data cci550_clk_parents[] = { 371 CCU_PARENT_HW(pll1_d5_491p52), 372 CCU_PARENT_HW(pll1_d4_614p4), 373 CCU_PARENT_HW(pll1_d3_819p2), 374 CCU_PARENT_HW(pll2_d3), 375 }; 376 CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 3, BIT(12), 0, 2, 377 CLK_IS_CRITICAL); 378 379 static const struct clk_parent_data cpu_c0_hi_clk_parents[] = { 380 CCU_PARENT_HW(pll3_d2), 381 CCU_PARENT_HW(pll3_d1), 382 }; 383 CCU_MUX_DEFINE(cpu_c0_hi_clk, cpu_c0_hi_clk_parents, APMU_CPU_C0_CLK_CTRL, 13, 1, 0); 384 static const struct clk_parent_data cpu_c0_clk_parents[] = { 385 CCU_PARENT_HW(pll1_d4_614p4), 386 CCU_PARENT_HW(pll1_d3_819p2), 387 CCU_PARENT_HW(pll1_d6_409p6), 388 CCU_PARENT_HW(pll1_d5_491p52), 389 CCU_PARENT_HW(pll1_d2_1228p8), 390 CCU_PARENT_HW(pll3_d3), 391 CCU_PARENT_HW(pll2_d3), 392 CCU_PARENT_HW(cpu_c0_hi_clk), 393 }; 394 CCU_MUX_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, BIT(12), 0, 3, 395 CLK_IS_CRITICAL); 396 CCU_DIV_DEFINE(cpu_c0_ace_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 6, 3, 397 CLK_IS_CRITICAL); 398 CCU_DIV_DEFINE(cpu_c0_tcm_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 9, 3, 399 CLK_IS_CRITICAL); 400 401 static const struct clk_parent_data cpu_c1_hi_clk_parents[] = { 402 CCU_PARENT_HW(pll3_d2), 403 CCU_PARENT_HW(pll3_d1), 404 }; 405 CCU_MUX_DEFINE(cpu_c1_hi_clk, cpu_c1_hi_clk_parents, APMU_CPU_C1_CLK_CTRL, 13, 1, 0); 406 static const struct clk_parent_data cpu_c1_clk_parents[] = { 407 CCU_PARENT_HW(pll1_d4_614p4), 408 CCU_PARENT_HW(pll1_d3_819p2), 409 CCU_PARENT_HW(pll1_d6_409p6), 410 CCU_PARENT_HW(pll1_d5_491p52), 411 CCU_PARENT_HW(pll1_d2_1228p8), 412 CCU_PARENT_HW(pll3_d3), 413 CCU_PARENT_HW(pll2_d3), 414 CCU_PARENT_HW(cpu_c1_hi_clk), 415 }; 416 CCU_MUX_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, BIT(12), 0, 3, 417 CLK_IS_CRITICAL); 418 CCU_DIV_DEFINE(cpu_c1_ace_clk, CCU_PARENT_HW(cpu_c1_core_clk), APMU_CPU_C1_CLK_CTRL, 6, 3, 419 CLK_IS_CRITICAL); 420 421 static const struct clk_parent_data jpg_parents[] = { 422 CCU_PARENT_HW(pll1_d4_614p4), 423 CCU_PARENT_HW(pll1_d6_409p6), 424 CCU_PARENT_HW(pll1_d5_491p52), 425 CCU_PARENT_HW(pll1_d3_819p2), 426 CCU_PARENT_HW(pll1_d2_1228p8), 427 CCU_PARENT_HW(pll2_d4), 428 CCU_PARENT_HW(pll2_d3), 429 }; 430 CCU_MUX_DIV_GATE_FC_DEFINE(jpg_clk, jpg_parents, APMU_JPG_CLK_RES_CTRL, 5, 3, BIT(15), 2, 3, 431 BIT(1), 0); 432 433 static const struct clk_parent_data ccic2phy_parents[] = { 434 CCU_PARENT_HW(pll1_d24_102p4), 435 CCU_PARENT_HW(pll1_d48_51p2_ap), 436 }; 437 CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); 438 439 static const struct clk_parent_data ccic3phy_parents[] = { 440 CCU_PARENT_HW(pll1_d24_102p4), 441 CCU_PARENT_HW(pll1_d48_51p2_ap), 442 }; 443 CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); 444 445 static const struct clk_parent_data csi_parents[] = { 446 CCU_PARENT_HW(pll1_d5_491p52), 447 CCU_PARENT_HW(pll1_d6_409p6), 448 CCU_PARENT_HW(pll1_d4_614p4), 449 CCU_PARENT_HW(pll1_d3_819p2), 450 CCU_PARENT_HW(pll2_d2), 451 CCU_PARENT_HW(pll2_d3), 452 CCU_PARENT_HW(pll2_d4), 453 CCU_PARENT_HW(pll1_d2_1228p8), 454 }; 455 CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), 456 16, 3, BIT(4), 0); 457 458 static const struct clk_parent_data camm_parents[] = { 459 CCU_PARENT_HW(pll1_d8_307p2), 460 CCU_PARENT_HW(pll2_d5), 461 CCU_PARENT_HW(pll1_d6_409p6), 462 CCU_PARENT_NAME(vctcxo_24m), 463 }; 464 CCU_MUX_DIV_GATE_DEFINE(camm0_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 465 BIT(28), 0); 466 CCU_MUX_DIV_GATE_DEFINE(camm1_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 467 BIT(6), 0); 468 CCU_MUX_DIV_GATE_DEFINE(camm2_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 469 BIT(3), 0); 470 471 static const struct clk_parent_data isp_cpp_parents[] = { 472 CCU_PARENT_HW(pll1_d8_307p2), 473 CCU_PARENT_HW(pll1_d6_409p6), 474 }; 475 CCU_MUX_DIV_GATE_DEFINE(isp_cpp_clk, isp_cpp_parents, APMU_ISP_CLK_RES_CTRL, 24, 2, 26, 1, 476 BIT(28), 0); 477 static const struct clk_parent_data isp_bus_parents[] = { 478 CCU_PARENT_HW(pll1_d6_409p6), 479 CCU_PARENT_HW(pll1_d5_491p52), 480 CCU_PARENT_HW(pll1_d8_307p2), 481 CCU_PARENT_HW(pll1_d10_245p76), 482 }; 483 CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), 484 21, 2, BIT(17), 0); 485 static const struct clk_parent_data isp_parents[] = { 486 CCU_PARENT_HW(pll1_d6_409p6), 487 CCU_PARENT_HW(pll1_d5_491p52), 488 CCU_PARENT_HW(pll1_d4_614p4), 489 CCU_PARENT_HW(pll1_d8_307p2), 490 }; 491 CCU_MUX_DIV_GATE_FC_DEFINE(isp_clk, isp_parents, APMU_ISP_CLK_RES_CTRL, 4, 3, BIT(7), 8, 2, 492 BIT(1), 0); 493 494 static const struct clk_parent_data dpumclk_parents[] = { 495 CCU_PARENT_HW(pll1_d6_409p6), 496 CCU_PARENT_HW(pll1_d5_491p52), 497 CCU_PARENT_HW(pll1_d4_614p4), 498 CCU_PARENT_HW(pll1_d8_307p2), 499 }; 500 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_mclk, dpumclk_parents, APMU_LCD_CLK_RES_CTRL2, 501 APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); 502 503 static const struct clk_parent_data dpuesc_parents[] = { 504 CCU_PARENT_HW(pll1_d48_51p2_ap), 505 CCU_PARENT_HW(pll1_d52_47p26), 506 CCU_PARENT_HW(pll1_d96_25p6), 507 CCU_PARENT_HW(pll1_d32_76p8), 508 }; 509 CCU_MUX_GATE_DEFINE(dpu_esc_clk, dpuesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); 510 511 static const struct clk_parent_data dpubit_parents[] = { 512 CCU_PARENT_HW(pll1_d3_819p2), 513 CCU_PARENT_HW(pll2_d2), 514 CCU_PARENT_HW(pll2_d3), 515 CCU_PARENT_HW(pll1_d2_1228p8), 516 CCU_PARENT_HW(pll2_d4), 517 CCU_PARENT_HW(pll2_d5), 518 CCU_PARENT_HW(pll2_d7), 519 CCU_PARENT_HW(pll2_d8), 520 }; 521 CCU_MUX_DIV_GATE_FC_DEFINE(dpu_bit_clk, dpubit_parents, APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(31), 522 20, 3, BIT(16), 0); 523 524 static const struct clk_parent_data dpupx_parents[] = { 525 CCU_PARENT_HW(pll1_d6_409p6), 526 CCU_PARENT_HW(pll1_d5_491p52), 527 CCU_PARENT_HW(pll1_d4_614p4), 528 CCU_PARENT_HW(pll1_d8_307p2), 529 CCU_PARENT_HW(pll2_d7), 530 CCU_PARENT_HW(pll2_d8), 531 }; 532 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_pxclk, dpupx_parents, APMU_LCD_CLK_RES_CTRL2, 533 APMU_LCD_CLK_RES_CTRL1, 17, 4, BIT(30), 21, 3, BIT(16), 0); 534 535 CCU_GATE_DEFINE(dpu_hclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_CLK_RES_CTRL1, 536 BIT(5), 0); 537 538 static const struct clk_parent_data dpu_spi_parents[] = { 539 CCU_PARENT_HW(pll1_d8_307p2), 540 CCU_PARENT_HW(pll1_d6_409p6), 541 CCU_PARENT_HW(pll1_d10_245p76), 542 CCU_PARENT_HW(pll1_d11_223p4), 543 CCU_PARENT_HW(pll1_d13_189), 544 CCU_PARENT_HW(pll1_d23_106p8), 545 CCU_PARENT_HW(pll2_d3), 546 CCU_PARENT_HW(pll2_d5), 547 }; 548 CCU_MUX_DIV_GATE_FC_DEFINE(dpu_spi_clk, dpu_spi_parents, APMU_LCD_SPI_CLK_RES_CTRL, 8, 3, 549 BIT(7), 12, 3, BIT(1), 0); 550 CCU_GATE_DEFINE(dpu_spi_hbus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(3), 0); 551 CCU_GATE_DEFINE(dpu_spi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(5), 0); 552 CCU_GATE_DEFINE(dpu_spi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(6), 0); 553 554 static const struct clk_parent_data v2d_parents[] = { 555 CCU_PARENT_HW(pll1_d5_491p52), 556 CCU_PARENT_HW(pll1_d6_409p6), 557 CCU_PARENT_HW(pll1_d8_307p2), 558 CCU_PARENT_HW(pll1_d4_614p4), 559 }; 560 CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, 561 BIT(8), 0); 562 563 static const struct clk_parent_data ccic_4x_parents[] = { 564 CCU_PARENT_HW(pll1_d5_491p52), 565 CCU_PARENT_HW(pll1_d6_409p6), 566 CCU_PARENT_HW(pll1_d4_614p4), 567 CCU_PARENT_HW(pll1_d3_819p2), 568 CCU_PARENT_HW(pll2_d2), 569 CCU_PARENT_HW(pll2_d3), 570 CCU_PARENT_HW(pll2_d4), 571 CCU_PARENT_HW(pll1_d2_1228p8), 572 }; 573 CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, 574 BIT(15), 23, 2, BIT(4), 0); 575 576 static const struct clk_parent_data ccic1phy_parents[] = { 577 CCU_PARENT_HW(pll1_d24_102p4), 578 CCU_PARENT_HW(pll1_d48_51p2_ap), 579 }; 580 CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); 581 582 CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); 583 static const struct clk_parent_data sdh01_parents[] = { 584 CCU_PARENT_HW(pll1_d6_409p6), 585 CCU_PARENT_HW(pll1_d4_614p4), 586 CCU_PARENT_HW(pll2_d8), 587 CCU_PARENT_HW(pll2_d5), 588 CCU_PARENT_HW(pll1_d11_223p4), 589 CCU_PARENT_HW(pll1_d13_189), 590 CCU_PARENT_HW(pll1_d23_106p8), 591 }; 592 CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 593 BIT(4), 0); 594 CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 595 BIT(4), 0); 596 static const struct clk_parent_data sdh2_parents[] = { 597 CCU_PARENT_HW(pll1_d6_409p6), 598 CCU_PARENT_HW(pll1_d4_614p4), 599 CCU_PARENT_HW(pll2_d8), 600 CCU_PARENT_HW(pll1_d3_819p2), 601 CCU_PARENT_HW(pll1_d11_223p4), 602 CCU_PARENT_HW(pll1_d13_189), 603 CCU_PARENT_HW(pll1_d23_106p8), 604 }; 605 CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 606 BIT(4), 0); 607 608 CCU_GATE_DEFINE(usb_axi_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); 609 CCU_GATE_DEFINE(usb_p1_aclk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(5), 0); 610 CCU_GATE_DEFINE(usb30_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); 611 612 static const struct clk_parent_data qspi_parents[] = { 613 CCU_PARENT_HW(pll1_d6_409p6), 614 CCU_PARENT_HW(pll2_d8), 615 CCU_PARENT_HW(pll1_d8_307p2), 616 CCU_PARENT_HW(pll1_d10_245p76), 617 CCU_PARENT_HW(pll1_d11_223p4), 618 CCU_PARENT_HW(pll1_d23_106p8), 619 CCU_PARENT_HW(pll1_d5_491p52), 620 CCU_PARENT_HW(pll1_d13_189), 621 }; 622 CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, BIT(12), 6, 3, 623 BIT(4), 0); 624 CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); 625 CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(pmua_aclk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); 626 627 static const struct clk_parent_data aes_parents[] = { 628 CCU_PARENT_HW(pll1_d12_204p8), 629 CCU_PARENT_HW(pll1_d24_102p4), 630 }; 631 CCU_MUX_GATE_DEFINE(aes_clk, aes_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); 632 633 static const struct clk_parent_data vpu_parents[] = { 634 CCU_PARENT_HW(pll1_d4_614p4), 635 CCU_PARENT_HW(pll1_d5_491p52), 636 CCU_PARENT_HW(pll1_d3_819p2), 637 CCU_PARENT_HW(pll1_d6_409p6), 638 CCU_PARENT_HW(pll3_d6), 639 CCU_PARENT_HW(pll2_d3), 640 CCU_PARENT_HW(pll2_d4), 641 CCU_PARENT_HW(pll2_d5), 642 }; 643 CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, BIT(21), 10, 3, 644 BIT(3), 0); 645 646 static const struct clk_parent_data gpu_parents[] = { 647 CCU_PARENT_HW(pll1_d4_614p4), 648 CCU_PARENT_HW(pll1_d5_491p52), 649 CCU_PARENT_HW(pll1_d3_819p2), 650 CCU_PARENT_HW(pll1_d6_409p6), 651 CCU_PARENT_HW(pll3_d6), 652 CCU_PARENT_HW(pll2_d3), 653 CCU_PARENT_HW(pll2_d4), 654 CCU_PARENT_HW(pll2_d5), 655 }; 656 CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, BIT(15), 18, 3, 657 BIT(4), 0); 658 659 static const struct clk_parent_data emmc_parents[] = { 660 CCU_PARENT_HW(pll1_d6_409p6), 661 CCU_PARENT_HW(pll1_d4_614p4), 662 CCU_PARENT_HW(pll1_d52_47p26), 663 CCU_PARENT_HW(pll1_d3_819p2), 664 }; 665 CCU_MUX_DIV_GATE_FC_DEFINE(emmc_clk, emmc_parents, APMU_PMUA_EM_CLK_RES_CTRL, 8, 3, BIT(11), 666 6, 2, BIT(4), 0); 667 CCU_DIV_GATE_DEFINE(emmc_x_clk, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMUA_EM_CLK_RES_CTRL, 12, 668 3, BIT(15), 0); 669 670 static const struct clk_parent_data audio_parents[] = { 671 CCU_PARENT_HW(pll1_aud_245p7), 672 CCU_PARENT_HW(pll1_d8_307p2), 673 CCU_PARENT_HW(pll1_d6_409p6), 674 }; 675 CCU_MUX_DIV_GATE_FC_DEFINE(audio_clk, audio_parents, APMU_AUDIO_CLK_RES_CTRL, 4, 3, BIT(15), 676 7, 3, BIT(12), 0); 677 678 static const struct clk_parent_data hdmi_parents[] = { 679 CCU_PARENT_HW(pll1_d6_409p6), 680 CCU_PARENT_HW(pll1_d5_491p52), 681 CCU_PARENT_HW(pll1_d4_614p4), 682 CCU_PARENT_HW(pll1_d8_307p2), 683 }; 684 CCU_MUX_DIV_GATE_FC_DEFINE(hdmi_mclk, hdmi_parents, APMU_HDMI_CLK_RES_CTRL, 1, 4, BIT(29), 5, 685 3, BIT(0), 0); 686 687 CCU_GATE_DEFINE(pcie0_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(2), 0); 688 CCU_GATE_DEFINE(pcie0_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(1), 0); 689 CCU_GATE_DEFINE(pcie0_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(0), 0); 690 691 CCU_GATE_DEFINE(pcie1_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(2), 0); 692 CCU_GATE_DEFINE(pcie1_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(1), 0); 693 CCU_GATE_DEFINE(pcie1_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(0), 0); 694 695 CCU_GATE_DEFINE(pcie2_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(2), 0); 696 CCU_GATE_DEFINE(pcie2_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(1), 0); 697 CCU_GATE_DEFINE(pcie2_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(0), 0); 698 699 CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); 700 CCU_GATE_DEFINE(emac0_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC0_CLK_RES_CTRL, BIT(15), 0); 701 CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); 702 CCU_GATE_DEFINE(emac1_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC1_CLK_RES_CTRL, BIT(15), 0); 703 704 CCU_GATE_DEFINE(emmc_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_PMUA_EM_CLK_RES_CTRL, BIT(3), 0); 705 /* APMU clocks end */ 706 707 static struct clk_hw *k1_ccu_pll_hws[] = { 708 [CLK_PLL1] = &pll1.common.hw, 709 [CLK_PLL2] = &pll2.common.hw, 710 [CLK_PLL3] = &pll3.common.hw, 711 [CLK_PLL1_D2] = &pll1_d2.common.hw, 712 [CLK_PLL1_D3] = &pll1_d3.common.hw, 713 [CLK_PLL1_D4] = &pll1_d4.common.hw, 714 [CLK_PLL1_D5] = &pll1_d5.common.hw, 715 [CLK_PLL1_D6] = &pll1_d6.common.hw, 716 [CLK_PLL1_D7] = &pll1_d7.common.hw, 717 [CLK_PLL1_D8] = &pll1_d8.common.hw, 718 [CLK_PLL1_D11] = &pll1_d11_223p4.common.hw, 719 [CLK_PLL1_D13] = &pll1_d13_189.common.hw, 720 [CLK_PLL1_D23] = &pll1_d23_106p8.common.hw, 721 [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, 722 [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, 723 [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, 724 [CLK_PLL2_D1] = &pll2_d1.common.hw, 725 [CLK_PLL2_D2] = &pll2_d2.common.hw, 726 [CLK_PLL2_D3] = &pll2_d3.common.hw, 727 [CLK_PLL2_D4] = &pll2_d4.common.hw, 728 [CLK_PLL2_D5] = &pll2_d5.common.hw, 729 [CLK_PLL2_D6] = &pll2_d6.common.hw, 730 [CLK_PLL2_D7] = &pll2_d7.common.hw, 731 [CLK_PLL2_D8] = &pll2_d8.common.hw, 732 [CLK_PLL3_D1] = &pll3_d1.common.hw, 733 [CLK_PLL3_D2] = &pll3_d2.common.hw, 734 [CLK_PLL3_D3] = &pll3_d3.common.hw, 735 [CLK_PLL3_D4] = &pll3_d4.common.hw, 736 [CLK_PLL3_D5] = &pll3_d5.common.hw, 737 [CLK_PLL3_D6] = &pll3_d6.common.hw, 738 [CLK_PLL3_D7] = &pll3_d7.common.hw, 739 [CLK_PLL3_D8] = &pll3_d8.common.hw, 740 [CLK_PLL3_80] = &pll3_80.common.hw, 741 [CLK_PLL3_40] = &pll3_40.common.hw, 742 [CLK_PLL3_20] = &pll3_20.common.hw, 743 }; 744 745 static const struct spacemit_ccu_data k1_ccu_pll_data = { 746 /* The PLL CCU implements no resets */ 747 .hws = k1_ccu_pll_hws, 748 .num = ARRAY_SIZE(k1_ccu_pll_hws), 749 }; 750 751 static struct clk_hw *k1_ccu_mpmu_hws[] = { 752 [CLK_PLL1_307P2] = &pll1_d8_307p2.common.hw, 753 [CLK_PLL1_76P8] = &pll1_d32_76p8.common.hw, 754 [CLK_PLL1_61P44] = &pll1_d40_61p44.common.hw, 755 [CLK_PLL1_153P6] = &pll1_d16_153p6.common.hw, 756 [CLK_PLL1_102P4] = &pll1_d24_102p4.common.hw, 757 [CLK_PLL1_51P2] = &pll1_d48_51p2.common.hw, 758 [CLK_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, 759 [CLK_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, 760 [CLK_PLL1_25P6] = &pll1_d96_25p6.common.hw, 761 [CLK_PLL1_12P8] = &pll1_d192_12p8.common.hw, 762 [CLK_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, 763 [CLK_PLL1_6P4] = &pll1_d384_6p4.common.hw, 764 [CLK_PLL1_3P2] = &pll1_d768_3p2.common.hw, 765 [CLK_PLL1_1P6] = &pll1_d1536_1p6.common.hw, 766 [CLK_PLL1_0P8] = &pll1_d3072_0p8.common.hw, 767 [CLK_PLL1_409P6] = &pll1_d6_409p6.common.hw, 768 [CLK_PLL1_204P8] = &pll1_d12_204p8.common.hw, 769 [CLK_PLL1_491] = &pll1_d5_491p52.common.hw, 770 [CLK_PLL1_245P76] = &pll1_d10_245p76.common.hw, 771 [CLK_PLL1_614] = &pll1_d4_614p4.common.hw, 772 [CLK_PLL1_47P26] = &pll1_d52_47p26.common.hw, 773 [CLK_PLL1_31P5] = &pll1_d78_31p5.common.hw, 774 [CLK_PLL1_819] = &pll1_d3_819p2.common.hw, 775 [CLK_PLL1_1228] = &pll1_d2_1228p8.common.hw, 776 [CLK_SLOW_UART] = &slow_uart.common.hw, 777 [CLK_SLOW_UART1] = &slow_uart1_14p74.common.hw, 778 [CLK_SLOW_UART2] = &slow_uart2_48.common.hw, 779 [CLK_WDT] = &wdt_clk.common.hw, 780 [CLK_RIPC] = &ripc_clk.common.hw, 781 [CLK_I2S_SYSCLK] = &i2s_sysclk.common.hw, 782 [CLK_I2S_BCLK] = &i2s_bclk.common.hw, 783 [CLK_APB] = &apb_clk.common.hw, 784 [CLK_WDT_BUS] = &wdt_bus_clk.common.hw, 785 [CLK_I2S_153P6] = &i2s_153p6.common.hw, 786 [CLK_I2S_153P6_BASE] = &i2s_153p6_base.common.hw, 787 [CLK_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw, 788 [CLK_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw, 789 }; 790 791 static const struct spacemit_ccu_data k1_ccu_mpmu_data = { 792 .reset_name = "k1-mpmu-reset", 793 .hws = k1_ccu_mpmu_hws, 794 .num = ARRAY_SIZE(k1_ccu_mpmu_hws), 795 }; 796 797 static struct clk_hw *k1_ccu_apbc_hws[] = { 798 [CLK_UART0] = &uart0_clk.common.hw, 799 [CLK_UART2] = &uart2_clk.common.hw, 800 [CLK_UART3] = &uart3_clk.common.hw, 801 [CLK_UART4] = &uart4_clk.common.hw, 802 [CLK_UART5] = &uart5_clk.common.hw, 803 [CLK_UART6] = &uart6_clk.common.hw, 804 [CLK_UART7] = &uart7_clk.common.hw, 805 [CLK_UART8] = &uart8_clk.common.hw, 806 [CLK_UART9] = &uart9_clk.common.hw, 807 [CLK_GPIO] = &gpio_clk.common.hw, 808 [CLK_PWM0] = &pwm0_clk.common.hw, 809 [CLK_PWM1] = &pwm1_clk.common.hw, 810 [CLK_PWM2] = &pwm2_clk.common.hw, 811 [CLK_PWM3] = &pwm3_clk.common.hw, 812 [CLK_PWM4] = &pwm4_clk.common.hw, 813 [CLK_PWM5] = &pwm5_clk.common.hw, 814 [CLK_PWM6] = &pwm6_clk.common.hw, 815 [CLK_PWM7] = &pwm7_clk.common.hw, 816 [CLK_PWM8] = &pwm8_clk.common.hw, 817 [CLK_PWM9] = &pwm9_clk.common.hw, 818 [CLK_PWM10] = &pwm10_clk.common.hw, 819 [CLK_PWM11] = &pwm11_clk.common.hw, 820 [CLK_PWM12] = &pwm12_clk.common.hw, 821 [CLK_PWM13] = &pwm13_clk.common.hw, 822 [CLK_PWM14] = &pwm14_clk.common.hw, 823 [CLK_PWM15] = &pwm15_clk.common.hw, 824 [CLK_PWM16] = &pwm16_clk.common.hw, 825 [CLK_PWM17] = &pwm17_clk.common.hw, 826 [CLK_PWM18] = &pwm18_clk.common.hw, 827 [CLK_PWM19] = &pwm19_clk.common.hw, 828 [CLK_SSP3] = &ssp3_clk.common.hw, 829 [CLK_RTC] = &rtc_clk.common.hw, 830 [CLK_TWSI0] = &twsi0_clk.common.hw, 831 [CLK_TWSI1] = &twsi1_clk.common.hw, 832 [CLK_TWSI2] = &twsi2_clk.common.hw, 833 [CLK_TWSI4] = &twsi4_clk.common.hw, 834 [CLK_TWSI5] = &twsi5_clk.common.hw, 835 [CLK_TWSI6] = &twsi6_clk.common.hw, 836 [CLK_TWSI7] = &twsi7_clk.common.hw, 837 [CLK_TWSI8] = &twsi8_clk.common.hw, 838 [CLK_TIMERS1] = &timers1_clk.common.hw, 839 [CLK_TIMERS2] = &timers2_clk.common.hw, 840 [CLK_AIB] = &aib_clk.common.hw, 841 [CLK_ONEWIRE] = &onewire_clk.common.hw, 842 [CLK_SSPA0] = &sspa0_clk.common.hw, 843 [CLK_SSPA1] = &sspa1_clk.common.hw, 844 [CLK_DRO] = &dro_clk.common.hw, 845 [CLK_IR] = &ir_clk.common.hw, 846 [CLK_TSEN] = &tsen_clk.common.hw, 847 [CLK_IPC_AP2AUD] = &ipc_ap2aud_clk.common.hw, 848 [CLK_CAN0] = &can0_clk.common.hw, 849 [CLK_CAN0_BUS] = &can0_bus_clk.common.hw, 850 [CLK_UART0_BUS] = &uart0_bus_clk.common.hw, 851 [CLK_UART2_BUS] = &uart2_bus_clk.common.hw, 852 [CLK_UART3_BUS] = &uart3_bus_clk.common.hw, 853 [CLK_UART4_BUS] = &uart4_bus_clk.common.hw, 854 [CLK_UART5_BUS] = &uart5_bus_clk.common.hw, 855 [CLK_UART6_BUS] = &uart6_bus_clk.common.hw, 856 [CLK_UART7_BUS] = &uart7_bus_clk.common.hw, 857 [CLK_UART8_BUS] = &uart8_bus_clk.common.hw, 858 [CLK_UART9_BUS] = &uart9_bus_clk.common.hw, 859 [CLK_GPIO_BUS] = &gpio_bus_clk.common.hw, 860 [CLK_PWM0_BUS] = &pwm0_bus_clk.common.hw, 861 [CLK_PWM1_BUS] = &pwm1_bus_clk.common.hw, 862 [CLK_PWM2_BUS] = &pwm2_bus_clk.common.hw, 863 [CLK_PWM3_BUS] = &pwm3_bus_clk.common.hw, 864 [CLK_PWM4_BUS] = &pwm4_bus_clk.common.hw, 865 [CLK_PWM5_BUS] = &pwm5_bus_clk.common.hw, 866 [CLK_PWM6_BUS] = &pwm6_bus_clk.common.hw, 867 [CLK_PWM7_BUS] = &pwm7_bus_clk.common.hw, 868 [CLK_PWM8_BUS] = &pwm8_bus_clk.common.hw, 869 [CLK_PWM9_BUS] = &pwm9_bus_clk.common.hw, 870 [CLK_PWM10_BUS] = &pwm10_bus_clk.common.hw, 871 [CLK_PWM11_BUS] = &pwm11_bus_clk.common.hw, 872 [CLK_PWM12_BUS] = &pwm12_bus_clk.common.hw, 873 [CLK_PWM13_BUS] = &pwm13_bus_clk.common.hw, 874 [CLK_PWM14_BUS] = &pwm14_bus_clk.common.hw, 875 [CLK_PWM15_BUS] = &pwm15_bus_clk.common.hw, 876 [CLK_PWM16_BUS] = &pwm16_bus_clk.common.hw, 877 [CLK_PWM17_BUS] = &pwm17_bus_clk.common.hw, 878 [CLK_PWM18_BUS] = &pwm18_bus_clk.common.hw, 879 [CLK_PWM19_BUS] = &pwm19_bus_clk.common.hw, 880 [CLK_SSP3_BUS] = &ssp3_bus_clk.common.hw, 881 [CLK_RTC_BUS] = &rtc_bus_clk.common.hw, 882 [CLK_TWSI0_BUS] = &twsi0_bus_clk.common.hw, 883 [CLK_TWSI1_BUS] = &twsi1_bus_clk.common.hw, 884 [CLK_TWSI2_BUS] = &twsi2_bus_clk.common.hw, 885 [CLK_TWSI4_BUS] = &twsi4_bus_clk.common.hw, 886 [CLK_TWSI5_BUS] = &twsi5_bus_clk.common.hw, 887 [CLK_TWSI6_BUS] = &twsi6_bus_clk.common.hw, 888 [CLK_TWSI7_BUS] = &twsi7_bus_clk.common.hw, 889 [CLK_TWSI8_BUS] = &twsi8_bus_clk.common.hw, 890 [CLK_TIMERS1_BUS] = &timers1_bus_clk.common.hw, 891 [CLK_TIMERS2_BUS] = &timers2_bus_clk.common.hw, 892 [CLK_AIB_BUS] = &aib_bus_clk.common.hw, 893 [CLK_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, 894 [CLK_SSPA0_BUS] = &sspa0_bus_clk.common.hw, 895 [CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw, 896 [CLK_TSEN_BUS] = &tsen_bus_clk.common.hw, 897 [CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw, 898 [CLK_SSPA0_I2S_BCLK] = &sspa0_i2s_bclk.common.hw, 899 [CLK_SSPA1_I2S_BCLK] = &sspa1_i2s_bclk.common.hw, 900 }; 901 902 static const struct spacemit_ccu_data k1_ccu_apbc_data = { 903 .reset_name = "k1-apbc-reset", 904 .hws = k1_ccu_apbc_hws, 905 .num = ARRAY_SIZE(k1_ccu_apbc_hws), 906 }; 907 908 static struct clk_hw *k1_ccu_apmu_hws[] = { 909 [CLK_CCI550] = &cci550_clk.common.hw, 910 [CLK_CPU_C0_HI] = &cpu_c0_hi_clk.common.hw, 911 [CLK_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, 912 [CLK_CPU_C0_ACE] = &cpu_c0_ace_clk.common.hw, 913 [CLK_CPU_C0_TCM] = &cpu_c0_tcm_clk.common.hw, 914 [CLK_CPU_C1_HI] = &cpu_c1_hi_clk.common.hw, 915 [CLK_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, 916 [CLK_CPU_C1_ACE] = &cpu_c1_ace_clk.common.hw, 917 [CLK_CCIC_4X] = &ccic_4x_clk.common.hw, 918 [CLK_CCIC1PHY] = &ccic1phy_clk.common.hw, 919 [CLK_SDH_AXI] = &sdh_axi_aclk.common.hw, 920 [CLK_SDH0] = &sdh0_clk.common.hw, 921 [CLK_SDH1] = &sdh1_clk.common.hw, 922 [CLK_SDH2] = &sdh2_clk.common.hw, 923 [CLK_USB_P1] = &usb_p1_aclk.common.hw, 924 [CLK_USB_AXI] = &usb_axi_clk.common.hw, 925 [CLK_USB30] = &usb30_clk.common.hw, 926 [CLK_QSPI] = &qspi_clk.common.hw, 927 [CLK_QSPI_BUS] = &qspi_bus_clk.common.hw, 928 [CLK_DMA] = &dma_clk.common.hw, 929 [CLK_AES] = &aes_clk.common.hw, 930 [CLK_VPU] = &vpu_clk.common.hw, 931 [CLK_GPU] = &gpu_clk.common.hw, 932 [CLK_EMMC] = &emmc_clk.common.hw, 933 [CLK_EMMC_X] = &emmc_x_clk.common.hw, 934 [CLK_AUDIO] = &audio_clk.common.hw, 935 [CLK_HDMI] = &hdmi_mclk.common.hw, 936 [CLK_PMUA_ACLK] = &pmua_aclk.common.hw, 937 [CLK_PCIE0_MASTER] = &pcie0_master_clk.common.hw, 938 [CLK_PCIE0_SLAVE] = &pcie0_slave_clk.common.hw, 939 [CLK_PCIE0_DBI] = &pcie0_dbi_clk.common.hw, 940 [CLK_PCIE1_MASTER] = &pcie1_master_clk.common.hw, 941 [CLK_PCIE1_SLAVE] = &pcie1_slave_clk.common.hw, 942 [CLK_PCIE1_DBI] = &pcie1_dbi_clk.common.hw, 943 [CLK_PCIE2_MASTER] = &pcie2_master_clk.common.hw, 944 [CLK_PCIE2_SLAVE] = &pcie2_slave_clk.common.hw, 945 [CLK_PCIE2_DBI] = &pcie2_dbi_clk.common.hw, 946 [CLK_EMAC0_BUS] = &emac0_bus_clk.common.hw, 947 [CLK_EMAC0_PTP] = &emac0_ptp_clk.common.hw, 948 [CLK_EMAC1_BUS] = &emac1_bus_clk.common.hw, 949 [CLK_EMAC1_PTP] = &emac1_ptp_clk.common.hw, 950 [CLK_JPG] = &jpg_clk.common.hw, 951 [CLK_CCIC2PHY] = &ccic2phy_clk.common.hw, 952 [CLK_CCIC3PHY] = &ccic3phy_clk.common.hw, 953 [CLK_CSI] = &csi_clk.common.hw, 954 [CLK_CAMM0] = &camm0_clk.common.hw, 955 [CLK_CAMM1] = &camm1_clk.common.hw, 956 [CLK_CAMM2] = &camm2_clk.common.hw, 957 [CLK_ISP_CPP] = &isp_cpp_clk.common.hw, 958 [CLK_ISP_BUS] = &isp_bus_clk.common.hw, 959 [CLK_ISP] = &isp_clk.common.hw, 960 [CLK_DPU_MCLK] = &dpu_mclk.common.hw, 961 [CLK_DPU_ESC] = &dpu_esc_clk.common.hw, 962 [CLK_DPU_BIT] = &dpu_bit_clk.common.hw, 963 [CLK_DPU_PXCLK] = &dpu_pxclk.common.hw, 964 [CLK_DPU_HCLK] = &dpu_hclk.common.hw, 965 [CLK_DPU_SPI] = &dpu_spi_clk.common.hw, 966 [CLK_DPU_SPI_HBUS] = &dpu_spi_hbus_clk.common.hw, 967 [CLK_DPU_SPIBUS] = &dpu_spi_bus_clk.common.hw, 968 [CLK_DPU_SPI_ACLK] = &dpu_spi_aclk.common.hw, 969 [CLK_V2D] = &v2d_clk.common.hw, 970 [CLK_EMMC_BUS] = &emmc_bus_clk.common.hw, 971 }; 972 973 static const struct spacemit_ccu_data k1_ccu_apmu_data = { 974 .reset_name = "k1-apmu-reset", 975 .hws = k1_ccu_apmu_hws, 976 .num = ARRAY_SIZE(k1_ccu_apmu_hws), 977 }; 978 979 static const struct spacemit_ccu_data k1_ccu_rcpu_data = { 980 .reset_name = "k1-rcpu-reset", 981 }; 982 983 static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { 984 .reset_name = "k1-rcpu2-reset", 985 }; 986 987 static const struct spacemit_ccu_data k1_ccu_apbc2_data = { 988 .reset_name = "k1-apbc2-reset", 989 }; 990 991 static const struct of_device_id of_k1_ccu_match[] = { 992 { 993 .compatible = "spacemit,k1-pll", 994 .data = &k1_ccu_pll_data, 995 }, 996 { 997 .compatible = "spacemit,k1-syscon-mpmu", 998 .data = &k1_ccu_mpmu_data, 999 }, 1000 { 1001 .compatible = "spacemit,k1-syscon-apbc", 1002 .data = &k1_ccu_apbc_data, 1003 }, 1004 { 1005 .compatible = "spacemit,k1-syscon-apmu", 1006 .data = &k1_ccu_apmu_data, 1007 }, 1008 { 1009 .compatible = "spacemit,k1-syscon-rcpu", 1010 .data = &k1_ccu_rcpu_data, 1011 }, 1012 { 1013 .compatible = "spacemit,k1-syscon-rcpu2", 1014 .data = &k1_ccu_rcpu2_data, 1015 }, 1016 { 1017 .compatible = "spacemit,k1-syscon-apbc2", 1018 .data = &k1_ccu_apbc2_data, 1019 }, 1020 { } 1021 }; 1022 MODULE_DEVICE_TABLE(of, of_k1_ccu_match); 1023 1024 static int k1_ccu_probe(struct platform_device *pdev) 1025 { 1026 return spacemit_ccu_probe(pdev, "spacemit,k1-pll"); 1027 } 1028 1029 static struct platform_driver k1_ccu_driver = { 1030 .driver = { 1031 .name = "spacemit,k1-ccu", 1032 .of_match_table = of_k1_ccu_match, 1033 }, 1034 .probe = k1_ccu_probe, 1035 }; 1036 module_platform_driver(k1_ccu_driver); 1037 1038 MODULE_IMPORT_NS("CLK_SPACEMIT"); 1039 MODULE_DESCRIPTION("SpacemiT K1 CCU driver"); 1040 MODULE_AUTHOR("Haylen Chu <heylenay@4d2.org>"); 1041 MODULE_LICENSE("GPL"); 1042