1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 SpacemiT Technology Co. Ltd 4 * Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org> 5 */ 6 7 #include <linux/array_size.h> 8 #include <linux/auxiliary_bus.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/idr.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/minmax.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <soc/spacemit/k1-syscon.h> 18 19 #include "ccu_common.h" 20 #include "ccu_pll.h" 21 #include "ccu_mix.h" 22 #include "ccu_ddn.h" 23 24 #include <dt-bindings/clock/spacemit,k1-syscon.h> 25 26 struct spacemit_ccu_data { 27 const char *reset_name; 28 struct clk_hw **hws; 29 size_t num; 30 }; 31 32 static DEFINE_IDA(auxiliary_ids); 33 34 /* APBS clocks start, APBS region contains and only contains all PLL clocks */ 35 36 /* 37 * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for 38 * peripherals. 39 */ 40 static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = { 41 CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), 42 }; 43 44 static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { 45 CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), 46 }; 47 48 static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { 49 CCU_PLL_RATE(1600000000UL, 0x0050cd61, 0x43eaaaab), 50 CCU_PLL_RATE(1800000000UL, 0x0050cd61, 0x4b000000), 51 CCU_PLL_RATE(2000000000UL, 0x0050dd62, 0x2aeaaaab), 52 CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd), 53 CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000), 54 CCU_PLL_RATE(3200000000UL, 0x0050dd67, 0x43eaaaab), 55 }; 56 57 CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK, 58 CLK_SET_RATE_GATE); 59 CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK, 60 CLK_SET_RATE_GATE); 61 CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK, 62 CLK_SET_RATE_GATE); 63 64 CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1); 65 CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1); 66 CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1); 67 CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1); 68 CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1); 69 CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1); 70 CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1, 71 CLK_IS_CRITICAL); 72 CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1); 73 CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1); 74 CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1); 75 CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(0), 64, 1); 76 CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(10), 10, 1); 77 CCU_FACTOR_GATE_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(11), 100, 1); 78 79 CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1); 80 CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1); 81 CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1); 82 CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1); 83 CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1); 84 CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1); 85 CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1); 86 CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1); 87 88 CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1); 89 CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1); 90 CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1); 91 CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1); 92 CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1); 93 CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1); 94 CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1); 95 CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1); 96 97 CCU_FACTOR_DEFINE(pll3_20, CCU_PARENT_HW(pll3_d8), 20, 1); 98 CCU_FACTOR_DEFINE(pll3_40, CCU_PARENT_HW(pll3_d8), 10, 1); 99 CCU_FACTOR_DEFINE(pll3_80, CCU_PARENT_HW(pll3_d8), 5, 1); 100 101 /* APBS clocks end */ 102 103 /* MPMU clocks start */ 104 CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0); 105 106 CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1); 107 108 CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1); 109 110 CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1); 111 CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1); 112 CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1); 113 CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1); 114 CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3); 115 CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1); 116 CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1); 117 CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1); 118 CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1); 119 120 CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1); 121 CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1); 122 CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1); 123 124 CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0); 125 CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1); 126 127 CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0); 128 CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1); 129 130 CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0); 131 CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1); 132 CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2); 133 134 CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0); 135 136 CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0); 137 138 CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED); 139 CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 0); 140 CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 0); 141 142 CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0); 143 144 CCU_FACTOR_GATE_DEFINE(i2s_sysclk, CCU_PARENT_HW(pll1_d16_153p6), MPMU_ISCCR, BIT(31), 50, 1); 145 CCU_FACTOR_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_sysclk), MPMU_ISCCR, BIT(29), 1, 1); 146 147 static const struct clk_parent_data apb_parents[] = { 148 CCU_PARENT_HW(pll1_d96_25p6), 149 CCU_PARENT_HW(pll1_d48_51p2), 150 CCU_PARENT_HW(pll1_d96_25p6), 151 CCU_PARENT_HW(pll1_d24_102p4), 152 }; 153 CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0); 154 155 CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0); 156 157 CCU_GATE_DEFINE(ripc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, 0x1, 0); 158 /* MPMU clocks end */ 159 160 /* APBC clocks start */ 161 static const struct clk_parent_data uart_clk_parents[] = { 162 CCU_PARENT_HW(pll1_m3d128_57p6), 163 CCU_PARENT_HW(slow_uart1_14p74), 164 CCU_PARENT_HW(slow_uart2_48), 165 }; 166 CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART1_CLK_RST, 4, 3, BIT(1), 0); 167 CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0); 168 CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0); 169 CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0); 170 CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0); 171 CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0); 172 CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0); 173 CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0); 174 CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0); 175 176 CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0); 177 178 static const struct clk_parent_data pwm_parents[] = { 179 CCU_PARENT_HW(pll1_d192_12p8), 180 CCU_PARENT_NAME(osc), 181 }; 182 CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0); 183 CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0); 184 CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0); 185 CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0); 186 CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0); 187 CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0); 188 CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0); 189 CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0); 190 CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0); 191 CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0); 192 CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0); 193 CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0); 194 CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0); 195 CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0); 196 CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0); 197 CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0); 198 CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0); 199 CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0); 200 CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0); 201 CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0); 202 203 static const struct clk_parent_data ssp_parents[] = { 204 CCU_PARENT_HW(pll1_d384_6p4), 205 CCU_PARENT_HW(pll1_d192_12p8), 206 CCU_PARENT_HW(pll1_d96_25p6), 207 CCU_PARENT_HW(pll1_d48_51p2), 208 CCU_PARENT_HW(pll1_d768_3p2), 209 CCU_PARENT_HW(pll1_d1536_1p6), 210 CCU_PARENT_HW(pll1_d3072_0p8), 211 }; 212 CCU_MUX_GATE_DEFINE(ssp3_clk, ssp_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0); 213 214 CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc), APBC_RTC_CLK_RST, 215 BIT(7) | BIT(1), 0); 216 217 static const struct clk_parent_data twsi_parents[] = { 218 CCU_PARENT_HW(pll1_d78_31p5), 219 CCU_PARENT_HW(pll1_d48_51p2), 220 CCU_PARENT_HW(pll1_d40_61p44), 221 }; 222 CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0); 223 CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0); 224 CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0); 225 CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0); 226 CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0); 227 CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0); 228 CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0); 229 /* 230 * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero. 231 * Combine functional and bus bits together as a gate to avoid sharing the 232 * write-only register between different clock hardwares. 233 */ 234 CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0); 235 236 static const struct clk_parent_data timer_parents[] = { 237 CCU_PARENT_HW(pll1_d192_12p8), 238 CCU_PARENT_NAME(osc), 239 CCU_PARENT_HW(pll1_d384_6p4), 240 CCU_PARENT_NAME(vctcxo_3m), 241 CCU_PARENT_NAME(vctcxo_1m), 242 }; 243 CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0); 244 CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0); 245 246 CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0); 247 248 CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0); 249 250 static const struct clk_parent_data sspa_parents[] = { 251 CCU_PARENT_HW(pll1_d384_6p4), 252 CCU_PARENT_HW(pll1_d192_12p8), 253 CCU_PARENT_HW(pll1_d96_25p6), 254 CCU_PARENT_HW(pll1_d48_51p2), 255 CCU_PARENT_HW(pll1_d768_3p2), 256 CCU_PARENT_HW(pll1_d1536_1p6), 257 CCU_PARENT_HW(pll1_d3072_0p8), 258 CCU_PARENT_HW(i2s_bclk), 259 }; 260 CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0); 261 CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0); 262 CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0); 263 CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0); 264 CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0); 265 CCU_GATE_DEFINE(ipc_ap2aud_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0); 266 267 static const struct clk_parent_data can_parents[] = { 268 CCU_PARENT_HW(pll3_20), 269 CCU_PARENT_HW(pll3_40), 270 CCU_PARENT_HW(pll3_80), 271 }; 272 CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0); 273 CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_CAN0_CLK_RST, BIT(0), 0); 274 275 CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART1_CLK_RST, BIT(0), 0); 276 CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0); 277 CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0); 278 CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0); 279 CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0); 280 CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0); 281 CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0); 282 CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0); 283 CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0); 284 285 CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0); 286 287 CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0); 288 CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0); 289 CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0); 290 CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0); 291 CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0); 292 CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0); 293 CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0); 294 CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0); 295 CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0); 296 CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0); 297 CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0); 298 CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0); 299 CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0); 300 CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0); 301 CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0); 302 CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0); 303 CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0); 304 CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0); 305 CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0); 306 CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0); 307 308 CCU_GATE_DEFINE(ssp3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0); 309 310 CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0); 311 312 CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0); 313 CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0); 314 CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0); 315 CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0); 316 CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0); 317 CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0); 318 CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0); 319 /* Placeholder to workaround quirk of the register */ 320 CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1); 321 322 CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0); 323 CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0); 324 325 CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0); 326 327 CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0); 328 329 CCU_GATE_DEFINE(sspa0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0); 330 CCU_GATE_DEFINE(sspa1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0); 331 332 CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0); 333 334 CCU_GATE_DEFINE(ipc_ap2aud_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0); 335 /* APBC clocks end */ 336 337 /* APMU clocks start */ 338 static const struct clk_parent_data pmua_aclk_parents[] = { 339 CCU_PARENT_HW(pll1_d10_245p76), 340 CCU_PARENT_HW(pll1_d8_307p2), 341 }; 342 CCU_MUX_DIV_FC_DEFINE(pmua_aclk, pmua_aclk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0); 343 344 static const struct clk_parent_data cci550_clk_parents[] = { 345 CCU_PARENT_HW(pll1_d5_491p52), 346 CCU_PARENT_HW(pll1_d4_614p4), 347 CCU_PARENT_HW(pll1_d3_819p2), 348 CCU_PARENT_HW(pll2_d3), 349 }; 350 CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 3, BIT(12), 0, 2, 351 CLK_IS_CRITICAL); 352 353 static const struct clk_parent_data cpu_c0_hi_clk_parents[] = { 354 CCU_PARENT_HW(pll3_d2), 355 CCU_PARENT_HW(pll3_d1), 356 }; 357 CCU_MUX_DEFINE(cpu_c0_hi_clk, cpu_c0_hi_clk_parents, APMU_CPU_C0_CLK_CTRL, 13, 1, 0); 358 static const struct clk_parent_data cpu_c0_clk_parents[] = { 359 CCU_PARENT_HW(pll1_d4_614p4), 360 CCU_PARENT_HW(pll1_d3_819p2), 361 CCU_PARENT_HW(pll1_d6_409p6), 362 CCU_PARENT_HW(pll1_d5_491p52), 363 CCU_PARENT_HW(pll1_d2_1228p8), 364 CCU_PARENT_HW(pll3_d3), 365 CCU_PARENT_HW(pll2_d3), 366 CCU_PARENT_HW(cpu_c0_hi_clk), 367 }; 368 CCU_MUX_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, BIT(12), 0, 3, 369 CLK_IS_CRITICAL); 370 CCU_DIV_DEFINE(cpu_c0_ace_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 6, 3, 371 CLK_IS_CRITICAL); 372 CCU_DIV_DEFINE(cpu_c0_tcm_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 9, 3, 373 CLK_IS_CRITICAL); 374 375 static const struct clk_parent_data cpu_c1_hi_clk_parents[] = { 376 CCU_PARENT_HW(pll3_d2), 377 CCU_PARENT_HW(pll3_d1), 378 }; 379 CCU_MUX_DEFINE(cpu_c1_hi_clk, cpu_c1_hi_clk_parents, APMU_CPU_C1_CLK_CTRL, 13, 1, 0); 380 static const struct clk_parent_data cpu_c1_clk_parents[] = { 381 CCU_PARENT_HW(pll1_d4_614p4), 382 CCU_PARENT_HW(pll1_d3_819p2), 383 CCU_PARENT_HW(pll1_d6_409p6), 384 CCU_PARENT_HW(pll1_d5_491p52), 385 CCU_PARENT_HW(pll1_d2_1228p8), 386 CCU_PARENT_HW(pll3_d3), 387 CCU_PARENT_HW(pll2_d3), 388 CCU_PARENT_HW(cpu_c1_hi_clk), 389 }; 390 CCU_MUX_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, BIT(12), 0, 3, 391 CLK_IS_CRITICAL); 392 CCU_DIV_DEFINE(cpu_c1_ace_clk, CCU_PARENT_HW(cpu_c1_core_clk), APMU_CPU_C1_CLK_CTRL, 6, 3, 393 CLK_IS_CRITICAL); 394 395 static const struct clk_parent_data jpg_parents[] = { 396 CCU_PARENT_HW(pll1_d4_614p4), 397 CCU_PARENT_HW(pll1_d6_409p6), 398 CCU_PARENT_HW(pll1_d5_491p52), 399 CCU_PARENT_HW(pll1_d3_819p2), 400 CCU_PARENT_HW(pll1_d2_1228p8), 401 CCU_PARENT_HW(pll2_d4), 402 CCU_PARENT_HW(pll2_d3), 403 }; 404 CCU_MUX_DIV_GATE_FC_DEFINE(jpg_clk, jpg_parents, APMU_JPG_CLK_RES_CTRL, 5, 3, BIT(15), 2, 3, 405 BIT(1), 0); 406 407 static const struct clk_parent_data ccic2phy_parents[] = { 408 CCU_PARENT_HW(pll1_d24_102p4), 409 CCU_PARENT_HW(pll1_d48_51p2_ap), 410 }; 411 CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0); 412 413 static const struct clk_parent_data ccic3phy_parents[] = { 414 CCU_PARENT_HW(pll1_d24_102p4), 415 CCU_PARENT_HW(pll1_d48_51p2_ap), 416 }; 417 CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0); 418 419 static const struct clk_parent_data csi_parents[] = { 420 CCU_PARENT_HW(pll1_d5_491p52), 421 CCU_PARENT_HW(pll1_d6_409p6), 422 CCU_PARENT_HW(pll1_d4_614p4), 423 CCU_PARENT_HW(pll1_d3_819p2), 424 CCU_PARENT_HW(pll2_d2), 425 CCU_PARENT_HW(pll2_d3), 426 CCU_PARENT_HW(pll2_d4), 427 CCU_PARENT_HW(pll1_d2_1228p8), 428 }; 429 CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15), 430 16, 3, BIT(4), 0); 431 432 static const struct clk_parent_data camm_parents[] = { 433 CCU_PARENT_HW(pll1_d8_307p2), 434 CCU_PARENT_HW(pll2_d5), 435 CCU_PARENT_HW(pll1_d6_409p6), 436 CCU_PARENT_NAME(vctcxo_24m), 437 }; 438 CCU_MUX_DIV_GATE_DEFINE(camm0_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 439 BIT(28), 0); 440 CCU_MUX_DIV_GATE_DEFINE(camm1_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 441 BIT(6), 0); 442 CCU_MUX_DIV_GATE_DEFINE(camm2_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2, 443 BIT(3), 0); 444 445 static const struct clk_parent_data isp_cpp_parents[] = { 446 CCU_PARENT_HW(pll1_d8_307p2), 447 CCU_PARENT_HW(pll1_d6_409p6), 448 }; 449 CCU_MUX_DIV_GATE_DEFINE(isp_cpp_clk, isp_cpp_parents, APMU_ISP_CLK_RES_CTRL, 24, 2, 26, 1, 450 BIT(28), 0); 451 static const struct clk_parent_data isp_bus_parents[] = { 452 CCU_PARENT_HW(pll1_d6_409p6), 453 CCU_PARENT_HW(pll1_d5_491p52), 454 CCU_PARENT_HW(pll1_d8_307p2), 455 CCU_PARENT_HW(pll1_d10_245p76), 456 }; 457 CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23), 458 21, 2, BIT(17), 0); 459 static const struct clk_parent_data isp_parents[] = { 460 CCU_PARENT_HW(pll1_d6_409p6), 461 CCU_PARENT_HW(pll1_d5_491p52), 462 CCU_PARENT_HW(pll1_d4_614p4), 463 CCU_PARENT_HW(pll1_d8_307p2), 464 }; 465 CCU_MUX_DIV_GATE_FC_DEFINE(isp_clk, isp_parents, APMU_ISP_CLK_RES_CTRL, 4, 3, BIT(7), 8, 2, 466 BIT(1), 0); 467 468 static const struct clk_parent_data dpumclk_parents[] = { 469 CCU_PARENT_HW(pll1_d6_409p6), 470 CCU_PARENT_HW(pll1_d5_491p52), 471 CCU_PARENT_HW(pll1_d4_614p4), 472 CCU_PARENT_HW(pll1_d8_307p2), 473 }; 474 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_mclk, dpumclk_parents, APMU_LCD_CLK_RES_CTRL2, 475 APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0); 476 477 static const struct clk_parent_data dpuesc_parents[] = { 478 CCU_PARENT_HW(pll1_d48_51p2_ap), 479 CCU_PARENT_HW(pll1_d52_47p26), 480 CCU_PARENT_HW(pll1_d96_25p6), 481 CCU_PARENT_HW(pll1_d32_76p8), 482 }; 483 CCU_MUX_GATE_DEFINE(dpu_esc_clk, dpuesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0); 484 485 static const struct clk_parent_data dpubit_parents[] = { 486 CCU_PARENT_HW(pll1_d3_819p2), 487 CCU_PARENT_HW(pll2_d2), 488 CCU_PARENT_HW(pll2_d3), 489 CCU_PARENT_HW(pll1_d2_1228p8), 490 CCU_PARENT_HW(pll2_d4), 491 CCU_PARENT_HW(pll2_d5), 492 CCU_PARENT_HW(pll2_d7), 493 CCU_PARENT_HW(pll2_d8), 494 }; 495 CCU_MUX_DIV_GATE_FC_DEFINE(dpu_bit_clk, dpubit_parents, APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(31), 496 20, 3, BIT(16), 0); 497 498 static const struct clk_parent_data dpupx_parents[] = { 499 CCU_PARENT_HW(pll1_d6_409p6), 500 CCU_PARENT_HW(pll1_d5_491p52), 501 CCU_PARENT_HW(pll1_d4_614p4), 502 CCU_PARENT_HW(pll1_d8_307p2), 503 CCU_PARENT_HW(pll2_d7), 504 CCU_PARENT_HW(pll2_d8), 505 }; 506 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_pxclk, dpupx_parents, APMU_LCD_CLK_RES_CTRL2, 507 APMU_LCD_CLK_RES_CTRL1, 17, 4, BIT(30), 21, 3, BIT(16), 0); 508 509 CCU_GATE_DEFINE(dpu_hclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_CLK_RES_CTRL1, 510 BIT(5), 0); 511 512 static const struct clk_parent_data dpu_spi_parents[] = { 513 CCU_PARENT_HW(pll1_d8_307p2), 514 CCU_PARENT_HW(pll1_d6_409p6), 515 CCU_PARENT_HW(pll1_d10_245p76), 516 CCU_PARENT_HW(pll1_d11_223p4), 517 CCU_PARENT_HW(pll1_d13_189), 518 CCU_PARENT_HW(pll1_d23_106p8), 519 CCU_PARENT_HW(pll2_d3), 520 CCU_PARENT_HW(pll2_d5), 521 }; 522 CCU_MUX_DIV_GATE_FC_DEFINE(dpu_spi_clk, dpu_spi_parents, APMU_LCD_SPI_CLK_RES_CTRL, 8, 3, 523 BIT(7), 12, 3, BIT(1), 0); 524 CCU_GATE_DEFINE(dpu_spi_hbus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(3), 0); 525 CCU_GATE_DEFINE(dpu_spi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(5), 0); 526 CCU_GATE_DEFINE(dpu_spi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(6), 0); 527 528 static const struct clk_parent_data v2d_parents[] = { 529 CCU_PARENT_HW(pll1_d5_491p52), 530 CCU_PARENT_HW(pll1_d6_409p6), 531 CCU_PARENT_HW(pll1_d8_307p2), 532 CCU_PARENT_HW(pll1_d4_614p4), 533 }; 534 CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2, 535 BIT(8), 0); 536 537 static const struct clk_parent_data ccic_4x_parents[] = { 538 CCU_PARENT_HW(pll1_d5_491p52), 539 CCU_PARENT_HW(pll1_d6_409p6), 540 CCU_PARENT_HW(pll1_d4_614p4), 541 CCU_PARENT_HW(pll1_d3_819p2), 542 CCU_PARENT_HW(pll2_d2), 543 CCU_PARENT_HW(pll2_d3), 544 CCU_PARENT_HW(pll2_d4), 545 CCU_PARENT_HW(pll1_d2_1228p8), 546 }; 547 CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3, 548 BIT(15), 23, 2, BIT(4), 0); 549 550 static const struct clk_parent_data ccic1phy_parents[] = { 551 CCU_PARENT_HW(pll1_d24_102p4), 552 CCU_PARENT_HW(pll1_d48_51p2_ap), 553 }; 554 CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0); 555 556 CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0); 557 static const struct clk_parent_data sdh01_parents[] = { 558 CCU_PARENT_HW(pll1_d6_409p6), 559 CCU_PARENT_HW(pll1_d4_614p4), 560 CCU_PARENT_HW(pll2_d8), 561 CCU_PARENT_HW(pll2_d5), 562 CCU_PARENT_HW(pll1_d11_223p4), 563 CCU_PARENT_HW(pll1_d13_189), 564 CCU_PARENT_HW(pll1_d23_106p8), 565 }; 566 CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 567 BIT(4), 0); 568 CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 569 BIT(4), 0); 570 static const struct clk_parent_data sdh2_parents[] = { 571 CCU_PARENT_HW(pll1_d6_409p6), 572 CCU_PARENT_HW(pll1_d4_614p4), 573 CCU_PARENT_HW(pll2_d8), 574 CCU_PARENT_HW(pll1_d3_819p2), 575 CCU_PARENT_HW(pll1_d11_223p4), 576 CCU_PARENT_HW(pll1_d13_189), 577 CCU_PARENT_HW(pll1_d23_106p8), 578 }; 579 CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3, 580 BIT(4), 0); 581 582 CCU_GATE_DEFINE(usb_axi_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(1), 0); 583 CCU_GATE_DEFINE(usb_p1_aclk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(5), 0); 584 CCU_GATE_DEFINE(usb30_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(8), 0); 585 586 static const struct clk_parent_data qspi_parents[] = { 587 CCU_PARENT_HW(pll1_d6_409p6), 588 CCU_PARENT_HW(pll2_d8), 589 CCU_PARENT_HW(pll1_d8_307p2), 590 CCU_PARENT_HW(pll1_d10_245p76), 591 CCU_PARENT_HW(pll1_d11_223p4), 592 CCU_PARENT_HW(pll1_d23_106p8), 593 CCU_PARENT_HW(pll1_d5_491p52), 594 CCU_PARENT_HW(pll1_d13_189), 595 }; 596 CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, BIT(12), 6, 3, 597 BIT(4), 0); 598 CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0); 599 CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(pmua_aclk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0); 600 601 static const struct clk_parent_data aes_parents[] = { 602 CCU_PARENT_HW(pll1_d12_204p8), 603 CCU_PARENT_HW(pll1_d24_102p4), 604 }; 605 CCU_MUX_GATE_DEFINE(aes_clk, aes_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0); 606 607 static const struct clk_parent_data vpu_parents[] = { 608 CCU_PARENT_HW(pll1_d4_614p4), 609 CCU_PARENT_HW(pll1_d5_491p52), 610 CCU_PARENT_HW(pll1_d3_819p2), 611 CCU_PARENT_HW(pll1_d6_409p6), 612 CCU_PARENT_HW(pll3_d6), 613 CCU_PARENT_HW(pll2_d3), 614 CCU_PARENT_HW(pll2_d4), 615 CCU_PARENT_HW(pll2_d5), 616 }; 617 CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, BIT(21), 10, 3, 618 BIT(3), 0); 619 620 static const struct clk_parent_data gpu_parents[] = { 621 CCU_PARENT_HW(pll1_d4_614p4), 622 CCU_PARENT_HW(pll1_d5_491p52), 623 CCU_PARENT_HW(pll1_d3_819p2), 624 CCU_PARENT_HW(pll1_d6_409p6), 625 CCU_PARENT_HW(pll3_d6), 626 CCU_PARENT_HW(pll2_d3), 627 CCU_PARENT_HW(pll2_d4), 628 CCU_PARENT_HW(pll2_d5), 629 }; 630 CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, BIT(15), 18, 3, 631 BIT(4), 0); 632 633 static const struct clk_parent_data emmc_parents[] = { 634 CCU_PARENT_HW(pll1_d6_409p6), 635 CCU_PARENT_HW(pll1_d4_614p4), 636 CCU_PARENT_HW(pll1_d52_47p26), 637 CCU_PARENT_HW(pll1_d3_819p2), 638 }; 639 CCU_MUX_DIV_GATE_FC_DEFINE(emmc_clk, emmc_parents, APMU_PMUA_EM_CLK_RES_CTRL, 8, 3, BIT(11), 640 6, 2, BIT(4), 0); 641 CCU_DIV_GATE_DEFINE(emmc_x_clk, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMUA_EM_CLK_RES_CTRL, 12, 642 3, BIT(15), 0); 643 644 static const struct clk_parent_data audio_parents[] = { 645 CCU_PARENT_HW(pll1_aud_245p7), 646 CCU_PARENT_HW(pll1_d8_307p2), 647 CCU_PARENT_HW(pll1_d6_409p6), 648 }; 649 CCU_MUX_DIV_GATE_FC_DEFINE(audio_clk, audio_parents, APMU_AUDIO_CLK_RES_CTRL, 4, 3, BIT(15), 650 7, 3, BIT(12), 0); 651 652 static const struct clk_parent_data hdmi_parents[] = { 653 CCU_PARENT_HW(pll1_d6_409p6), 654 CCU_PARENT_HW(pll1_d5_491p52), 655 CCU_PARENT_HW(pll1_d4_614p4), 656 CCU_PARENT_HW(pll1_d8_307p2), 657 }; 658 CCU_MUX_DIV_GATE_FC_DEFINE(hdmi_mclk, hdmi_parents, APMU_HDMI_CLK_RES_CTRL, 1, 4, BIT(29), 5, 659 3, BIT(0), 0); 660 661 CCU_GATE_DEFINE(pcie0_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(2), 0); 662 CCU_GATE_DEFINE(pcie0_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(1), 0); 663 CCU_GATE_DEFINE(pcie0_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(0), 0); 664 665 CCU_GATE_DEFINE(pcie1_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(2), 0); 666 CCU_GATE_DEFINE(pcie1_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(1), 0); 667 CCU_GATE_DEFINE(pcie1_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(0), 0); 668 669 CCU_GATE_DEFINE(pcie2_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(2), 0); 670 CCU_GATE_DEFINE(pcie2_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(1), 0); 671 CCU_GATE_DEFINE(pcie2_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(0), 0); 672 673 CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0); 674 CCU_GATE_DEFINE(emac0_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC0_CLK_RES_CTRL, BIT(15), 0); 675 CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0); 676 CCU_GATE_DEFINE(emac1_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC1_CLK_RES_CTRL, BIT(15), 0); 677 678 CCU_GATE_DEFINE(emmc_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_PMUA_EM_CLK_RES_CTRL, BIT(3), 0); 679 /* APMU clocks end */ 680 681 static struct clk_hw *k1_ccu_pll_hws[] = { 682 [CLK_PLL1] = &pll1.common.hw, 683 [CLK_PLL2] = &pll2.common.hw, 684 [CLK_PLL3] = &pll3.common.hw, 685 [CLK_PLL1_D2] = &pll1_d2.common.hw, 686 [CLK_PLL1_D3] = &pll1_d3.common.hw, 687 [CLK_PLL1_D4] = &pll1_d4.common.hw, 688 [CLK_PLL1_D5] = &pll1_d5.common.hw, 689 [CLK_PLL1_D6] = &pll1_d6.common.hw, 690 [CLK_PLL1_D7] = &pll1_d7.common.hw, 691 [CLK_PLL1_D8] = &pll1_d8.common.hw, 692 [CLK_PLL1_D11] = &pll1_d11_223p4.common.hw, 693 [CLK_PLL1_D13] = &pll1_d13_189.common.hw, 694 [CLK_PLL1_D23] = &pll1_d23_106p8.common.hw, 695 [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw, 696 [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw, 697 [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw, 698 [CLK_PLL2_D1] = &pll2_d1.common.hw, 699 [CLK_PLL2_D2] = &pll2_d2.common.hw, 700 [CLK_PLL2_D3] = &pll2_d3.common.hw, 701 [CLK_PLL2_D4] = &pll2_d4.common.hw, 702 [CLK_PLL2_D5] = &pll2_d5.common.hw, 703 [CLK_PLL2_D6] = &pll2_d6.common.hw, 704 [CLK_PLL2_D7] = &pll2_d7.common.hw, 705 [CLK_PLL2_D8] = &pll2_d8.common.hw, 706 [CLK_PLL3_D1] = &pll3_d1.common.hw, 707 [CLK_PLL3_D2] = &pll3_d2.common.hw, 708 [CLK_PLL3_D3] = &pll3_d3.common.hw, 709 [CLK_PLL3_D4] = &pll3_d4.common.hw, 710 [CLK_PLL3_D5] = &pll3_d5.common.hw, 711 [CLK_PLL3_D6] = &pll3_d6.common.hw, 712 [CLK_PLL3_D7] = &pll3_d7.common.hw, 713 [CLK_PLL3_D8] = &pll3_d8.common.hw, 714 [CLK_PLL3_80] = &pll3_80.common.hw, 715 [CLK_PLL3_40] = &pll3_40.common.hw, 716 [CLK_PLL3_20] = &pll3_20.common.hw, 717 }; 718 719 static const struct spacemit_ccu_data k1_ccu_pll_data = { 720 /* The PLL CCU implements no resets */ 721 .hws = k1_ccu_pll_hws, 722 .num = ARRAY_SIZE(k1_ccu_pll_hws), 723 }; 724 725 static struct clk_hw *k1_ccu_mpmu_hws[] = { 726 [CLK_PLL1_307P2] = &pll1_d8_307p2.common.hw, 727 [CLK_PLL1_76P8] = &pll1_d32_76p8.common.hw, 728 [CLK_PLL1_61P44] = &pll1_d40_61p44.common.hw, 729 [CLK_PLL1_153P6] = &pll1_d16_153p6.common.hw, 730 [CLK_PLL1_102P4] = &pll1_d24_102p4.common.hw, 731 [CLK_PLL1_51P2] = &pll1_d48_51p2.common.hw, 732 [CLK_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw, 733 [CLK_PLL1_57P6] = &pll1_m3d128_57p6.common.hw, 734 [CLK_PLL1_25P6] = &pll1_d96_25p6.common.hw, 735 [CLK_PLL1_12P8] = &pll1_d192_12p8.common.hw, 736 [CLK_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw, 737 [CLK_PLL1_6P4] = &pll1_d384_6p4.common.hw, 738 [CLK_PLL1_3P2] = &pll1_d768_3p2.common.hw, 739 [CLK_PLL1_1P6] = &pll1_d1536_1p6.common.hw, 740 [CLK_PLL1_0P8] = &pll1_d3072_0p8.common.hw, 741 [CLK_PLL1_409P6] = &pll1_d6_409p6.common.hw, 742 [CLK_PLL1_204P8] = &pll1_d12_204p8.common.hw, 743 [CLK_PLL1_491] = &pll1_d5_491p52.common.hw, 744 [CLK_PLL1_245P76] = &pll1_d10_245p76.common.hw, 745 [CLK_PLL1_614] = &pll1_d4_614p4.common.hw, 746 [CLK_PLL1_47P26] = &pll1_d52_47p26.common.hw, 747 [CLK_PLL1_31P5] = &pll1_d78_31p5.common.hw, 748 [CLK_PLL1_819] = &pll1_d3_819p2.common.hw, 749 [CLK_PLL1_1228] = &pll1_d2_1228p8.common.hw, 750 [CLK_SLOW_UART] = &slow_uart.common.hw, 751 [CLK_SLOW_UART1] = &slow_uart1_14p74.common.hw, 752 [CLK_SLOW_UART2] = &slow_uart2_48.common.hw, 753 [CLK_WDT] = &wdt_clk.common.hw, 754 [CLK_RIPC] = &ripc_clk.common.hw, 755 [CLK_I2S_SYSCLK] = &i2s_sysclk.common.hw, 756 [CLK_I2S_BCLK] = &i2s_bclk.common.hw, 757 [CLK_APB] = &apb_clk.common.hw, 758 [CLK_WDT_BUS] = &wdt_bus_clk.common.hw, 759 }; 760 761 static const struct spacemit_ccu_data k1_ccu_mpmu_data = { 762 .reset_name = "mpmu-reset", 763 .hws = k1_ccu_mpmu_hws, 764 .num = ARRAY_SIZE(k1_ccu_mpmu_hws), 765 }; 766 767 static struct clk_hw *k1_ccu_apbc_hws[] = { 768 [CLK_UART0] = &uart0_clk.common.hw, 769 [CLK_UART2] = &uart2_clk.common.hw, 770 [CLK_UART3] = &uart3_clk.common.hw, 771 [CLK_UART4] = &uart4_clk.common.hw, 772 [CLK_UART5] = &uart5_clk.common.hw, 773 [CLK_UART6] = &uart6_clk.common.hw, 774 [CLK_UART7] = &uart7_clk.common.hw, 775 [CLK_UART8] = &uart8_clk.common.hw, 776 [CLK_UART9] = &uart9_clk.common.hw, 777 [CLK_GPIO] = &gpio_clk.common.hw, 778 [CLK_PWM0] = &pwm0_clk.common.hw, 779 [CLK_PWM1] = &pwm1_clk.common.hw, 780 [CLK_PWM2] = &pwm2_clk.common.hw, 781 [CLK_PWM3] = &pwm3_clk.common.hw, 782 [CLK_PWM4] = &pwm4_clk.common.hw, 783 [CLK_PWM5] = &pwm5_clk.common.hw, 784 [CLK_PWM6] = &pwm6_clk.common.hw, 785 [CLK_PWM7] = &pwm7_clk.common.hw, 786 [CLK_PWM8] = &pwm8_clk.common.hw, 787 [CLK_PWM9] = &pwm9_clk.common.hw, 788 [CLK_PWM10] = &pwm10_clk.common.hw, 789 [CLK_PWM11] = &pwm11_clk.common.hw, 790 [CLK_PWM12] = &pwm12_clk.common.hw, 791 [CLK_PWM13] = &pwm13_clk.common.hw, 792 [CLK_PWM14] = &pwm14_clk.common.hw, 793 [CLK_PWM15] = &pwm15_clk.common.hw, 794 [CLK_PWM16] = &pwm16_clk.common.hw, 795 [CLK_PWM17] = &pwm17_clk.common.hw, 796 [CLK_PWM18] = &pwm18_clk.common.hw, 797 [CLK_PWM19] = &pwm19_clk.common.hw, 798 [CLK_SSP3] = &ssp3_clk.common.hw, 799 [CLK_RTC] = &rtc_clk.common.hw, 800 [CLK_TWSI0] = &twsi0_clk.common.hw, 801 [CLK_TWSI1] = &twsi1_clk.common.hw, 802 [CLK_TWSI2] = &twsi2_clk.common.hw, 803 [CLK_TWSI4] = &twsi4_clk.common.hw, 804 [CLK_TWSI5] = &twsi5_clk.common.hw, 805 [CLK_TWSI6] = &twsi6_clk.common.hw, 806 [CLK_TWSI7] = &twsi7_clk.common.hw, 807 [CLK_TWSI8] = &twsi8_clk.common.hw, 808 [CLK_TIMERS1] = &timers1_clk.common.hw, 809 [CLK_TIMERS2] = &timers2_clk.common.hw, 810 [CLK_AIB] = &aib_clk.common.hw, 811 [CLK_ONEWIRE] = &onewire_clk.common.hw, 812 [CLK_SSPA0] = &sspa0_clk.common.hw, 813 [CLK_SSPA1] = &sspa1_clk.common.hw, 814 [CLK_DRO] = &dro_clk.common.hw, 815 [CLK_IR] = &ir_clk.common.hw, 816 [CLK_TSEN] = &tsen_clk.common.hw, 817 [CLK_IPC_AP2AUD] = &ipc_ap2aud_clk.common.hw, 818 [CLK_CAN0] = &can0_clk.common.hw, 819 [CLK_CAN0_BUS] = &can0_bus_clk.common.hw, 820 [CLK_UART0_BUS] = &uart0_bus_clk.common.hw, 821 [CLK_UART2_BUS] = &uart2_bus_clk.common.hw, 822 [CLK_UART3_BUS] = &uart3_bus_clk.common.hw, 823 [CLK_UART4_BUS] = &uart4_bus_clk.common.hw, 824 [CLK_UART5_BUS] = &uart5_bus_clk.common.hw, 825 [CLK_UART6_BUS] = &uart6_bus_clk.common.hw, 826 [CLK_UART7_BUS] = &uart7_bus_clk.common.hw, 827 [CLK_UART8_BUS] = &uart8_bus_clk.common.hw, 828 [CLK_UART9_BUS] = &uart9_bus_clk.common.hw, 829 [CLK_GPIO_BUS] = &gpio_bus_clk.common.hw, 830 [CLK_PWM0_BUS] = &pwm0_bus_clk.common.hw, 831 [CLK_PWM1_BUS] = &pwm1_bus_clk.common.hw, 832 [CLK_PWM2_BUS] = &pwm2_bus_clk.common.hw, 833 [CLK_PWM3_BUS] = &pwm3_bus_clk.common.hw, 834 [CLK_PWM4_BUS] = &pwm4_bus_clk.common.hw, 835 [CLK_PWM5_BUS] = &pwm5_bus_clk.common.hw, 836 [CLK_PWM6_BUS] = &pwm6_bus_clk.common.hw, 837 [CLK_PWM7_BUS] = &pwm7_bus_clk.common.hw, 838 [CLK_PWM8_BUS] = &pwm8_bus_clk.common.hw, 839 [CLK_PWM9_BUS] = &pwm9_bus_clk.common.hw, 840 [CLK_PWM10_BUS] = &pwm10_bus_clk.common.hw, 841 [CLK_PWM11_BUS] = &pwm11_bus_clk.common.hw, 842 [CLK_PWM12_BUS] = &pwm12_bus_clk.common.hw, 843 [CLK_PWM13_BUS] = &pwm13_bus_clk.common.hw, 844 [CLK_PWM14_BUS] = &pwm14_bus_clk.common.hw, 845 [CLK_PWM15_BUS] = &pwm15_bus_clk.common.hw, 846 [CLK_PWM16_BUS] = &pwm16_bus_clk.common.hw, 847 [CLK_PWM17_BUS] = &pwm17_bus_clk.common.hw, 848 [CLK_PWM18_BUS] = &pwm18_bus_clk.common.hw, 849 [CLK_PWM19_BUS] = &pwm19_bus_clk.common.hw, 850 [CLK_SSP3_BUS] = &ssp3_bus_clk.common.hw, 851 [CLK_RTC_BUS] = &rtc_bus_clk.common.hw, 852 [CLK_TWSI0_BUS] = &twsi0_bus_clk.common.hw, 853 [CLK_TWSI1_BUS] = &twsi1_bus_clk.common.hw, 854 [CLK_TWSI2_BUS] = &twsi2_bus_clk.common.hw, 855 [CLK_TWSI4_BUS] = &twsi4_bus_clk.common.hw, 856 [CLK_TWSI5_BUS] = &twsi5_bus_clk.common.hw, 857 [CLK_TWSI6_BUS] = &twsi6_bus_clk.common.hw, 858 [CLK_TWSI7_BUS] = &twsi7_bus_clk.common.hw, 859 [CLK_TWSI8_BUS] = &twsi8_bus_clk.common.hw, 860 [CLK_TIMERS1_BUS] = &timers1_bus_clk.common.hw, 861 [CLK_TIMERS2_BUS] = &timers2_bus_clk.common.hw, 862 [CLK_AIB_BUS] = &aib_bus_clk.common.hw, 863 [CLK_ONEWIRE_BUS] = &onewire_bus_clk.common.hw, 864 [CLK_SSPA0_BUS] = &sspa0_bus_clk.common.hw, 865 [CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw, 866 [CLK_TSEN_BUS] = &tsen_bus_clk.common.hw, 867 [CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw, 868 }; 869 870 static const struct spacemit_ccu_data k1_ccu_apbc_data = { 871 .reset_name = "apbc-reset", 872 .hws = k1_ccu_apbc_hws, 873 .num = ARRAY_SIZE(k1_ccu_apbc_hws), 874 }; 875 876 static struct clk_hw *k1_ccu_apmu_hws[] = { 877 [CLK_CCI550] = &cci550_clk.common.hw, 878 [CLK_CPU_C0_HI] = &cpu_c0_hi_clk.common.hw, 879 [CLK_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw, 880 [CLK_CPU_C0_ACE] = &cpu_c0_ace_clk.common.hw, 881 [CLK_CPU_C0_TCM] = &cpu_c0_tcm_clk.common.hw, 882 [CLK_CPU_C1_HI] = &cpu_c1_hi_clk.common.hw, 883 [CLK_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw, 884 [CLK_CPU_C1_ACE] = &cpu_c1_ace_clk.common.hw, 885 [CLK_CCIC_4X] = &ccic_4x_clk.common.hw, 886 [CLK_CCIC1PHY] = &ccic1phy_clk.common.hw, 887 [CLK_SDH_AXI] = &sdh_axi_aclk.common.hw, 888 [CLK_SDH0] = &sdh0_clk.common.hw, 889 [CLK_SDH1] = &sdh1_clk.common.hw, 890 [CLK_SDH2] = &sdh2_clk.common.hw, 891 [CLK_USB_P1] = &usb_p1_aclk.common.hw, 892 [CLK_USB_AXI] = &usb_axi_clk.common.hw, 893 [CLK_USB30] = &usb30_clk.common.hw, 894 [CLK_QSPI] = &qspi_clk.common.hw, 895 [CLK_QSPI_BUS] = &qspi_bus_clk.common.hw, 896 [CLK_DMA] = &dma_clk.common.hw, 897 [CLK_AES] = &aes_clk.common.hw, 898 [CLK_VPU] = &vpu_clk.common.hw, 899 [CLK_GPU] = &gpu_clk.common.hw, 900 [CLK_EMMC] = &emmc_clk.common.hw, 901 [CLK_EMMC_X] = &emmc_x_clk.common.hw, 902 [CLK_AUDIO] = &audio_clk.common.hw, 903 [CLK_HDMI] = &hdmi_mclk.common.hw, 904 [CLK_PMUA_ACLK] = &pmua_aclk.common.hw, 905 [CLK_PCIE0_MASTER] = &pcie0_master_clk.common.hw, 906 [CLK_PCIE0_SLAVE] = &pcie0_slave_clk.common.hw, 907 [CLK_PCIE0_DBI] = &pcie0_dbi_clk.common.hw, 908 [CLK_PCIE1_MASTER] = &pcie1_master_clk.common.hw, 909 [CLK_PCIE1_SLAVE] = &pcie1_slave_clk.common.hw, 910 [CLK_PCIE1_DBI] = &pcie1_dbi_clk.common.hw, 911 [CLK_PCIE2_MASTER] = &pcie2_master_clk.common.hw, 912 [CLK_PCIE2_SLAVE] = &pcie2_slave_clk.common.hw, 913 [CLK_PCIE2_DBI] = &pcie2_dbi_clk.common.hw, 914 [CLK_EMAC0_BUS] = &emac0_bus_clk.common.hw, 915 [CLK_EMAC0_PTP] = &emac0_ptp_clk.common.hw, 916 [CLK_EMAC1_BUS] = &emac1_bus_clk.common.hw, 917 [CLK_EMAC1_PTP] = &emac1_ptp_clk.common.hw, 918 [CLK_JPG] = &jpg_clk.common.hw, 919 [CLK_CCIC2PHY] = &ccic2phy_clk.common.hw, 920 [CLK_CCIC3PHY] = &ccic3phy_clk.common.hw, 921 [CLK_CSI] = &csi_clk.common.hw, 922 [CLK_CAMM0] = &camm0_clk.common.hw, 923 [CLK_CAMM1] = &camm1_clk.common.hw, 924 [CLK_CAMM2] = &camm2_clk.common.hw, 925 [CLK_ISP_CPP] = &isp_cpp_clk.common.hw, 926 [CLK_ISP_BUS] = &isp_bus_clk.common.hw, 927 [CLK_ISP] = &isp_clk.common.hw, 928 [CLK_DPU_MCLK] = &dpu_mclk.common.hw, 929 [CLK_DPU_ESC] = &dpu_esc_clk.common.hw, 930 [CLK_DPU_BIT] = &dpu_bit_clk.common.hw, 931 [CLK_DPU_PXCLK] = &dpu_pxclk.common.hw, 932 [CLK_DPU_HCLK] = &dpu_hclk.common.hw, 933 [CLK_DPU_SPI] = &dpu_spi_clk.common.hw, 934 [CLK_DPU_SPI_HBUS] = &dpu_spi_hbus_clk.common.hw, 935 [CLK_DPU_SPIBUS] = &dpu_spi_bus_clk.common.hw, 936 [CLK_DPU_SPI_ACLK] = &dpu_spi_aclk.common.hw, 937 [CLK_V2D] = &v2d_clk.common.hw, 938 [CLK_EMMC_BUS] = &emmc_bus_clk.common.hw, 939 }; 940 941 static const struct spacemit_ccu_data k1_ccu_apmu_data = { 942 .reset_name = "apmu-reset", 943 .hws = k1_ccu_apmu_hws, 944 .num = ARRAY_SIZE(k1_ccu_apmu_hws), 945 }; 946 947 static const struct spacemit_ccu_data k1_ccu_rcpu_data = { 948 .reset_name = "rcpu-reset", 949 }; 950 951 static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { 952 .reset_name = "rcpu2-reset", 953 }; 954 955 static const struct spacemit_ccu_data k1_ccu_apbc2_data = { 956 .reset_name = "apbc2-reset", 957 }; 958 959 static int spacemit_ccu_register(struct device *dev, 960 struct regmap *regmap, 961 struct regmap *lock_regmap, 962 const struct spacemit_ccu_data *data) 963 { 964 struct clk_hw_onecell_data *clk_data; 965 int i, ret; 966 967 /* Nothing to do if the CCU does not implement any clocks */ 968 if (!data->hws) 969 return 0; 970 971 clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), 972 GFP_KERNEL); 973 if (!clk_data) 974 return -ENOMEM; 975 976 for (i = 0; i < data->num; i++) { 977 struct clk_hw *hw = data->hws[i]; 978 struct ccu_common *common; 979 const char *name; 980 981 if (!hw) { 982 clk_data->hws[i] = ERR_PTR(-ENOENT); 983 continue; 984 } 985 986 name = hw->init->name; 987 988 common = hw_to_ccu_common(hw); 989 common->regmap = regmap; 990 common->lock_regmap = lock_regmap; 991 992 ret = devm_clk_hw_register(dev, hw); 993 if (ret) { 994 dev_err(dev, "Cannot register clock %d - %s\n", 995 i, name); 996 return ret; 997 } 998 999 clk_data->hws[i] = hw; 1000 } 1001 1002 clk_data->num = data->num; 1003 1004 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); 1005 if (ret) 1006 dev_err(dev, "failed to add clock hardware provider (%d)\n", ret); 1007 1008 return ret; 1009 } 1010 1011 static void spacemit_cadev_release(struct device *dev) 1012 { 1013 struct auxiliary_device *adev = to_auxiliary_dev(dev); 1014 1015 ida_free(&auxiliary_ids, adev->id); 1016 kfree(to_spacemit_ccu_adev(adev)); 1017 } 1018 1019 static void spacemit_adev_unregister(void *data) 1020 { 1021 struct auxiliary_device *adev = data; 1022 1023 auxiliary_device_delete(adev); 1024 auxiliary_device_uninit(adev); 1025 } 1026 1027 static int spacemit_ccu_reset_register(struct device *dev, 1028 struct regmap *regmap, 1029 const char *reset_name) 1030 { 1031 struct spacemit_ccu_adev *cadev; 1032 struct auxiliary_device *adev; 1033 int ret; 1034 1035 /* Nothing to do if the CCU does not implement a reset controller */ 1036 if (!reset_name) 1037 return 0; 1038 1039 cadev = kzalloc(sizeof(*cadev), GFP_KERNEL); 1040 if (!cadev) 1041 return -ENOMEM; 1042 1043 cadev->regmap = regmap; 1044 1045 adev = &cadev->adev; 1046 adev->name = reset_name; 1047 adev->dev.parent = dev; 1048 adev->dev.release = spacemit_cadev_release; 1049 adev->dev.of_node = dev->of_node; 1050 ret = ida_alloc(&auxiliary_ids, GFP_KERNEL); 1051 if (ret < 0) 1052 goto err_free_cadev; 1053 adev->id = ret; 1054 1055 ret = auxiliary_device_init(adev); 1056 if (ret) 1057 goto err_free_aux_id; 1058 1059 ret = auxiliary_device_add(adev); 1060 if (ret) { 1061 auxiliary_device_uninit(adev); 1062 return ret; 1063 } 1064 1065 return devm_add_action_or_reset(dev, spacemit_adev_unregister, adev); 1066 1067 err_free_aux_id: 1068 ida_free(&auxiliary_ids, adev->id); 1069 err_free_cadev: 1070 kfree(cadev); 1071 1072 return ret; 1073 } 1074 1075 static int k1_ccu_probe(struct platform_device *pdev) 1076 { 1077 struct regmap *base_regmap, *lock_regmap = NULL; 1078 const struct spacemit_ccu_data *data; 1079 struct device *dev = &pdev->dev; 1080 int ret; 1081 1082 base_regmap = device_node_to_regmap(dev->of_node); 1083 if (IS_ERR(base_regmap)) 1084 return dev_err_probe(dev, PTR_ERR(base_regmap), 1085 "failed to get regmap\n"); 1086 1087 /* 1088 * The lock status of PLLs locate in MPMU region, while PLLs themselves 1089 * are in APBS region. Reference to MPMU syscon is required to check PLL 1090 * status. 1091 */ 1092 if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) { 1093 struct device_node *mpmu = of_parse_phandle(dev->of_node, 1094 "spacemit,mpmu", 0); 1095 if (!mpmu) 1096 return dev_err_probe(dev, -ENODEV, 1097 "Cannot parse MPMU region\n"); 1098 1099 lock_regmap = device_node_to_regmap(mpmu); 1100 of_node_put(mpmu); 1101 1102 if (IS_ERR(lock_regmap)) 1103 return dev_err_probe(dev, PTR_ERR(lock_regmap), 1104 "failed to get lock regmap\n"); 1105 } 1106 1107 data = of_device_get_match_data(dev); 1108 1109 ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); 1110 if (ret) 1111 return dev_err_probe(dev, ret, "failed to register clocks\n"); 1112 1113 ret = spacemit_ccu_reset_register(dev, base_regmap, data->reset_name); 1114 if (ret) 1115 return dev_err_probe(dev, ret, "failed to register resets\n"); 1116 1117 return 0; 1118 } 1119 1120 static const struct of_device_id of_k1_ccu_match[] = { 1121 { 1122 .compatible = "spacemit,k1-pll", 1123 .data = &k1_ccu_pll_data, 1124 }, 1125 { 1126 .compatible = "spacemit,k1-syscon-mpmu", 1127 .data = &k1_ccu_mpmu_data, 1128 }, 1129 { 1130 .compatible = "spacemit,k1-syscon-apbc", 1131 .data = &k1_ccu_apbc_data, 1132 }, 1133 { 1134 .compatible = "spacemit,k1-syscon-apmu", 1135 .data = &k1_ccu_apmu_data, 1136 }, 1137 { 1138 .compatible = "spacemit,k1-syscon-rcpu", 1139 .data = &k1_ccu_rcpu_data, 1140 }, 1141 { 1142 .compatible = "spacemit,k1-syscon-rcpu2", 1143 .data = &k1_ccu_rcpu2_data, 1144 }, 1145 { 1146 .compatible = "spacemit,k1-syscon-apbc2", 1147 .data = &k1_ccu_apbc2_data, 1148 }, 1149 { } 1150 }; 1151 MODULE_DEVICE_TABLE(of, of_k1_ccu_match); 1152 1153 static struct platform_driver k1_ccu_driver = { 1154 .driver = { 1155 .name = "spacemit,k1-ccu", 1156 .of_match_table = of_k1_ccu_match, 1157 }, 1158 .probe = k1_ccu_probe, 1159 }; 1160 module_platform_driver(k1_ccu_driver); 1161 1162 MODULE_DESCRIPTION("SpacemiT K1 CCU driver"); 1163 MODULE_AUTHOR("Haylen Chu <heylenay@4d2.org>"); 1164 MODULE_LICENSE("GPL"); 1165