180fd61ecSInochi Amaoto# SPDX-License-Identifier: GPL-2.0 280fd61ecSInochi Amaoto# common clock support for SOPHGO SoC family. 380fd61ecSInochi Amaoto 480fd61ecSInochi Amaotoconfig CLK_SOPHGO_CV1800 580fd61ecSInochi Amaoto tristate "Support for the Sophgo CV1800 series SoCs clock controller" 680fd61ecSInochi Amaoto depends on ARCH_SOPHGO || COMPILE_TEST 780fd61ecSInochi Amaoto help 880fd61ecSInochi Amaoto This driver supports clock controller of Sophgo CV18XX series SoC. 980fd61ecSInochi Amaoto The driver require a 25MHz Oscillator to function generate clock. 1080fd61ecSInochi Amaoto It includes PLLs, common clock function and some vendor clock for 1180fd61ecSInochi Amaoto IPs of CV18XX series SoC 1248cf7e01SChen Wang 1348cf7e01SChen Wangconfig CLK_SOPHGO_SG2042_PLL 1448cf7e01SChen Wang tristate "Sophgo SG2042 PLL clock support" 1548cf7e01SChen Wang depends on ARCH_SOPHGO || COMPILE_TEST 1648cf7e01SChen Wang help 1748cf7e01SChen Wang This driver supports the PLL clock controller on the 1848cf7e01SChen Wang Sophgo SG2042 SoC. This clock IP uses three oscillators with 1948cf7e01SChen Wang frequency of 25 MHz as input, which are used for Main/Fixed 2048cf7e01SChen Wang PLL, DDR PLL 0 and DDR PLL 1 respectively. 2148cf7e01SChen Wang 2248cf7e01SChen Wangconfig CLK_SOPHGO_SG2042_CLKGEN 2348cf7e01SChen Wang tristate "Sophgo SG2042 Clock Generator support" 2448cf7e01SChen Wang depends on CLK_SOPHGO_SG2042_PLL 2548cf7e01SChen Wang help 2648cf7e01SChen Wang This driver supports the Clock Generator on the 2748cf7e01SChen Wang Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock 2848cf7e01SChen Wang because it uses PLL clocks as input. 2948cf7e01SChen Wang This driver provides clock function such as DIV/Mux/Gate. 3048cf7e01SChen Wang 3148cf7e01SChen Wangconfig CLK_SOPHGO_SG2042_RPGATE 3248cf7e01SChen Wang tristate "Sophgo SG2042 RP subsystem clock controller support" 3348cf7e01SChen Wang depends on CLK_SOPHGO_SG2042_CLKGEN 3448cf7e01SChen Wang help 3548cf7e01SChen Wang This driver supports the RP((Riscv Processors)) subsystem clock 3648cf7e01SChen Wang controller on the Sophgo SG2042 SoC. 3748cf7e01SChen Wang This clock IP depends on SG2042 Clock Generator because it uses 3848cf7e01SChen Wang clock from Clock Generator IP as input. 3948cf7e01SChen Wang This driver provides Gate function for RP. 40*ff524079SInochi Amaoto 41*ff524079SInochi Amaotoconfig CLK_SOPHGO_SG2044_PLL 42*ff524079SInochi Amaoto tristate "Sophgo SG2044 PLL clock controller support" 43*ff524079SInochi Amaoto depends on ARCH_SOPHGO || COMPILE_TEST 44*ff524079SInochi Amaoto select MFD_SYSCON 45*ff524079SInochi Amaoto select REGMAP_MMIO 46*ff524079SInochi Amaoto help 47*ff524079SInochi Amaoto This driver supports the PLL clock controller on the Sophgo 48*ff524079SInochi Amaoto SG2044 SoC. This controller requires 25M oscillator as input. 49*ff524079SInochi Amaoto This clock control provides PLL clocks on the SoC. 50