180fd61ecSInochi Amaoto# SPDX-License-Identifier: GPL-2.0 280fd61ecSInochi Amaoto# common clock support for SOPHGO SoC family. 380fd61ecSInochi Amaoto 480fd61ecSInochi Amaotoconfig CLK_SOPHGO_CV1800 580fd61ecSInochi Amaoto tristate "Support for the Sophgo CV1800 series SoCs clock controller" 680fd61ecSInochi Amaoto depends on ARCH_SOPHGO || COMPILE_TEST 780fd61ecSInochi Amaoto help 880fd61ecSInochi Amaoto This driver supports clock controller of Sophgo CV18XX series SoC. 980fd61ecSInochi Amaoto The driver require a 25MHz Oscillator to function generate clock. 1080fd61ecSInochi Amaoto It includes PLLs, common clock function and some vendor clock for 1180fd61ecSInochi Amaoto IPs of CV18XX series SoC 12*48cf7e01SChen Wang 13*48cf7e01SChen Wangconfig CLK_SOPHGO_SG2042_PLL 14*48cf7e01SChen Wang tristate "Sophgo SG2042 PLL clock support" 15*48cf7e01SChen Wang depends on ARCH_SOPHGO || COMPILE_TEST 16*48cf7e01SChen Wang help 17*48cf7e01SChen Wang This driver supports the PLL clock controller on the 18*48cf7e01SChen Wang Sophgo SG2042 SoC. This clock IP uses three oscillators with 19*48cf7e01SChen Wang frequency of 25 MHz as input, which are used for Main/Fixed 20*48cf7e01SChen Wang PLL, DDR PLL 0 and DDR PLL 1 respectively. 21*48cf7e01SChen Wang 22*48cf7e01SChen Wangconfig CLK_SOPHGO_SG2042_CLKGEN 23*48cf7e01SChen Wang tristate "Sophgo SG2042 Clock Generator support" 24*48cf7e01SChen Wang depends on CLK_SOPHGO_SG2042_PLL 25*48cf7e01SChen Wang help 26*48cf7e01SChen Wang This driver supports the Clock Generator on the 27*48cf7e01SChen Wang Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock 28*48cf7e01SChen Wang because it uses PLL clocks as input. 29*48cf7e01SChen Wang This driver provides clock function such as DIV/Mux/Gate. 30*48cf7e01SChen Wang 31*48cf7e01SChen Wangconfig CLK_SOPHGO_SG2042_RPGATE 32*48cf7e01SChen Wang tristate "Sophgo SG2042 RP subsystem clock controller support" 33*48cf7e01SChen Wang depends on CLK_SOPHGO_SG2042_CLKGEN 34*48cf7e01SChen Wang help 35*48cf7e01SChen Wang This driver supports the RP((Riscv Processors)) subsystem clock 36*48cf7e01SChen Wang controller on the Sophgo SG2042 SoC. 37*48cf7e01SChen Wang This clock IP depends on SG2042 Clock Generator because it uses 38*48cf7e01SChen Wang clock from Clock Generator IP as input. 39*48cf7e01SChen Wang This driver provides Gate function for RP. 40