1*66314223SDinh Nguyen /* 2*66314223SDinh Nguyen * Copyright (C) 2012 Altera Corporation <www.altera.com> 3*66314223SDinh Nguyen * 4*66314223SDinh Nguyen * This program is free software; you can redistribute it and/or modify 5*66314223SDinh Nguyen * it under the terms of the GNU General Public License as published by 6*66314223SDinh Nguyen * the Free Software Foundation; either version 2 of the License, or 7*66314223SDinh Nguyen * (at your option) any later version. 8*66314223SDinh Nguyen * 9*66314223SDinh Nguyen * This program is distributed in the hope that it will be useful, 10*66314223SDinh Nguyen * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*66314223SDinh Nguyen * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*66314223SDinh Nguyen * GNU General Public License for more details. 13*66314223SDinh Nguyen * 14*66314223SDinh Nguyen * You should have received a copy of the GNU General Public License 15*66314223SDinh Nguyen * along with this program. If not, see <http://www.gnu.org/licenses/>. 16*66314223SDinh Nguyen */ 17*66314223SDinh Nguyen #include <linux/clk.h> 18*66314223SDinh Nguyen #include <linux/clkdev.h> 19*66314223SDinh Nguyen #include <linux/clk-provider.h> 20*66314223SDinh Nguyen 21*66314223SDinh Nguyen #define SOCFPGA_OSC1_CLK 10000000 22*66314223SDinh Nguyen #define SOCFPGA_MPU_CLK 800000000 23*66314223SDinh Nguyen #define SOCFPGA_MAIN_QSPI_CLK 432000000 24*66314223SDinh Nguyen #define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000 25*66314223SDinh Nguyen #define SOCFPGA_S2F_USR_CLK 125000000 26*66314223SDinh Nguyen 27*66314223SDinh Nguyen void __init socfpga_init_clocks(void) 28*66314223SDinh Nguyen { 29*66314223SDinh Nguyen struct clk *clk; 30*66314223SDinh Nguyen 31*66314223SDinh Nguyen clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK); 32*66314223SDinh Nguyen clk_register_clkdev(clk, "osc1_clk", NULL); 33*66314223SDinh Nguyen 34*66314223SDinh Nguyen clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK); 35*66314223SDinh Nguyen clk_register_clkdev(clk, "mpu_clk", NULL); 36*66314223SDinh Nguyen 37*66314223SDinh Nguyen clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2); 38*66314223SDinh Nguyen clk_register_clkdev(clk, "main_clk", NULL); 39*66314223SDinh Nguyen 40*66314223SDinh Nguyen clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2); 41*66314223SDinh Nguyen clk_register_clkdev(clk, "dbg_base_clk", NULL); 42*66314223SDinh Nguyen 43*66314223SDinh Nguyen clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK); 44*66314223SDinh Nguyen clk_register_clkdev(clk, "main_qspi_clk", NULL); 45*66314223SDinh Nguyen 46*66314223SDinh Nguyen clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK); 47*66314223SDinh Nguyen clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL); 48*66314223SDinh Nguyen 49*66314223SDinh Nguyen clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK); 50*66314223SDinh Nguyen clk_register_clkdev(clk, "s2f_usr_clk", NULL); 51*66314223SDinh Nguyen } 52