1 /* 2 * Copyright (C) 2015 Altera Corporation. All rights reserved 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/of.h> 20 #include <linux/regmap.h> 21 22 #include "clk.h" 23 24 #define streq(a, b) (strcmp((a), (b)) == 0) 25 26 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) 27 28 /* SDMMC Group for System Manager defines */ 29 #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28 30 31 static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, 32 unsigned long parent_rate) 33 { 34 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 35 u32 div = 1, val; 36 37 if (socfpgaclk->fixed_div) 38 div = socfpgaclk->fixed_div; 39 else if (socfpgaclk->div_reg) { 40 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; 41 val &= div_mask(socfpgaclk->width); 42 div = (1 << val); 43 } 44 45 return parent_rate / div; 46 } 47 48 static int socfpga_clk_prepare(struct clk_hw *hwclk) 49 { 50 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 51 int i; 52 u32 hs_timing; 53 u32 clk_phase[2]; 54 55 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { 56 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { 57 switch (socfpgaclk->clk_phase[i]) { 58 case 0: 59 clk_phase[i] = 0; 60 break; 61 case 45: 62 clk_phase[i] = 1; 63 break; 64 case 90: 65 clk_phase[i] = 2; 66 break; 67 case 135: 68 clk_phase[i] = 3; 69 break; 70 case 180: 71 clk_phase[i] = 4; 72 break; 73 case 225: 74 clk_phase[i] = 5; 75 break; 76 case 270: 77 clk_phase[i] = 6; 78 break; 79 case 315: 80 clk_phase[i] = 7; 81 break; 82 default: 83 clk_phase[i] = 0; 84 break; 85 } 86 } 87 88 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); 89 if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) 90 regmap_write(socfpgaclk->sys_mgr_base_addr, 91 SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); 92 else 93 pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n", 94 __func__); 95 } 96 return 0; 97 } 98 99 static struct clk_ops gateclk_ops = { 100 .prepare = socfpga_clk_prepare, 101 .recalc_rate = socfpga_gate_clk_recalc_rate, 102 }; 103 104 static void __init __socfpga_gate_init(struct device_node *node, 105 const struct clk_ops *ops) 106 { 107 u32 clk_gate[2]; 108 u32 div_reg[3]; 109 u32 clk_phase[2]; 110 u32 fixed_div; 111 struct clk *clk; 112 struct socfpga_gate_clk *socfpga_clk; 113 const char *clk_name = node->name; 114 const char *parent_name[SOCFPGA_MAX_PARENTS]; 115 struct clk_init_data init; 116 int rc; 117 int i = 0; 118 119 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); 120 if (WARN_ON(!socfpga_clk)) 121 return; 122 123 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); 124 if (rc) 125 clk_gate[0] = 0; 126 127 if (clk_gate[0]) { 128 socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0]; 129 socfpga_clk->hw.bit_idx = clk_gate[1]; 130 131 gateclk_ops.enable = clk_gate_ops.enable; 132 gateclk_ops.disable = clk_gate_ops.disable; 133 } 134 135 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 136 if (rc) 137 socfpga_clk->fixed_div = 0; 138 else 139 socfpga_clk->fixed_div = fixed_div; 140 141 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); 142 if (!rc) { 143 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; 144 socfpga_clk->shift = div_reg[1]; 145 socfpga_clk->width = div_reg[2]; 146 } else { 147 socfpga_clk->div_reg = NULL; 148 } 149 150 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); 151 if (!rc) { 152 socfpga_clk->clk_phase[0] = clk_phase[0]; 153 socfpga_clk->clk_phase[1] = clk_phase[1]; 154 155 socfpga_clk->sys_mgr_base_addr = 156 syscon_regmap_lookup_by_compatible("altr,sys-mgr"); 157 if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) { 158 pr_err("%s: failed to find altr,sys-mgr regmap!\n", 159 __func__); 160 return; 161 } 162 } 163 164 of_property_read_string(node, "clock-output-names", &clk_name); 165 166 init.name = clk_name; 167 init.ops = ops; 168 init.flags = 0; 169 while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] = 170 of_clk_get_parent_name(node, i)) != NULL) 171 i++; 172 173 init.parent_names = parent_name; 174 init.num_parents = i; 175 socfpga_clk->hw.hw.init = &init; 176 177 clk = clk_register(NULL, &socfpga_clk->hw.hw); 178 if (WARN_ON(IS_ERR(clk))) { 179 kfree(socfpga_clk); 180 return; 181 } 182 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 183 if (WARN_ON(rc)) 184 return; 185 } 186 187 void __init socfpga_a10_gate_init(struct device_node *node) 188 { 189 __socfpga_gate_init(node, &gateclk_ops); 190 } 191