13b218baaSKrzysztof Kozlowski# SPDX-License-Identifier: GPL-2.0 2*cdb1e8b4SKrzysztof Kozlowskiconfig CLK_INTEL_SOCFPGA 3*cdb1e8b4SKrzysztof Kozlowski bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_INTEL_SOCFPGA 4*cdb1e8b4SKrzysztof Kozlowski default ARCH_INTEL_SOCFPGA 5*cdb1e8b4SKrzysztof Kozlowski help 6*cdb1e8b4SKrzysztof Kozlowski Support for the clock controllers present on Intel SoCFPGA and eASIC 7*cdb1e8b4SKrzysztof Kozlowski devices like Stratix 10, Agilex and N5X eASIC. 8*cdb1e8b4SKrzysztof Kozlowski 9*cdb1e8b4SKrzysztof Kozlowskiif CLK_INTEL_SOCFPGA 10*cdb1e8b4SKrzysztof Kozlowski 113b218baaSKrzysztof Kozlowskiconfig CLK_INTEL_SOCFPGA64 12*cdb1e8b4SKrzysztof Kozlowski bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA) 134a9a1a56SKrzysztof Kozlowski default ARM64 && ARCH_INTEL_SOCFPGA 14*cdb1e8b4SKrzysztof Kozlowski 15*cdb1e8b4SKrzysztof Kozlowskiendif # CLK_INTEL_SOCFPGA 16