1c816e1ddSZong Li /* SPDX-License-Identifier: GPL-2.0 */ 2c816e1ddSZong Li /* 3c816e1ddSZong Li * Copyright (C) 2018-2019 SiFive, Inc. 4c816e1ddSZong Li * Wesley Terpstra 5c816e1ddSZong Li * Paul Walmsley 6c816e1ddSZong Li * Zong Li 7c816e1ddSZong Li */ 8c816e1ddSZong Li 9c816e1ddSZong Li #ifndef __SIFIVE_CLK_SIFIVE_PRCI_H 10c816e1ddSZong Li #define __SIFIVE_CLK_SIFIVE_PRCI_H 11c816e1ddSZong Li 12c816e1ddSZong Li #include <linux/clk/analogbits-wrpll-cln28hpc.h> 13c816e1ddSZong Li #include <linux/clk-provider.h> 14c816e1ddSZong Li #include <linux/platform_device.h> 15c816e1ddSZong Li 16c816e1ddSZong Li /* 17c816e1ddSZong Li * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: 18c816e1ddSZong Li * hfclk and rtcclk 19c816e1ddSZong Li */ 20c816e1ddSZong Li #define EXPECTED_CLK_PARENT_COUNT 2 21c816e1ddSZong Li 22c816e1ddSZong Li /* 23c816e1ddSZong Li * Register offsets and bitmasks 24c816e1ddSZong Li */ 25c816e1ddSZong Li 26c816e1ddSZong Li /* COREPLLCFG0 */ 27c816e1ddSZong Li #define PRCI_COREPLLCFG0_OFFSET 0x4 28c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVR_SHIFT 0 29c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) 30c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVF_SHIFT 6 31c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) 32c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 33c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) 34c816e1ddSZong Li #define PRCI_COREPLLCFG0_RANGE_SHIFT 18 35c816e1ddSZong Li #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) 36c816e1ddSZong Li #define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 37c816e1ddSZong Li #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) 38c816e1ddSZong Li #define PRCI_COREPLLCFG0_FSE_SHIFT 25 39c816e1ddSZong Li #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) 40c816e1ddSZong Li #define PRCI_COREPLLCFG0_LOCK_SHIFT 31 41c816e1ddSZong Li #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) 42c816e1ddSZong Li 43732374a0SPragnesh Patel /* COREPLLCFG1 */ 44732374a0SPragnesh Patel #define PRCI_COREPLLCFG1_OFFSET 0x8 45732374a0SPragnesh Patel #define PRCI_COREPLLCFG1_CKE_SHIFT 31 46732374a0SPragnesh Patel #define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) 47732374a0SPragnesh Patel 48c816e1ddSZong Li /* DDRPLLCFG0 */ 49c816e1ddSZong Li #define PRCI_DDRPLLCFG0_OFFSET 0xc 50c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 51c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) 52c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 53c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) 54c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 55c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) 56c816e1ddSZong Li #define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 57c816e1ddSZong Li #define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) 58c816e1ddSZong Li #define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 59c816e1ddSZong Li #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) 60c816e1ddSZong Li #define PRCI_DDRPLLCFG0_FSE_SHIFT 25 61c816e1ddSZong Li #define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) 62c816e1ddSZong Li #define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 63c816e1ddSZong Li #define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) 64c816e1ddSZong Li 65c816e1ddSZong Li /* DDRPLLCFG1 */ 66c816e1ddSZong Li #define PRCI_DDRPLLCFG1_OFFSET 0x10 67263ac390SZong Li #define PRCI_DDRPLLCFG1_CKE_SHIFT 31 68c816e1ddSZong Li #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) 69c816e1ddSZong Li 70*c61287bfSGreentime Hu /* PCIEAUX */ 71*c61287bfSGreentime Hu #define PRCI_PCIE_AUX_OFFSET 0x14 72*c61287bfSGreentime Hu #define PRCI_PCIE_AUX_EN_SHIFT 0 73*c61287bfSGreentime Hu #define PRCI_PCIE_AUX_EN_MASK (0x1 << PRCI_PCIE_AUX_EN_SHIFT) 74*c61287bfSGreentime Hu 75c816e1ddSZong Li /* GEMGXLPLLCFG0 */ 76c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c 77c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 78c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) 79c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 80c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) 81c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 82c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) 83c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 84c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) 85c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 86c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) 87c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 88c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) 89c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 90c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) 91c816e1ddSZong Li 92c816e1ddSZong Li /* GEMGXLPLLCFG1 */ 93c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 94263ac390SZong Li #define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 95c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) 96c816e1ddSZong Li 97c816e1ddSZong Li /* CORECLKSEL */ 98c816e1ddSZong Li #define PRCI_CORECLKSEL_OFFSET 0x24 99c816e1ddSZong Li #define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 100c816e1ddSZong Li #define PRCI_CORECLKSEL_CORECLKSEL_MASK \ 101c816e1ddSZong Li (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) 102c816e1ddSZong Li 103c816e1ddSZong Li /* DEVICESRESETREG */ 104c816e1ddSZong Li #define PRCI_DEVICESRESETREG_OFFSET 0x28 105c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 106c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ 107c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) 108c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 109c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ 110c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) 111c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 112c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ 113c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) 114c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 115c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ 116c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) 117c816e1ddSZong Li #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 118c816e1ddSZong Li #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ 119c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) 120c816e1ddSZong Li #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT 6 121c816e1ddSZong Li #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ 122c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) 123c816e1ddSZong Li 124c816e1ddSZong Li /* CLKMUXSTATUSREG */ 125c816e1ddSZong Li #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c 126c816e1ddSZong Li #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 127c816e1ddSZong Li #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ 128c816e1ddSZong Li (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) 129c816e1ddSZong Li 130efc91ae4SZong Li /* CLTXPLLCFG0 */ 131efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_OFFSET 0x30 132efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0 133efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT) 134efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6 135efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT) 136efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15 137efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT) 138efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18 139efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT) 140efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24 141efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT) 142efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_FSE_SHIFT 25 143efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT) 144efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31 145efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT) 146efc91ae4SZong Li 147efc91ae4SZong Li /* CLTXPLLCFG1 */ 148efc91ae4SZong Li #define PRCI_CLTXPLLCFG1_OFFSET 0x34 149efc91ae4SZong Li #define PRCI_CLTXPLLCFG1_CKE_SHIFT 31 150efc91ae4SZong Li #define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT) 151efc91ae4SZong Li 152efc91ae4SZong Li /* DVFSCOREPLLCFG0 */ 153efc91ae4SZong Li #define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38 154efc91ae4SZong Li 155efc91ae4SZong Li /* DVFSCOREPLLCFG1 */ 156efc91ae4SZong Li #define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c 157efc91ae4SZong Li #define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 31 158efc91ae4SZong Li #define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT) 159efc91ae4SZong Li 160efc91ae4SZong Li /* COREPLLSEL */ 161efc91ae4SZong Li #define PRCI_COREPLLSEL_OFFSET 0x40 162efc91ae4SZong Li #define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0 163efc91ae4SZong Li #define PRCI_COREPLLSEL_COREPLLSEL_MASK \ 164efc91ae4SZong Li (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT) 165efc91ae4SZong Li 166efc91ae4SZong Li /* HFPCLKPLLCFG0 */ 167efc91ae4SZong Li #define PRCI_HFPCLKPLLCFG0_OFFSET 0x50 168efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0 169efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \ 170efc91ae4SZong Li (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT) 171efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6 172efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \ 173efc91ae4SZong Li (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT) 174efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15 175efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \ 176efc91ae4SZong Li (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT) 177efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18 178efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \ 179efc91ae4SZong Li (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT) 180efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24 181efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \ 182efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT) 183efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25 184efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_FSE_MASK \ 185efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT) 186efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31 187efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \ 188efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT) 189efc91ae4SZong Li 190efc91ae4SZong Li /* HFPCLKPLLCFG1 */ 191efc91ae4SZong Li #define PRCI_HFPCLKPLLCFG1_OFFSET 0x54 192efc91ae4SZong Li #define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 31 193efc91ae4SZong Li #define PRCI_HFPCLKPLLCFG1_CKE_MASK \ 194efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT) 195efc91ae4SZong Li 196efc91ae4SZong Li /* HFPCLKPLLSEL */ 197efc91ae4SZong Li #define PRCI_HFPCLKPLLSEL_OFFSET 0x58 198efc91ae4SZong Li #define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0 199efc91ae4SZong Li #define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \ 200efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT) 201efc91ae4SZong Li 202efc91ae4SZong Li /* HFPCLKPLLDIV */ 203efc91ae4SZong Li #define PRCI_HFPCLKPLLDIV_OFFSET 0x5c 204efc91ae4SZong Li 205efc91ae4SZong Li /* PRCIPLL */ 206efc91ae4SZong Li #define PRCI_PRCIPLL_OFFSET 0xe0 207efc91ae4SZong Li 208efc91ae4SZong Li /* PROCMONCFG */ 209efc91ae4SZong Li #define PRCI_PROCMONCFG_OFFSET 0xf0 210efc91ae4SZong Li 211c816e1ddSZong Li /* 212c816e1ddSZong Li * Private structures 213c816e1ddSZong Li */ 214c816e1ddSZong Li 215c816e1ddSZong Li /** 216c816e1ddSZong Li * struct __prci_data - per-device-instance data 217c816e1ddSZong Li * @va: base virtual address of the PRCI IP block 218c816e1ddSZong Li * @hw_clks: encapsulates struct clk_hw records 219c816e1ddSZong Li * 220c816e1ddSZong Li * PRCI per-device instance data 221c816e1ddSZong Li */ 222c816e1ddSZong Li struct __prci_data { 223c816e1ddSZong Li void __iomem *va; 224c816e1ddSZong Li struct clk_hw_onecell_data hw_clks; 225c816e1ddSZong Li }; 226c816e1ddSZong Li 227c816e1ddSZong Li /** 228c816e1ddSZong Li * struct __prci_wrpll_data - WRPLL configuration and integration data 229c816e1ddSZong Li * @c: WRPLL current configuration record 230c816e1ddSZong Li * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) 231c816e1ddSZong Li * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) 232c816e1ddSZong Li * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address 233732374a0SPragnesh Patel * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address 234c816e1ddSZong Li * 235c816e1ddSZong Li * @enable_bypass and @disable_bypass are used for WRPLL instances 236c816e1ddSZong Li * that contain a separate external glitchless clock mux downstream 237c816e1ddSZong Li * from the PLL. The WRPLL internal bypass mux is not glitchless. 238c816e1ddSZong Li */ 239c816e1ddSZong Li struct __prci_wrpll_data { 240c816e1ddSZong Li struct wrpll_cfg c; 241c816e1ddSZong Li void (*enable_bypass)(struct __prci_data *pd); 242c816e1ddSZong Li void (*disable_bypass)(struct __prci_data *pd); 243c816e1ddSZong Li u8 cfg0_offs; 244732374a0SPragnesh Patel u8 cfg1_offs; 245c816e1ddSZong Li }; 246c816e1ddSZong Li 247c816e1ddSZong Li /** 248c816e1ddSZong Li * struct __prci_clock - describes a clock device managed by PRCI 249c816e1ddSZong Li * @name: user-readable clock name string - should match the manual 250c816e1ddSZong Li * @parent_name: parent name for this clock 251c816e1ddSZong Li * @ops: struct clk_ops for the Linux clock framework to use for control 252c816e1ddSZong Li * @hw: Linux-private clock data 253c816e1ddSZong Li * @pwd: WRPLL-specific data, associated with this clock (if not NULL) 254c816e1ddSZong Li * @pd: PRCI-specific data associated with this clock (if not NULL) 255c816e1ddSZong Li * 256c816e1ddSZong Li * PRCI clock data. Used by the PRCI driver to register PRCI-provided 257c816e1ddSZong Li * clocks to the Linux clock infrastructure. 258c816e1ddSZong Li */ 259c816e1ddSZong Li struct __prci_clock { 260c816e1ddSZong Li const char *name; 261c816e1ddSZong Li const char *parent_name; 262c816e1ddSZong Li const struct clk_ops *ops; 263c816e1ddSZong Li struct clk_hw hw; 264c816e1ddSZong Li struct __prci_wrpll_data *pwd; 265c816e1ddSZong Li struct __prci_data *pd; 266c816e1ddSZong Li }; 267c816e1ddSZong Li 268c816e1ddSZong Li #define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw) 269c816e1ddSZong Li 270c816e1ddSZong Li /* 271c816e1ddSZong Li * struct prci_clk_desc - describes the information of clocks of each SoCs 272c816e1ddSZong Li * @clks: point to a array of __prci_clock 273c816e1ddSZong Li * @num_clks: the number of element of clks 274c816e1ddSZong Li */ 275c816e1ddSZong Li struct prci_clk_desc { 276c816e1ddSZong Li struct __prci_clock *clks; 277c816e1ddSZong Li size_t num_clks; 278c816e1ddSZong Li }; 279c816e1ddSZong Li 280c816e1ddSZong Li /* Core clock mux control */ 281c816e1ddSZong Li void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd); 282c816e1ddSZong Li void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd); 283efc91ae4SZong Li void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd); 284efc91ae4SZong Li void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd); 285efc91ae4SZong Li void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd); 286efc91ae4SZong Li void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd); 287efc91ae4SZong Li void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd); 288c816e1ddSZong Li 289c816e1ddSZong Li /* Linux clock framework integration */ 290c816e1ddSZong Li long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate, 291c816e1ddSZong Li unsigned long *parent_rate); 292c816e1ddSZong Li int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate, 293c816e1ddSZong Li unsigned long parent_rate); 294732374a0SPragnesh Patel int sifive_clk_is_enabled(struct clk_hw *hw); 295732374a0SPragnesh Patel int sifive_prci_clock_enable(struct clk_hw *hw); 296732374a0SPragnesh Patel void sifive_prci_clock_disable(struct clk_hw *hw); 297c816e1ddSZong Li unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw, 298c816e1ddSZong Li unsigned long parent_rate); 299c816e1ddSZong Li unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw, 300c816e1ddSZong Li unsigned long parent_rate); 301efc91ae4SZong Li unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw, 302efc91ae4SZong Li unsigned long parent_rate); 303c816e1ddSZong Li 304*c61287bfSGreentime Hu int sifive_prci_pcie_aux_clock_is_enabled(struct clk_hw *hw); 305*c61287bfSGreentime Hu int sifive_prci_pcie_aux_clock_enable(struct clk_hw *hw); 306*c61287bfSGreentime Hu void sifive_prci_pcie_aux_clock_disable(struct clk_hw *hw); 307*c61287bfSGreentime Hu 308c816e1ddSZong Li #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ 309