1c816e1ddSZong Li /* SPDX-License-Identifier: GPL-2.0 */ 2c816e1ddSZong Li /* 3c816e1ddSZong Li * Copyright (C) 2018-2019 SiFive, Inc. 4c816e1ddSZong Li * Wesley Terpstra 5c816e1ddSZong Li * Paul Walmsley 6c816e1ddSZong Li * Zong Li 7c816e1ddSZong Li */ 8c816e1ddSZong Li 9c816e1ddSZong Li #ifndef __SIFIVE_CLK_SIFIVE_PRCI_H 10c816e1ddSZong Li #define __SIFIVE_CLK_SIFIVE_PRCI_H 11c816e1ddSZong Li 12c816e1ddSZong Li #include <linux/clk/analogbits-wrpll-cln28hpc.h> 13c816e1ddSZong Li #include <linux/clk-provider.h> 14c816e1ddSZong Li #include <linux/platform_device.h> 15c816e1ddSZong Li 16c816e1ddSZong Li /* 17c816e1ddSZong Li * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: 18c816e1ddSZong Li * hfclk and rtcclk 19c816e1ddSZong Li */ 20c816e1ddSZong Li #define EXPECTED_CLK_PARENT_COUNT 2 21c816e1ddSZong Li 22c816e1ddSZong Li /* 23c816e1ddSZong Li * Register offsets and bitmasks 24c816e1ddSZong Li */ 25c816e1ddSZong Li 26c816e1ddSZong Li /* COREPLLCFG0 */ 27c816e1ddSZong Li #define PRCI_COREPLLCFG0_OFFSET 0x4 28c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVR_SHIFT 0 29c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) 30c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVF_SHIFT 6 31c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) 32c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 33c816e1ddSZong Li #define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) 34c816e1ddSZong Li #define PRCI_COREPLLCFG0_RANGE_SHIFT 18 35c816e1ddSZong Li #define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) 36c816e1ddSZong Li #define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 37c816e1ddSZong Li #define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) 38c816e1ddSZong Li #define PRCI_COREPLLCFG0_FSE_SHIFT 25 39c816e1ddSZong Li #define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) 40c816e1ddSZong Li #define PRCI_COREPLLCFG0_LOCK_SHIFT 31 41c816e1ddSZong Li #define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) 42c816e1ddSZong Li 43*732374a0SPragnesh Patel /* COREPLLCFG1 */ 44*732374a0SPragnesh Patel #define PRCI_COREPLLCFG1_OFFSET 0x8 45*732374a0SPragnesh Patel #define PRCI_COREPLLCFG1_CKE_SHIFT 31 46*732374a0SPragnesh Patel #define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) 47*732374a0SPragnesh Patel 48c816e1ddSZong Li /* DDRPLLCFG0 */ 49c816e1ddSZong Li #define PRCI_DDRPLLCFG0_OFFSET 0xc 50c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 51c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) 52c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 53c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) 54c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 55c816e1ddSZong Li #define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) 56c816e1ddSZong Li #define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 57c816e1ddSZong Li #define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) 58c816e1ddSZong Li #define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 59c816e1ddSZong Li #define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) 60c816e1ddSZong Li #define PRCI_DDRPLLCFG0_FSE_SHIFT 25 61c816e1ddSZong Li #define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) 62c816e1ddSZong Li #define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 63c816e1ddSZong Li #define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) 64c816e1ddSZong Li 65c816e1ddSZong Li /* DDRPLLCFG1 */ 66c816e1ddSZong Li #define PRCI_DDRPLLCFG1_OFFSET 0x10 67263ac390SZong Li #define PRCI_DDRPLLCFG1_CKE_SHIFT 31 68c816e1ddSZong Li #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) 69c816e1ddSZong Li 70c816e1ddSZong Li /* GEMGXLPLLCFG0 */ 71c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c 72c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 73c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVR_MASK (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) 74c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 75c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVF_MASK (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) 76c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 77c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) 78c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 79c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_RANGE_MASK (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) 80c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 81c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_BYPASS_MASK (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) 82c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 83c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_FSE_MASK (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) 84c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 85c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) 86c816e1ddSZong Li 87c816e1ddSZong Li /* GEMGXLPLLCFG1 */ 88c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 89263ac390SZong Li #define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 90c816e1ddSZong Li #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) 91c816e1ddSZong Li 92c816e1ddSZong Li /* CORECLKSEL */ 93c816e1ddSZong Li #define PRCI_CORECLKSEL_OFFSET 0x24 94c816e1ddSZong Li #define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 95c816e1ddSZong Li #define PRCI_CORECLKSEL_CORECLKSEL_MASK \ 96c816e1ddSZong Li (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) 97c816e1ddSZong Li 98c816e1ddSZong Li /* DEVICESRESETREG */ 99c816e1ddSZong Li #define PRCI_DEVICESRESETREG_OFFSET 0x28 100c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 101c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ 102c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) 103c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 104c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ 105c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) 106c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 107c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ 108c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) 109c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 110c816e1ddSZong Li #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ 111c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) 112c816e1ddSZong Li #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 113c816e1ddSZong Li #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ 114c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) 115c816e1ddSZong Li #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT 6 116c816e1ddSZong Li #define PRCI_DEVICESRESETREG_CHIPLINK_RST_N_MASK \ 117c816e1ddSZong Li (0x1 << PRCI_DEVICESRESETREG_CHIPLINK_RST_N_SHIFT) 118c816e1ddSZong Li 119c816e1ddSZong Li /* CLKMUXSTATUSREG */ 120c816e1ddSZong Li #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c 121c816e1ddSZong Li #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 122c816e1ddSZong Li #define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ 123c816e1ddSZong Li (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) 124c816e1ddSZong Li 125efc91ae4SZong Li /* CLTXPLLCFG0 */ 126efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_OFFSET 0x30 127efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0 128efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT) 129efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6 130efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT) 131efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15 132efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT) 133efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18 134efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT) 135efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24 136efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT) 137efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_FSE_SHIFT 25 138efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT) 139efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31 140efc91ae4SZong Li #define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT) 141efc91ae4SZong Li 142efc91ae4SZong Li /* CLTXPLLCFG1 */ 143efc91ae4SZong Li #define PRCI_CLTXPLLCFG1_OFFSET 0x34 144efc91ae4SZong Li #define PRCI_CLTXPLLCFG1_CKE_SHIFT 31 145efc91ae4SZong Li #define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT) 146efc91ae4SZong Li 147efc91ae4SZong Li /* DVFSCOREPLLCFG0 */ 148efc91ae4SZong Li #define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38 149efc91ae4SZong Li 150efc91ae4SZong Li /* DVFSCOREPLLCFG1 */ 151efc91ae4SZong Li #define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c 152efc91ae4SZong Li #define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 31 153efc91ae4SZong Li #define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT) 154efc91ae4SZong Li 155efc91ae4SZong Li /* COREPLLSEL */ 156efc91ae4SZong Li #define PRCI_COREPLLSEL_OFFSET 0x40 157efc91ae4SZong Li #define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0 158efc91ae4SZong Li #define PRCI_COREPLLSEL_COREPLLSEL_MASK \ 159efc91ae4SZong Li (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT) 160efc91ae4SZong Li 161efc91ae4SZong Li /* HFPCLKPLLCFG0 */ 162efc91ae4SZong Li #define PRCI_HFPCLKPLLCFG0_OFFSET 0x50 163efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0 164efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \ 165efc91ae4SZong Li (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT) 166efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6 167efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \ 168efc91ae4SZong Li (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT) 169efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15 170efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \ 171efc91ae4SZong Li (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT) 172efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18 173efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \ 174efc91ae4SZong Li (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT) 175efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24 176efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \ 177efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT) 178efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25 179efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_FSE_MASK \ 180efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT) 181efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31 182efc91ae4SZong Li #define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \ 183efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT) 184efc91ae4SZong Li 185efc91ae4SZong Li /* HFPCLKPLLCFG1 */ 186efc91ae4SZong Li #define PRCI_HFPCLKPLLCFG1_OFFSET 0x54 187efc91ae4SZong Li #define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 31 188efc91ae4SZong Li #define PRCI_HFPCLKPLLCFG1_CKE_MASK \ 189efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT) 190efc91ae4SZong Li 191efc91ae4SZong Li /* HFPCLKPLLSEL */ 192efc91ae4SZong Li #define PRCI_HFPCLKPLLSEL_OFFSET 0x58 193efc91ae4SZong Li #define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0 194efc91ae4SZong Li #define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \ 195efc91ae4SZong Li (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT) 196efc91ae4SZong Li 197efc91ae4SZong Li /* HFPCLKPLLDIV */ 198efc91ae4SZong Li #define PRCI_HFPCLKPLLDIV_OFFSET 0x5c 199efc91ae4SZong Li 200efc91ae4SZong Li /* PRCIPLL */ 201efc91ae4SZong Li #define PRCI_PRCIPLL_OFFSET 0xe0 202efc91ae4SZong Li 203efc91ae4SZong Li /* PROCMONCFG */ 204efc91ae4SZong Li #define PRCI_PROCMONCFG_OFFSET 0xf0 205efc91ae4SZong Li 206c816e1ddSZong Li /* 207c816e1ddSZong Li * Private structures 208c816e1ddSZong Li */ 209c816e1ddSZong Li 210c816e1ddSZong Li /** 211c816e1ddSZong Li * struct __prci_data - per-device-instance data 212c816e1ddSZong Li * @va: base virtual address of the PRCI IP block 213c816e1ddSZong Li * @hw_clks: encapsulates struct clk_hw records 214c816e1ddSZong Li * 215c816e1ddSZong Li * PRCI per-device instance data 216c816e1ddSZong Li */ 217c816e1ddSZong Li struct __prci_data { 218c816e1ddSZong Li void __iomem *va; 219c816e1ddSZong Li struct clk_hw_onecell_data hw_clks; 220c816e1ddSZong Li }; 221c816e1ddSZong Li 222c816e1ddSZong Li /** 223c816e1ddSZong Li * struct __prci_wrpll_data - WRPLL configuration and integration data 224c816e1ddSZong Li * @c: WRPLL current configuration record 225c816e1ddSZong Li * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) 226c816e1ddSZong Li * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) 227c816e1ddSZong Li * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address 228*732374a0SPragnesh Patel * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address 229c816e1ddSZong Li * 230c816e1ddSZong Li * @enable_bypass and @disable_bypass are used for WRPLL instances 231c816e1ddSZong Li * that contain a separate external glitchless clock mux downstream 232c816e1ddSZong Li * from the PLL. The WRPLL internal bypass mux is not glitchless. 233c816e1ddSZong Li */ 234c816e1ddSZong Li struct __prci_wrpll_data { 235c816e1ddSZong Li struct wrpll_cfg c; 236c816e1ddSZong Li void (*enable_bypass)(struct __prci_data *pd); 237c816e1ddSZong Li void (*disable_bypass)(struct __prci_data *pd); 238c816e1ddSZong Li u8 cfg0_offs; 239*732374a0SPragnesh Patel u8 cfg1_offs; 240c816e1ddSZong Li }; 241c816e1ddSZong Li 242c816e1ddSZong Li /** 243c816e1ddSZong Li * struct __prci_clock - describes a clock device managed by PRCI 244c816e1ddSZong Li * @name: user-readable clock name string - should match the manual 245c816e1ddSZong Li * @parent_name: parent name for this clock 246c816e1ddSZong Li * @ops: struct clk_ops for the Linux clock framework to use for control 247c816e1ddSZong Li * @hw: Linux-private clock data 248c816e1ddSZong Li * @pwd: WRPLL-specific data, associated with this clock (if not NULL) 249c816e1ddSZong Li * @pd: PRCI-specific data associated with this clock (if not NULL) 250c816e1ddSZong Li * 251c816e1ddSZong Li * PRCI clock data. Used by the PRCI driver to register PRCI-provided 252c816e1ddSZong Li * clocks to the Linux clock infrastructure. 253c816e1ddSZong Li */ 254c816e1ddSZong Li struct __prci_clock { 255c816e1ddSZong Li const char *name; 256c816e1ddSZong Li const char *parent_name; 257c816e1ddSZong Li const struct clk_ops *ops; 258c816e1ddSZong Li struct clk_hw hw; 259c816e1ddSZong Li struct __prci_wrpll_data *pwd; 260c816e1ddSZong Li struct __prci_data *pd; 261c816e1ddSZong Li }; 262c816e1ddSZong Li 263c816e1ddSZong Li #define clk_hw_to_prci_clock(pwd) container_of(pwd, struct __prci_clock, hw) 264c816e1ddSZong Li 265c816e1ddSZong Li /* 266c816e1ddSZong Li * struct prci_clk_desc - describes the information of clocks of each SoCs 267c816e1ddSZong Li * @clks: point to a array of __prci_clock 268c816e1ddSZong Li * @num_clks: the number of element of clks 269c816e1ddSZong Li */ 270c816e1ddSZong Li struct prci_clk_desc { 271c816e1ddSZong Li struct __prci_clock *clks; 272c816e1ddSZong Li size_t num_clks; 273c816e1ddSZong Li }; 274c816e1ddSZong Li 275c816e1ddSZong Li /* Core clock mux control */ 276c816e1ddSZong Li void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd); 277c816e1ddSZong Li void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd); 278efc91ae4SZong Li void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd); 279efc91ae4SZong Li void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd); 280efc91ae4SZong Li void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd); 281efc91ae4SZong Li void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd); 282efc91ae4SZong Li void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd); 283c816e1ddSZong Li 284c816e1ddSZong Li /* Linux clock framework integration */ 285c816e1ddSZong Li long sifive_prci_wrpll_round_rate(struct clk_hw *hw, unsigned long rate, 286c816e1ddSZong Li unsigned long *parent_rate); 287c816e1ddSZong Li int sifive_prci_wrpll_set_rate(struct clk_hw *hw, unsigned long rate, 288c816e1ddSZong Li unsigned long parent_rate); 289*732374a0SPragnesh Patel int sifive_clk_is_enabled(struct clk_hw *hw); 290*732374a0SPragnesh Patel int sifive_prci_clock_enable(struct clk_hw *hw); 291*732374a0SPragnesh Patel void sifive_prci_clock_disable(struct clk_hw *hw); 292c816e1ddSZong Li unsigned long sifive_prci_wrpll_recalc_rate(struct clk_hw *hw, 293c816e1ddSZong Li unsigned long parent_rate); 294c816e1ddSZong Li unsigned long sifive_prci_tlclksel_recalc_rate(struct clk_hw *hw, 295c816e1ddSZong Li unsigned long parent_rate); 296efc91ae4SZong Li unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct clk_hw *hw, 297efc91ae4SZong Li unsigned long parent_rate); 298c816e1ddSZong Li 299c816e1ddSZong Li #endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ 300