1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> 5 * 6 * Based on clock drivers for S3C64xx and Exynos4 SoCs. 7 * 8 * Common Clock Framework support for all S5PC110/S5PV210 SoCs. 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/of_address.h> 13 14 #include "clk.h" 15 #include "clk-pll.h" 16 17 #include <dt-bindings/clock/s5pv210.h> 18 19 /* S5PC110/S5PV210 clock controller register offsets */ 20 #define APLL_LOCK 0x0000 21 #define MPLL_LOCK 0x0008 22 #define EPLL_LOCK 0x0010 23 #define VPLL_LOCK 0x0020 24 #define APLL_CON0 0x0100 25 #define APLL_CON1 0x0104 26 #define MPLL_CON 0x0108 27 #define EPLL_CON0 0x0110 28 #define EPLL_CON1 0x0114 29 #define VPLL_CON 0x0120 30 #define CLK_SRC0 0x0200 31 #define CLK_SRC1 0x0204 32 #define CLK_SRC2 0x0208 33 #define CLK_SRC3 0x020c 34 #define CLK_SRC4 0x0210 35 #define CLK_SRC5 0x0214 36 #define CLK_SRC6 0x0218 37 #define CLK_SRC_MASK0 0x0280 38 #define CLK_SRC_MASK1 0x0284 39 #define CLK_DIV0 0x0300 40 #define CLK_DIV1 0x0304 41 #define CLK_DIV2 0x0308 42 #define CLK_DIV3 0x030c 43 #define CLK_DIV4 0x0310 44 #define CLK_DIV5 0x0314 45 #define CLK_DIV6 0x0318 46 #define CLK_DIV7 0x031c 47 #define CLK_GATE_MAIN0 0x0400 48 #define CLK_GATE_MAIN1 0x0404 49 #define CLK_GATE_MAIN2 0x0408 50 #define CLK_GATE_PERI0 0x0420 51 #define CLK_GATE_PERI1 0x0424 52 #define CLK_GATE_SCLK0 0x0440 53 #define CLK_GATE_SCLK1 0x0444 54 #define CLK_GATE_IP0 0x0460 55 #define CLK_GATE_IP1 0x0464 56 #define CLK_GATE_IP2 0x0468 57 #define CLK_GATE_IP3 0x046c 58 #define CLK_GATE_IP4 0x0470 59 #define CLK_GATE_BLOCK 0x0480 60 #define CLK_GATE_IP5 0x0484 61 #define CLK_OUT 0x0500 62 #define MISC 0xe000 63 #define OM_STAT 0xe100 64 65 /* IDs of PLLs available on S5PV210/S5P6442 SoCs */ 66 enum { 67 apll, 68 mpll, 69 epll, 70 vpll, 71 }; 72 73 /* IDs of external clocks (used for legacy boards) */ 74 enum { 75 xxti, 76 xusbxti, 77 }; 78 79 static void __iomem *reg_base; 80 81 /* List of registers that need to be preserved across suspend/resume. */ 82 static unsigned long s5pv210_clk_regs[] __initdata = { 83 CLK_SRC0, 84 CLK_SRC1, 85 CLK_SRC2, 86 CLK_SRC3, 87 CLK_SRC4, 88 CLK_SRC5, 89 CLK_SRC6, 90 CLK_SRC_MASK0, 91 CLK_SRC_MASK1, 92 CLK_DIV0, 93 CLK_DIV1, 94 CLK_DIV2, 95 CLK_DIV3, 96 CLK_DIV4, 97 CLK_DIV5, 98 CLK_DIV6, 99 CLK_DIV7, 100 CLK_GATE_MAIN0, 101 CLK_GATE_MAIN1, 102 CLK_GATE_MAIN2, 103 CLK_GATE_PERI0, 104 CLK_GATE_PERI1, 105 CLK_GATE_SCLK0, 106 CLK_GATE_SCLK1, 107 CLK_GATE_IP0, 108 CLK_GATE_IP1, 109 CLK_GATE_IP2, 110 CLK_GATE_IP3, 111 CLK_GATE_IP4, 112 CLK_GATE_IP5, 113 CLK_GATE_BLOCK, 114 APLL_LOCK, 115 MPLL_LOCK, 116 EPLL_LOCK, 117 VPLL_LOCK, 118 APLL_CON0, 119 APLL_CON1, 120 MPLL_CON, 121 EPLL_CON0, 122 EPLL_CON1, 123 VPLL_CON, 124 CLK_OUT, 125 }; 126 127 /* Mux parent lists. */ 128 static const char *const fin_pll_p[] __initconst = { 129 "xxti", 130 "xusbxti" 131 }; 132 133 static const char *const mout_apll_p[] __initconst = { 134 "fin_pll", 135 "fout_apll" 136 }; 137 138 static const char *const mout_mpll_p[] __initconst = { 139 "fin_pll", 140 "fout_mpll" 141 }; 142 143 static const char *const mout_epll_p[] __initconst = { 144 "fin_pll", 145 "fout_epll" 146 }; 147 148 static const char *const mout_vpllsrc_p[] __initconst = { 149 "fin_pll", 150 "sclk_hdmi27m" 151 }; 152 153 static const char *const mout_vpll_p[] __initconst = { 154 "mout_vpllsrc", 155 "fout_vpll" 156 }; 157 158 static const char *const mout_group1_p[] __initconst = { 159 "dout_a2m", 160 "mout_mpll", 161 "mout_epll", 162 "mout_vpll" 163 }; 164 165 static const char *const mout_group2_p[] __initconst = { 166 "xxti", 167 "xusbxti", 168 "sclk_hdmi27m", 169 "sclk_usbphy0", 170 "sclk_usbphy1", 171 "sclk_hdmiphy", 172 "mout_mpll", 173 "mout_epll", 174 "mout_vpll", 175 }; 176 177 static const char *const mout_audio0_p[] __initconst = { 178 "xxti", 179 "pcmcdclk0", 180 "sclk_hdmi27m", 181 "sclk_usbphy0", 182 "sclk_usbphy1", 183 "sclk_hdmiphy", 184 "mout_mpll", 185 "mout_epll", 186 "mout_vpll", 187 }; 188 189 static const char *const mout_audio1_p[] __initconst = { 190 "i2scdclk1", 191 "pcmcdclk1", 192 "sclk_hdmi27m", 193 "sclk_usbphy0", 194 "sclk_usbphy1", 195 "sclk_hdmiphy", 196 "mout_mpll", 197 "mout_epll", 198 "mout_vpll", 199 }; 200 201 static const char *const mout_audio2_p[] __initconst = { 202 "i2scdclk2", 203 "pcmcdclk2", 204 "sclk_hdmi27m", 205 "sclk_usbphy0", 206 "sclk_usbphy1", 207 "sclk_hdmiphy", 208 "mout_mpll", 209 "mout_epll", 210 "mout_vpll", 211 }; 212 213 static const char *const mout_spdif_p[] __initconst = { 214 "dout_audio0", 215 "dout_audio1", 216 "dout_audio3", 217 }; 218 219 static const char *const mout_group3_p[] __initconst = { 220 "mout_apll", 221 "mout_mpll" 222 }; 223 224 static const char *const mout_group4_p[] __initconst = { 225 "mout_mpll", 226 "dout_a2m" 227 }; 228 229 static const char *const mout_flash_p[] __initconst = { 230 "dout_hclkd", 231 "dout_hclkp" 232 }; 233 234 static const char *const mout_dac_p[] __initconst = { 235 "mout_vpll", 236 "sclk_hdmiphy" 237 }; 238 239 static const char *const mout_hdmi_p[] __initconst = { 240 "sclk_hdmiphy", 241 "dout_tblk" 242 }; 243 244 static const char *const mout_mixer_p[] __initconst = { 245 "mout_dac", 246 "mout_hdmi" 247 }; 248 249 static const char *const mout_vpll_6442_p[] __initconst = { 250 "fin_pll", 251 "fout_vpll" 252 }; 253 254 static const char *const mout_mixer_6442_p[] __initconst = { 255 "mout_vpll", 256 "dout_mixer" 257 }; 258 259 static const char *const mout_d0sync_6442_p[] __initconst = { 260 "mout_dsys", 261 "div_apll" 262 }; 263 264 static const char *const mout_d1sync_6442_p[] __initconst = { 265 "mout_psys", 266 "div_apll" 267 }; 268 269 static const char *const mout_group2_6442_p[] __initconst = { 270 "fin_pll", 271 "none", 272 "none", 273 "sclk_usbphy0", 274 "none", 275 "none", 276 "mout_mpll", 277 "mout_epll", 278 "mout_vpll", 279 }; 280 281 static const char *const mout_audio0_6442_p[] __initconst = { 282 "fin_pll", 283 "pcmcdclk0", 284 "none", 285 "sclk_usbphy0", 286 "none", 287 "none", 288 "mout_mpll", 289 "mout_epll", 290 "mout_vpll", 291 }; 292 293 static const char *const mout_audio1_6442_p[] __initconst = { 294 "i2scdclk1", 295 "pcmcdclk1", 296 "none", 297 "sclk_usbphy0", 298 "none", 299 "none", 300 "mout_mpll", 301 "mout_epll", 302 "mout_vpll", 303 "fin_pll", 304 }; 305 306 static const char *const mout_clksel_p[] __initconst = { 307 "fout_apll_clkout", 308 "fout_mpll_clkout", 309 "fout_epll", 310 "fout_vpll", 311 "sclk_usbphy0", 312 "sclk_usbphy1", 313 "sclk_hdmiphy", 314 "rtc", 315 "rtc_tick", 316 "dout_hclkm", 317 "dout_pclkm", 318 "dout_hclkd", 319 "dout_pclkd", 320 "dout_hclkp", 321 "dout_pclkp", 322 "dout_apll_clkout", 323 "dout_hpm", 324 "xxti", 325 "xusbxti", 326 "div_dclk" 327 }; 328 329 static const char *const mout_clksel_6442_p[] __initconst = { 330 "fout_apll_clkout", 331 "fout_mpll_clkout", 332 "fout_epll", 333 "fout_vpll", 334 "sclk_usbphy0", 335 "none", 336 "none", 337 "rtc", 338 "rtc_tick", 339 "none", 340 "none", 341 "dout_hclkd", 342 "dout_pclkd", 343 "dout_hclkp", 344 "dout_pclkp", 345 "dout_apll_clkout", 346 "none", 347 "fin_pll", 348 "none", 349 "div_dclk" 350 }; 351 352 static const char *const mout_clkout_p[] __initconst = { 353 "dout_clkout", 354 "none", 355 "xxti", 356 "xusbxti" 357 }; 358 359 /* Common fixed factor clocks. */ 360 static const struct samsung_fixed_factor_clock ffactor_clks[] __initconst = { 361 FFACTOR(FOUT_APLL_CLKOUT, "fout_apll_clkout", "fout_apll", 1, 4, 0), 362 FFACTOR(FOUT_MPLL_CLKOUT, "fout_mpll_clkout", "fout_mpll", 1, 2, 0), 363 FFACTOR(DOUT_APLL_CLKOUT, "dout_apll_clkout", "dout_apll", 1, 4, 0), 364 }; 365 366 /* PLL input mux (fin_pll), which needs to be registered before PLLs. */ 367 static const struct samsung_mux_clock early_mux_clks[] __initconst = { 368 MUX_F(FIN_PLL, "fin_pll", fin_pll_p, OM_STAT, 0, 1, 369 CLK_MUX_READ_ONLY, 0), 370 }; 371 372 /* Common clock muxes. */ 373 static const struct samsung_mux_clock mux_clks[] __initconst = { 374 MUX(MOUT_FLASH, "mout_flash", mout_flash_p, CLK_SRC0, 28, 1), 375 MUX(MOUT_PSYS, "mout_psys", mout_group4_p, CLK_SRC0, 24, 1), 376 MUX(MOUT_DSYS, "mout_dsys", mout_group4_p, CLK_SRC0, 20, 1), 377 MUX(MOUT_MSYS, "mout_msys", mout_group3_p, CLK_SRC0, 16, 1), 378 MUX(MOUT_EPLL, "mout_epll", mout_epll_p, CLK_SRC0, 8, 1), 379 MUX(MOUT_MPLL, "mout_mpll", mout_mpll_p, CLK_SRC0, 4, 1), 380 MUX(MOUT_APLL, "mout_apll", mout_apll_p, CLK_SRC0, 0, 1), 381 382 MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2), 383 }; 384 385 /* S5PV210-specific clock muxes. */ 386 static const struct samsung_mux_clock s5pv210_mux_clks[] __initconst = { 387 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_p, CLK_SRC0, 12, 1), 388 389 MUX(MOUT_VPLLSRC, "mout_vpllsrc", mout_vpllsrc_p, CLK_SRC1, 28, 1), 390 MUX(MOUT_CSIS, "mout_csis", mout_group2_p, CLK_SRC1, 24, 4), 391 MUX(MOUT_FIMD, "mout_fimd", mout_group2_p, CLK_SRC1, 20, 4), 392 MUX(MOUT_CAM1, "mout_cam1", mout_group2_p, CLK_SRC1, 16, 4), 393 MUX(MOUT_CAM0, "mout_cam0", mout_group2_p, CLK_SRC1, 12, 4), 394 MUX(MOUT_DAC, "mout_dac", mout_dac_p, CLK_SRC1, 8, 1), 395 MUX(MOUT_MIXER, "mout_mixer", mout_mixer_p, CLK_SRC1, 4, 1), 396 MUX(MOUT_HDMI, "mout_hdmi", mout_hdmi_p, CLK_SRC1, 0, 1), 397 398 MUX(MOUT_G2D, "mout_g2d", mout_group1_p, CLK_SRC2, 8, 2), 399 MUX(MOUT_MFC, "mout_mfc", mout_group1_p, CLK_SRC2, 4, 2), 400 MUX(MOUT_G3D, "mout_g3d", mout_group1_p, CLK_SRC2, 0, 2), 401 402 MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_p, CLK_SRC3, 20, 4), 403 MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_p, CLK_SRC3, 16, 4), 404 MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_p, CLK_SRC3, 12, 4), 405 406 MUX(MOUT_UART3, "mout_uart3", mout_group2_p, CLK_SRC4, 28, 4), 407 MUX(MOUT_UART2, "mout_uart2", mout_group2_p, CLK_SRC4, 24, 4), 408 MUX(MOUT_UART1, "mout_uart1", mout_group2_p, CLK_SRC4, 20, 4), 409 MUX(MOUT_UART0, "mout_uart0", mout_group2_p, CLK_SRC4, 16, 4), 410 MUX(MOUT_MMC3, "mout_mmc3", mout_group2_p, CLK_SRC4, 12, 4), 411 MUX(MOUT_MMC2, "mout_mmc2", mout_group2_p, CLK_SRC4, 8, 4), 412 MUX(MOUT_MMC1, "mout_mmc1", mout_group2_p, CLK_SRC4, 4, 4), 413 MUX(MOUT_MMC0, "mout_mmc0", mout_group2_p, CLK_SRC4, 0, 4), 414 415 MUX(MOUT_PWM, "mout_pwm", mout_group2_p, CLK_SRC5, 12, 4), 416 MUX(MOUT_SPI1, "mout_spi1", mout_group2_p, CLK_SRC5, 4, 4), 417 MUX(MOUT_SPI0, "mout_spi0", mout_group2_p, CLK_SRC5, 0, 4), 418 419 MUX(MOUT_DMC0, "mout_dmc0", mout_group1_p, CLK_SRC6, 24, 2), 420 MUX(MOUT_PWI, "mout_pwi", mout_group2_p, CLK_SRC6, 20, 4), 421 MUX(MOUT_HPM, "mout_hpm", mout_group3_p, CLK_SRC6, 16, 1), 422 MUX(MOUT_SPDIF, "mout_spdif", mout_spdif_p, CLK_SRC6, 12, 2), 423 MUX(MOUT_AUDIO2, "mout_audio2", mout_audio2_p, CLK_SRC6, 8, 4), 424 MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_p, CLK_SRC6, 4, 4), 425 MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_p, CLK_SRC6, 0, 4), 426 427 MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_p, CLK_OUT, 12, 5), 428 }; 429 430 /* S5P6442-specific clock muxes. */ 431 static const struct samsung_mux_clock s5p6442_mux_clks[] __initconst = { 432 MUX(MOUT_VPLL, "mout_vpll", mout_vpll_6442_p, CLK_SRC0, 12, 1), 433 434 MUX(MOUT_FIMD, "mout_fimd", mout_group2_6442_p, CLK_SRC1, 20, 4), 435 MUX(MOUT_CAM1, "mout_cam1", mout_group2_6442_p, CLK_SRC1, 16, 4), 436 MUX(MOUT_CAM0, "mout_cam0", mout_group2_6442_p, CLK_SRC1, 12, 4), 437 MUX(MOUT_MIXER, "mout_mixer", mout_mixer_6442_p, CLK_SRC1, 4, 1), 438 439 MUX(MOUT_D0SYNC, "mout_d0sync", mout_d0sync_6442_p, CLK_SRC2, 28, 1), 440 MUX(MOUT_D1SYNC, "mout_d1sync", mout_d1sync_6442_p, CLK_SRC2, 24, 1), 441 442 MUX(MOUT_FIMC2, "mout_fimc2", mout_group2_6442_p, CLK_SRC3, 20, 4), 443 MUX(MOUT_FIMC1, "mout_fimc1", mout_group2_6442_p, CLK_SRC3, 16, 4), 444 MUX(MOUT_FIMC0, "mout_fimc0", mout_group2_6442_p, CLK_SRC3, 12, 4), 445 446 MUX(MOUT_UART2, "mout_uart2", mout_group2_6442_p, CLK_SRC4, 24, 4), 447 MUX(MOUT_UART1, "mout_uart1", mout_group2_6442_p, CLK_SRC4, 20, 4), 448 MUX(MOUT_UART0, "mout_uart0", mout_group2_6442_p, CLK_SRC4, 16, 4), 449 MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4), 450 MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4), 451 MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4), 452 453 MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4), 454 MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4), 455 456 MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4), 457 MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4), 458 459 MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5), 460 }; 461 462 /* S5PV210-specific fixed rate clocks generated inside the SoC. */ 463 static const struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initconst = { 464 FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, 0, 27000000), 465 FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 27000000), 466 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 48000000), 467 FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, 0, 48000000), 468 }; 469 470 /* S5P6442-specific fixed rate clocks generated inside the SoC. */ 471 static const struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initconst = { 472 FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, 0, 30000000), 473 }; 474 475 /* Common clock dividers. */ 476 static const struct samsung_div_clock div_clks[] __initconst = { 477 DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3), 478 DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3), 479 DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3), 480 DIV(DOUT_APLL, "dout_apll", "mout_msys", CLK_DIV0, 0, 3), 481 482 DIV(DOUT_FIMD, "dout_fimd", "mout_fimd", CLK_DIV1, 20, 4), 483 DIV(DOUT_CAM1, "dout_cam1", "mout_cam1", CLK_DIV1, 16, 4), 484 DIV(DOUT_CAM0, "dout_cam0", "mout_cam0", CLK_DIV1, 12, 4), 485 486 DIV(DOUT_FIMC2, "dout_fimc2", "mout_fimc2", CLK_DIV3, 20, 4), 487 DIV(DOUT_FIMC1, "dout_fimc1", "mout_fimc1", CLK_DIV3, 16, 4), 488 DIV(DOUT_FIMC0, "dout_fimc0", "mout_fimc0", CLK_DIV3, 12, 4), 489 490 DIV(DOUT_UART2, "dout_uart2", "mout_uart2", CLK_DIV4, 24, 4), 491 DIV(DOUT_UART1, "dout_uart1", "mout_uart1", CLK_DIV4, 20, 4), 492 DIV(DOUT_UART0, "dout_uart0", "mout_uart0", CLK_DIV4, 16, 4), 493 DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV4, 8, 4), 494 DIV(DOUT_MMC1, "dout_mmc1", "mout_mmc1", CLK_DIV4, 4, 4), 495 DIV(DOUT_MMC0, "dout_mmc0", "mout_mmc0", CLK_DIV4, 0, 4), 496 497 DIV(DOUT_PWM, "dout_pwm", "mout_pwm", CLK_DIV5, 12, 4), 498 DIV(DOUT_SPI0, "dout_spi0", "mout_spi0", CLK_DIV5, 0, 4), 499 500 DIV(DOUT_FLASH, "dout_flash", "mout_flash", CLK_DIV6, 12, 3), 501 DIV(DOUT_AUDIO1, "dout_audio1", "mout_audio1", CLK_DIV6, 4, 4), 502 DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV6, 0, 4), 503 504 DIV(DOUT_CLKOUT, "dout_clkout", "mout_clksel", CLK_OUT, 20, 4), 505 }; 506 507 /* S5PV210-specific clock dividers. */ 508 static const struct samsung_div_clock s5pv210_div_clks[] __initconst = { 509 DIV(DOUT_HCLKP, "dout_hclkp", "mout_psys", CLK_DIV0, 24, 4), 510 DIV(DOUT_HCLKD, "dout_hclkd", "mout_dsys", CLK_DIV0, 16, 4), 511 DIV(DOUT_PCLKM, "dout_pclkm", "dout_hclkm", CLK_DIV0, 12, 3), 512 DIV(DOUT_HCLKM, "dout_hclkm", "dout_apll", CLK_DIV0, 8, 3), 513 514 DIV(DOUT_CSIS, "dout_csis", "mout_csis", CLK_DIV1, 28, 4), 515 DIV(DOUT_TBLK, "dout_tblk", "mout_vpll", CLK_DIV1, 0, 4), 516 517 DIV(DOUT_G2D, "dout_g2d", "mout_g2d", CLK_DIV2, 8, 4), 518 DIV(DOUT_MFC, "dout_mfc", "mout_mfc", CLK_DIV2, 4, 4), 519 DIV(DOUT_G3D, "dout_g3d", "mout_g3d", CLK_DIV2, 0, 4), 520 521 DIV(DOUT_UART3, "dout_uart3", "mout_uart3", CLK_DIV4, 28, 4), 522 DIV(DOUT_MMC3, "dout_mmc3", "mout_mmc3", CLK_DIV4, 12, 4), 523 524 DIV(DOUT_SPI1, "dout_spi1", "mout_spi1", CLK_DIV5, 4, 4), 525 526 DIV(DOUT_DMC0, "dout_dmc0", "mout_dmc0", CLK_DIV6, 28, 4), 527 DIV(DOUT_PWI, "dout_pwi", "mout_pwi", CLK_DIV6, 24, 4), 528 DIV(DOUT_HPM, "dout_hpm", "dout_copy", CLK_DIV6, 20, 3), 529 DIV(DOUT_COPY, "dout_copy", "mout_hpm", CLK_DIV6, 16, 3), 530 DIV(DOUT_AUDIO2, "dout_audio2", "mout_audio2", CLK_DIV6, 8, 4), 531 532 DIV(DOUT_DPM, "dout_dpm", "dout_pclkp", CLK_DIV7, 8, 7), 533 DIV(DOUT_DVSEM, "dout_dvsem", "dout_pclkp", CLK_DIV7, 0, 7), 534 }; 535 536 /* S5P6442-specific clock dividers. */ 537 static const struct samsung_div_clock s5p6442_div_clks[] __initconst = { 538 DIV(DOUT_HCLKP, "dout_hclkp", "mout_d1sync", CLK_DIV0, 24, 4), 539 DIV(DOUT_HCLKD, "dout_hclkd", "mout_d0sync", CLK_DIV0, 16, 4), 540 541 DIV(DOUT_MIXER, "dout_mixer", "mout_vpll", CLK_DIV1, 0, 4), 542 }; 543 544 /* Common clock gates. */ 545 static const struct samsung_gate_clock gate_clks[] __initconst = { 546 GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0), 547 GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0), 548 GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0), 549 GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0), 550 GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0), 551 GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0), 552 553 GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0), 554 GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0), 555 GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0), 556 GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0), 557 GATE(CLK_MIXER, "mixer", "dout_hclkd", CLK_GATE_IP1, 9, 0, 0), 558 GATE(CLK_VP, "vp", "dout_hclkd", CLK_GATE_IP1, 8, 0, 0), 559 GATE(CLK_FIMD, "fimd", "dout_hclkd", CLK_GATE_IP1, 0, 0, 0), 560 561 GATE(CLK_HSMMC2, "hsmmc2", "dout_hclkp", CLK_GATE_IP2, 18, 0, 0), 562 GATE(CLK_HSMMC1, "hsmmc1", "dout_hclkp", CLK_GATE_IP2, 17, 0, 0), 563 GATE(CLK_HSMMC0, "hsmmc0", "dout_hclkp", CLK_GATE_IP2, 16, 0, 0), 564 GATE(CLK_MODEMIF, "modemif", "dout_hclkp", CLK_GATE_IP2, 9, 0, 0), 565 GATE(CLK_SECSS, "secss", "dout_hclkp", CLK_GATE_IP2, 0, 0, 0), 566 567 GATE(CLK_PCM1, "pcm1", "dout_pclkp", CLK_GATE_IP3, 29, 0, 0), 568 GATE(CLK_PCM0, "pcm0", "dout_pclkp", CLK_GATE_IP3, 28, 0, 0), 569 GATE(CLK_TSADC, "tsadc", "dout_pclkp", CLK_GATE_IP3, 24, 0, 0), 570 GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0), 571 GATE(CLK_WDT, "watchdog", "dout_pclkp", CLK_GATE_IP3, 22, 0, 0), 572 GATE(CLK_KEYIF, "keyif", "dout_pclkp", CLK_GATE_IP3, 21, 0, 0), 573 GATE(CLK_UART2, "uart2", "dout_pclkp", CLK_GATE_IP3, 19, 0, 0), 574 GATE(CLK_UART1, "uart1", "dout_pclkp", CLK_GATE_IP3, 18, 0, 0), 575 GATE(CLK_UART0, "uart0", "dout_pclkp", CLK_GATE_IP3, 17, 0, 0), 576 GATE(CLK_SYSTIMER, "systimer", "dout_pclkp", CLK_GATE_IP3, 16, 0, 0), 577 GATE(CLK_RTC, "rtc", "dout_pclkp", CLK_GATE_IP3, 15, 0, 0), 578 GATE(CLK_SPI0, "spi0", "dout_pclkp", CLK_GATE_IP3, 12, 0, 0), 579 GATE(CLK_I2C2, "i2c2", "dout_pclkp", CLK_GATE_IP3, 9, 0, 0), 580 GATE(CLK_I2C0, "i2c0", "dout_pclkp", CLK_GATE_IP3, 7, 0, 0), 581 GATE(CLK_I2S1, "i2s1", "dout_pclkp", CLK_GATE_IP3, 5, 0, 0), 582 GATE(CLK_I2S0, "i2s0", "dout_pclkp", CLK_GATE_IP3, 4, 0, 0), 583 584 GATE(CLK_SECKEY, "seckey", "dout_pclkp", CLK_GATE_IP4, 3, 0, 0), 585 GATE(CLK_CHIPID, "chipid", "dout_pclkp", CLK_GATE_IP4, 0, 0, 0), 586 587 GATE(SCLK_AUDIO1, "sclk_audio1", "dout_audio1", CLK_SRC_MASK0, 25, 588 CLK_SET_RATE_PARENT, 0), 589 GATE(SCLK_AUDIO0, "sclk_audio0", "dout_audio0", CLK_SRC_MASK0, 24, 590 CLK_SET_RATE_PARENT, 0), 591 GATE(SCLK_PWM, "sclk_pwm", "dout_pwm", CLK_SRC_MASK0, 19, 592 CLK_SET_RATE_PARENT, 0), 593 GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16, 594 CLK_SET_RATE_PARENT, 0), 595 GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14, 596 CLK_SET_RATE_PARENT, 0), 597 GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13, 598 CLK_SET_RATE_PARENT, 0), 599 GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12, 600 CLK_SET_RATE_PARENT, 0), 601 GATE(SCLK_MMC2, "sclk_mmc2", "dout_mmc2", CLK_SRC_MASK0, 10, 602 CLK_SET_RATE_PARENT, 0), 603 GATE(SCLK_MMC1, "sclk_mmc1", "dout_mmc1", CLK_SRC_MASK0, 9, 604 CLK_SET_RATE_PARENT, 0), 605 GATE(SCLK_MMC0, "sclk_mmc0", "dout_mmc0", CLK_SRC_MASK0, 8, 606 CLK_SET_RATE_PARENT, 0), 607 GATE(SCLK_FIMD, "sclk_fimd", "dout_fimd", CLK_SRC_MASK0, 5, 608 CLK_SET_RATE_PARENT, 0), 609 GATE(SCLK_CAM1, "sclk_cam1", "dout_cam1", CLK_SRC_MASK0, 4, 610 CLK_SET_RATE_PARENT, 0), 611 GATE(SCLK_CAM0, "sclk_cam0", "dout_cam0", CLK_SRC_MASK0, 3, 612 CLK_SET_RATE_PARENT, 0), 613 GATE(SCLK_MIXER, "sclk_mixer", "mout_mixer", CLK_SRC_MASK0, 1, 614 CLK_SET_RATE_PARENT, 0), 615 616 GATE(SCLK_FIMC2, "sclk_fimc2", "dout_fimc2", CLK_SRC_MASK1, 4, 617 CLK_SET_RATE_PARENT, 0), 618 GATE(SCLK_FIMC1, "sclk_fimc1", "dout_fimc1", CLK_SRC_MASK1, 3, 619 CLK_SET_RATE_PARENT, 0), 620 GATE(SCLK_FIMC0, "sclk_fimc0", "dout_fimc0", CLK_SRC_MASK1, 2, 621 CLK_SET_RATE_PARENT, 0), 622 }; 623 624 /* S5PV210-specific clock gates. */ 625 static const struct samsung_gate_clock s5pv210_gate_clks[] __initconst = { 626 GATE(CLK_CSIS, "clk_csis", "dout_hclkd", CLK_GATE_IP0, 31, 0, 0), 627 GATE(CLK_MFC, "mfc", "dout_hclkm", CLK_GATE_IP0, 16, 0, 0), 628 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), 629 GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0), 630 GATE(CLK_IMEM, "imem", "dout_hclkm", CLK_GATE_IP0, 5, 0, 0), 631 GATE(CLK_PDMA1, "pdma1", "dout_hclkp", CLK_GATE_IP0, 4, 0, 0), 632 633 GATE(CLK_NFCON, "nfcon", "dout_hclkp", CLK_GATE_IP1, 28, 0, 0), 634 GATE(CLK_CFCON, "cfcon", "dout_hclkp", CLK_GATE_IP1, 25, 0, 0), 635 GATE(CLK_USB_HOST, "usb_host", "dout_hclkp", CLK_GATE_IP1, 17, 0, 0), 636 GATE(CLK_HDMI, "hdmi", "dout_hclkd", CLK_GATE_IP1, 11, 0, 0), 637 GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0), 638 639 GATE(CLK_TZIC3, "tzic3", "dout_hclkm", CLK_GATE_IP2, 31, 0, 0), 640 GATE(CLK_TZIC2, "tzic2", "dout_hclkm", CLK_GATE_IP2, 30, 0, 0), 641 GATE(CLK_TZIC1, "tzic1", "dout_hclkm", CLK_GATE_IP2, 29, 0, 0), 642 GATE(CLK_TZIC0, "tzic0", "dout_hclkm", CLK_GATE_IP2, 28, 0, 0), 643 GATE(CLK_TSI, "tsi", "dout_hclkd", CLK_GATE_IP2, 20, 0, 0), 644 GATE(CLK_HSMMC3, "hsmmc3", "dout_hclkp", CLK_GATE_IP2, 19, 0, 0), 645 GATE(CLK_JTAG, "jtag", "dout_hclkp", CLK_GATE_IP2, 11, 0, 0), 646 GATE(CLK_CORESIGHT, "coresight", "dout_pclkp", CLK_GATE_IP2, 8, 0, 0), 647 GATE(CLK_SDM, "sdm", "dout_pclkm", CLK_GATE_IP2, 1, 0, 0), 648 649 GATE(CLK_PCM2, "pcm2", "dout_pclkp", CLK_GATE_IP3, 30, 0, 0), 650 GATE(CLK_UART3, "uart3", "dout_pclkp", CLK_GATE_IP3, 20, 0, 0), 651 GATE(CLK_SPI1, "spi1", "dout_pclkp", CLK_GATE_IP3, 13, 0, 0), 652 GATE(CLK_I2C_HDMI_PHY, "i2c_hdmi_phy", "dout_pclkd", 653 CLK_GATE_IP3, 11, 0, 0), 654 GATE(CLK_I2C1, "i2c1", "dout_pclkd", CLK_GATE_IP3, 10, 0, 0), 655 GATE(CLK_I2S2, "i2s2", "dout_pclkp", CLK_GATE_IP3, 6, 0, 0), 656 GATE(CLK_AC97, "ac97", "dout_pclkp", CLK_GATE_IP3, 1, 0, 0), 657 GATE(CLK_SPDIF, "spdif", "dout_pclkp", CLK_GATE_IP3, 0, 0, 0), 658 659 GATE(CLK_TZPC3, "tzpc.3", "dout_pclkd", CLK_GATE_IP4, 8, 0, 0), 660 GATE(CLK_TZPC2, "tzpc.2", "dout_pclkd", CLK_GATE_IP4, 7, 0, 0), 661 GATE(CLK_TZPC1, "tzpc.1", "dout_pclkp", CLK_GATE_IP4, 6, 0, 0), 662 GATE(CLK_TZPC0, "tzpc.0", "dout_pclkm", CLK_GATE_IP4, 5, 0, 0), 663 GATE(CLK_IEM_APC, "iem_apc", "dout_pclkp", CLK_GATE_IP4, 2, 0, 0), 664 GATE(CLK_IEM_IEC, "iem_iec", "dout_pclkp", CLK_GATE_IP4, 1, 0, 0), 665 666 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP5, 29, 0, 0), 667 668 GATE(SCLK_SPDIF, "sclk_spdif", "mout_spdif", CLK_SRC_MASK0, 27, 669 CLK_SET_RATE_PARENT, 0), 670 GATE(SCLK_AUDIO2, "sclk_audio2", "dout_audio2", CLK_SRC_MASK0, 26, 671 CLK_SET_RATE_PARENT, 0), 672 GATE(SCLK_SPI1, "sclk_spi1", "dout_spi1", CLK_SRC_MASK0, 17, 673 CLK_SET_RATE_PARENT, 0), 674 GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15, 675 CLK_SET_RATE_PARENT, 0), 676 GATE(SCLK_MMC3, "sclk_mmc3", "dout_mmc3", CLK_SRC_MASK0, 11, 677 CLK_SET_RATE_PARENT, 0), 678 GATE(SCLK_CSIS, "sclk_csis", "dout_csis", CLK_SRC_MASK0, 6, 679 CLK_SET_RATE_PARENT, 0), 680 GATE(SCLK_DAC, "sclk_dac", "mout_dac", CLK_SRC_MASK0, 2, 681 CLK_SET_RATE_PARENT, 0), 682 GATE(SCLK_HDMI, "sclk_hdmi", "mout_hdmi", CLK_SRC_MASK0, 0, 683 CLK_SET_RATE_PARENT, 0), 684 }; 685 686 /* S5P6442-specific clock gates. */ 687 static const struct samsung_gate_clock s5p6442_gate_clks[] __initconst = { 688 GATE(CLK_JPEG, "jpeg", "dout_hclkd", CLK_GATE_IP0, 28, 0, 0), 689 GATE(CLK_MFC, "mfc", "dout_hclkd", CLK_GATE_IP0, 16, 0, 0), 690 GATE(CLK_G2D, "g2d", "dout_hclkd", CLK_GATE_IP0, 12, 0, 0), 691 GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0), 692 GATE(CLK_IMEM, "imem", "dout_hclkd", CLK_GATE_IP0, 5, 0, 0), 693 694 GATE(CLK_ETB, "etb", "dout_hclkd", CLK_GATE_IP1, 31, 0, 0), 695 GATE(CLK_ETM, "etm", "dout_hclkd", CLK_GATE_IP1, 30, 0, 0), 696 697 GATE(CLK_I2C1, "i2c1", "dout_pclkp", CLK_GATE_IP3, 8, 0, 0), 698 699 GATE(SCLK_DAC, "sclk_dac", "mout_vpll", CLK_SRC_MASK0, 2, 700 CLK_SET_RATE_PARENT, 0), 701 }; 702 703 /* 704 * Clock aliases for legacy clkdev look-up. 705 * NOTE: Needed only to support legacy board files. 706 */ 707 static const struct samsung_clock_alias s5pv210_aliases[] __initconst = { 708 ALIAS(DOUT_APLL, NULL, "armclk"), 709 ALIAS(DOUT_HCLKM, NULL, "hclk_msys"), 710 ALIAS(MOUT_DMC0, NULL, "sclk_dmc0"), 711 }; 712 713 /* S5PV210-specific PLLs. */ 714 static const struct samsung_pll_clock s5pv210_pll_clks[] __initconst = { 715 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll", 716 APLL_LOCK, APLL_CON0, NULL), 717 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 718 MPLL_LOCK, MPLL_CON, NULL), 719 [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll", 720 EPLL_LOCK, EPLL_CON0, NULL), 721 [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 722 VPLL_LOCK, VPLL_CON, NULL), 723 }; 724 725 /* S5P6442-specific PLLs. */ 726 static const struct samsung_pll_clock s5p6442_pll_clks[] __initconst = { 727 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll", 728 APLL_LOCK, APLL_CON0, NULL), 729 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 730 MPLL_LOCK, MPLL_CON, NULL), 731 [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll", 732 EPLL_LOCK, EPLL_CON0, NULL), 733 [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll", 734 VPLL_LOCK, VPLL_CON, NULL), 735 }; 736 737 static void __init __s5pv210_clk_init(struct device_node *np, 738 unsigned long xxti_f, 739 unsigned long xusbxti_f, 740 bool is_s5p6442) 741 { 742 struct samsung_clk_provider *ctx; 743 struct clk_hw **hws; 744 745 ctx = samsung_clk_init(NULL, reg_base, NR_CLKS); 746 hws = ctx->clk_data.hws; 747 748 samsung_clk_register_mux(ctx, early_mux_clks, 749 ARRAY_SIZE(early_mux_clks)); 750 751 if (is_s5p6442) { 752 samsung_clk_register_fixed_rate(ctx, s5p6442_frate_clks, 753 ARRAY_SIZE(s5p6442_frate_clks)); 754 samsung_clk_register_pll(ctx, s5p6442_pll_clks, 755 ARRAY_SIZE(s5p6442_pll_clks)); 756 samsung_clk_register_mux(ctx, s5p6442_mux_clks, 757 ARRAY_SIZE(s5p6442_mux_clks)); 758 samsung_clk_register_div(ctx, s5p6442_div_clks, 759 ARRAY_SIZE(s5p6442_div_clks)); 760 samsung_clk_register_gate(ctx, s5p6442_gate_clks, 761 ARRAY_SIZE(s5p6442_gate_clks)); 762 } else { 763 samsung_clk_register_fixed_rate(ctx, s5pv210_frate_clks, 764 ARRAY_SIZE(s5pv210_frate_clks)); 765 samsung_clk_register_pll(ctx, s5pv210_pll_clks, 766 ARRAY_SIZE(s5pv210_pll_clks)); 767 samsung_clk_register_mux(ctx, s5pv210_mux_clks, 768 ARRAY_SIZE(s5pv210_mux_clks)); 769 samsung_clk_register_div(ctx, s5pv210_div_clks, 770 ARRAY_SIZE(s5pv210_div_clks)); 771 samsung_clk_register_gate(ctx, s5pv210_gate_clks, 772 ARRAY_SIZE(s5pv210_gate_clks)); 773 } 774 775 samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks)); 776 samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks)); 777 samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks)); 778 779 samsung_clk_register_fixed_factor(ctx, ffactor_clks, 780 ARRAY_SIZE(ffactor_clks)); 781 782 samsung_clk_register_alias(ctx, s5pv210_aliases, 783 ARRAY_SIZE(s5pv210_aliases)); 784 785 samsung_clk_sleep_init(reg_base, s5pv210_clk_regs, 786 ARRAY_SIZE(s5pv210_clk_regs)); 787 788 samsung_clk_of_add_provider(np, ctx); 789 790 pr_info("%s clocks: mout_apll = %ld, mout_mpll = %ld\n" 791 "\tmout_epll = %ld, mout_vpll = %ld\n", 792 is_s5p6442 ? "S5P6442" : "S5PV210", 793 clk_hw_get_rate(hws[MOUT_APLL]), 794 clk_hw_get_rate(hws[MOUT_MPLL]), 795 clk_hw_get_rate(hws[MOUT_EPLL]), 796 clk_hw_get_rate(hws[MOUT_VPLL])); 797 } 798 799 static void __init s5pv210_clk_dt_init(struct device_node *np) 800 { 801 reg_base = of_iomap(np, 0); 802 if (!reg_base) 803 panic("%s: failed to map registers\n", __func__); 804 805 __s5pv210_clk_init(np, 0, 0, false); 806 } 807 CLK_OF_DECLARE(s5pv210_clk, "samsung,s5pv210-clock", s5pv210_clk_dt_init); 808 809 static void __init s5p6442_clk_dt_init(struct device_node *np) 810 { 811 reg_base = of_iomap(np, 0); 812 if (!reg_base) 813 panic("%s: failed to map registers\n", __func__); 814 815 __s5pv210_clk_init(np, 0, 0, true); 816 } 817 CLK_OF_DECLARE(s5p6442_clk, "samsung,s5p6442-clock", s5p6442_clk_dt_init); 818