1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com> 4 * 5 * Based on Exynos Audio Subsystem Clock Controller driver: 6 * 7 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 8 * Author: Padmavathi Venna <padma.v@samsung.com> 9 * 10 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/of_address.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/init.h> 20 #include <linux/platform_device.h> 21 22 #include <dt-bindings/clock/s5pv210-audss.h> 23 24 static DEFINE_SPINLOCK(lock); 25 static void __iomem *reg_base; 26 static struct clk_hw_onecell_data *clk_data; 27 28 #define ASS_CLK_SRC 0x0 29 #define ASS_CLK_DIV 0x4 30 #define ASS_CLK_GATE 0x8 31 32 #ifdef CONFIG_PM_SLEEP 33 static unsigned long reg_save[][2] = { 34 {ASS_CLK_SRC, 0}, 35 {ASS_CLK_DIV, 0}, 36 {ASS_CLK_GATE, 0}, 37 }; 38 39 static int s5pv210_audss_clk_suspend(void) 40 { 41 int i; 42 43 for (i = 0; i < ARRAY_SIZE(reg_save); i++) 44 reg_save[i][1] = readl(reg_base + reg_save[i][0]); 45 46 return 0; 47 } 48 49 static void s5pv210_audss_clk_resume(void) 50 { 51 int i; 52 53 for (i = 0; i < ARRAY_SIZE(reg_save); i++) 54 writel(reg_save[i][1], reg_base + reg_save[i][0]); 55 } 56 57 static struct syscore_ops s5pv210_audss_clk_syscore_ops = { 58 .suspend = s5pv210_audss_clk_suspend, 59 .resume = s5pv210_audss_clk_resume, 60 }; 61 #endif /* CONFIG_PM_SLEEP */ 62 63 /* register s5pv210_audss clocks */ 64 static int s5pv210_audss_clk_probe(struct platform_device *pdev) 65 { 66 int i, ret = 0; 67 const char *mout_audss_p[2]; 68 const char *mout_i2s_p[3]; 69 const char *hclk_p; 70 struct clk_hw **clk_table; 71 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; 72 73 reg_base = devm_platform_ioremap_resource(pdev, 0); 74 if (IS_ERR(reg_base)) 75 return PTR_ERR(reg_base); 76 77 clk_data = devm_kzalloc(&pdev->dev, 78 struct_size(clk_data, hws, AUDSS_MAX_CLKS), 79 GFP_KERNEL); 80 81 if (!clk_data) 82 return -ENOMEM; 83 84 clk_data->num = AUDSS_MAX_CLKS; 85 clk_table = clk_data->hws; 86 87 hclk = devm_clk_get(&pdev->dev, "hclk"); 88 if (IS_ERR(hclk)) { 89 dev_err(&pdev->dev, "failed to get hclk clock\n"); 90 return PTR_ERR(hclk); 91 } 92 93 pll_in = devm_clk_get(&pdev->dev, "fout_epll"); 94 if (IS_ERR(pll_in)) { 95 dev_err(&pdev->dev, "failed to get fout_epll clock\n"); 96 return PTR_ERR(pll_in); 97 } 98 99 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0"); 100 if (IS_ERR(sclk_audio)) { 101 dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n"); 102 return PTR_ERR(sclk_audio); 103 } 104 105 /* iiscdclk0 is an optional external I2S codec clock */ 106 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); 107 pll_ref = devm_clk_get(&pdev->dev, "xxti"); 108 109 if (!IS_ERR(pll_ref)) 110 mout_audss_p[0] = __clk_get_name(pll_ref); 111 else 112 mout_audss_p[0] = "xxti"; 113 mout_audss_p[1] = __clk_get_name(pll_in); 114 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", 115 mout_audss_p, ARRAY_SIZE(mout_audss_p), 116 CLK_SET_RATE_NO_REPARENT, 117 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 118 119 mout_i2s_p[0] = "mout_audss"; 120 if (!IS_ERR(cdclk)) 121 mout_i2s_p[1] = __clk_get_name(cdclk); 122 else 123 mout_i2s_p[1] = "iiscdclk0"; 124 mout_i2s_p[2] = __clk_get_name(sclk_audio); 125 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", 126 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 127 CLK_SET_RATE_NO_REPARENT, 128 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 129 130 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, 131 "dout_aud_bus", "mout_audss", 0, 132 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); 133 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, 134 "dout_i2s_audss", "mout_i2s_audss", 0, 135 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); 136 137 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", 138 "dout_i2s_audss", CLK_SET_RATE_PARENT, 139 reg_base + ASS_CLK_GATE, 6, 0, &lock); 140 141 hclk_p = __clk_get_name(hclk); 142 143 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", 144 hclk_p, CLK_IGNORE_UNUSED, 145 reg_base + ASS_CLK_GATE, 5, 0, &lock); 146 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", 147 hclk_p, CLK_IGNORE_UNUSED, 148 reg_base + ASS_CLK_GATE, 4, 0, &lock); 149 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", 150 hclk_p, CLK_IGNORE_UNUSED, 151 reg_base + ASS_CLK_GATE, 3, 0, &lock); 152 clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss", 153 hclk_p, CLK_IGNORE_UNUSED, 154 reg_base + ASS_CLK_GATE, 2, 0, &lock); 155 clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss", 156 hclk_p, CLK_IGNORE_UNUSED, 157 reg_base + ASS_CLK_GATE, 1, 0, &lock); 158 clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss", 159 hclk_p, CLK_IGNORE_UNUSED, 160 reg_base + ASS_CLK_GATE, 0, 0, &lock); 161 162 for (i = 0; i < clk_data->num; i++) { 163 if (IS_ERR(clk_table[i])) { 164 dev_err(&pdev->dev, "failed to register clock %d\n", i); 165 ret = PTR_ERR(clk_table[i]); 166 goto unregister; 167 } 168 } 169 170 ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, 171 clk_data); 172 if (ret) { 173 dev_err(&pdev->dev, "failed to add clock provider\n"); 174 goto unregister; 175 } 176 177 #ifdef CONFIG_PM_SLEEP 178 register_syscore_ops(&s5pv210_audss_clk_syscore_ops); 179 #endif 180 181 return 0; 182 183 unregister: 184 for (i = 0; i < clk_data->num; i++) { 185 if (!IS_ERR(clk_table[i])) 186 clk_hw_unregister(clk_table[i]); 187 } 188 189 return ret; 190 } 191 192 static const struct of_device_id s5pv210_audss_clk_of_match[] = { 193 { .compatible = "samsung,s5pv210-audss-clock", }, 194 {}, 195 }; 196 197 static struct platform_driver s5pv210_audss_clk_driver = { 198 .driver = { 199 .name = "s5pv210-audss-clk", 200 .suppress_bind_attrs = true, 201 .of_match_table = s5pv210_audss_clk_of_match, 202 }, 203 .probe = s5pv210_audss_clk_probe, 204 }; 205 206 static int __init s5pv210_audss_clk_init(void) 207 { 208 return platform_driver_register(&s5pv210_audss_clk_driver); 209 } 210 core_initcall(s5pv210_audss_clk_init); 211