1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Tomasz Figa <t.figa@samsung.com> 4 * 5 * Based on Exynos Audio Subsystem Clock Controller driver: 6 * 7 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 8 * Author: Padmavathi Venna <padma.v@samsung.com> 9 * 10 * Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs. 11 */ 12 13 #include <linux/io.h> 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/of_address.h> 17 #include <linux/syscore_ops.h> 18 #include <linux/init.h> 19 #include <linux/platform_device.h> 20 21 #include <dt-bindings/clock/s5pv210-audss.h> 22 23 static DEFINE_SPINLOCK(lock); 24 static void __iomem *reg_base; 25 static struct clk_hw_onecell_data *clk_data; 26 27 #define ASS_CLK_SRC 0x0 28 #define ASS_CLK_DIV 0x4 29 #define ASS_CLK_GATE 0x8 30 31 #ifdef CONFIG_PM_SLEEP 32 static unsigned long reg_save[][2] = { 33 {ASS_CLK_SRC, 0}, 34 {ASS_CLK_DIV, 0}, 35 {ASS_CLK_GATE, 0}, 36 }; 37 38 static int s5pv210_audss_clk_suspend(void) 39 { 40 int i; 41 42 for (i = 0; i < ARRAY_SIZE(reg_save); i++) 43 reg_save[i][1] = readl(reg_base + reg_save[i][0]); 44 45 return 0; 46 } 47 48 static void s5pv210_audss_clk_resume(void) 49 { 50 int i; 51 52 for (i = 0; i < ARRAY_SIZE(reg_save); i++) 53 writel(reg_save[i][1], reg_base + reg_save[i][0]); 54 } 55 56 static struct syscore_ops s5pv210_audss_clk_syscore_ops = { 57 .suspend = s5pv210_audss_clk_suspend, 58 .resume = s5pv210_audss_clk_resume, 59 }; 60 #endif /* CONFIG_PM_SLEEP */ 61 62 /* register s5pv210_audss clocks */ 63 static int s5pv210_audss_clk_probe(struct platform_device *pdev) 64 { 65 int i, ret = 0; 66 struct resource *res; 67 const char *mout_audss_p[2]; 68 const char *mout_i2s_p[3]; 69 const char *hclk_p; 70 struct clk_hw **clk_table; 71 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; 72 73 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 74 reg_base = devm_ioremap_resource(&pdev->dev, res); 75 if (IS_ERR(reg_base)) { 76 dev_err(&pdev->dev, "failed to map audss registers\n"); 77 return PTR_ERR(reg_base); 78 } 79 80 clk_data = devm_kzalloc(&pdev->dev, 81 struct_size(clk_data, hws, AUDSS_MAX_CLKS), 82 GFP_KERNEL); 83 84 if (!clk_data) 85 return -ENOMEM; 86 87 clk_data->num = AUDSS_MAX_CLKS; 88 clk_table = clk_data->hws; 89 90 hclk = devm_clk_get(&pdev->dev, "hclk"); 91 if (IS_ERR(hclk)) { 92 dev_err(&pdev->dev, "failed to get hclk clock\n"); 93 return PTR_ERR(hclk); 94 } 95 96 pll_in = devm_clk_get(&pdev->dev, "fout_epll"); 97 if (IS_ERR(pll_in)) { 98 dev_err(&pdev->dev, "failed to get fout_epll clock\n"); 99 return PTR_ERR(pll_in); 100 } 101 102 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0"); 103 if (IS_ERR(sclk_audio)) { 104 dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n"); 105 return PTR_ERR(sclk_audio); 106 } 107 108 /* iiscdclk0 is an optional external I2S codec clock */ 109 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); 110 pll_ref = devm_clk_get(&pdev->dev, "xxti"); 111 112 if (!IS_ERR(pll_ref)) 113 mout_audss_p[0] = __clk_get_name(pll_ref); 114 else 115 mout_audss_p[0] = "xxti"; 116 mout_audss_p[1] = __clk_get_name(pll_in); 117 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", 118 mout_audss_p, ARRAY_SIZE(mout_audss_p), 119 CLK_SET_RATE_NO_REPARENT, 120 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 121 122 mout_i2s_p[0] = "mout_audss"; 123 if (!IS_ERR(cdclk)) 124 mout_i2s_p[1] = __clk_get_name(cdclk); 125 else 126 mout_i2s_p[1] = "iiscdclk0"; 127 mout_i2s_p[2] = __clk_get_name(sclk_audio); 128 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", 129 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 130 CLK_SET_RATE_NO_REPARENT, 131 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 132 133 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, 134 "dout_aud_bus", "mout_audss", 0, 135 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); 136 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, 137 "dout_i2s_audss", "mout_i2s_audss", 0, 138 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); 139 140 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", 141 "dout_i2s_audss", CLK_SET_RATE_PARENT, 142 reg_base + ASS_CLK_GATE, 6, 0, &lock); 143 144 hclk_p = __clk_get_name(hclk); 145 146 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", 147 hclk_p, CLK_IGNORE_UNUSED, 148 reg_base + ASS_CLK_GATE, 5, 0, &lock); 149 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", 150 hclk_p, CLK_IGNORE_UNUSED, 151 reg_base + ASS_CLK_GATE, 4, 0, &lock); 152 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", 153 hclk_p, CLK_IGNORE_UNUSED, 154 reg_base + ASS_CLK_GATE, 3, 0, &lock); 155 clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss", 156 hclk_p, CLK_IGNORE_UNUSED, 157 reg_base + ASS_CLK_GATE, 2, 0, &lock); 158 clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss", 159 hclk_p, CLK_IGNORE_UNUSED, 160 reg_base + ASS_CLK_GATE, 1, 0, &lock); 161 clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss", 162 hclk_p, CLK_IGNORE_UNUSED, 163 reg_base + ASS_CLK_GATE, 0, 0, &lock); 164 165 for (i = 0; i < clk_data->num; i++) { 166 if (IS_ERR(clk_table[i])) { 167 dev_err(&pdev->dev, "failed to register clock %d\n", i); 168 ret = PTR_ERR(clk_table[i]); 169 goto unregister; 170 } 171 } 172 173 ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, 174 clk_data); 175 if (ret) { 176 dev_err(&pdev->dev, "failed to add clock provider\n"); 177 goto unregister; 178 } 179 180 #ifdef CONFIG_PM_SLEEP 181 register_syscore_ops(&s5pv210_audss_clk_syscore_ops); 182 #endif 183 184 return 0; 185 186 unregister: 187 for (i = 0; i < clk_data->num; i++) { 188 if (!IS_ERR(clk_table[i])) 189 clk_hw_unregister(clk_table[i]); 190 } 191 192 return ret; 193 } 194 195 static const struct of_device_id s5pv210_audss_clk_of_match[] = { 196 { .compatible = "samsung,s5pv210-audss-clock", }, 197 {}, 198 }; 199 200 static struct platform_driver s5pv210_audss_clk_driver = { 201 .driver = { 202 .name = "s5pv210-audss-clk", 203 .suppress_bind_attrs = true, 204 .of_match_table = s5pv210_audss_clk_of_match, 205 }, 206 .probe = s5pv210_audss_clk_probe, 207 }; 208 209 static int __init s5pv210_audss_clk_init(void) 210 { 211 return platform_driver_register(&s5pv210_audss_clk_driver); 212 } 213 core_initcall(s5pv210_audss_clk_init); 214