1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2013 Linaro Ltd. 5 * 6 * Common Clock Framework support for all PLL's in Samsung platforms 7 */ 8 9 #ifndef __SAMSUNG_CLK_PLL_H 10 #define __SAMSUNG_CLK_PLL_H 11 12 enum samsung_pll_type { 13 pll_2126, 14 pll_3000, 15 pll_35xx, 16 pll_36xx, 17 pll_2550, 18 pll_2650, 19 pll_4500, 20 pll_4502, 21 pll_4508, 22 pll_4600, 23 pll_4650, 24 pll_4650c, 25 pll_6552, 26 pll_6552_s3c2416, 27 pll_6553, 28 pll_2550x, 29 pll_2550xx, 30 pll_2650x, 31 pll_2650xx, 32 pll_1417x, 33 pll_1418x, 34 pll_1450x, 35 pll_1451x, 36 pll_1452x, 37 pll_1460x, 38 pll_0818x, 39 pll_0822x, 40 pll_0831x, 41 pll_142xx, 42 pll_0516x, 43 pll_0517x, 44 pll_0518x, 45 pll_531x, 46 pll_1051x, 47 pll_1052x, 48 pll_0717x, 49 pll_0718x, 50 pll_0732x, 51 pll_4311, 52 pll_1017x, 53 pll_1031x, 54 pll_a9fracm, 55 pll_a9fraco, 56 }; 57 58 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ 59 ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) << (_s))) 60 #define PLL_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \ 61 BUILD_BUG_ON_ZERO(PLL_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout))) 62 63 #define PLL_FRACO_RATE(_fin, _m, _p, _s, _k, _ks) \ 64 ((u64)(_fin) * (BIT(_ks) * (_m) + (_k)) / BIT(_ks) / ((_p) * ((_s) + 1))) 65 #define PLL_FRACO_VALID_RATE(_fin, _fout, _m, _p, _s, _k, _ks) ((_fout) + \ 66 BUILD_BUG_ON_ZERO(PLL_FRACO_RATE(_fin, _m, _p, _s, _k, _ks) != (_fout))) 67 68 #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \ 69 { \ 70 .rate = PLL_VALID_RATE(_fin, _rate, \ 71 _m, _p, _s, 0, 16), \ 72 .mdiv = (_m), \ 73 .pdiv = (_p), \ 74 .sdiv = (_s), \ 75 } 76 77 #define PLL_36XX_RATE(_fin, _rate, _m, _p, _s, _k) \ 78 { \ 79 .rate = PLL_VALID_RATE(_fin, _rate, \ 80 _m, _p, _s, _k, 16), \ 81 .mdiv = (_m), \ 82 .pdiv = (_p), \ 83 .sdiv = (_s), \ 84 .kdiv = (_k), \ 85 } 86 87 #define PLL_4508_RATE(_fin, _rate, _m, _p, _s, _afc) \ 88 { \ 89 .rate = PLL_VALID_RATE(_fin, _rate, \ 90 _m, _p, _s - 1, 0, 16), \ 91 .mdiv = (_m), \ 92 .pdiv = (_p), \ 93 .sdiv = (_s), \ 94 .afc = (_afc), \ 95 } 96 97 #define PLL_4600_RATE(_fin, _rate, _m, _p, _s, _k, _vsel) \ 98 { \ 99 .rate = PLL_VALID_RATE(_fin, _rate, \ 100 _m, _p, _s, _k, 16), \ 101 .mdiv = (_m), \ 102 .pdiv = (_p), \ 103 .sdiv = (_s), \ 104 .kdiv = (_k), \ 105 .vsel = (_vsel), \ 106 } 107 108 #define PLL_4650_RATE(_fin, _rate, _m, _p, _s, _k, _mfr, _mrr, _vsel) \ 109 { \ 110 .rate = PLL_VALID_RATE(_fin, _rate, \ 111 _m, _p, _s, _k, 10), \ 112 .mdiv = (_m), \ 113 .pdiv = (_p), \ 114 .sdiv = (_s), \ 115 .kdiv = (_k), \ 116 .mfr = (_mfr), \ 117 .mrr = (_mrr), \ 118 .vsel = (_vsel), \ 119 } 120 121 #define PLL_A9FRACO_RATE(_fin, _rate, _m, _p, _s, _k) \ 122 { \ 123 .rate = PLL_FRACO_VALID_RATE(_fin, _rate, \ 124 _m, _p, _s, _k, 24), \ 125 .mdiv = (_m), \ 126 .pdiv = (_p), \ 127 .sdiv = (_s), \ 128 .kdiv = (_k), \ 129 } 130 131 /* NOTE: Rate table should be kept sorted in descending order. */ 132 133 struct samsung_pll_rate_table { 134 unsigned int rate; 135 unsigned int pdiv; 136 unsigned int mdiv; 137 unsigned int sdiv; 138 unsigned int kdiv; 139 unsigned int afc; 140 unsigned int mfr; 141 unsigned int mrr; 142 unsigned int vsel; 143 }; 144 145 #endif /* __SAMSUNG_CLK_PLL_H */ 146