1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2013 Linaro Ltd. 5 * 6 * This file contains the utility functions to register the pll clocks. 7 */ 8 9 #include <linux/errno.h> 10 #include <linux/hrtimer.h> 11 #include <linux/iopoll.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/timekeeping.h> 15 #include <linux/clk-provider.h> 16 #include <linux/io.h> 17 #include "clk.h" 18 #include "clk-pll.h" 19 20 #define PLL_TIMEOUT_US 20000U 21 #define PLL_TIMEOUT_LOOPS 1000000U 22 23 struct samsung_clk_pll { 24 struct clk_hw hw; 25 void __iomem *lock_reg; 26 void __iomem *con_reg; 27 /* PLL enable control bit offset in @con_reg register */ 28 unsigned short enable_offs; 29 /* PLL lock status bit offset in @con_reg register */ 30 unsigned short lock_offs; 31 enum samsung_pll_type type; 32 unsigned int rate_count; 33 const struct samsung_pll_rate_table *rate_table; 34 }; 35 36 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) 37 38 static const struct samsung_pll_rate_table *samsung_get_pll_settings( 39 struct samsung_clk_pll *pll, unsigned long rate) 40 { 41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; 42 int i; 43 44 for (i = 0; i < pll->rate_count; i++) { 45 if (rate == rate_table[i].rate) 46 return &rate_table[i]; 47 } 48 49 return NULL; 50 } 51 52 static long samsung_pll_round_rate(struct clk_hw *hw, 53 unsigned long drate, unsigned long *prate) 54 { 55 struct samsung_clk_pll *pll = to_clk_pll(hw); 56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; 57 int i; 58 59 /* Assumming rate_table is in descending order */ 60 for (i = 0; i < pll->rate_count; i++) { 61 if (drate >= rate_table[i].rate) 62 return rate_table[i].rate; 63 } 64 65 /* return minimum supported value */ 66 return rate_table[i - 1].rate; 67 } 68 69 static bool pll_early_timeout = true; 70 71 static int __init samsung_pll_disable_early_timeout(void) 72 { 73 pll_early_timeout = false; 74 return 0; 75 } 76 arch_initcall(samsung_pll_disable_early_timeout); 77 78 /* Wait until the PLL is locked */ 79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, 80 unsigned int reg_mask) 81 { 82 int i, ret; 83 u32 val; 84 85 /* 86 * This function might be called when the timekeeping API can't be used 87 * to detect timeouts. One situation is when the clocksource is not yet 88 * initialized, another when the timekeeping is suspended. udelay() also 89 * cannot be used when the clocksource is not running on arm64, since 90 * the current timer is used as cycle counter. So a simple busy loop 91 * is used here in that special cases. The limit of iterations has been 92 * derived from experimental measurements of various PLLs on multiple 93 * Exynos SoC variants. Single register read time was usually in range 94 * 0.4...1.5 us, never less than 0.4 us. 95 */ 96 if (pll_early_timeout || timekeeping_suspended) { 97 i = PLL_TIMEOUT_LOOPS; 98 while (i-- > 0) { 99 if (readl_relaxed(pll->con_reg) & reg_mask) 100 return 0; 101 102 cpu_relax(); 103 } 104 ret = -ETIMEDOUT; 105 } else { 106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, 107 val & reg_mask, 0, PLL_TIMEOUT_US); 108 } 109 110 if (ret < 0) 111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); 112 113 return ret; 114 } 115 116 static int samsung_pll3xxx_enable(struct clk_hw *hw) 117 { 118 struct samsung_clk_pll *pll = to_clk_pll(hw); 119 u32 tmp; 120 121 tmp = readl_relaxed(pll->con_reg); 122 tmp |= BIT(pll->enable_offs); 123 writel_relaxed(tmp, pll->con_reg); 124 125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 126 } 127 128 static void samsung_pll3xxx_disable(struct clk_hw *hw) 129 { 130 struct samsung_clk_pll *pll = to_clk_pll(hw); 131 u32 tmp; 132 133 tmp = readl_relaxed(pll->con_reg); 134 tmp &= ~BIT(pll->enable_offs); 135 writel_relaxed(tmp, pll->con_reg); 136 } 137 138 /* 139 * PLL2126 Clock Type 140 */ 141 142 #define PLL2126_MDIV_MASK (0xff) 143 #define PLL2126_PDIV_MASK (0x3f) 144 #define PLL2126_SDIV_MASK (0x3) 145 #define PLL2126_MDIV_SHIFT (16) 146 #define PLL2126_PDIV_SHIFT (8) 147 #define PLL2126_SDIV_SHIFT (0) 148 149 static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, 150 unsigned long parent_rate) 151 { 152 struct samsung_clk_pll *pll = to_clk_pll(hw); 153 u32 pll_con, mdiv, pdiv, sdiv; 154 u64 fvco = parent_rate; 155 156 pll_con = readl_relaxed(pll->con_reg); 157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; 158 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; 159 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; 160 161 fvco *= (mdiv + 8); 162 do_div(fvco, (pdiv + 2) << sdiv); 163 164 return (unsigned long)fvco; 165 } 166 167 static const struct clk_ops samsung_pll2126_clk_ops = { 168 .recalc_rate = samsung_pll2126_recalc_rate, 169 }; 170 171 /* 172 * PLL3000 Clock Type 173 */ 174 175 #define PLL3000_MDIV_MASK (0xff) 176 #define PLL3000_PDIV_MASK (0x3) 177 #define PLL3000_SDIV_MASK (0x3) 178 #define PLL3000_MDIV_SHIFT (16) 179 #define PLL3000_PDIV_SHIFT (8) 180 #define PLL3000_SDIV_SHIFT (0) 181 182 static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, 183 unsigned long parent_rate) 184 { 185 struct samsung_clk_pll *pll = to_clk_pll(hw); 186 u32 pll_con, mdiv, pdiv, sdiv; 187 u64 fvco = parent_rate; 188 189 pll_con = readl_relaxed(pll->con_reg); 190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; 191 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; 192 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; 193 194 fvco *= (2 * (mdiv + 8)); 195 do_div(fvco, pdiv << sdiv); 196 197 return (unsigned long)fvco; 198 } 199 200 static const struct clk_ops samsung_pll3000_clk_ops = { 201 .recalc_rate = samsung_pll3000_recalc_rate, 202 }; 203 204 /* 205 * PLL35xx Clock Type 206 */ 207 /* Maximum lock time can be 270 * PDIV cycles */ 208 #define PLL35XX_LOCK_FACTOR (270) 209 210 #define PLL35XX_MDIV_MASK (0x3FF) 211 #define PLL35XX_PDIV_MASK (0x3F) 212 #define PLL35XX_SDIV_MASK (0x7) 213 #define PLL35XX_MDIV_SHIFT (16) 214 #define PLL35XX_PDIV_SHIFT (8) 215 #define PLL35XX_SDIV_SHIFT (0) 216 #define PLL35XX_LOCK_STAT_SHIFT (29) 217 #define PLL35XX_ENABLE_SHIFT (31) 218 219 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, 220 unsigned long parent_rate) 221 { 222 struct samsung_clk_pll *pll = to_clk_pll(hw); 223 u32 mdiv, pdiv, sdiv, pll_con; 224 u64 fvco = parent_rate; 225 226 pll_con = readl_relaxed(pll->con_reg); 227 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; 228 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; 229 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; 230 231 fvco *= mdiv; 232 do_div(fvco, (pdiv << sdiv)); 233 234 return (unsigned long)fvco; 235 } 236 237 static inline bool samsung_pll35xx_mp_change( 238 const struct samsung_pll_rate_table *rate, u32 pll_con) 239 { 240 u32 old_mdiv, old_pdiv; 241 242 old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; 243 old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; 244 245 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); 246 } 247 248 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, 249 unsigned long prate) 250 { 251 struct samsung_clk_pll *pll = to_clk_pll(hw); 252 const struct samsung_pll_rate_table *rate; 253 u32 tmp; 254 255 /* Get required rate settings from table */ 256 rate = samsung_get_pll_settings(pll, drate); 257 if (!rate) { 258 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 259 drate, clk_hw_get_name(hw)); 260 return -EINVAL; 261 } 262 263 tmp = readl_relaxed(pll->con_reg); 264 265 if (!(samsung_pll35xx_mp_change(rate, tmp))) { 266 /* If only s change, change just s value only*/ 267 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); 268 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; 269 writel_relaxed(tmp, pll->con_reg); 270 271 return 0; 272 } 273 274 /* Set PLL lock time. */ 275 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, 276 pll->lock_reg); 277 278 /* Change PLL PMS values */ 279 tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) | 280 (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) | 281 (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT)); 282 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | 283 (rate->pdiv << PLL35XX_PDIV_SHIFT) | 284 (rate->sdiv << PLL35XX_SDIV_SHIFT); 285 writel_relaxed(tmp, pll->con_reg); 286 287 /* Wait for PLL lock if the PLL is enabled */ 288 if (tmp & BIT(pll->enable_offs)) 289 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 290 291 return 0; 292 } 293 294 static const struct clk_ops samsung_pll35xx_clk_ops = { 295 .recalc_rate = samsung_pll35xx_recalc_rate, 296 .round_rate = samsung_pll_round_rate, 297 .set_rate = samsung_pll35xx_set_rate, 298 .enable = samsung_pll3xxx_enable, 299 .disable = samsung_pll3xxx_disable, 300 }; 301 302 static const struct clk_ops samsung_pll35xx_clk_min_ops = { 303 .recalc_rate = samsung_pll35xx_recalc_rate, 304 }; 305 306 /* 307 * PLL36xx Clock Type 308 */ 309 /* Maximum lock time can be 3000 * PDIV cycles */ 310 #define PLL36XX_LOCK_FACTOR (3000) 311 312 #define PLL36XX_KDIV_MASK (0xFFFF) 313 #define PLL36XX_MDIV_MASK (0x1FF) 314 #define PLL36XX_PDIV_MASK (0x3F) 315 #define PLL36XX_SDIV_MASK (0x7) 316 #define PLL36XX_MDIV_SHIFT (16) 317 #define PLL36XX_PDIV_SHIFT (8) 318 #define PLL36XX_SDIV_SHIFT (0) 319 #define PLL36XX_KDIV_SHIFT (0) 320 #define PLL36XX_LOCK_STAT_SHIFT (29) 321 #define PLL36XX_ENABLE_SHIFT (31) 322 323 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, 324 unsigned long parent_rate) 325 { 326 struct samsung_clk_pll *pll = to_clk_pll(hw); 327 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; 328 s16 kdiv; 329 u64 fvco = parent_rate; 330 331 pll_con0 = readl_relaxed(pll->con_reg); 332 pll_con1 = readl_relaxed(pll->con_reg + 4); 333 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 334 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 335 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; 336 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK); 337 338 fvco *= (mdiv << 16) + kdiv; 339 do_div(fvco, (pdiv << sdiv)); 340 fvco >>= 16; 341 342 return (unsigned long)fvco; 343 } 344 345 static inline bool samsung_pll36xx_mpk_change( 346 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) 347 { 348 u32 old_mdiv, old_pdiv, old_kdiv; 349 350 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 351 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 352 old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK; 353 354 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || 355 rate->kdiv != old_kdiv); 356 } 357 358 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, 359 unsigned long parent_rate) 360 { 361 struct samsung_clk_pll *pll = to_clk_pll(hw); 362 u32 pll_con0, pll_con1; 363 const struct samsung_pll_rate_table *rate; 364 365 rate = samsung_get_pll_settings(pll, drate); 366 if (!rate) { 367 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 368 drate, clk_hw_get_name(hw)); 369 return -EINVAL; 370 } 371 372 pll_con0 = readl_relaxed(pll->con_reg); 373 pll_con1 = readl_relaxed(pll->con_reg + 4); 374 375 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { 376 /* If only s change, change just s value only*/ 377 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); 378 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); 379 writel_relaxed(pll_con0, pll->con_reg); 380 381 return 0; 382 } 383 384 /* Set PLL lock time. */ 385 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); 386 387 /* Change PLL PMS values */ 388 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | 389 (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) | 390 (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT)); 391 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | 392 (rate->pdiv << PLL36XX_PDIV_SHIFT) | 393 (rate->sdiv << PLL36XX_SDIV_SHIFT); 394 writel_relaxed(pll_con0, pll->con_reg); 395 396 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); 397 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; 398 writel_relaxed(pll_con1, pll->con_reg + 4); 399 400 if (pll_con0 & BIT(pll->enable_offs)) 401 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 402 403 return 0; 404 } 405 406 static const struct clk_ops samsung_pll36xx_clk_ops = { 407 .recalc_rate = samsung_pll36xx_recalc_rate, 408 .set_rate = samsung_pll36xx_set_rate, 409 .round_rate = samsung_pll_round_rate, 410 .enable = samsung_pll3xxx_enable, 411 .disable = samsung_pll3xxx_disable, 412 }; 413 414 static const struct clk_ops samsung_pll36xx_clk_min_ops = { 415 .recalc_rate = samsung_pll36xx_recalc_rate, 416 }; 417 418 /* 419 * PLL0822x Clock Type 420 */ 421 /* Maximum lock time can be 150 * PDIV cycles */ 422 #define PLL0822X_LOCK_FACTOR (150) 423 424 #define PLL0822X_MDIV_MASK (0x3FF) 425 #define PLL0822X_PDIV_MASK (0x3F) 426 #define PLL0822X_SDIV_MASK (0x7) 427 #define PLL0822X_MDIV_SHIFT (16) 428 #define PLL0822X_PDIV_SHIFT (8) 429 #define PLL0822X_SDIV_SHIFT (0) 430 #define PLL0822X_LOCK_STAT_SHIFT (29) 431 #define PLL0822X_ENABLE_SHIFT (31) 432 433 /* 434 * PLL1418x, PLL0717x and PLL0718x are similar 435 * to PLL0822x, except that MDIV is one bit smaller 436 */ 437 #define PLL1418X_MDIV_MASK (0x1FF) 438 439 static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, 440 unsigned long parent_rate) 441 { 442 struct samsung_clk_pll *pll = to_clk_pll(hw); 443 u32 mdiv, pdiv, sdiv, pll_con3; 444 u64 fvco = parent_rate; 445 446 pll_con3 = readl_relaxed(pll->con_reg); 447 448 if (pll->type != pll_1418x && 449 pll->type != pll_0717x && 450 pll->type != pll_0718x) 451 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; 452 else 453 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK; 454 455 pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; 456 sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; 457 458 fvco *= mdiv; 459 if (pll->type == pll_0516x) 460 fvco *= 2; 461 462 do_div(fvco, (pdiv << sdiv)); 463 464 return (unsigned long)fvco; 465 } 466 467 static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, 468 unsigned long prate) 469 { 470 const struct samsung_pll_rate_table *rate; 471 struct samsung_clk_pll *pll = to_clk_pll(hw); 472 u32 mdiv_mask, pll_con3; 473 474 if (pll->type != pll_1418x) 475 mdiv_mask = PLL0822X_MDIV_MASK; 476 else 477 mdiv_mask = PLL1418X_MDIV_MASK; 478 479 /* Get required rate settings from table */ 480 rate = samsung_get_pll_settings(pll, drate); 481 if (!rate) { 482 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 483 drate, clk_hw_get_name(hw)); 484 return -EINVAL; 485 } 486 487 /* Change PLL PMS values */ 488 pll_con3 = readl_relaxed(pll->con_reg); 489 pll_con3 &= ~((mdiv_mask << PLL0822X_MDIV_SHIFT) | 490 (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | 491 (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); 492 pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | 493 (rate->pdiv << PLL0822X_PDIV_SHIFT) | 494 (rate->sdiv << PLL0822X_SDIV_SHIFT); 495 496 /* Set PLL lock time */ 497 writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR, 498 pll->lock_reg); 499 500 /* Write PMS values */ 501 writel_relaxed(pll_con3, pll->con_reg); 502 503 /* Wait for PLL lock if the PLL is enabled */ 504 if (pll_con3 & BIT(pll->enable_offs)) 505 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 506 507 return 0; 508 } 509 510 static const struct clk_ops samsung_pll0822x_clk_ops = { 511 .recalc_rate = samsung_pll0822x_recalc_rate, 512 .round_rate = samsung_pll_round_rate, 513 .set_rate = samsung_pll0822x_set_rate, 514 .enable = samsung_pll3xxx_enable, 515 .disable = samsung_pll3xxx_disable, 516 }; 517 518 static const struct clk_ops samsung_pll0822x_clk_min_ops = { 519 .recalc_rate = samsung_pll0822x_recalc_rate, 520 }; 521 522 /* 523 * PLL0831x Clock Type 524 */ 525 /* Maximum lock time can be 500 * PDIV cycles */ 526 #define PLL0831X_LOCK_FACTOR (500) 527 528 #define PLL0831X_KDIV_MASK (0xFFFF) 529 #define PLL0831X_MDIV_MASK (0x1FF) 530 #define PLL0831X_PDIV_MASK (0x3F) 531 #define PLL0831X_SDIV_MASK (0x7) 532 #define PLL0831X_MDIV_SHIFT (16) 533 #define PLL0831X_PDIV_SHIFT (8) 534 #define PLL0831X_SDIV_SHIFT (0) 535 #define PLL0831X_KDIV_SHIFT (0) 536 #define PLL0831X_LOCK_STAT_SHIFT (29) 537 #define PLL0831X_ENABLE_SHIFT (31) 538 539 static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw, 540 unsigned long parent_rate) 541 { 542 struct samsung_clk_pll *pll = to_clk_pll(hw); 543 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; 544 s16 kdiv; 545 u64 fvco = parent_rate; 546 547 pll_con3 = readl_relaxed(pll->con_reg); 548 pll_con5 = readl_relaxed(pll->con_reg + 8); 549 mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK; 550 pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK; 551 sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK; 552 kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK); 553 554 fvco *= (mdiv << 16) + kdiv; 555 do_div(fvco, (pdiv << sdiv)); 556 fvco >>= 16; 557 558 return (unsigned long)fvco; 559 } 560 561 static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate, 562 unsigned long parent_rate) 563 { 564 const struct samsung_pll_rate_table *rate; 565 struct samsung_clk_pll *pll = to_clk_pll(hw); 566 u32 pll_con3, pll_con5; 567 568 /* Get required rate settings from table */ 569 rate = samsung_get_pll_settings(pll, drate); 570 if (!rate) { 571 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 572 drate, clk_hw_get_name(hw)); 573 return -EINVAL; 574 } 575 576 pll_con3 = readl_relaxed(pll->con_reg); 577 pll_con5 = readl_relaxed(pll->con_reg + 8); 578 579 /* Change PLL PMSK values */ 580 pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) | 581 (PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) | 582 (PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT)); 583 pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) | 584 (rate->pdiv << PLL0831X_PDIV_SHIFT) | 585 (rate->sdiv << PLL0831X_SDIV_SHIFT); 586 pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT); 587 /* 588 * kdiv is 16-bit 2's complement (s16), but stored as unsigned int. 589 * Cast it to u16 to avoid leading 0xffff's in case of negative value. 590 */ 591 pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT); 592 593 /* Set PLL lock time */ 594 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg); 595 596 /* Write PMSK values */ 597 writel_relaxed(pll_con3, pll->con_reg); 598 writel_relaxed(pll_con5, pll->con_reg + 8); 599 600 /* Wait for PLL lock if the PLL is enabled */ 601 if (pll_con3 & BIT(pll->enable_offs)) 602 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 603 604 return 0; 605 } 606 607 static const struct clk_ops samsung_pll0831x_clk_ops = { 608 .recalc_rate = samsung_pll0831x_recalc_rate, 609 .set_rate = samsung_pll0831x_set_rate, 610 .round_rate = samsung_pll_round_rate, 611 .enable = samsung_pll3xxx_enable, 612 .disable = samsung_pll3xxx_disable, 613 }; 614 615 static const struct clk_ops samsung_pll0831x_clk_min_ops = { 616 .recalc_rate = samsung_pll0831x_recalc_rate, 617 }; 618 619 /* 620 * PLL45xx Clock Type 621 */ 622 #define PLL4502_LOCK_FACTOR 400 623 #define PLL4508_LOCK_FACTOR 240 624 625 #define PLL45XX_MDIV_MASK (0x3FF) 626 #define PLL45XX_PDIV_MASK (0x3F) 627 #define PLL45XX_SDIV_MASK (0x7) 628 #define PLL45XX_AFC_MASK (0x1F) 629 #define PLL45XX_MDIV_SHIFT (16) 630 #define PLL45XX_PDIV_SHIFT (8) 631 #define PLL45XX_SDIV_SHIFT (0) 632 #define PLL45XX_AFC_SHIFT (0) 633 634 #define PLL45XX_ENABLE BIT(31) 635 #define PLL45XX_LOCKED BIT(29) 636 637 static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, 638 unsigned long parent_rate) 639 { 640 struct samsung_clk_pll *pll = to_clk_pll(hw); 641 u32 mdiv, pdiv, sdiv, pll_con; 642 u64 fvco = parent_rate; 643 644 pll_con = readl_relaxed(pll->con_reg); 645 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; 646 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; 647 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; 648 649 if (pll->type == pll_4508) 650 sdiv = sdiv - 1; 651 652 fvco *= mdiv; 653 do_div(fvco, (pdiv << sdiv)); 654 655 return (unsigned long)fvco; 656 } 657 658 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1, 659 const struct samsung_pll_rate_table *rate) 660 { 661 u32 old_mdiv, old_pdiv, old_afc; 662 663 old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; 664 old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; 665 old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK; 666 667 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv 668 || old_afc != rate->afc); 669 } 670 671 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, 672 unsigned long prate) 673 { 674 struct samsung_clk_pll *pll = to_clk_pll(hw); 675 const struct samsung_pll_rate_table *rate; 676 u32 con0, con1; 677 678 /* Get required rate settings from table */ 679 rate = samsung_get_pll_settings(pll, drate); 680 if (!rate) { 681 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 682 drate, clk_hw_get_name(hw)); 683 return -EINVAL; 684 } 685 686 con0 = readl_relaxed(pll->con_reg); 687 con1 = readl_relaxed(pll->con_reg + 0x4); 688 689 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { 690 /* If only s change, change just s value only*/ 691 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); 692 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; 693 writel_relaxed(con0, pll->con_reg); 694 695 return 0; 696 } 697 698 /* Set PLL PMS values. */ 699 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | 700 (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) | 701 (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT)); 702 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | 703 (rate->pdiv << PLL45XX_PDIV_SHIFT) | 704 (rate->sdiv << PLL45XX_SDIV_SHIFT); 705 706 /* Set PLL AFC value. */ 707 con1 = readl_relaxed(pll->con_reg + 0x4); 708 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); 709 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); 710 711 /* Set PLL lock time. */ 712 switch (pll->type) { 713 case pll_4502: 714 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); 715 break; 716 case pll_4508: 717 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); 718 break; 719 default: 720 break; 721 } 722 723 /* Set new configuration. */ 724 writel_relaxed(con1, pll->con_reg + 0x4); 725 writel_relaxed(con0, pll->con_reg); 726 727 /* Wait for PLL lock */ 728 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); 729 } 730 731 static const struct clk_ops samsung_pll45xx_clk_ops = { 732 .recalc_rate = samsung_pll45xx_recalc_rate, 733 .round_rate = samsung_pll_round_rate, 734 .set_rate = samsung_pll45xx_set_rate, 735 }; 736 737 static const struct clk_ops samsung_pll45xx_clk_min_ops = { 738 .recalc_rate = samsung_pll45xx_recalc_rate, 739 }; 740 741 /* 742 * PLL46xx Clock Type 743 */ 744 #define PLL46XX_LOCK_FACTOR 3000 745 746 #define PLL46XX_VSEL_MASK (1) 747 #define PLL46XX_MDIV_MASK (0x1FF) 748 #define PLL1460X_MDIV_MASK (0x3FF) 749 750 #define PLL46XX_PDIV_MASK (0x3F) 751 #define PLL46XX_SDIV_MASK (0x7) 752 #define PLL46XX_VSEL_SHIFT (27) 753 #define PLL46XX_MDIV_SHIFT (16) 754 #define PLL46XX_PDIV_SHIFT (8) 755 #define PLL46XX_SDIV_SHIFT (0) 756 757 #define PLL46XX_KDIV_MASK (0xFFFF) 758 #define PLL4650C_KDIV_MASK (0xFFF) 759 #define PLL46XX_KDIV_SHIFT (0) 760 #define PLL46XX_MFR_MASK (0x3F) 761 #define PLL46XX_MRR_MASK (0x1F) 762 #define PLL46XX_KDIV_SHIFT (0) 763 #define PLL46XX_MFR_SHIFT (16) 764 #define PLL46XX_MRR_SHIFT (24) 765 766 #define PLL46XX_ENABLE BIT(31) 767 #define PLL46XX_LOCKED BIT(29) 768 #define PLL46XX_VSEL BIT(27) 769 770 static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, 771 unsigned long parent_rate) 772 { 773 struct samsung_clk_pll *pll = to_clk_pll(hw); 774 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; 775 u64 fvco = parent_rate; 776 777 pll_con0 = readl_relaxed(pll->con_reg); 778 pll_con1 = readl_relaxed(pll->con_reg + 4); 779 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? 780 PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); 781 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; 782 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; 783 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : 784 pll_con1 & PLL46XX_KDIV_MASK; 785 786 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; 787 788 fvco *= (mdiv << shift) + kdiv; 789 do_div(fvco, (pdiv << sdiv)); 790 fvco >>= shift; 791 792 return (unsigned long)fvco; 793 } 794 795 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, 796 const struct samsung_pll_rate_table *rate) 797 { 798 u32 old_mdiv, old_pdiv, old_kdiv; 799 800 old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; 801 old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; 802 old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK; 803 804 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv 805 || old_kdiv != rate->kdiv); 806 } 807 808 static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, 809 unsigned long prate) 810 { 811 struct samsung_clk_pll *pll = to_clk_pll(hw); 812 const struct samsung_pll_rate_table *rate; 813 u32 con0, con1, lock; 814 815 /* Get required rate settings from table */ 816 rate = samsung_get_pll_settings(pll, drate); 817 if (!rate) { 818 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 819 drate, clk_hw_get_name(hw)); 820 return -EINVAL; 821 } 822 823 con0 = readl_relaxed(pll->con_reg); 824 con1 = readl_relaxed(pll->con_reg + 0x4); 825 826 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { 827 /* If only s change, change just s value only*/ 828 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); 829 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; 830 writel_relaxed(con0, pll->con_reg); 831 832 return 0; 833 } 834 835 /* Set PLL lock time. */ 836 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; 837 if (lock > 0xffff) 838 /* Maximum lock time bitfield is 16-bit. */ 839 lock = 0xffff; 840 841 /* Set PLL PMS and VSEL values. */ 842 if (pll->type == pll_1460x) { 843 con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | 844 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | 845 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); 846 } else { 847 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | 848 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | 849 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | 850 (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); 851 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; 852 } 853 854 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | 855 (rate->pdiv << PLL46XX_PDIV_SHIFT) | 856 (rate->sdiv << PLL46XX_SDIV_SHIFT); 857 858 /* Set PLL K, MFR and MRR values. */ 859 con1 = readl_relaxed(pll->con_reg + 0x4); 860 con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | 861 (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | 862 (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); 863 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | 864 (rate->mfr << PLL46XX_MFR_SHIFT) | 865 (rate->mrr << PLL46XX_MRR_SHIFT); 866 867 /* Write configuration to PLL */ 868 writel_relaxed(lock, pll->lock_reg); 869 writel_relaxed(con0, pll->con_reg); 870 writel_relaxed(con1, pll->con_reg + 0x4); 871 872 /* Wait for PLL lock */ 873 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); 874 } 875 876 static const struct clk_ops samsung_pll46xx_clk_ops = { 877 .recalc_rate = samsung_pll46xx_recalc_rate, 878 .round_rate = samsung_pll_round_rate, 879 .set_rate = samsung_pll46xx_set_rate, 880 }; 881 882 static const struct clk_ops samsung_pll46xx_clk_min_ops = { 883 .recalc_rate = samsung_pll46xx_recalc_rate, 884 }; 885 886 /* 887 * PLL6552 Clock Type 888 */ 889 890 #define PLL6552_MDIV_MASK 0x3ff 891 #define PLL6552_PDIV_MASK 0x3f 892 #define PLL6552_SDIV_MASK 0x7 893 #define PLL6552_MDIV_SHIFT 16 894 #define PLL6552_MDIV_SHIFT_2416 14 895 #define PLL6552_PDIV_SHIFT 8 896 #define PLL6552_PDIV_SHIFT_2416 5 897 #define PLL6552_SDIV_SHIFT 0 898 899 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, 900 unsigned long parent_rate) 901 { 902 struct samsung_clk_pll *pll = to_clk_pll(hw); 903 u32 mdiv, pdiv, sdiv, pll_con; 904 u64 fvco = parent_rate; 905 906 pll_con = readl_relaxed(pll->con_reg); 907 if (pll->type == pll_6552_s3c2416) { 908 mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK; 909 pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK; 910 } else { 911 mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK; 912 pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK; 913 } 914 sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK; 915 916 fvco *= mdiv; 917 do_div(fvco, (pdiv << sdiv)); 918 919 return (unsigned long)fvco; 920 } 921 922 static const struct clk_ops samsung_pll6552_clk_ops = { 923 .recalc_rate = samsung_pll6552_recalc_rate, 924 }; 925 926 /* 927 * PLL6553 Clock Type 928 */ 929 930 #define PLL6553_MDIV_MASK 0xff 931 #define PLL6553_PDIV_MASK 0x3f 932 #define PLL6553_SDIV_MASK 0x7 933 #define PLL6553_KDIV_MASK 0xffff 934 #define PLL6553_MDIV_SHIFT 16 935 #define PLL6553_PDIV_SHIFT 8 936 #define PLL6553_SDIV_SHIFT 0 937 #define PLL6553_KDIV_SHIFT 0 938 939 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, 940 unsigned long parent_rate) 941 { 942 struct samsung_clk_pll *pll = to_clk_pll(hw); 943 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; 944 u64 fvco = parent_rate; 945 946 pll_con0 = readl_relaxed(pll->con_reg); 947 pll_con1 = readl_relaxed(pll->con_reg + 0x4); 948 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; 949 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; 950 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; 951 kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK; 952 953 fvco *= (mdiv << 16) + kdiv; 954 do_div(fvco, (pdiv << sdiv)); 955 fvco >>= 16; 956 957 return (unsigned long)fvco; 958 } 959 960 static const struct clk_ops samsung_pll6553_clk_ops = { 961 .recalc_rate = samsung_pll6553_recalc_rate, 962 }; 963 964 /* 965 * PLL2550x Clock Type 966 */ 967 968 #define PLL2550X_R_MASK (0x1) 969 #define PLL2550X_P_MASK (0x3F) 970 #define PLL2550X_M_MASK (0x3FF) 971 #define PLL2550X_S_MASK (0x7) 972 #define PLL2550X_R_SHIFT (20) 973 #define PLL2550X_P_SHIFT (14) 974 #define PLL2550X_M_SHIFT (4) 975 #define PLL2550X_S_SHIFT (0) 976 977 static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, 978 unsigned long parent_rate) 979 { 980 struct samsung_clk_pll *pll = to_clk_pll(hw); 981 u32 r, p, m, s, pll_stat; 982 u64 fvco = parent_rate; 983 984 pll_stat = readl_relaxed(pll->con_reg); 985 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK; 986 if (!r) 987 return 0; 988 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK; 989 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK; 990 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK; 991 992 fvco *= m; 993 do_div(fvco, (p << s)); 994 995 return (unsigned long)fvco; 996 } 997 998 static const struct clk_ops samsung_pll2550x_clk_ops = { 999 .recalc_rate = samsung_pll2550x_recalc_rate, 1000 }; 1001 1002 /* 1003 * PLL2550xx Clock Type 1004 */ 1005 1006 /* Maximum lock time can be 270 * PDIV cycles */ 1007 #define PLL2550XX_LOCK_FACTOR 270 1008 1009 #define PLL2550XX_M_MASK 0x3FF 1010 #define PLL2550XX_P_MASK 0x3F 1011 #define PLL2550XX_S_MASK 0x7 1012 #define PLL2550XX_LOCK_STAT_MASK 0x1 1013 #define PLL2550XX_M_SHIFT 9 1014 #define PLL2550XX_P_SHIFT 3 1015 #define PLL2550XX_S_SHIFT 0 1016 #define PLL2550XX_LOCK_STAT_SHIFT 21 1017 1018 static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, 1019 unsigned long parent_rate) 1020 { 1021 struct samsung_clk_pll *pll = to_clk_pll(hw); 1022 u32 mdiv, pdiv, sdiv, pll_con; 1023 u64 fvco = parent_rate; 1024 1025 pll_con = readl_relaxed(pll->con_reg); 1026 mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; 1027 pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; 1028 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; 1029 1030 fvco *= mdiv; 1031 do_div(fvco, (pdiv << sdiv)); 1032 1033 return (unsigned long)fvco; 1034 } 1035 1036 static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) 1037 { 1038 u32 old_mdiv, old_pdiv; 1039 1040 old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; 1041 old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; 1042 1043 return mdiv != old_mdiv || pdiv != old_pdiv; 1044 } 1045 1046 static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, 1047 unsigned long prate) 1048 { 1049 struct samsung_clk_pll *pll = to_clk_pll(hw); 1050 const struct samsung_pll_rate_table *rate; 1051 u32 tmp; 1052 1053 /* Get required rate settings from table */ 1054 rate = samsung_get_pll_settings(pll, drate); 1055 if (!rate) { 1056 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1057 drate, clk_hw_get_name(hw)); 1058 return -EINVAL; 1059 } 1060 1061 tmp = readl_relaxed(pll->con_reg); 1062 1063 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { 1064 /* If only s change, change just s value only*/ 1065 tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); 1066 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; 1067 writel_relaxed(tmp, pll->con_reg); 1068 1069 return 0; 1070 } 1071 1072 /* Set PLL lock time. */ 1073 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); 1074 1075 /* Change PLL PMS values */ 1076 tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | 1077 (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) | 1078 (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT)); 1079 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | 1080 (rate->pdiv << PLL2550XX_P_SHIFT) | 1081 (rate->sdiv << PLL2550XX_S_SHIFT); 1082 writel_relaxed(tmp, pll->con_reg); 1083 1084 /* Wait for PLL lock */ 1085 return samsung_pll_lock_wait(pll, 1086 PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT); 1087 } 1088 1089 static const struct clk_ops samsung_pll2550xx_clk_ops = { 1090 .recalc_rate = samsung_pll2550xx_recalc_rate, 1091 .round_rate = samsung_pll_round_rate, 1092 .set_rate = samsung_pll2550xx_set_rate, 1093 }; 1094 1095 static const struct clk_ops samsung_pll2550xx_clk_min_ops = { 1096 .recalc_rate = samsung_pll2550xx_recalc_rate, 1097 }; 1098 1099 /* 1100 * PLL2650x Clock Type 1101 */ 1102 1103 /* Maximum lock time can be 3000 * PDIV cycles */ 1104 #define PLL2650X_LOCK_FACTOR 3000 1105 1106 #define PLL2650X_M_MASK 0x1ff 1107 #define PLL2650X_P_MASK 0x3f 1108 #define PLL2650X_S_MASK 0x7 1109 #define PLL2650X_K_MASK 0xffff 1110 #define PLL2650X_LOCK_STAT_MASK 0x1 1111 #define PLL2650X_M_SHIFT 16 1112 #define PLL2650X_P_SHIFT 8 1113 #define PLL2650X_S_SHIFT 0 1114 #define PLL2650X_K_SHIFT 0 1115 #define PLL2650X_LOCK_STAT_SHIFT 29 1116 #define PLL2650X_PLL_ENABLE_SHIFT 31 1117 1118 static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw, 1119 unsigned long parent_rate) 1120 { 1121 struct samsung_clk_pll *pll = to_clk_pll(hw); 1122 u64 fout = parent_rate; 1123 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; 1124 s16 kdiv; 1125 1126 pll_con0 = readl_relaxed(pll->con_reg); 1127 mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK; 1128 pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK; 1129 sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK; 1130 1131 pll_con1 = readl_relaxed(pll->con_reg + 4); 1132 kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK); 1133 1134 fout *= (mdiv << 16) + kdiv; 1135 do_div(fout, (pdiv << sdiv)); 1136 fout >>= 16; 1137 1138 return (unsigned long)fout; 1139 } 1140 1141 static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate, 1142 unsigned long prate) 1143 { 1144 struct samsung_clk_pll *pll = to_clk_pll(hw); 1145 const struct samsung_pll_rate_table *rate; 1146 u32 con0, con1; 1147 1148 /* Get required rate settings from table */ 1149 rate = samsung_get_pll_settings(pll, drate); 1150 if (!rate) { 1151 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1152 drate, clk_hw_get_name(hw)); 1153 return -EINVAL; 1154 } 1155 1156 con0 = readl_relaxed(pll->con_reg); 1157 con1 = readl_relaxed(pll->con_reg + 4); 1158 1159 /* Set PLL lock time. */ 1160 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); 1161 1162 /* Change PLL PMS values */ 1163 con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) | 1164 (PLL2650X_P_MASK << PLL2650X_P_SHIFT) | 1165 (PLL2650X_S_MASK << PLL2650X_S_SHIFT)); 1166 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | 1167 (rate->pdiv << PLL2650X_P_SHIFT) | 1168 (rate->sdiv << PLL2650X_S_SHIFT); 1169 con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT); 1170 writel_relaxed(con0, pll->con_reg); 1171 1172 con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT); 1173 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); 1174 writel_relaxed(con1, pll->con_reg + 4); 1175 1176 /* Wait for PLL lock */ 1177 return samsung_pll_lock_wait(pll, 1178 PLL2650X_LOCK_STAT_MASK << PLL2650X_LOCK_STAT_SHIFT); 1179 } 1180 1181 static const struct clk_ops samsung_pll2650x_clk_ops = { 1182 .recalc_rate = samsung_pll2650x_recalc_rate, 1183 .round_rate = samsung_pll_round_rate, 1184 .set_rate = samsung_pll2650x_set_rate, 1185 }; 1186 1187 static const struct clk_ops samsung_pll2650x_clk_min_ops = { 1188 .recalc_rate = samsung_pll2650x_recalc_rate, 1189 }; 1190 1191 /* 1192 * PLL2650XX Clock Type 1193 */ 1194 1195 /* Maximum lock time can be 3000 * PDIV cycles */ 1196 #define PLL2650XX_LOCK_FACTOR 3000 1197 1198 #define PLL2650XX_MDIV_SHIFT 9 1199 #define PLL2650XX_PDIV_SHIFT 3 1200 #define PLL2650XX_SDIV_SHIFT 0 1201 #define PLL2650XX_KDIV_SHIFT 0 1202 #define PLL2650XX_MDIV_MASK 0x1ff 1203 #define PLL2650XX_PDIV_MASK 0x3f 1204 #define PLL2650XX_SDIV_MASK 0x7 1205 #define PLL2650XX_KDIV_MASK 0xffff 1206 #define PLL2650XX_PLL_ENABLE_SHIFT 23 1207 #define PLL2650XX_PLL_LOCKTIME_SHIFT 21 1208 #define PLL2650XX_PLL_FOUTMASK_SHIFT 31 1209 1210 static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, 1211 unsigned long parent_rate) 1212 { 1213 struct samsung_clk_pll *pll = to_clk_pll(hw); 1214 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; 1215 s16 kdiv; 1216 u64 fvco = parent_rate; 1217 1218 pll_con0 = readl_relaxed(pll->con_reg); 1219 pll_con2 = readl_relaxed(pll->con_reg + 8); 1220 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; 1221 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; 1222 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; 1223 kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK); 1224 1225 fvco *= (mdiv << 16) + kdiv; 1226 do_div(fvco, (pdiv << sdiv)); 1227 fvco >>= 16; 1228 1229 return (unsigned long)fvco; 1230 } 1231 1232 static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, 1233 unsigned long parent_rate) 1234 { 1235 struct samsung_clk_pll *pll = to_clk_pll(hw); 1236 u32 pll_con0, pll_con2; 1237 const struct samsung_pll_rate_table *rate; 1238 1239 rate = samsung_get_pll_settings(pll, drate); 1240 if (!rate) { 1241 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1242 drate, clk_hw_get_name(hw)); 1243 return -EINVAL; 1244 } 1245 1246 pll_con0 = readl_relaxed(pll->con_reg); 1247 pll_con2 = readl_relaxed(pll->con_reg + 8); 1248 1249 /* Change PLL PMS values */ 1250 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | 1251 PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT | 1252 PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); 1253 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; 1254 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; 1255 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; 1256 pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; 1257 pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; 1258 1259 pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT); 1260 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) 1261 << PLL2650XX_KDIV_SHIFT; 1262 1263 /* Set PLL lock time. */ 1264 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); 1265 1266 writel_relaxed(pll_con0, pll->con_reg); 1267 writel_relaxed(pll_con2, pll->con_reg + 8); 1268 1269 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); 1270 } 1271 1272 static const struct clk_ops samsung_pll2650xx_clk_ops = { 1273 .recalc_rate = samsung_pll2650xx_recalc_rate, 1274 .set_rate = samsung_pll2650xx_set_rate, 1275 .round_rate = samsung_pll_round_rate, 1276 }; 1277 1278 static const struct clk_ops samsung_pll2650xx_clk_min_ops = { 1279 .recalc_rate = samsung_pll2650xx_recalc_rate, 1280 }; 1281 1282 /* 1283 * PLL531X Clock Type 1284 */ 1285 /* Maximum lock time can be 500 * PDIV cycles */ 1286 #define PLL531X_LOCK_FACTOR (500) 1287 #define PLL531X_MDIV_MASK (0x3FF) 1288 #define PLL531X_PDIV_MASK (0x3F) 1289 #define PLL531X_SDIV_MASK (0x7) 1290 #define PLL531X_FDIV_MASK (0xFFFFFFFF) 1291 #define PLL531X_MDIV_SHIFT (16) 1292 #define PLL531X_PDIV_SHIFT (8) 1293 #define PLL531X_SDIV_SHIFT (0) 1294 1295 static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw, 1296 unsigned long parent_rate) 1297 { 1298 struct samsung_clk_pll *pll = to_clk_pll(hw); 1299 u32 pdiv, sdiv, fdiv, pll_con0, pll_con8; 1300 u64 mdiv, fout = parent_rate; 1301 1302 pll_con0 = readl_relaxed(pll->con_reg); 1303 pll_con8 = readl_relaxed(pll->con_reg + 20); 1304 mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK; 1305 pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK; 1306 sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK; 1307 fdiv = (pll_con8 & PLL531X_FDIV_MASK); 1308 1309 if (fdiv >> 31) 1310 mdiv--; 1311 1312 fout *= (mdiv << 24) + (fdiv >> 8); 1313 do_div(fout, (pdiv << sdiv)); 1314 fout >>= 24; 1315 1316 return (unsigned long)fout; 1317 } 1318 1319 static const struct clk_ops samsung_pll531x_clk_ops = { 1320 .recalc_rate = samsung_pll531x_recalc_rate, 1321 }; 1322 1323 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1324 const struct samsung_pll_clock *pll_clk) 1325 { 1326 struct samsung_clk_pll *pll; 1327 struct clk_init_data init; 1328 int ret, len; 1329 1330 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1331 if (!pll) { 1332 pr_err("%s: could not allocate pll clk %s\n", 1333 __func__, pll_clk->name); 1334 return; 1335 } 1336 1337 init.name = pll_clk->name; 1338 init.flags = pll_clk->flags; 1339 init.parent_names = &pll_clk->parent_name; 1340 init.num_parents = 1; 1341 1342 if (pll_clk->rate_table) { 1343 /* find count of rates in rate_table */ 1344 for (len = 0; pll_clk->rate_table[len].rate != 0; ) 1345 len++; 1346 1347 pll->rate_count = len; 1348 pll->rate_table = kmemdup_array(pll_clk->rate_table, 1349 pll->rate_count, 1350 sizeof(*pll->rate_table), 1351 GFP_KERNEL); 1352 WARN(!pll->rate_table, 1353 "%s: could not allocate rate table for %s\n", 1354 __func__, pll_clk->name); 1355 } 1356 1357 switch (pll_clk->type) { 1358 case pll_2126: 1359 init.ops = &samsung_pll2126_clk_ops; 1360 break; 1361 case pll_3000: 1362 init.ops = &samsung_pll3000_clk_ops; 1363 break; 1364 /* clk_ops for 35xx and 2550 are similar */ 1365 case pll_35xx: 1366 case pll_2550: 1367 case pll_1450x: 1368 case pll_1451x: 1369 case pll_1452x: 1370 case pll_142xx: 1371 pll->enable_offs = PLL35XX_ENABLE_SHIFT; 1372 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; 1373 if (!pll->rate_table) 1374 init.ops = &samsung_pll35xx_clk_min_ops; 1375 else 1376 init.ops = &samsung_pll35xx_clk_ops; 1377 break; 1378 case pll_1417x: 1379 case pll_1418x: 1380 case pll_1051x: 1381 case pll_1052x: 1382 case pll_0818x: 1383 case pll_0822x: 1384 case pll_0516x: 1385 case pll_0517x: 1386 case pll_0518x: 1387 case pll_0717x: 1388 case pll_0718x: 1389 case pll_0732x: 1390 pll->enable_offs = PLL0822X_ENABLE_SHIFT; 1391 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; 1392 if (!pll->rate_table) 1393 init.ops = &samsung_pll0822x_clk_min_ops; 1394 else 1395 init.ops = &samsung_pll0822x_clk_ops; 1396 break; 1397 case pll_4500: 1398 init.ops = &samsung_pll45xx_clk_min_ops; 1399 break; 1400 case pll_4502: 1401 case pll_4508: 1402 if (!pll->rate_table) 1403 init.ops = &samsung_pll45xx_clk_min_ops; 1404 else 1405 init.ops = &samsung_pll45xx_clk_ops; 1406 break; 1407 /* clk_ops for 36xx and 2650 are similar */ 1408 case pll_36xx: 1409 case pll_2650: 1410 pll->enable_offs = PLL36XX_ENABLE_SHIFT; 1411 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; 1412 if (!pll->rate_table) 1413 init.ops = &samsung_pll36xx_clk_min_ops; 1414 else 1415 init.ops = &samsung_pll36xx_clk_ops; 1416 break; 1417 case pll_0831x: 1418 pll->enable_offs = PLL0831X_ENABLE_SHIFT; 1419 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; 1420 if (!pll->rate_table) 1421 init.ops = &samsung_pll0831x_clk_min_ops; 1422 else 1423 init.ops = &samsung_pll0831x_clk_ops; 1424 break; 1425 case pll_6552: 1426 case pll_6552_s3c2416: 1427 init.ops = &samsung_pll6552_clk_ops; 1428 break; 1429 case pll_6553: 1430 init.ops = &samsung_pll6553_clk_ops; 1431 break; 1432 case pll_4600: 1433 case pll_4650: 1434 case pll_4650c: 1435 case pll_1460x: 1436 if (!pll->rate_table) 1437 init.ops = &samsung_pll46xx_clk_min_ops; 1438 else 1439 init.ops = &samsung_pll46xx_clk_ops; 1440 break; 1441 case pll_2550x: 1442 init.ops = &samsung_pll2550x_clk_ops; 1443 break; 1444 case pll_2550xx: 1445 if (!pll->rate_table) 1446 init.ops = &samsung_pll2550xx_clk_min_ops; 1447 else 1448 init.ops = &samsung_pll2550xx_clk_ops; 1449 break; 1450 case pll_2650x: 1451 if (!pll->rate_table) 1452 init.ops = &samsung_pll2650x_clk_min_ops; 1453 else 1454 init.ops = &samsung_pll2650x_clk_ops; 1455 break; 1456 case pll_2650xx: 1457 if (!pll->rate_table) 1458 init.ops = &samsung_pll2650xx_clk_min_ops; 1459 else 1460 init.ops = &samsung_pll2650xx_clk_ops; 1461 break; 1462 case pll_531x: 1463 init.ops = &samsung_pll531x_clk_ops; 1464 break; 1465 default: 1466 pr_warn("%s: Unknown pll type for pll clk %s\n", 1467 __func__, pll_clk->name); 1468 } 1469 1470 pll->hw.init = &init; 1471 pll->type = pll_clk->type; 1472 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset; 1473 pll->con_reg = ctx->reg_base + pll_clk->con_offset; 1474 1475 ret = clk_hw_register(ctx->dev, &pll->hw); 1476 if (ret) { 1477 pr_err("%s: failed to register pll clock %s : %d\n", 1478 __func__, pll_clk->name, ret); 1479 kfree(pll->rate_table); 1480 kfree(pll); 1481 return; 1482 } 1483 1484 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); 1485 } 1486 1487 void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1488 const struct samsung_pll_clock *pll_list, 1489 unsigned int nr_pll) 1490 { 1491 int cnt; 1492 1493 for (cnt = 0; cnt < nr_pll; cnt++) 1494 _samsung_clk_register_pll(ctx, &pll_list[cnt]); 1495 } 1496