1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2013 Linaro Ltd. 5 * 6 * This file contains the utility functions to register the pll clocks. 7 */ 8 9 #include <linux/errno.h> 10 #include <linux/hrtimer.h> 11 #include <linux/iopoll.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/timekeeping.h> 15 #include <linux/clk-provider.h> 16 #include <linux/io.h> 17 #include "clk.h" 18 #include "clk-pll.h" 19 20 #define PLL_TIMEOUT_US 20000U 21 #define PLL_TIMEOUT_LOOPS 1000000U 22 23 struct samsung_clk_pll { 24 struct clk_hw hw; 25 void __iomem *lock_reg; 26 void __iomem *con_reg; 27 /* PLL enable control bit offset in @con_reg register */ 28 unsigned short enable_offs; 29 /* PLL lock status bit offset in @con_reg register */ 30 unsigned short lock_offs; 31 enum samsung_pll_type type; 32 unsigned int rate_count; 33 const struct samsung_pll_rate_table *rate_table; 34 }; 35 36 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) 37 38 static const struct samsung_pll_rate_table *samsung_get_pll_settings( 39 struct samsung_clk_pll *pll, unsigned long rate) 40 { 41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; 42 int i; 43 44 for (i = 0; i < pll->rate_count; i++) { 45 if (rate == rate_table[i].rate) 46 return &rate_table[i]; 47 } 48 49 return NULL; 50 } 51 52 static long samsung_pll_round_rate(struct clk_hw *hw, 53 unsigned long drate, unsigned long *prate) 54 { 55 struct samsung_clk_pll *pll = to_clk_pll(hw); 56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; 57 int i; 58 59 /* Assumming rate_table is in descending order */ 60 for (i = 0; i < pll->rate_count; i++) { 61 if (drate >= rate_table[i].rate) 62 return rate_table[i].rate; 63 } 64 65 /* return minimum supported value */ 66 return rate_table[i - 1].rate; 67 } 68 69 static bool pll_early_timeout = true; 70 71 static int __init samsung_pll_disable_early_timeout(void) 72 { 73 pll_early_timeout = false; 74 return 0; 75 } 76 arch_initcall(samsung_pll_disable_early_timeout); 77 78 /* Wait until the PLL is locked */ 79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, 80 unsigned int reg_mask) 81 { 82 int i, ret; 83 u32 val; 84 85 /* 86 * This function might be called when the timekeeping API can't be used 87 * to detect timeouts. One situation is when the clocksource is not yet 88 * initialized, another when the timekeeping is suspended. udelay() also 89 * cannot be used when the clocksource is not running on arm64, since 90 * the current timer is used as cycle counter. So a simple busy loop 91 * is used here in that special cases. The limit of iterations has been 92 * derived from experimental measurements of various PLLs on multiple 93 * Exynos SoC variants. Single register read time was usually in range 94 * 0.4...1.5 us, never less than 0.4 us. 95 */ 96 if (pll_early_timeout || timekeeping_suspended) { 97 i = PLL_TIMEOUT_LOOPS; 98 while (i-- > 0) { 99 if (readl_relaxed(pll->con_reg) & reg_mask) 100 return 0; 101 102 cpu_relax(); 103 } 104 ret = -ETIMEDOUT; 105 } else { 106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, 107 val & reg_mask, 0, PLL_TIMEOUT_US); 108 } 109 110 if (ret < 0) 111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); 112 113 return ret; 114 } 115 116 static int samsung_pll3xxx_enable(struct clk_hw *hw) 117 { 118 struct samsung_clk_pll *pll = to_clk_pll(hw); 119 u32 tmp; 120 121 tmp = readl_relaxed(pll->con_reg); 122 tmp |= BIT(pll->enable_offs); 123 writel_relaxed(tmp, pll->con_reg); 124 125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 126 } 127 128 static void samsung_pll3xxx_disable(struct clk_hw *hw) 129 { 130 struct samsung_clk_pll *pll = to_clk_pll(hw); 131 u32 tmp; 132 133 tmp = readl_relaxed(pll->con_reg); 134 tmp &= ~BIT(pll->enable_offs); 135 writel_relaxed(tmp, pll->con_reg); 136 } 137 138 /* 139 * PLL2126 Clock Type 140 */ 141 142 #define PLL2126_MDIV_MASK (0xff) 143 #define PLL2126_PDIV_MASK (0x3f) 144 #define PLL2126_SDIV_MASK (0x3) 145 #define PLL2126_MDIV_SHIFT (16) 146 #define PLL2126_PDIV_SHIFT (8) 147 #define PLL2126_SDIV_SHIFT (0) 148 149 static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, 150 unsigned long parent_rate) 151 { 152 struct samsung_clk_pll *pll = to_clk_pll(hw); 153 u32 pll_con, mdiv, pdiv, sdiv; 154 u64 fvco = parent_rate; 155 156 pll_con = readl_relaxed(pll->con_reg); 157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; 158 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; 159 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; 160 161 fvco *= (mdiv + 8); 162 do_div(fvco, (pdiv + 2) << sdiv); 163 164 return (unsigned long)fvco; 165 } 166 167 static const struct clk_ops samsung_pll2126_clk_ops = { 168 .recalc_rate = samsung_pll2126_recalc_rate, 169 }; 170 171 /* 172 * PLL3000 Clock Type 173 */ 174 175 #define PLL3000_MDIV_MASK (0xff) 176 #define PLL3000_PDIV_MASK (0x3) 177 #define PLL3000_SDIV_MASK (0x3) 178 #define PLL3000_MDIV_SHIFT (16) 179 #define PLL3000_PDIV_SHIFT (8) 180 #define PLL3000_SDIV_SHIFT (0) 181 182 static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, 183 unsigned long parent_rate) 184 { 185 struct samsung_clk_pll *pll = to_clk_pll(hw); 186 u32 pll_con, mdiv, pdiv, sdiv; 187 u64 fvco = parent_rate; 188 189 pll_con = readl_relaxed(pll->con_reg); 190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; 191 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; 192 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; 193 194 fvco *= (2 * (mdiv + 8)); 195 do_div(fvco, pdiv << sdiv); 196 197 return (unsigned long)fvco; 198 } 199 200 static const struct clk_ops samsung_pll3000_clk_ops = { 201 .recalc_rate = samsung_pll3000_recalc_rate, 202 }; 203 204 /* 205 * PLL35xx Clock Type 206 */ 207 /* Maximum lock time can be 270 * PDIV cycles */ 208 #define PLL35XX_LOCK_FACTOR (270) 209 210 #define PLL35XX_MDIV_MASK (0x3FF) 211 #define PLL35XX_PDIV_MASK (0x3F) 212 #define PLL35XX_SDIV_MASK (0x7) 213 #define PLL35XX_MDIV_SHIFT (16) 214 #define PLL35XX_PDIV_SHIFT (8) 215 #define PLL35XX_SDIV_SHIFT (0) 216 #define PLL35XX_LOCK_STAT_SHIFT (29) 217 #define PLL35XX_ENABLE_SHIFT (31) 218 219 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, 220 unsigned long parent_rate) 221 { 222 struct samsung_clk_pll *pll = to_clk_pll(hw); 223 u32 mdiv, pdiv, sdiv, pll_con; 224 u64 fvco = parent_rate; 225 226 pll_con = readl_relaxed(pll->con_reg); 227 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; 228 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; 229 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; 230 231 fvco *= mdiv; 232 do_div(fvco, (pdiv << sdiv)); 233 234 return (unsigned long)fvco; 235 } 236 237 static inline bool samsung_pll35xx_mp_change( 238 const struct samsung_pll_rate_table *rate, u32 pll_con) 239 { 240 u32 old_mdiv, old_pdiv; 241 242 old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; 243 old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; 244 245 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); 246 } 247 248 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, 249 unsigned long prate) 250 { 251 struct samsung_clk_pll *pll = to_clk_pll(hw); 252 const struct samsung_pll_rate_table *rate; 253 u32 tmp; 254 255 /* Get required rate settings from table */ 256 rate = samsung_get_pll_settings(pll, drate); 257 if (!rate) { 258 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 259 drate, clk_hw_get_name(hw)); 260 return -EINVAL; 261 } 262 263 tmp = readl_relaxed(pll->con_reg); 264 265 if (!(samsung_pll35xx_mp_change(rate, tmp))) { 266 /* If only s change, change just s value only*/ 267 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); 268 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; 269 writel_relaxed(tmp, pll->con_reg); 270 271 return 0; 272 } 273 274 /* Set PLL lock time. */ 275 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, 276 pll->lock_reg); 277 278 /* Change PLL PMS values */ 279 tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) | 280 (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) | 281 (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT)); 282 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | 283 (rate->pdiv << PLL35XX_PDIV_SHIFT) | 284 (rate->sdiv << PLL35XX_SDIV_SHIFT); 285 writel_relaxed(tmp, pll->con_reg); 286 287 /* Wait for PLL lock if the PLL is enabled */ 288 if (tmp & BIT(pll->enable_offs)) 289 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 290 291 return 0; 292 } 293 294 static const struct clk_ops samsung_pll35xx_clk_ops = { 295 .recalc_rate = samsung_pll35xx_recalc_rate, 296 .round_rate = samsung_pll_round_rate, 297 .set_rate = samsung_pll35xx_set_rate, 298 .enable = samsung_pll3xxx_enable, 299 .disable = samsung_pll3xxx_disable, 300 }; 301 302 static const struct clk_ops samsung_pll35xx_clk_min_ops = { 303 .recalc_rate = samsung_pll35xx_recalc_rate, 304 }; 305 306 /* 307 * PLL36xx Clock Type 308 */ 309 /* Maximum lock time can be 3000 * PDIV cycles */ 310 #define PLL36XX_LOCK_FACTOR (3000) 311 312 #define PLL36XX_KDIV_MASK (0xFFFF) 313 #define PLL36XX_MDIV_MASK (0x1FF) 314 #define PLL36XX_PDIV_MASK (0x3F) 315 #define PLL36XX_SDIV_MASK (0x7) 316 #define PLL36XX_MDIV_SHIFT (16) 317 #define PLL36XX_PDIV_SHIFT (8) 318 #define PLL36XX_SDIV_SHIFT (0) 319 #define PLL36XX_KDIV_SHIFT (0) 320 #define PLL36XX_LOCK_STAT_SHIFT (29) 321 #define PLL36XX_ENABLE_SHIFT (31) 322 323 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, 324 unsigned long parent_rate) 325 { 326 struct samsung_clk_pll *pll = to_clk_pll(hw); 327 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; 328 s16 kdiv; 329 u64 fvco = parent_rate; 330 331 pll_con0 = readl_relaxed(pll->con_reg); 332 pll_con1 = readl_relaxed(pll->con_reg + 4); 333 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 334 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 335 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; 336 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK); 337 338 fvco *= (mdiv << 16) + kdiv; 339 do_div(fvco, (pdiv << sdiv)); 340 fvco >>= 16; 341 342 return (unsigned long)fvco; 343 } 344 345 static inline bool samsung_pll36xx_mpk_change( 346 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) 347 { 348 u32 old_mdiv, old_pdiv, old_kdiv; 349 350 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 351 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 352 old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK; 353 354 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || 355 rate->kdiv != old_kdiv); 356 } 357 358 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, 359 unsigned long parent_rate) 360 { 361 struct samsung_clk_pll *pll = to_clk_pll(hw); 362 u32 pll_con0, pll_con1; 363 const struct samsung_pll_rate_table *rate; 364 365 rate = samsung_get_pll_settings(pll, drate); 366 if (!rate) { 367 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 368 drate, clk_hw_get_name(hw)); 369 return -EINVAL; 370 } 371 372 pll_con0 = readl_relaxed(pll->con_reg); 373 pll_con1 = readl_relaxed(pll->con_reg + 4); 374 375 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { 376 /* If only s change, change just s value only*/ 377 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); 378 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); 379 writel_relaxed(pll_con0, pll->con_reg); 380 381 return 0; 382 } 383 384 /* Set PLL lock time. */ 385 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); 386 387 /* Change PLL PMS values */ 388 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | 389 (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) | 390 (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT)); 391 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | 392 (rate->pdiv << PLL36XX_PDIV_SHIFT) | 393 (rate->sdiv << PLL36XX_SDIV_SHIFT); 394 writel_relaxed(pll_con0, pll->con_reg); 395 396 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); 397 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; 398 writel_relaxed(pll_con1, pll->con_reg + 4); 399 400 if (pll_con0 & BIT(pll->enable_offs)) 401 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 402 403 return 0; 404 } 405 406 static const struct clk_ops samsung_pll36xx_clk_ops = { 407 .recalc_rate = samsung_pll36xx_recalc_rate, 408 .set_rate = samsung_pll36xx_set_rate, 409 .round_rate = samsung_pll_round_rate, 410 .enable = samsung_pll3xxx_enable, 411 .disable = samsung_pll3xxx_disable, 412 }; 413 414 static const struct clk_ops samsung_pll36xx_clk_min_ops = { 415 .recalc_rate = samsung_pll36xx_recalc_rate, 416 }; 417 418 /* 419 * PLL0822x Clock Type 420 */ 421 /* Maximum lock time can be 150 * PDIV cycles */ 422 #define PLL0822X_LOCK_FACTOR (150) 423 424 #define PLL0822X_MDIV_MASK (0x3FF) 425 #define PLL0822X_PDIV_MASK (0x3F) 426 #define PLL0822X_SDIV_MASK (0x7) 427 #define PLL0822X_MDIV_SHIFT (16) 428 #define PLL0822X_PDIV_SHIFT (8) 429 #define PLL0822X_SDIV_SHIFT (0) 430 #define PLL0822X_LOCK_STAT_SHIFT (29) 431 #define PLL0822X_ENABLE_SHIFT (31) 432 433 static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, 434 unsigned long parent_rate) 435 { 436 struct samsung_clk_pll *pll = to_clk_pll(hw); 437 u32 mdiv, pdiv, sdiv, pll_con3; 438 u64 fvco = parent_rate; 439 440 pll_con3 = readl_relaxed(pll->con_reg); 441 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; 442 pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; 443 sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; 444 445 fvco *= mdiv; 446 if (pll->type == pll_0516x) 447 fvco *= 2; 448 449 do_div(fvco, (pdiv << sdiv)); 450 451 return (unsigned long)fvco; 452 } 453 454 static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, 455 unsigned long prate) 456 { 457 const struct samsung_pll_rate_table *rate; 458 struct samsung_clk_pll *pll = to_clk_pll(hw); 459 u32 pll_con3; 460 461 /* Get required rate settings from table */ 462 rate = samsung_get_pll_settings(pll, drate); 463 if (!rate) { 464 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 465 drate, clk_hw_get_name(hw)); 466 return -EINVAL; 467 } 468 469 /* Change PLL PMS values */ 470 pll_con3 = readl_relaxed(pll->con_reg); 471 pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) | 472 (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | 473 (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); 474 pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | 475 (rate->pdiv << PLL0822X_PDIV_SHIFT) | 476 (rate->sdiv << PLL0822X_SDIV_SHIFT); 477 478 /* Set PLL lock time */ 479 writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR, 480 pll->lock_reg); 481 482 /* Write PMS values */ 483 writel_relaxed(pll_con3, pll->con_reg); 484 485 /* Wait for PLL lock if the PLL is enabled */ 486 if (pll_con3 & BIT(pll->enable_offs)) 487 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 488 489 return 0; 490 } 491 492 static const struct clk_ops samsung_pll0822x_clk_ops = { 493 .recalc_rate = samsung_pll0822x_recalc_rate, 494 .round_rate = samsung_pll_round_rate, 495 .set_rate = samsung_pll0822x_set_rate, 496 .enable = samsung_pll3xxx_enable, 497 .disable = samsung_pll3xxx_disable, 498 }; 499 500 static const struct clk_ops samsung_pll0822x_clk_min_ops = { 501 .recalc_rate = samsung_pll0822x_recalc_rate, 502 }; 503 504 /* 505 * PLL0831x Clock Type 506 */ 507 /* Maximum lock time can be 500 * PDIV cycles */ 508 #define PLL0831X_LOCK_FACTOR (500) 509 510 #define PLL0831X_KDIV_MASK (0xFFFF) 511 #define PLL0831X_MDIV_MASK (0x1FF) 512 #define PLL0831X_PDIV_MASK (0x3F) 513 #define PLL0831X_SDIV_MASK (0x7) 514 #define PLL0831X_MDIV_SHIFT (16) 515 #define PLL0831X_PDIV_SHIFT (8) 516 #define PLL0831X_SDIV_SHIFT (0) 517 #define PLL0831X_KDIV_SHIFT (0) 518 #define PLL0831X_LOCK_STAT_SHIFT (29) 519 #define PLL0831X_ENABLE_SHIFT (31) 520 521 static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw, 522 unsigned long parent_rate) 523 { 524 struct samsung_clk_pll *pll = to_clk_pll(hw); 525 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; 526 s16 kdiv; 527 u64 fvco = parent_rate; 528 529 pll_con3 = readl_relaxed(pll->con_reg); 530 pll_con5 = readl_relaxed(pll->con_reg + 8); 531 mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK; 532 pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK; 533 sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK; 534 kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK); 535 536 fvco *= (mdiv << 16) + kdiv; 537 do_div(fvco, (pdiv << sdiv)); 538 fvco >>= 16; 539 540 return (unsigned long)fvco; 541 } 542 543 static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate, 544 unsigned long parent_rate) 545 { 546 const struct samsung_pll_rate_table *rate; 547 struct samsung_clk_pll *pll = to_clk_pll(hw); 548 u32 pll_con3, pll_con5; 549 550 /* Get required rate settings from table */ 551 rate = samsung_get_pll_settings(pll, drate); 552 if (!rate) { 553 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 554 drate, clk_hw_get_name(hw)); 555 return -EINVAL; 556 } 557 558 pll_con3 = readl_relaxed(pll->con_reg); 559 pll_con5 = readl_relaxed(pll->con_reg + 8); 560 561 /* Change PLL PMSK values */ 562 pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) | 563 (PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) | 564 (PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT)); 565 pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) | 566 (rate->pdiv << PLL0831X_PDIV_SHIFT) | 567 (rate->sdiv << PLL0831X_SDIV_SHIFT); 568 pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT); 569 /* 570 * kdiv is 16-bit 2's complement (s16), but stored as unsigned int. 571 * Cast it to u16 to avoid leading 0xffff's in case of negative value. 572 */ 573 pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT); 574 575 /* Set PLL lock time */ 576 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg); 577 578 /* Write PMSK values */ 579 writel_relaxed(pll_con3, pll->con_reg); 580 writel_relaxed(pll_con5, pll->con_reg + 8); 581 582 /* Wait for PLL lock if the PLL is enabled */ 583 if (pll_con3 & BIT(pll->enable_offs)) 584 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 585 586 return 0; 587 } 588 589 static const struct clk_ops samsung_pll0831x_clk_ops = { 590 .recalc_rate = samsung_pll0831x_recalc_rate, 591 .set_rate = samsung_pll0831x_set_rate, 592 .round_rate = samsung_pll_round_rate, 593 .enable = samsung_pll3xxx_enable, 594 .disable = samsung_pll3xxx_disable, 595 }; 596 597 static const struct clk_ops samsung_pll0831x_clk_min_ops = { 598 .recalc_rate = samsung_pll0831x_recalc_rate, 599 }; 600 601 /* 602 * PLL45xx Clock Type 603 */ 604 #define PLL4502_LOCK_FACTOR 400 605 #define PLL4508_LOCK_FACTOR 240 606 607 #define PLL45XX_MDIV_MASK (0x3FF) 608 #define PLL45XX_PDIV_MASK (0x3F) 609 #define PLL45XX_SDIV_MASK (0x7) 610 #define PLL45XX_AFC_MASK (0x1F) 611 #define PLL45XX_MDIV_SHIFT (16) 612 #define PLL45XX_PDIV_SHIFT (8) 613 #define PLL45XX_SDIV_SHIFT (0) 614 #define PLL45XX_AFC_SHIFT (0) 615 616 #define PLL45XX_ENABLE BIT(31) 617 #define PLL45XX_LOCKED BIT(29) 618 619 static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, 620 unsigned long parent_rate) 621 { 622 struct samsung_clk_pll *pll = to_clk_pll(hw); 623 u32 mdiv, pdiv, sdiv, pll_con; 624 u64 fvco = parent_rate; 625 626 pll_con = readl_relaxed(pll->con_reg); 627 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; 628 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; 629 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; 630 631 if (pll->type == pll_4508) 632 sdiv = sdiv - 1; 633 634 fvco *= mdiv; 635 do_div(fvco, (pdiv << sdiv)); 636 637 return (unsigned long)fvco; 638 } 639 640 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1, 641 const struct samsung_pll_rate_table *rate) 642 { 643 u32 old_mdiv, old_pdiv, old_afc; 644 645 old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; 646 old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; 647 old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK; 648 649 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv 650 || old_afc != rate->afc); 651 } 652 653 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, 654 unsigned long prate) 655 { 656 struct samsung_clk_pll *pll = to_clk_pll(hw); 657 const struct samsung_pll_rate_table *rate; 658 u32 con0, con1; 659 660 /* Get required rate settings from table */ 661 rate = samsung_get_pll_settings(pll, drate); 662 if (!rate) { 663 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 664 drate, clk_hw_get_name(hw)); 665 return -EINVAL; 666 } 667 668 con0 = readl_relaxed(pll->con_reg); 669 con1 = readl_relaxed(pll->con_reg + 0x4); 670 671 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { 672 /* If only s change, change just s value only*/ 673 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); 674 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; 675 writel_relaxed(con0, pll->con_reg); 676 677 return 0; 678 } 679 680 /* Set PLL PMS values. */ 681 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | 682 (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) | 683 (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT)); 684 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | 685 (rate->pdiv << PLL45XX_PDIV_SHIFT) | 686 (rate->sdiv << PLL45XX_SDIV_SHIFT); 687 688 /* Set PLL AFC value. */ 689 con1 = readl_relaxed(pll->con_reg + 0x4); 690 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); 691 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); 692 693 /* Set PLL lock time. */ 694 switch (pll->type) { 695 case pll_4502: 696 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); 697 break; 698 case pll_4508: 699 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); 700 break; 701 default: 702 break; 703 } 704 705 /* Set new configuration. */ 706 writel_relaxed(con1, pll->con_reg + 0x4); 707 writel_relaxed(con0, pll->con_reg); 708 709 /* Wait for PLL lock */ 710 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); 711 } 712 713 static const struct clk_ops samsung_pll45xx_clk_ops = { 714 .recalc_rate = samsung_pll45xx_recalc_rate, 715 .round_rate = samsung_pll_round_rate, 716 .set_rate = samsung_pll45xx_set_rate, 717 }; 718 719 static const struct clk_ops samsung_pll45xx_clk_min_ops = { 720 .recalc_rate = samsung_pll45xx_recalc_rate, 721 }; 722 723 /* 724 * PLL46xx Clock Type 725 */ 726 #define PLL46XX_LOCK_FACTOR 3000 727 728 #define PLL46XX_VSEL_MASK (1) 729 #define PLL46XX_MDIV_MASK (0x1FF) 730 #define PLL1460X_MDIV_MASK (0x3FF) 731 732 #define PLL46XX_PDIV_MASK (0x3F) 733 #define PLL46XX_SDIV_MASK (0x7) 734 #define PLL46XX_VSEL_SHIFT (27) 735 #define PLL46XX_MDIV_SHIFT (16) 736 #define PLL46XX_PDIV_SHIFT (8) 737 #define PLL46XX_SDIV_SHIFT (0) 738 739 #define PLL46XX_KDIV_MASK (0xFFFF) 740 #define PLL4650C_KDIV_MASK (0xFFF) 741 #define PLL46XX_KDIV_SHIFT (0) 742 #define PLL46XX_MFR_MASK (0x3F) 743 #define PLL46XX_MRR_MASK (0x1F) 744 #define PLL46XX_KDIV_SHIFT (0) 745 #define PLL46XX_MFR_SHIFT (16) 746 #define PLL46XX_MRR_SHIFT (24) 747 748 #define PLL46XX_ENABLE BIT(31) 749 #define PLL46XX_LOCKED BIT(29) 750 #define PLL46XX_VSEL BIT(27) 751 752 static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, 753 unsigned long parent_rate) 754 { 755 struct samsung_clk_pll *pll = to_clk_pll(hw); 756 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; 757 u64 fvco = parent_rate; 758 759 pll_con0 = readl_relaxed(pll->con_reg); 760 pll_con1 = readl_relaxed(pll->con_reg + 4); 761 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? 762 PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); 763 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; 764 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; 765 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : 766 pll_con1 & PLL46XX_KDIV_MASK; 767 768 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; 769 770 fvco *= (mdiv << shift) + kdiv; 771 do_div(fvco, (pdiv << sdiv)); 772 fvco >>= shift; 773 774 return (unsigned long)fvco; 775 } 776 777 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, 778 const struct samsung_pll_rate_table *rate) 779 { 780 u32 old_mdiv, old_pdiv, old_kdiv; 781 782 old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; 783 old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; 784 old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK; 785 786 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv 787 || old_kdiv != rate->kdiv); 788 } 789 790 static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, 791 unsigned long prate) 792 { 793 struct samsung_clk_pll *pll = to_clk_pll(hw); 794 const struct samsung_pll_rate_table *rate; 795 u32 con0, con1, lock; 796 797 /* Get required rate settings from table */ 798 rate = samsung_get_pll_settings(pll, drate); 799 if (!rate) { 800 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 801 drate, clk_hw_get_name(hw)); 802 return -EINVAL; 803 } 804 805 con0 = readl_relaxed(pll->con_reg); 806 con1 = readl_relaxed(pll->con_reg + 0x4); 807 808 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { 809 /* If only s change, change just s value only*/ 810 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); 811 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; 812 writel_relaxed(con0, pll->con_reg); 813 814 return 0; 815 } 816 817 /* Set PLL lock time. */ 818 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; 819 if (lock > 0xffff) 820 /* Maximum lock time bitfield is 16-bit. */ 821 lock = 0xffff; 822 823 /* Set PLL PMS and VSEL values. */ 824 if (pll->type == pll_1460x) { 825 con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | 826 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | 827 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); 828 } else { 829 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | 830 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | 831 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | 832 (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); 833 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; 834 } 835 836 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | 837 (rate->pdiv << PLL46XX_PDIV_SHIFT) | 838 (rate->sdiv << PLL46XX_SDIV_SHIFT); 839 840 /* Set PLL K, MFR and MRR values. */ 841 con1 = readl_relaxed(pll->con_reg + 0x4); 842 con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | 843 (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | 844 (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); 845 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | 846 (rate->mfr << PLL46XX_MFR_SHIFT) | 847 (rate->mrr << PLL46XX_MRR_SHIFT); 848 849 /* Write configuration to PLL */ 850 writel_relaxed(lock, pll->lock_reg); 851 writel_relaxed(con0, pll->con_reg); 852 writel_relaxed(con1, pll->con_reg + 0x4); 853 854 /* Wait for PLL lock */ 855 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); 856 } 857 858 static const struct clk_ops samsung_pll46xx_clk_ops = { 859 .recalc_rate = samsung_pll46xx_recalc_rate, 860 .round_rate = samsung_pll_round_rate, 861 .set_rate = samsung_pll46xx_set_rate, 862 }; 863 864 static const struct clk_ops samsung_pll46xx_clk_min_ops = { 865 .recalc_rate = samsung_pll46xx_recalc_rate, 866 }; 867 868 /* 869 * PLL6552 Clock Type 870 */ 871 872 #define PLL6552_MDIV_MASK 0x3ff 873 #define PLL6552_PDIV_MASK 0x3f 874 #define PLL6552_SDIV_MASK 0x7 875 #define PLL6552_MDIV_SHIFT 16 876 #define PLL6552_MDIV_SHIFT_2416 14 877 #define PLL6552_PDIV_SHIFT 8 878 #define PLL6552_PDIV_SHIFT_2416 5 879 #define PLL6552_SDIV_SHIFT 0 880 881 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, 882 unsigned long parent_rate) 883 { 884 struct samsung_clk_pll *pll = to_clk_pll(hw); 885 u32 mdiv, pdiv, sdiv, pll_con; 886 u64 fvco = parent_rate; 887 888 pll_con = readl_relaxed(pll->con_reg); 889 if (pll->type == pll_6552_s3c2416) { 890 mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK; 891 pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK; 892 } else { 893 mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK; 894 pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK; 895 } 896 sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK; 897 898 fvco *= mdiv; 899 do_div(fvco, (pdiv << sdiv)); 900 901 return (unsigned long)fvco; 902 } 903 904 static const struct clk_ops samsung_pll6552_clk_ops = { 905 .recalc_rate = samsung_pll6552_recalc_rate, 906 }; 907 908 /* 909 * PLL6553 Clock Type 910 */ 911 912 #define PLL6553_MDIV_MASK 0xff 913 #define PLL6553_PDIV_MASK 0x3f 914 #define PLL6553_SDIV_MASK 0x7 915 #define PLL6553_KDIV_MASK 0xffff 916 #define PLL6553_MDIV_SHIFT 16 917 #define PLL6553_PDIV_SHIFT 8 918 #define PLL6553_SDIV_SHIFT 0 919 #define PLL6553_KDIV_SHIFT 0 920 921 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, 922 unsigned long parent_rate) 923 { 924 struct samsung_clk_pll *pll = to_clk_pll(hw); 925 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; 926 u64 fvco = parent_rate; 927 928 pll_con0 = readl_relaxed(pll->con_reg); 929 pll_con1 = readl_relaxed(pll->con_reg + 0x4); 930 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; 931 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; 932 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; 933 kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK; 934 935 fvco *= (mdiv << 16) + kdiv; 936 do_div(fvco, (pdiv << sdiv)); 937 fvco >>= 16; 938 939 return (unsigned long)fvco; 940 } 941 942 static const struct clk_ops samsung_pll6553_clk_ops = { 943 .recalc_rate = samsung_pll6553_recalc_rate, 944 }; 945 946 /* 947 * PLL2550x Clock Type 948 */ 949 950 #define PLL2550X_R_MASK (0x1) 951 #define PLL2550X_P_MASK (0x3F) 952 #define PLL2550X_M_MASK (0x3FF) 953 #define PLL2550X_S_MASK (0x7) 954 #define PLL2550X_R_SHIFT (20) 955 #define PLL2550X_P_SHIFT (14) 956 #define PLL2550X_M_SHIFT (4) 957 #define PLL2550X_S_SHIFT (0) 958 959 static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, 960 unsigned long parent_rate) 961 { 962 struct samsung_clk_pll *pll = to_clk_pll(hw); 963 u32 r, p, m, s, pll_stat; 964 u64 fvco = parent_rate; 965 966 pll_stat = readl_relaxed(pll->con_reg); 967 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK; 968 if (!r) 969 return 0; 970 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK; 971 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK; 972 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK; 973 974 fvco *= m; 975 do_div(fvco, (p << s)); 976 977 return (unsigned long)fvco; 978 } 979 980 static const struct clk_ops samsung_pll2550x_clk_ops = { 981 .recalc_rate = samsung_pll2550x_recalc_rate, 982 }; 983 984 /* 985 * PLL2550xx Clock Type 986 */ 987 988 /* Maximum lock time can be 270 * PDIV cycles */ 989 #define PLL2550XX_LOCK_FACTOR 270 990 991 #define PLL2550XX_M_MASK 0x3FF 992 #define PLL2550XX_P_MASK 0x3F 993 #define PLL2550XX_S_MASK 0x7 994 #define PLL2550XX_LOCK_STAT_MASK 0x1 995 #define PLL2550XX_M_SHIFT 9 996 #define PLL2550XX_P_SHIFT 3 997 #define PLL2550XX_S_SHIFT 0 998 #define PLL2550XX_LOCK_STAT_SHIFT 21 999 1000 static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, 1001 unsigned long parent_rate) 1002 { 1003 struct samsung_clk_pll *pll = to_clk_pll(hw); 1004 u32 mdiv, pdiv, sdiv, pll_con; 1005 u64 fvco = parent_rate; 1006 1007 pll_con = readl_relaxed(pll->con_reg); 1008 mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; 1009 pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; 1010 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; 1011 1012 fvco *= mdiv; 1013 do_div(fvco, (pdiv << sdiv)); 1014 1015 return (unsigned long)fvco; 1016 } 1017 1018 static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) 1019 { 1020 u32 old_mdiv, old_pdiv; 1021 1022 old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; 1023 old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; 1024 1025 return mdiv != old_mdiv || pdiv != old_pdiv; 1026 } 1027 1028 static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, 1029 unsigned long prate) 1030 { 1031 struct samsung_clk_pll *pll = to_clk_pll(hw); 1032 const struct samsung_pll_rate_table *rate; 1033 u32 tmp; 1034 1035 /* Get required rate settings from table */ 1036 rate = samsung_get_pll_settings(pll, drate); 1037 if (!rate) { 1038 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1039 drate, clk_hw_get_name(hw)); 1040 return -EINVAL; 1041 } 1042 1043 tmp = readl_relaxed(pll->con_reg); 1044 1045 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { 1046 /* If only s change, change just s value only*/ 1047 tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); 1048 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; 1049 writel_relaxed(tmp, pll->con_reg); 1050 1051 return 0; 1052 } 1053 1054 /* Set PLL lock time. */ 1055 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); 1056 1057 /* Change PLL PMS values */ 1058 tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | 1059 (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) | 1060 (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT)); 1061 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | 1062 (rate->pdiv << PLL2550XX_P_SHIFT) | 1063 (rate->sdiv << PLL2550XX_S_SHIFT); 1064 writel_relaxed(tmp, pll->con_reg); 1065 1066 /* Wait for PLL lock */ 1067 return samsung_pll_lock_wait(pll, 1068 PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT); 1069 } 1070 1071 static const struct clk_ops samsung_pll2550xx_clk_ops = { 1072 .recalc_rate = samsung_pll2550xx_recalc_rate, 1073 .round_rate = samsung_pll_round_rate, 1074 .set_rate = samsung_pll2550xx_set_rate, 1075 }; 1076 1077 static const struct clk_ops samsung_pll2550xx_clk_min_ops = { 1078 .recalc_rate = samsung_pll2550xx_recalc_rate, 1079 }; 1080 1081 /* 1082 * PLL2650x Clock Type 1083 */ 1084 1085 /* Maximum lock time can be 3000 * PDIV cycles */ 1086 #define PLL2650X_LOCK_FACTOR 3000 1087 1088 #define PLL2650X_M_MASK 0x1ff 1089 #define PLL2650X_P_MASK 0x3f 1090 #define PLL2650X_S_MASK 0x7 1091 #define PLL2650X_K_MASK 0xffff 1092 #define PLL2650X_LOCK_STAT_MASK 0x1 1093 #define PLL2650X_M_SHIFT 16 1094 #define PLL2650X_P_SHIFT 8 1095 #define PLL2650X_S_SHIFT 0 1096 #define PLL2650X_K_SHIFT 0 1097 #define PLL2650X_LOCK_STAT_SHIFT 29 1098 #define PLL2650X_PLL_ENABLE_SHIFT 31 1099 1100 static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw, 1101 unsigned long parent_rate) 1102 { 1103 struct samsung_clk_pll *pll = to_clk_pll(hw); 1104 u64 fout = parent_rate; 1105 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; 1106 s16 kdiv; 1107 1108 pll_con0 = readl_relaxed(pll->con_reg); 1109 mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK; 1110 pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK; 1111 sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK; 1112 1113 pll_con1 = readl_relaxed(pll->con_reg + 4); 1114 kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK); 1115 1116 fout *= (mdiv << 16) + kdiv; 1117 do_div(fout, (pdiv << sdiv)); 1118 fout >>= 16; 1119 1120 return (unsigned long)fout; 1121 } 1122 1123 static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate, 1124 unsigned long prate) 1125 { 1126 struct samsung_clk_pll *pll = to_clk_pll(hw); 1127 const struct samsung_pll_rate_table *rate; 1128 u32 con0, con1; 1129 1130 /* Get required rate settings from table */ 1131 rate = samsung_get_pll_settings(pll, drate); 1132 if (!rate) { 1133 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1134 drate, clk_hw_get_name(hw)); 1135 return -EINVAL; 1136 } 1137 1138 con0 = readl_relaxed(pll->con_reg); 1139 con1 = readl_relaxed(pll->con_reg + 4); 1140 1141 /* Set PLL lock time. */ 1142 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); 1143 1144 /* Change PLL PMS values */ 1145 con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) | 1146 (PLL2650X_P_MASK << PLL2650X_P_SHIFT) | 1147 (PLL2650X_S_MASK << PLL2650X_S_SHIFT)); 1148 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | 1149 (rate->pdiv << PLL2650X_P_SHIFT) | 1150 (rate->sdiv << PLL2650X_S_SHIFT); 1151 con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT); 1152 writel_relaxed(con0, pll->con_reg); 1153 1154 con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT); 1155 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); 1156 writel_relaxed(con1, pll->con_reg + 4); 1157 1158 /* Wait for PLL lock */ 1159 return samsung_pll_lock_wait(pll, 1160 PLL2650X_LOCK_STAT_MASK << PLL2650X_LOCK_STAT_SHIFT); 1161 } 1162 1163 static const struct clk_ops samsung_pll2650x_clk_ops = { 1164 .recalc_rate = samsung_pll2650x_recalc_rate, 1165 .round_rate = samsung_pll_round_rate, 1166 .set_rate = samsung_pll2650x_set_rate, 1167 }; 1168 1169 static const struct clk_ops samsung_pll2650x_clk_min_ops = { 1170 .recalc_rate = samsung_pll2650x_recalc_rate, 1171 }; 1172 1173 /* 1174 * PLL2650XX Clock Type 1175 */ 1176 1177 /* Maximum lock time can be 3000 * PDIV cycles */ 1178 #define PLL2650XX_LOCK_FACTOR 3000 1179 1180 #define PLL2650XX_MDIV_SHIFT 9 1181 #define PLL2650XX_PDIV_SHIFT 3 1182 #define PLL2650XX_SDIV_SHIFT 0 1183 #define PLL2650XX_KDIV_SHIFT 0 1184 #define PLL2650XX_MDIV_MASK 0x1ff 1185 #define PLL2650XX_PDIV_MASK 0x3f 1186 #define PLL2650XX_SDIV_MASK 0x7 1187 #define PLL2650XX_KDIV_MASK 0xffff 1188 #define PLL2650XX_PLL_ENABLE_SHIFT 23 1189 #define PLL2650XX_PLL_LOCKTIME_SHIFT 21 1190 #define PLL2650XX_PLL_FOUTMASK_SHIFT 31 1191 1192 static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, 1193 unsigned long parent_rate) 1194 { 1195 struct samsung_clk_pll *pll = to_clk_pll(hw); 1196 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; 1197 s16 kdiv; 1198 u64 fvco = parent_rate; 1199 1200 pll_con0 = readl_relaxed(pll->con_reg); 1201 pll_con2 = readl_relaxed(pll->con_reg + 8); 1202 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; 1203 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; 1204 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; 1205 kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK); 1206 1207 fvco *= (mdiv << 16) + kdiv; 1208 do_div(fvco, (pdiv << sdiv)); 1209 fvco >>= 16; 1210 1211 return (unsigned long)fvco; 1212 } 1213 1214 static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, 1215 unsigned long parent_rate) 1216 { 1217 struct samsung_clk_pll *pll = to_clk_pll(hw); 1218 u32 pll_con0, pll_con2; 1219 const struct samsung_pll_rate_table *rate; 1220 1221 rate = samsung_get_pll_settings(pll, drate); 1222 if (!rate) { 1223 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1224 drate, clk_hw_get_name(hw)); 1225 return -EINVAL; 1226 } 1227 1228 pll_con0 = readl_relaxed(pll->con_reg); 1229 pll_con2 = readl_relaxed(pll->con_reg + 8); 1230 1231 /* Change PLL PMS values */ 1232 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | 1233 PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT | 1234 PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); 1235 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; 1236 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; 1237 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; 1238 pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; 1239 pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; 1240 1241 pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT); 1242 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) 1243 << PLL2650XX_KDIV_SHIFT; 1244 1245 /* Set PLL lock time. */ 1246 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); 1247 1248 writel_relaxed(pll_con0, pll->con_reg); 1249 writel_relaxed(pll_con2, pll->con_reg + 8); 1250 1251 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); 1252 } 1253 1254 static const struct clk_ops samsung_pll2650xx_clk_ops = { 1255 .recalc_rate = samsung_pll2650xx_recalc_rate, 1256 .set_rate = samsung_pll2650xx_set_rate, 1257 .round_rate = samsung_pll_round_rate, 1258 }; 1259 1260 static const struct clk_ops samsung_pll2650xx_clk_min_ops = { 1261 .recalc_rate = samsung_pll2650xx_recalc_rate, 1262 }; 1263 1264 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1265 const struct samsung_pll_clock *pll_clk) 1266 { 1267 struct samsung_clk_pll *pll; 1268 struct clk_init_data init; 1269 int ret, len; 1270 1271 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1272 if (!pll) { 1273 pr_err("%s: could not allocate pll clk %s\n", 1274 __func__, pll_clk->name); 1275 return; 1276 } 1277 1278 init.name = pll_clk->name; 1279 init.flags = pll_clk->flags; 1280 init.parent_names = &pll_clk->parent_name; 1281 init.num_parents = 1; 1282 1283 if (pll_clk->rate_table) { 1284 /* find count of rates in rate_table */ 1285 for (len = 0; pll_clk->rate_table[len].rate != 0; ) 1286 len++; 1287 1288 pll->rate_count = len; 1289 pll->rate_table = kmemdup(pll_clk->rate_table, 1290 pll->rate_count * 1291 sizeof(struct samsung_pll_rate_table), 1292 GFP_KERNEL); 1293 WARN(!pll->rate_table, 1294 "%s: could not allocate rate table for %s\n", 1295 __func__, pll_clk->name); 1296 } 1297 1298 switch (pll_clk->type) { 1299 case pll_2126: 1300 init.ops = &samsung_pll2126_clk_ops; 1301 break; 1302 case pll_3000: 1303 init.ops = &samsung_pll3000_clk_ops; 1304 break; 1305 /* clk_ops for 35xx and 2550 are similar */ 1306 case pll_35xx: 1307 case pll_2550: 1308 case pll_1450x: 1309 case pll_1451x: 1310 case pll_1452x: 1311 case pll_142xx: 1312 pll->enable_offs = PLL35XX_ENABLE_SHIFT; 1313 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; 1314 if (!pll->rate_table) 1315 init.ops = &samsung_pll35xx_clk_min_ops; 1316 else 1317 init.ops = &samsung_pll35xx_clk_ops; 1318 break; 1319 case pll_1417x: 1320 case pll_0818x: 1321 case pll_0822x: 1322 case pll_0516x: 1323 case pll_0517x: 1324 case pll_0518x: 1325 pll->enable_offs = PLL0822X_ENABLE_SHIFT; 1326 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; 1327 if (!pll->rate_table) 1328 init.ops = &samsung_pll0822x_clk_min_ops; 1329 else 1330 init.ops = &samsung_pll0822x_clk_ops; 1331 break; 1332 case pll_4500: 1333 init.ops = &samsung_pll45xx_clk_min_ops; 1334 break; 1335 case pll_4502: 1336 case pll_4508: 1337 if (!pll->rate_table) 1338 init.ops = &samsung_pll45xx_clk_min_ops; 1339 else 1340 init.ops = &samsung_pll45xx_clk_ops; 1341 break; 1342 /* clk_ops for 36xx and 2650 are similar */ 1343 case pll_36xx: 1344 case pll_2650: 1345 pll->enable_offs = PLL36XX_ENABLE_SHIFT; 1346 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; 1347 if (!pll->rate_table) 1348 init.ops = &samsung_pll36xx_clk_min_ops; 1349 else 1350 init.ops = &samsung_pll36xx_clk_ops; 1351 break; 1352 case pll_0831x: 1353 pll->enable_offs = PLL0831X_ENABLE_SHIFT; 1354 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; 1355 if (!pll->rate_table) 1356 init.ops = &samsung_pll0831x_clk_min_ops; 1357 else 1358 init.ops = &samsung_pll0831x_clk_ops; 1359 break; 1360 case pll_6552: 1361 case pll_6552_s3c2416: 1362 init.ops = &samsung_pll6552_clk_ops; 1363 break; 1364 case pll_6553: 1365 init.ops = &samsung_pll6553_clk_ops; 1366 break; 1367 case pll_4600: 1368 case pll_4650: 1369 case pll_4650c: 1370 case pll_1460x: 1371 if (!pll->rate_table) 1372 init.ops = &samsung_pll46xx_clk_min_ops; 1373 else 1374 init.ops = &samsung_pll46xx_clk_ops; 1375 break; 1376 case pll_2550x: 1377 init.ops = &samsung_pll2550x_clk_ops; 1378 break; 1379 case pll_2550xx: 1380 if (!pll->rate_table) 1381 init.ops = &samsung_pll2550xx_clk_min_ops; 1382 else 1383 init.ops = &samsung_pll2550xx_clk_ops; 1384 break; 1385 case pll_2650x: 1386 if (!pll->rate_table) 1387 init.ops = &samsung_pll2650x_clk_min_ops; 1388 else 1389 init.ops = &samsung_pll2650x_clk_ops; 1390 break; 1391 case pll_2650xx: 1392 if (!pll->rate_table) 1393 init.ops = &samsung_pll2650xx_clk_min_ops; 1394 else 1395 init.ops = &samsung_pll2650xx_clk_ops; 1396 break; 1397 default: 1398 pr_warn("%s: Unknown pll type for pll clk %s\n", 1399 __func__, pll_clk->name); 1400 } 1401 1402 pll->hw.init = &init; 1403 pll->type = pll_clk->type; 1404 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset; 1405 pll->con_reg = ctx->reg_base + pll_clk->con_offset; 1406 1407 ret = clk_hw_register(ctx->dev, &pll->hw); 1408 if (ret) { 1409 pr_err("%s: failed to register pll clock %s : %d\n", 1410 __func__, pll_clk->name, ret); 1411 kfree(pll->rate_table); 1412 kfree(pll); 1413 return; 1414 } 1415 1416 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); 1417 } 1418 1419 void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1420 const struct samsung_pll_clock *pll_list, 1421 unsigned int nr_pll) 1422 { 1423 int cnt; 1424 1425 for (cnt = 0; cnt < nr_pll; cnt++) 1426 _samsung_clk_register_pll(ctx, &pll_list[cnt]); 1427 } 1428