1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2013 Linaro Ltd. 5 * 6 * This file contains the utility functions to register the pll clocks. 7 */ 8 9 #include <linux/errno.h> 10 #include <linux/hrtimer.h> 11 #include <linux/iopoll.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/timekeeping.h> 15 #include <linux/clk-provider.h> 16 #include <linux/io.h> 17 #include "clk.h" 18 #include "clk-pll.h" 19 20 #define PLL_TIMEOUT_US 20000U 21 #define PLL_TIMEOUT_LOOPS 1000000U 22 23 struct samsung_clk_pll { 24 struct clk_hw hw; 25 void __iomem *lock_reg; 26 void __iomem *con_reg; 27 /* PLL enable control bit offset in @con_reg register */ 28 unsigned short enable_offs; 29 /* PLL lock status bit offset in @con_reg register */ 30 unsigned short lock_offs; 31 enum samsung_pll_type type; 32 unsigned int rate_count; 33 const struct samsung_pll_rate_table *rate_table; 34 }; 35 36 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw) 37 38 static const struct samsung_pll_rate_table *samsung_get_pll_settings( 39 struct samsung_clk_pll *pll, unsigned long rate) 40 { 41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; 42 int i; 43 44 for (i = 0; i < pll->rate_count; i++) { 45 if (rate == rate_table[i].rate) 46 return &rate_table[i]; 47 } 48 49 return NULL; 50 } 51 52 static long samsung_pll_round_rate(struct clk_hw *hw, 53 unsigned long drate, unsigned long *prate) 54 { 55 struct samsung_clk_pll *pll = to_clk_pll(hw); 56 const struct samsung_pll_rate_table *rate_table = pll->rate_table; 57 int i; 58 59 /* Assumming rate_table is in descending order */ 60 for (i = 0; i < pll->rate_count; i++) { 61 if (drate >= rate_table[i].rate) 62 return rate_table[i].rate; 63 } 64 65 /* return minimum supported value */ 66 return rate_table[i - 1].rate; 67 } 68 69 static bool pll_early_timeout = true; 70 71 static int __init samsung_pll_disable_early_timeout(void) 72 { 73 pll_early_timeout = false; 74 return 0; 75 } 76 arch_initcall(samsung_pll_disable_early_timeout); 77 78 /* Wait until the PLL is locked */ 79 static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, 80 unsigned int reg_mask) 81 { 82 int i, ret; 83 u32 val; 84 85 /* 86 * This function might be called when the timekeeping API can't be used 87 * to detect timeouts. One situation is when the clocksource is not yet 88 * initialized, another when the timekeeping is suspended. udelay() also 89 * cannot be used when the clocksource is not running on arm64, since 90 * the current timer is used as cycle counter. So a simple busy loop 91 * is used here in that special cases. The limit of iterations has been 92 * derived from experimental measurements of various PLLs on multiple 93 * Exynos SoC variants. Single register read time was usually in range 94 * 0.4...1.5 us, never less than 0.4 us. 95 */ 96 if (pll_early_timeout || timekeeping_suspended) { 97 i = PLL_TIMEOUT_LOOPS; 98 while (i-- > 0) { 99 if (readl_relaxed(pll->con_reg) & reg_mask) 100 return 0; 101 102 cpu_relax(); 103 } 104 ret = -ETIMEDOUT; 105 } else { 106 ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val, 107 val & reg_mask, 0, PLL_TIMEOUT_US); 108 } 109 110 if (ret < 0) 111 pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw)); 112 113 return ret; 114 } 115 116 static int samsung_pll3xxx_enable(struct clk_hw *hw) 117 { 118 struct samsung_clk_pll *pll = to_clk_pll(hw); 119 u32 tmp; 120 121 tmp = readl_relaxed(pll->con_reg); 122 tmp |= BIT(pll->enable_offs); 123 writel_relaxed(tmp, pll->con_reg); 124 125 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 126 } 127 128 static void samsung_pll3xxx_disable(struct clk_hw *hw) 129 { 130 struct samsung_clk_pll *pll = to_clk_pll(hw); 131 u32 tmp; 132 133 tmp = readl_relaxed(pll->con_reg); 134 tmp &= ~BIT(pll->enable_offs); 135 writel_relaxed(tmp, pll->con_reg); 136 } 137 138 /* 139 * PLL2126 Clock Type 140 */ 141 142 #define PLL2126_MDIV_MASK (0xff) 143 #define PLL2126_PDIV_MASK (0x3f) 144 #define PLL2126_SDIV_MASK (0x3) 145 #define PLL2126_MDIV_SHIFT (16) 146 #define PLL2126_PDIV_SHIFT (8) 147 #define PLL2126_SDIV_SHIFT (0) 148 149 static unsigned long samsung_pll2126_recalc_rate(struct clk_hw *hw, 150 unsigned long parent_rate) 151 { 152 struct samsung_clk_pll *pll = to_clk_pll(hw); 153 u32 pll_con, mdiv, pdiv, sdiv; 154 u64 fvco = parent_rate; 155 156 pll_con = readl_relaxed(pll->con_reg); 157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; 158 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; 159 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; 160 161 fvco *= (mdiv + 8); 162 do_div(fvco, (pdiv + 2) << sdiv); 163 164 return (unsigned long)fvco; 165 } 166 167 static const struct clk_ops samsung_pll2126_clk_ops = { 168 .recalc_rate = samsung_pll2126_recalc_rate, 169 }; 170 171 /* 172 * PLL3000 Clock Type 173 */ 174 175 #define PLL3000_MDIV_MASK (0xff) 176 #define PLL3000_PDIV_MASK (0x3) 177 #define PLL3000_SDIV_MASK (0x3) 178 #define PLL3000_MDIV_SHIFT (16) 179 #define PLL3000_PDIV_SHIFT (8) 180 #define PLL3000_SDIV_SHIFT (0) 181 182 static unsigned long samsung_pll3000_recalc_rate(struct clk_hw *hw, 183 unsigned long parent_rate) 184 { 185 struct samsung_clk_pll *pll = to_clk_pll(hw); 186 u32 pll_con, mdiv, pdiv, sdiv; 187 u64 fvco = parent_rate; 188 189 pll_con = readl_relaxed(pll->con_reg); 190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; 191 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; 192 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; 193 194 fvco *= (2 * (mdiv + 8)); 195 do_div(fvco, pdiv << sdiv); 196 197 return (unsigned long)fvco; 198 } 199 200 static const struct clk_ops samsung_pll3000_clk_ops = { 201 .recalc_rate = samsung_pll3000_recalc_rate, 202 }; 203 204 /* 205 * PLL35xx Clock Type 206 */ 207 /* Maximum lock time can be 270 * PDIV cycles */ 208 #define PLL35XX_LOCK_FACTOR (270) 209 #define PLL142XX_LOCK_FACTOR (150) 210 211 #define PLL35XX_MDIV_MASK (0x3FF) 212 #define PLL35XX_PDIV_MASK (0x3F) 213 #define PLL35XX_SDIV_MASK (0x7) 214 #define PLL35XX_MDIV_SHIFT (16) 215 #define PLL35XX_PDIV_SHIFT (8) 216 #define PLL35XX_SDIV_SHIFT (0) 217 #define PLL35XX_LOCK_STAT_SHIFT (29) 218 #define PLL35XX_ENABLE_SHIFT (31) 219 220 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, 221 unsigned long parent_rate) 222 { 223 struct samsung_clk_pll *pll = to_clk_pll(hw); 224 u32 mdiv, pdiv, sdiv, pll_con; 225 u64 fvco = parent_rate; 226 227 pll_con = readl_relaxed(pll->con_reg); 228 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; 229 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; 230 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; 231 232 fvco *= mdiv; 233 do_div(fvco, (pdiv << sdiv)); 234 235 return (unsigned long)fvco; 236 } 237 238 static inline bool samsung_pll35xx_mp_change( 239 const struct samsung_pll_rate_table *rate, u32 pll_con) 240 { 241 u32 old_mdiv, old_pdiv; 242 243 old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; 244 old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; 245 246 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); 247 } 248 249 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, 250 unsigned long prate) 251 { 252 struct samsung_clk_pll *pll = to_clk_pll(hw); 253 const struct samsung_pll_rate_table *rate; 254 u32 tmp; 255 256 /* Get required rate settings from table */ 257 rate = samsung_get_pll_settings(pll, drate); 258 if (!rate) { 259 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 260 drate, clk_hw_get_name(hw)); 261 return -EINVAL; 262 } 263 264 tmp = readl_relaxed(pll->con_reg); 265 266 if (!(samsung_pll35xx_mp_change(rate, tmp))) { 267 /* If only s change, change just s value only*/ 268 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); 269 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; 270 writel_relaxed(tmp, pll->con_reg); 271 272 return 0; 273 } 274 275 /* Set PLL lock time. */ 276 if (pll->type == pll_142xx) 277 writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, 278 pll->lock_reg); 279 else 280 writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR, 281 pll->lock_reg); 282 283 /* Change PLL PMS values */ 284 tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) | 285 (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) | 286 (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT)); 287 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) | 288 (rate->pdiv << PLL35XX_PDIV_SHIFT) | 289 (rate->sdiv << PLL35XX_SDIV_SHIFT); 290 writel_relaxed(tmp, pll->con_reg); 291 292 /* Wait for PLL lock if the PLL is enabled */ 293 if (tmp & BIT(pll->enable_offs)) 294 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 295 296 return 0; 297 } 298 299 static const struct clk_ops samsung_pll35xx_clk_ops = { 300 .recalc_rate = samsung_pll35xx_recalc_rate, 301 .round_rate = samsung_pll_round_rate, 302 .set_rate = samsung_pll35xx_set_rate, 303 .enable = samsung_pll3xxx_enable, 304 .disable = samsung_pll3xxx_disable, 305 }; 306 307 static const struct clk_ops samsung_pll35xx_clk_min_ops = { 308 .recalc_rate = samsung_pll35xx_recalc_rate, 309 }; 310 311 /* 312 * PLL36xx Clock Type 313 */ 314 /* Maximum lock time can be 3000 * PDIV cycles */ 315 #define PLL36XX_LOCK_FACTOR (3000) 316 317 #define PLL36XX_KDIV_MASK (0xFFFF) 318 #define PLL36XX_MDIV_MASK (0x1FF) 319 #define PLL36XX_PDIV_MASK (0x3F) 320 #define PLL36XX_SDIV_MASK (0x7) 321 #define PLL36XX_MDIV_SHIFT (16) 322 #define PLL36XX_PDIV_SHIFT (8) 323 #define PLL36XX_SDIV_SHIFT (0) 324 #define PLL36XX_KDIV_SHIFT (0) 325 #define PLL36XX_LOCK_STAT_SHIFT (29) 326 #define PLL36XX_ENABLE_SHIFT (31) 327 328 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, 329 unsigned long parent_rate) 330 { 331 struct samsung_clk_pll *pll = to_clk_pll(hw); 332 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; 333 s16 kdiv; 334 u64 fvco = parent_rate; 335 336 pll_con0 = readl_relaxed(pll->con_reg); 337 pll_con1 = readl_relaxed(pll->con_reg + 4); 338 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 339 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 340 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; 341 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK); 342 343 fvco *= (mdiv << 16) + kdiv; 344 do_div(fvco, (pdiv << sdiv)); 345 fvco >>= 16; 346 347 return (unsigned long)fvco; 348 } 349 350 static inline bool samsung_pll36xx_mpk_change( 351 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) 352 { 353 u32 old_mdiv, old_pdiv, old_kdiv; 354 355 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; 356 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; 357 old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK; 358 359 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv || 360 rate->kdiv != old_kdiv); 361 } 362 363 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, 364 unsigned long parent_rate) 365 { 366 struct samsung_clk_pll *pll = to_clk_pll(hw); 367 u32 pll_con0, pll_con1; 368 const struct samsung_pll_rate_table *rate; 369 370 rate = samsung_get_pll_settings(pll, drate); 371 if (!rate) { 372 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 373 drate, clk_hw_get_name(hw)); 374 return -EINVAL; 375 } 376 377 pll_con0 = readl_relaxed(pll->con_reg); 378 pll_con1 = readl_relaxed(pll->con_reg + 4); 379 380 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { 381 /* If only s change, change just s value only*/ 382 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); 383 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); 384 writel_relaxed(pll_con0, pll->con_reg); 385 386 return 0; 387 } 388 389 /* Set PLL lock time. */ 390 writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); 391 392 /* Change PLL PMS values */ 393 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | 394 (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) | 395 (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT)); 396 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | 397 (rate->pdiv << PLL36XX_PDIV_SHIFT) | 398 (rate->sdiv << PLL36XX_SDIV_SHIFT); 399 writel_relaxed(pll_con0, pll->con_reg); 400 401 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); 402 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; 403 writel_relaxed(pll_con1, pll->con_reg + 4); 404 405 if (pll_con0 & BIT(pll->enable_offs)) 406 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 407 408 return 0; 409 } 410 411 static const struct clk_ops samsung_pll36xx_clk_ops = { 412 .recalc_rate = samsung_pll36xx_recalc_rate, 413 .set_rate = samsung_pll36xx_set_rate, 414 .round_rate = samsung_pll_round_rate, 415 .enable = samsung_pll3xxx_enable, 416 .disable = samsung_pll3xxx_disable, 417 }; 418 419 static const struct clk_ops samsung_pll36xx_clk_min_ops = { 420 .recalc_rate = samsung_pll36xx_recalc_rate, 421 }; 422 423 /* 424 * PLL0822x Clock Type 425 */ 426 /* Maximum lock time can be 150 * PDIV cycles */ 427 #define PLL0822X_LOCK_FACTOR (150) 428 429 #define PLL0822X_MDIV_MASK (0x3FF) 430 #define PLL0822X_PDIV_MASK (0x3F) 431 #define PLL0822X_SDIV_MASK (0x7) 432 #define PLL0822X_MDIV_SHIFT (16) 433 #define PLL0822X_PDIV_SHIFT (8) 434 #define PLL0822X_SDIV_SHIFT (0) 435 #define PLL0822X_LOCK_STAT_SHIFT (29) 436 #define PLL0822X_ENABLE_SHIFT (31) 437 438 /* 439 * PLL1418x, PLL0717x and PLL0718x are similar 440 * to PLL0822x, except that MDIV is one bit smaller 441 */ 442 #define PLL1418X_MDIV_MASK (0x1FF) 443 444 static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, 445 unsigned long parent_rate) 446 { 447 struct samsung_clk_pll *pll = to_clk_pll(hw); 448 u32 mdiv, pdiv, sdiv, pll_con3; 449 u64 fvco = parent_rate; 450 451 pll_con3 = readl_relaxed(pll->con_reg); 452 453 if (pll->type != pll_1418x && 454 pll->type != pll_0717x && 455 pll->type != pll_0718x) 456 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; 457 else 458 mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK; 459 460 pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; 461 sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; 462 463 fvco *= mdiv; 464 if (pll->type == pll_0516x) 465 fvco *= 2; 466 467 do_div(fvco, (pdiv << sdiv)); 468 469 return (unsigned long)fvco; 470 } 471 472 static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, 473 unsigned long prate) 474 { 475 const struct samsung_pll_rate_table *rate; 476 struct samsung_clk_pll *pll = to_clk_pll(hw); 477 u32 mdiv_mask, pll_con3; 478 479 if (pll->type != pll_1418x) 480 mdiv_mask = PLL0822X_MDIV_MASK; 481 else 482 mdiv_mask = PLL1418X_MDIV_MASK; 483 484 /* Get required rate settings from table */ 485 rate = samsung_get_pll_settings(pll, drate); 486 if (!rate) { 487 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 488 drate, clk_hw_get_name(hw)); 489 return -EINVAL; 490 } 491 492 /* Change PLL PMS values */ 493 pll_con3 = readl_relaxed(pll->con_reg); 494 pll_con3 &= ~((mdiv_mask << PLL0822X_MDIV_SHIFT) | 495 (PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) | 496 (PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT)); 497 pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) | 498 (rate->pdiv << PLL0822X_PDIV_SHIFT) | 499 (rate->sdiv << PLL0822X_SDIV_SHIFT); 500 501 /* Set PLL lock time */ 502 writel_relaxed(rate->pdiv * PLL0822X_LOCK_FACTOR, 503 pll->lock_reg); 504 505 /* Write PMS values */ 506 writel_relaxed(pll_con3, pll->con_reg); 507 508 /* Wait for PLL lock if the PLL is enabled */ 509 if (pll_con3 & BIT(pll->enable_offs)) 510 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 511 512 return 0; 513 } 514 515 static const struct clk_ops samsung_pll0822x_clk_ops = { 516 .recalc_rate = samsung_pll0822x_recalc_rate, 517 .round_rate = samsung_pll_round_rate, 518 .set_rate = samsung_pll0822x_set_rate, 519 .enable = samsung_pll3xxx_enable, 520 .disable = samsung_pll3xxx_disable, 521 }; 522 523 static const struct clk_ops samsung_pll0822x_clk_min_ops = { 524 .recalc_rate = samsung_pll0822x_recalc_rate, 525 }; 526 527 /* 528 * PLL0831x Clock Type 529 */ 530 /* Maximum lock time can be 500 * PDIV cycles */ 531 #define PLL0831X_LOCK_FACTOR (500) 532 533 #define PLL0831X_KDIV_MASK (0xFFFF) 534 #define PLL0831X_MDIV_MASK (0x1FF) 535 #define PLL0831X_PDIV_MASK (0x3F) 536 #define PLL0831X_SDIV_MASK (0x7) 537 #define PLL0831X_MDIV_SHIFT (16) 538 #define PLL0831X_PDIV_SHIFT (8) 539 #define PLL0831X_SDIV_SHIFT (0) 540 #define PLL0831X_KDIV_SHIFT (0) 541 #define PLL0831X_LOCK_STAT_SHIFT (29) 542 #define PLL0831X_ENABLE_SHIFT (31) 543 544 static unsigned long samsung_pll0831x_recalc_rate(struct clk_hw *hw, 545 unsigned long parent_rate) 546 { 547 struct samsung_clk_pll *pll = to_clk_pll(hw); 548 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; 549 s16 kdiv; 550 u64 fvco = parent_rate; 551 552 pll_con3 = readl_relaxed(pll->con_reg); 553 pll_con5 = readl_relaxed(pll->con_reg + 8); 554 mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK; 555 pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK; 556 sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK; 557 kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK); 558 559 fvco *= (mdiv << 16) + kdiv; 560 do_div(fvco, (pdiv << sdiv)); 561 fvco >>= 16; 562 563 return (unsigned long)fvco; 564 } 565 566 static int samsung_pll0831x_set_rate(struct clk_hw *hw, unsigned long drate, 567 unsigned long parent_rate) 568 { 569 const struct samsung_pll_rate_table *rate; 570 struct samsung_clk_pll *pll = to_clk_pll(hw); 571 u32 pll_con3, pll_con5; 572 573 /* Get required rate settings from table */ 574 rate = samsung_get_pll_settings(pll, drate); 575 if (!rate) { 576 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 577 drate, clk_hw_get_name(hw)); 578 return -EINVAL; 579 } 580 581 pll_con3 = readl_relaxed(pll->con_reg); 582 pll_con5 = readl_relaxed(pll->con_reg + 8); 583 584 /* Change PLL PMSK values */ 585 pll_con3 &= ~((PLL0831X_MDIV_MASK << PLL0831X_MDIV_SHIFT) | 586 (PLL0831X_PDIV_MASK << PLL0831X_PDIV_SHIFT) | 587 (PLL0831X_SDIV_MASK << PLL0831X_SDIV_SHIFT)); 588 pll_con3 |= (rate->mdiv << PLL0831X_MDIV_SHIFT) | 589 (rate->pdiv << PLL0831X_PDIV_SHIFT) | 590 (rate->sdiv << PLL0831X_SDIV_SHIFT); 591 pll_con5 &= ~(PLL0831X_KDIV_MASK << PLL0831X_KDIV_SHIFT); 592 /* 593 * kdiv is 16-bit 2's complement (s16), but stored as unsigned int. 594 * Cast it to u16 to avoid leading 0xffff's in case of negative value. 595 */ 596 pll_con5 |= ((u16)rate->kdiv << PLL0831X_KDIV_SHIFT); 597 598 /* Set PLL lock time */ 599 writel_relaxed(rate->pdiv * PLL0831X_LOCK_FACTOR, pll->lock_reg); 600 601 /* Write PMSK values */ 602 writel_relaxed(pll_con3, pll->con_reg); 603 writel_relaxed(pll_con5, pll->con_reg + 8); 604 605 /* Wait for PLL lock if the PLL is enabled */ 606 if (pll_con3 & BIT(pll->enable_offs)) 607 return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); 608 609 return 0; 610 } 611 612 static const struct clk_ops samsung_pll0831x_clk_ops = { 613 .recalc_rate = samsung_pll0831x_recalc_rate, 614 .set_rate = samsung_pll0831x_set_rate, 615 .round_rate = samsung_pll_round_rate, 616 .enable = samsung_pll3xxx_enable, 617 .disable = samsung_pll3xxx_disable, 618 }; 619 620 static const struct clk_ops samsung_pll0831x_clk_min_ops = { 621 .recalc_rate = samsung_pll0831x_recalc_rate, 622 }; 623 624 /* 625 * PLL45xx Clock Type 626 */ 627 #define PLL4502_LOCK_FACTOR 400 628 #define PLL4508_LOCK_FACTOR 240 629 630 #define PLL45XX_MDIV_MASK (0x3FF) 631 #define PLL45XX_PDIV_MASK (0x3F) 632 #define PLL45XX_SDIV_MASK (0x7) 633 #define PLL45XX_AFC_MASK (0x1F) 634 #define PLL45XX_MDIV_SHIFT (16) 635 #define PLL45XX_PDIV_SHIFT (8) 636 #define PLL45XX_SDIV_SHIFT (0) 637 #define PLL45XX_AFC_SHIFT (0) 638 639 #define PLL45XX_ENABLE BIT(31) 640 #define PLL45XX_LOCKED BIT(29) 641 642 static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, 643 unsigned long parent_rate) 644 { 645 struct samsung_clk_pll *pll = to_clk_pll(hw); 646 u32 mdiv, pdiv, sdiv, pll_con; 647 u64 fvco = parent_rate; 648 649 pll_con = readl_relaxed(pll->con_reg); 650 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; 651 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; 652 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; 653 654 if (pll->type == pll_4508) 655 sdiv = sdiv - 1; 656 657 fvco *= mdiv; 658 do_div(fvco, (pdiv << sdiv)); 659 660 return (unsigned long)fvco; 661 } 662 663 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1, 664 const struct samsung_pll_rate_table *rate) 665 { 666 u32 old_mdiv, old_pdiv, old_afc; 667 668 old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; 669 old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; 670 old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK; 671 672 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv 673 || old_afc != rate->afc); 674 } 675 676 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate, 677 unsigned long prate) 678 { 679 struct samsung_clk_pll *pll = to_clk_pll(hw); 680 const struct samsung_pll_rate_table *rate; 681 u32 con0, con1; 682 683 /* Get required rate settings from table */ 684 rate = samsung_get_pll_settings(pll, drate); 685 if (!rate) { 686 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 687 drate, clk_hw_get_name(hw)); 688 return -EINVAL; 689 } 690 691 con0 = readl_relaxed(pll->con_reg); 692 con1 = readl_relaxed(pll->con_reg + 0x4); 693 694 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { 695 /* If only s change, change just s value only*/ 696 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT); 697 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT; 698 writel_relaxed(con0, pll->con_reg); 699 700 return 0; 701 } 702 703 /* Set PLL PMS values. */ 704 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) | 705 (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) | 706 (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT)); 707 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) | 708 (rate->pdiv << PLL45XX_PDIV_SHIFT) | 709 (rate->sdiv << PLL45XX_SDIV_SHIFT); 710 711 /* Set PLL AFC value. */ 712 con1 = readl_relaxed(pll->con_reg + 0x4); 713 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); 714 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); 715 716 /* Set PLL lock time. */ 717 switch (pll->type) { 718 case pll_4502: 719 writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); 720 break; 721 case pll_4508: 722 writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); 723 break; 724 default: 725 break; 726 } 727 728 /* Set new configuration. */ 729 writel_relaxed(con1, pll->con_reg + 0x4); 730 writel_relaxed(con0, pll->con_reg); 731 732 /* Wait for PLL lock */ 733 return samsung_pll_lock_wait(pll, PLL45XX_LOCKED); 734 } 735 736 static const struct clk_ops samsung_pll45xx_clk_ops = { 737 .recalc_rate = samsung_pll45xx_recalc_rate, 738 .round_rate = samsung_pll_round_rate, 739 .set_rate = samsung_pll45xx_set_rate, 740 }; 741 742 static const struct clk_ops samsung_pll45xx_clk_min_ops = { 743 .recalc_rate = samsung_pll45xx_recalc_rate, 744 }; 745 746 /* 747 * PLL46xx Clock Type 748 */ 749 #define PLL46XX_LOCK_FACTOR 3000 750 751 #define PLL46XX_VSEL_MASK (1) 752 #define PLL46XX_MDIV_MASK (0x1FF) 753 #define PLL1460X_MDIV_MASK (0x3FF) 754 755 #define PLL46XX_PDIV_MASK (0x3F) 756 #define PLL46XX_SDIV_MASK (0x7) 757 #define PLL46XX_VSEL_SHIFT (27) 758 #define PLL46XX_MDIV_SHIFT (16) 759 #define PLL46XX_PDIV_SHIFT (8) 760 #define PLL46XX_SDIV_SHIFT (0) 761 762 #define PLL46XX_KDIV_MASK (0xFFFF) 763 #define PLL4650C_KDIV_MASK (0xFFF) 764 #define PLL46XX_KDIV_SHIFT (0) 765 #define PLL46XX_MFR_MASK (0x3F) 766 #define PLL46XX_MRR_MASK (0x1F) 767 #define PLL46XX_KDIV_SHIFT (0) 768 #define PLL46XX_MFR_SHIFT (16) 769 #define PLL46XX_MRR_SHIFT (24) 770 771 #define PLL46XX_ENABLE BIT(31) 772 #define PLL46XX_LOCKED BIT(29) 773 #define PLL46XX_VSEL BIT(27) 774 775 static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, 776 unsigned long parent_rate) 777 { 778 struct samsung_clk_pll *pll = to_clk_pll(hw); 779 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; 780 u64 fvco = parent_rate; 781 782 pll_con0 = readl_relaxed(pll->con_reg); 783 pll_con1 = readl_relaxed(pll->con_reg + 4); 784 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? 785 PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); 786 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; 787 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; 788 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : 789 pll_con1 & PLL46XX_KDIV_MASK; 790 791 shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; 792 793 fvco *= (mdiv << shift) + kdiv; 794 do_div(fvco, (pdiv << sdiv)); 795 fvco >>= shift; 796 797 return (unsigned long)fvco; 798 } 799 800 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, 801 const struct samsung_pll_rate_table *rate) 802 { 803 u32 old_mdiv, old_pdiv, old_kdiv; 804 805 old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; 806 old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; 807 old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK; 808 809 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv 810 || old_kdiv != rate->kdiv); 811 } 812 813 static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, 814 unsigned long prate) 815 { 816 struct samsung_clk_pll *pll = to_clk_pll(hw); 817 const struct samsung_pll_rate_table *rate; 818 u32 con0, con1, lock; 819 820 /* Get required rate settings from table */ 821 rate = samsung_get_pll_settings(pll, drate); 822 if (!rate) { 823 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 824 drate, clk_hw_get_name(hw)); 825 return -EINVAL; 826 } 827 828 con0 = readl_relaxed(pll->con_reg); 829 con1 = readl_relaxed(pll->con_reg + 0x4); 830 831 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { 832 /* If only s change, change just s value only*/ 833 con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); 834 con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; 835 writel_relaxed(con0, pll->con_reg); 836 837 return 0; 838 } 839 840 /* Set PLL lock time. */ 841 lock = rate->pdiv * PLL46XX_LOCK_FACTOR; 842 if (lock > 0xffff) 843 /* Maximum lock time bitfield is 16-bit. */ 844 lock = 0xffff; 845 846 /* Set PLL PMS and VSEL values. */ 847 if (pll->type == pll_1460x) { 848 con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | 849 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | 850 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); 851 } else { 852 con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | 853 (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | 854 (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | 855 (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); 856 con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; 857 } 858 859 con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | 860 (rate->pdiv << PLL46XX_PDIV_SHIFT) | 861 (rate->sdiv << PLL46XX_SDIV_SHIFT); 862 863 /* Set PLL K, MFR and MRR values. */ 864 con1 = readl_relaxed(pll->con_reg + 0x4); 865 con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | 866 (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | 867 (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); 868 con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) | 869 (rate->mfr << PLL46XX_MFR_SHIFT) | 870 (rate->mrr << PLL46XX_MRR_SHIFT); 871 872 /* Write configuration to PLL */ 873 writel_relaxed(lock, pll->lock_reg); 874 writel_relaxed(con0, pll->con_reg); 875 writel_relaxed(con1, pll->con_reg + 0x4); 876 877 /* Wait for PLL lock */ 878 return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); 879 } 880 881 static const struct clk_ops samsung_pll46xx_clk_ops = { 882 .recalc_rate = samsung_pll46xx_recalc_rate, 883 .round_rate = samsung_pll_round_rate, 884 .set_rate = samsung_pll46xx_set_rate, 885 }; 886 887 static const struct clk_ops samsung_pll46xx_clk_min_ops = { 888 .recalc_rate = samsung_pll46xx_recalc_rate, 889 }; 890 891 /* 892 * PLL6552 Clock Type 893 */ 894 895 #define PLL6552_MDIV_MASK 0x3ff 896 #define PLL6552_PDIV_MASK 0x3f 897 #define PLL6552_SDIV_MASK 0x7 898 #define PLL6552_MDIV_SHIFT 16 899 #define PLL6552_MDIV_SHIFT_2416 14 900 #define PLL6552_PDIV_SHIFT 8 901 #define PLL6552_PDIV_SHIFT_2416 5 902 #define PLL6552_SDIV_SHIFT 0 903 904 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw, 905 unsigned long parent_rate) 906 { 907 struct samsung_clk_pll *pll = to_clk_pll(hw); 908 u32 mdiv, pdiv, sdiv, pll_con; 909 u64 fvco = parent_rate; 910 911 pll_con = readl_relaxed(pll->con_reg); 912 if (pll->type == pll_6552_s3c2416) { 913 mdiv = (pll_con >> PLL6552_MDIV_SHIFT_2416) & PLL6552_MDIV_MASK; 914 pdiv = (pll_con >> PLL6552_PDIV_SHIFT_2416) & PLL6552_PDIV_MASK; 915 } else { 916 mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK; 917 pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK; 918 } 919 sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK; 920 921 fvco *= mdiv; 922 do_div(fvco, (pdiv << sdiv)); 923 924 return (unsigned long)fvco; 925 } 926 927 static const struct clk_ops samsung_pll6552_clk_ops = { 928 .recalc_rate = samsung_pll6552_recalc_rate, 929 }; 930 931 /* 932 * PLL6553 Clock Type 933 */ 934 935 #define PLL6553_MDIV_MASK 0xff 936 #define PLL6553_PDIV_MASK 0x3f 937 #define PLL6553_SDIV_MASK 0x7 938 #define PLL6553_KDIV_MASK 0xffff 939 #define PLL6553_MDIV_SHIFT 16 940 #define PLL6553_PDIV_SHIFT 8 941 #define PLL6553_SDIV_SHIFT 0 942 #define PLL6553_KDIV_SHIFT 0 943 944 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw, 945 unsigned long parent_rate) 946 { 947 struct samsung_clk_pll *pll = to_clk_pll(hw); 948 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; 949 u64 fvco = parent_rate; 950 951 pll_con0 = readl_relaxed(pll->con_reg); 952 pll_con1 = readl_relaxed(pll->con_reg + 0x4); 953 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; 954 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; 955 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; 956 kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK; 957 958 fvco *= (mdiv << 16) + kdiv; 959 do_div(fvco, (pdiv << sdiv)); 960 fvco >>= 16; 961 962 return (unsigned long)fvco; 963 } 964 965 static const struct clk_ops samsung_pll6553_clk_ops = { 966 .recalc_rate = samsung_pll6553_recalc_rate, 967 }; 968 969 /* 970 * PLL2550x Clock Type 971 */ 972 973 #define PLL2550X_R_MASK (0x1) 974 #define PLL2550X_P_MASK (0x3F) 975 #define PLL2550X_M_MASK (0x3FF) 976 #define PLL2550X_S_MASK (0x7) 977 #define PLL2550X_R_SHIFT (20) 978 #define PLL2550X_P_SHIFT (14) 979 #define PLL2550X_M_SHIFT (4) 980 #define PLL2550X_S_SHIFT (0) 981 982 static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw, 983 unsigned long parent_rate) 984 { 985 struct samsung_clk_pll *pll = to_clk_pll(hw); 986 u32 r, p, m, s, pll_stat; 987 u64 fvco = parent_rate; 988 989 pll_stat = readl_relaxed(pll->con_reg); 990 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK; 991 if (!r) 992 return 0; 993 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK; 994 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK; 995 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK; 996 997 fvco *= m; 998 do_div(fvco, (p << s)); 999 1000 return (unsigned long)fvco; 1001 } 1002 1003 static const struct clk_ops samsung_pll2550x_clk_ops = { 1004 .recalc_rate = samsung_pll2550x_recalc_rate, 1005 }; 1006 1007 /* 1008 * PLL2550xx Clock Type 1009 */ 1010 1011 /* Maximum lock time can be 270 * PDIV cycles */ 1012 #define PLL2550XX_LOCK_FACTOR 270 1013 1014 #define PLL2550XX_M_MASK 0x3FF 1015 #define PLL2550XX_P_MASK 0x3F 1016 #define PLL2550XX_S_MASK 0x7 1017 #define PLL2550XX_LOCK_STAT_MASK 0x1 1018 #define PLL2550XX_M_SHIFT 9 1019 #define PLL2550XX_P_SHIFT 3 1020 #define PLL2550XX_S_SHIFT 0 1021 #define PLL2550XX_LOCK_STAT_SHIFT 21 1022 1023 static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, 1024 unsigned long parent_rate) 1025 { 1026 struct samsung_clk_pll *pll = to_clk_pll(hw); 1027 u32 mdiv, pdiv, sdiv, pll_con; 1028 u64 fvco = parent_rate; 1029 1030 pll_con = readl_relaxed(pll->con_reg); 1031 mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; 1032 pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; 1033 sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; 1034 1035 fvco *= mdiv; 1036 do_div(fvco, (pdiv << sdiv)); 1037 1038 return (unsigned long)fvco; 1039 } 1040 1041 static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) 1042 { 1043 u32 old_mdiv, old_pdiv; 1044 1045 old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; 1046 old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; 1047 1048 return mdiv != old_mdiv || pdiv != old_pdiv; 1049 } 1050 1051 static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, 1052 unsigned long prate) 1053 { 1054 struct samsung_clk_pll *pll = to_clk_pll(hw); 1055 const struct samsung_pll_rate_table *rate; 1056 u32 tmp; 1057 1058 /* Get required rate settings from table */ 1059 rate = samsung_get_pll_settings(pll, drate); 1060 if (!rate) { 1061 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1062 drate, clk_hw_get_name(hw)); 1063 return -EINVAL; 1064 } 1065 1066 tmp = readl_relaxed(pll->con_reg); 1067 1068 if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { 1069 /* If only s change, change just s value only*/ 1070 tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); 1071 tmp |= rate->sdiv << PLL2550XX_S_SHIFT; 1072 writel_relaxed(tmp, pll->con_reg); 1073 1074 return 0; 1075 } 1076 1077 /* Set PLL lock time. */ 1078 writel_relaxed(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); 1079 1080 /* Change PLL PMS values */ 1081 tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | 1082 (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) | 1083 (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT)); 1084 tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | 1085 (rate->pdiv << PLL2550XX_P_SHIFT) | 1086 (rate->sdiv << PLL2550XX_S_SHIFT); 1087 writel_relaxed(tmp, pll->con_reg); 1088 1089 /* Wait for PLL lock */ 1090 return samsung_pll_lock_wait(pll, 1091 PLL2550XX_LOCK_STAT_MASK << PLL2550XX_LOCK_STAT_SHIFT); 1092 } 1093 1094 static const struct clk_ops samsung_pll2550xx_clk_ops = { 1095 .recalc_rate = samsung_pll2550xx_recalc_rate, 1096 .round_rate = samsung_pll_round_rate, 1097 .set_rate = samsung_pll2550xx_set_rate, 1098 }; 1099 1100 static const struct clk_ops samsung_pll2550xx_clk_min_ops = { 1101 .recalc_rate = samsung_pll2550xx_recalc_rate, 1102 }; 1103 1104 /* 1105 * PLL2650x Clock Type 1106 */ 1107 1108 /* Maximum lock time can be 3000 * PDIV cycles */ 1109 #define PLL2650X_LOCK_FACTOR 3000 1110 1111 #define PLL2650X_M_MASK 0x1ff 1112 #define PLL2650X_P_MASK 0x3f 1113 #define PLL2650X_S_MASK 0x7 1114 #define PLL2650X_K_MASK 0xffff 1115 #define PLL2650X_LOCK_STAT_MASK 0x1 1116 #define PLL2650X_M_SHIFT 16 1117 #define PLL2650X_P_SHIFT 8 1118 #define PLL2650X_S_SHIFT 0 1119 #define PLL2650X_K_SHIFT 0 1120 #define PLL2650X_LOCK_STAT_SHIFT 29 1121 #define PLL2650X_PLL_ENABLE_SHIFT 31 1122 1123 static unsigned long samsung_pll2650x_recalc_rate(struct clk_hw *hw, 1124 unsigned long parent_rate) 1125 { 1126 struct samsung_clk_pll *pll = to_clk_pll(hw); 1127 u64 fout = parent_rate; 1128 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; 1129 s16 kdiv; 1130 1131 pll_con0 = readl_relaxed(pll->con_reg); 1132 mdiv = (pll_con0 >> PLL2650X_M_SHIFT) & PLL2650X_M_MASK; 1133 pdiv = (pll_con0 >> PLL2650X_P_SHIFT) & PLL2650X_P_MASK; 1134 sdiv = (pll_con0 >> PLL2650X_S_SHIFT) & PLL2650X_S_MASK; 1135 1136 pll_con1 = readl_relaxed(pll->con_reg + 4); 1137 kdiv = (s16)((pll_con1 >> PLL2650X_K_SHIFT) & PLL2650X_K_MASK); 1138 1139 fout *= (mdiv << 16) + kdiv; 1140 do_div(fout, (pdiv << sdiv)); 1141 fout >>= 16; 1142 1143 return (unsigned long)fout; 1144 } 1145 1146 static int samsung_pll2650x_set_rate(struct clk_hw *hw, unsigned long drate, 1147 unsigned long prate) 1148 { 1149 struct samsung_clk_pll *pll = to_clk_pll(hw); 1150 const struct samsung_pll_rate_table *rate; 1151 u32 con0, con1; 1152 1153 /* Get required rate settings from table */ 1154 rate = samsung_get_pll_settings(pll, drate); 1155 if (!rate) { 1156 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1157 drate, clk_hw_get_name(hw)); 1158 return -EINVAL; 1159 } 1160 1161 con0 = readl_relaxed(pll->con_reg); 1162 con1 = readl_relaxed(pll->con_reg + 4); 1163 1164 /* Set PLL lock time. */ 1165 writel_relaxed(rate->pdiv * PLL2650X_LOCK_FACTOR, pll->lock_reg); 1166 1167 /* Change PLL PMS values */ 1168 con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) | 1169 (PLL2650X_P_MASK << PLL2650X_P_SHIFT) | 1170 (PLL2650X_S_MASK << PLL2650X_S_SHIFT)); 1171 con0 |= (rate->mdiv << PLL2650X_M_SHIFT) | 1172 (rate->pdiv << PLL2650X_P_SHIFT) | 1173 (rate->sdiv << PLL2650X_S_SHIFT); 1174 con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT); 1175 writel_relaxed(con0, pll->con_reg); 1176 1177 con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT); 1178 con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT); 1179 writel_relaxed(con1, pll->con_reg + 4); 1180 1181 /* Wait for PLL lock */ 1182 return samsung_pll_lock_wait(pll, 1183 PLL2650X_LOCK_STAT_MASK << PLL2650X_LOCK_STAT_SHIFT); 1184 } 1185 1186 static const struct clk_ops samsung_pll2650x_clk_ops = { 1187 .recalc_rate = samsung_pll2650x_recalc_rate, 1188 .round_rate = samsung_pll_round_rate, 1189 .set_rate = samsung_pll2650x_set_rate, 1190 }; 1191 1192 static const struct clk_ops samsung_pll2650x_clk_min_ops = { 1193 .recalc_rate = samsung_pll2650x_recalc_rate, 1194 }; 1195 1196 /* 1197 * PLL2650XX Clock Type 1198 */ 1199 1200 /* Maximum lock time can be 3000 * PDIV cycles */ 1201 #define PLL2650XX_LOCK_FACTOR 3000 1202 1203 #define PLL2650XX_MDIV_SHIFT 9 1204 #define PLL2650XX_PDIV_SHIFT 3 1205 #define PLL2650XX_SDIV_SHIFT 0 1206 #define PLL2650XX_KDIV_SHIFT 0 1207 #define PLL2650XX_MDIV_MASK 0x1ff 1208 #define PLL2650XX_PDIV_MASK 0x3f 1209 #define PLL2650XX_SDIV_MASK 0x7 1210 #define PLL2650XX_KDIV_MASK 0xffff 1211 #define PLL2650XX_PLL_ENABLE_SHIFT 23 1212 #define PLL2650XX_PLL_LOCKTIME_SHIFT 21 1213 #define PLL2650XX_PLL_FOUTMASK_SHIFT 31 1214 1215 static unsigned long samsung_pll2650xx_recalc_rate(struct clk_hw *hw, 1216 unsigned long parent_rate) 1217 { 1218 struct samsung_clk_pll *pll = to_clk_pll(hw); 1219 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; 1220 s16 kdiv; 1221 u64 fvco = parent_rate; 1222 1223 pll_con0 = readl_relaxed(pll->con_reg); 1224 pll_con2 = readl_relaxed(pll->con_reg + 8); 1225 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; 1226 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; 1227 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; 1228 kdiv = (s16)(pll_con2 & PLL2650XX_KDIV_MASK); 1229 1230 fvco *= (mdiv << 16) + kdiv; 1231 do_div(fvco, (pdiv << sdiv)); 1232 fvco >>= 16; 1233 1234 return (unsigned long)fvco; 1235 } 1236 1237 static int samsung_pll2650xx_set_rate(struct clk_hw *hw, unsigned long drate, 1238 unsigned long parent_rate) 1239 { 1240 struct samsung_clk_pll *pll = to_clk_pll(hw); 1241 u32 pll_con0, pll_con2; 1242 const struct samsung_pll_rate_table *rate; 1243 1244 rate = samsung_get_pll_settings(pll, drate); 1245 if (!rate) { 1246 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, 1247 drate, clk_hw_get_name(hw)); 1248 return -EINVAL; 1249 } 1250 1251 pll_con0 = readl_relaxed(pll->con_reg); 1252 pll_con2 = readl_relaxed(pll->con_reg + 8); 1253 1254 /* Change PLL PMS values */ 1255 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | 1256 PLL2650XX_PDIV_MASK << PLL2650XX_PDIV_SHIFT | 1257 PLL2650XX_SDIV_MASK << PLL2650XX_SDIV_SHIFT); 1258 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; 1259 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; 1260 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; 1261 pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; 1262 pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; 1263 1264 pll_con2 &= ~(PLL2650XX_KDIV_MASK << PLL2650XX_KDIV_SHIFT); 1265 pll_con2 |= ((~(rate->kdiv) + 1) & PLL2650XX_KDIV_MASK) 1266 << PLL2650XX_KDIV_SHIFT; 1267 1268 /* Set PLL lock time. */ 1269 writel_relaxed(PLL2650XX_LOCK_FACTOR * rate->pdiv, pll->lock_reg); 1270 1271 writel_relaxed(pll_con0, pll->con_reg); 1272 writel_relaxed(pll_con2, pll->con_reg + 8); 1273 1274 return samsung_pll_lock_wait(pll, 0x1 << PLL2650XX_PLL_LOCKTIME_SHIFT); 1275 } 1276 1277 static const struct clk_ops samsung_pll2650xx_clk_ops = { 1278 .recalc_rate = samsung_pll2650xx_recalc_rate, 1279 .set_rate = samsung_pll2650xx_set_rate, 1280 .round_rate = samsung_pll_round_rate, 1281 }; 1282 1283 static const struct clk_ops samsung_pll2650xx_clk_min_ops = { 1284 .recalc_rate = samsung_pll2650xx_recalc_rate, 1285 }; 1286 1287 /* 1288 * PLL531X Clock Type 1289 */ 1290 /* Maximum lock time can be 500 * PDIV cycles */ 1291 #define PLL531X_LOCK_FACTOR (500) 1292 #define PLL531X_MDIV_MASK (0x3FF) 1293 #define PLL531X_PDIV_MASK (0x3F) 1294 #define PLL531X_SDIV_MASK (0x7) 1295 #define PLL531X_FDIV_MASK (0xFFFFFFFF) 1296 #define PLL531X_MDIV_SHIFT (16) 1297 #define PLL531X_PDIV_SHIFT (8) 1298 #define PLL531X_SDIV_SHIFT (0) 1299 1300 static unsigned long samsung_pll531x_recalc_rate(struct clk_hw *hw, 1301 unsigned long parent_rate) 1302 { 1303 struct samsung_clk_pll *pll = to_clk_pll(hw); 1304 u32 pdiv, sdiv, fdiv, pll_con0, pll_con8; 1305 u64 mdiv, fout = parent_rate; 1306 1307 pll_con0 = readl_relaxed(pll->con_reg); 1308 pll_con8 = readl_relaxed(pll->con_reg + 20); 1309 mdiv = (pll_con0 >> PLL531X_MDIV_SHIFT) & PLL531X_MDIV_MASK; 1310 pdiv = (pll_con0 >> PLL531X_PDIV_SHIFT) & PLL531X_PDIV_MASK; 1311 sdiv = (pll_con0 >> PLL531X_SDIV_SHIFT) & PLL531X_SDIV_MASK; 1312 fdiv = (pll_con8 & PLL531X_FDIV_MASK); 1313 1314 if (fdiv >> 31) 1315 mdiv--; 1316 1317 fout *= (mdiv << 24) + (fdiv >> 8); 1318 do_div(fout, (pdiv << sdiv)); 1319 fout >>= 24; 1320 1321 return (unsigned long)fout; 1322 } 1323 1324 static const struct clk_ops samsung_pll531x_clk_ops = { 1325 .recalc_rate = samsung_pll531x_recalc_rate, 1326 }; 1327 1328 static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1329 const struct samsung_pll_clock *pll_clk) 1330 { 1331 struct samsung_clk_pll *pll; 1332 struct clk_init_data init; 1333 int ret, len; 1334 1335 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1336 if (!pll) { 1337 pr_err("%s: could not allocate pll clk %s\n", 1338 __func__, pll_clk->name); 1339 return; 1340 } 1341 1342 init.name = pll_clk->name; 1343 init.flags = pll_clk->flags; 1344 init.parent_names = &pll_clk->parent_name; 1345 init.num_parents = 1; 1346 1347 if (pll_clk->rate_table) { 1348 /* find count of rates in rate_table */ 1349 for (len = 0; pll_clk->rate_table[len].rate != 0; ) 1350 len++; 1351 1352 pll->rate_count = len; 1353 pll->rate_table = kmemdup_array(pll_clk->rate_table, 1354 pll->rate_count, 1355 sizeof(*pll->rate_table), 1356 GFP_KERNEL); 1357 WARN(!pll->rate_table, 1358 "%s: could not allocate rate table for %s\n", 1359 __func__, pll_clk->name); 1360 } 1361 1362 switch (pll_clk->type) { 1363 case pll_2126: 1364 init.ops = &samsung_pll2126_clk_ops; 1365 break; 1366 case pll_3000: 1367 init.ops = &samsung_pll3000_clk_ops; 1368 break; 1369 /* clk_ops for 35xx and 2550 are similar */ 1370 case pll_35xx: 1371 case pll_2550: 1372 case pll_1450x: 1373 case pll_1451x: 1374 case pll_1452x: 1375 case pll_142xx: 1376 pll->enable_offs = PLL35XX_ENABLE_SHIFT; 1377 pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; 1378 if (!pll->rate_table) 1379 init.ops = &samsung_pll35xx_clk_min_ops; 1380 else 1381 init.ops = &samsung_pll35xx_clk_ops; 1382 break; 1383 case pll_1417x: 1384 case pll_1418x: 1385 case pll_1051x: 1386 case pll_1052x: 1387 case pll_0818x: 1388 case pll_0822x: 1389 case pll_0516x: 1390 case pll_0517x: 1391 case pll_0518x: 1392 case pll_0717x: 1393 case pll_0718x: 1394 case pll_0732x: 1395 pll->enable_offs = PLL0822X_ENABLE_SHIFT; 1396 pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; 1397 if (!pll->rate_table) 1398 init.ops = &samsung_pll0822x_clk_min_ops; 1399 else 1400 init.ops = &samsung_pll0822x_clk_ops; 1401 break; 1402 case pll_4500: 1403 init.ops = &samsung_pll45xx_clk_min_ops; 1404 break; 1405 case pll_4502: 1406 case pll_4508: 1407 if (!pll->rate_table) 1408 init.ops = &samsung_pll45xx_clk_min_ops; 1409 else 1410 init.ops = &samsung_pll45xx_clk_ops; 1411 break; 1412 /* clk_ops for 36xx and 2650 are similar */ 1413 case pll_36xx: 1414 case pll_2650: 1415 pll->enable_offs = PLL36XX_ENABLE_SHIFT; 1416 pll->lock_offs = PLL36XX_LOCK_STAT_SHIFT; 1417 if (!pll->rate_table) 1418 init.ops = &samsung_pll36xx_clk_min_ops; 1419 else 1420 init.ops = &samsung_pll36xx_clk_ops; 1421 break; 1422 case pll_0831x: 1423 pll->enable_offs = PLL0831X_ENABLE_SHIFT; 1424 pll->lock_offs = PLL0831X_LOCK_STAT_SHIFT; 1425 if (!pll->rate_table) 1426 init.ops = &samsung_pll0831x_clk_min_ops; 1427 else 1428 init.ops = &samsung_pll0831x_clk_ops; 1429 break; 1430 case pll_6552: 1431 case pll_6552_s3c2416: 1432 init.ops = &samsung_pll6552_clk_ops; 1433 break; 1434 case pll_6553: 1435 init.ops = &samsung_pll6553_clk_ops; 1436 break; 1437 case pll_4600: 1438 case pll_4650: 1439 case pll_4650c: 1440 case pll_1460x: 1441 if (!pll->rate_table) 1442 init.ops = &samsung_pll46xx_clk_min_ops; 1443 else 1444 init.ops = &samsung_pll46xx_clk_ops; 1445 break; 1446 case pll_2550x: 1447 init.ops = &samsung_pll2550x_clk_ops; 1448 break; 1449 case pll_2550xx: 1450 if (!pll->rate_table) 1451 init.ops = &samsung_pll2550xx_clk_min_ops; 1452 else 1453 init.ops = &samsung_pll2550xx_clk_ops; 1454 break; 1455 case pll_2650x: 1456 if (!pll->rate_table) 1457 init.ops = &samsung_pll2650x_clk_min_ops; 1458 else 1459 init.ops = &samsung_pll2650x_clk_ops; 1460 break; 1461 case pll_2650xx: 1462 if (!pll->rate_table) 1463 init.ops = &samsung_pll2650xx_clk_min_ops; 1464 else 1465 init.ops = &samsung_pll2650xx_clk_ops; 1466 break; 1467 case pll_531x: 1468 init.ops = &samsung_pll531x_clk_ops; 1469 break; 1470 default: 1471 pr_warn("%s: Unknown pll type for pll clk %s\n", 1472 __func__, pll_clk->name); 1473 } 1474 1475 pll->hw.init = &init; 1476 pll->type = pll_clk->type; 1477 pll->lock_reg = ctx->reg_base + pll_clk->lock_offset; 1478 pll->con_reg = ctx->reg_base + pll_clk->con_offset; 1479 1480 ret = clk_hw_register(ctx->dev, &pll->hw); 1481 if (ret) { 1482 pr_err("%s: failed to register pll clock %s : %d\n", 1483 __func__, pll_clk->name, ret); 1484 kfree(pll->rate_table); 1485 kfree(pll); 1486 return; 1487 } 1488 1489 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); 1490 } 1491 1492 void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1493 const struct samsung_pll_clock *pll_list, 1494 unsigned int nr_pll) 1495 { 1496 int cnt; 1497 1498 for (cnt = 0; cnt < nr_pll; cnt++) 1499 _samsung_clk_register_pll(ctx, &pll_list[cnt]); 1500 } 1501