1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2023 Linaro Ltd. 4 * Author: Peter Griffin <peter.griffin@linaro.org> 5 * 6 * Common Clock Framework support for GS101. 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 14 #include <dt-bindings/clock/google,gs101.h> 15 16 #include "clk.h" 17 #include "clk-exynos-arm64.h" 18 #include "clk-pll.h" 19 20 /* NOTE: Must be equal to the last clock ID increased by one */ 21 #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) 22 #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) 23 #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_DPU_PCLK + 1) 24 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1) 25 #define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1) 26 #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) 27 #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) 28 #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) 29 30 #define GS101_GATE_DBG_OFFSET 0x4000 31 #define GS101_DRCG_EN_OFFSET 0x104 32 #define GS101_MEMCLK_OFFSET 0x108 33 34 /* ---- CMU_TOP ------------------------------------------------------------- */ 35 36 /* Register Offset definitions for CMU_TOP (0x1e080000) */ 37 #define PLL_LOCKTIME_PLL_SHARED0 0x0000 38 #define PLL_LOCKTIME_PLL_SHARED1 0x0004 39 #define PLL_LOCKTIME_PLL_SHARED2 0x0008 40 #define PLL_LOCKTIME_PLL_SHARED3 0x000c 41 #define PLL_LOCKTIME_PLL_SPARE 0x0010 42 #define PLL_CON0_PLL_SHARED0 0x0100 43 #define PLL_CON1_PLL_SHARED0 0x0104 44 #define PLL_CON2_PLL_SHARED0 0x0108 45 #define PLL_CON3_PLL_SHARED0 0x010c 46 #define PLL_CON4_PLL_SHARED0 0x0110 47 #define PLL_CON0_PLL_SHARED1 0x0140 48 #define PLL_CON1_PLL_SHARED1 0x0144 49 #define PLL_CON2_PLL_SHARED1 0x0148 50 #define PLL_CON3_PLL_SHARED1 0x014c 51 #define PLL_CON4_PLL_SHARED1 0x0150 52 #define PLL_CON0_PLL_SHARED2 0x0180 53 #define PLL_CON1_PLL_SHARED2 0x0184 54 #define PLL_CON2_PLL_SHARED2 0x0188 55 #define PLL_CON3_PLL_SHARED2 0x018c 56 #define PLL_CON4_PLL_SHARED2 0x0190 57 #define PLL_CON0_PLL_SHARED3 0x01c0 58 #define PLL_CON1_PLL_SHARED3 0x01c4 59 #define PLL_CON2_PLL_SHARED3 0x01c8 60 #define PLL_CON3_PLL_SHARED3 0x01cc 61 #define PLL_CON4_PLL_SHARED3 0x01d0 62 #define PLL_CON0_PLL_SPARE 0x0200 63 #define PLL_CON1_PLL_SPARE 0x0204 64 #define PLL_CON2_PLL_SPARE 0x0208 65 #define PLL_CON3_PLL_SPARE 0x020c 66 #define PLL_CON4_PLL_SPARE 0x0210 67 #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800 68 #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810 69 #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840 70 #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844 71 #define CMU_HCHGEN_CLKMUX 0x0850 72 #define POWER_FAIL_DETECT_PLL 0x0864 73 #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870 74 #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874 75 #define EARLY_WAKEUP_APM_CTRL 0x0878 76 #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c 77 #define EARLY_WAKEUP_DPU_CTRL 0x0880 78 #define EARLY_WAKEUP_CSIS_CTRL 0x0884 79 #define EARLY_WAKEUP_APM_DEST 0x0890 80 #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894 81 #define EARLY_WAKEUP_DPU_DEST 0x0898 82 #define EARLY_WAKEUP_CSIS_DEST 0x089c 83 #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0 84 #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4 85 #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8 86 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0 87 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4 88 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8 89 #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0 90 #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4 91 #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8 92 #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0 93 #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4 94 #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8 95 #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000 96 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004 97 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008 98 #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c 99 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010 100 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014 101 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018 102 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c 103 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020 104 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024 105 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028 106 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c 107 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030 108 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034 109 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038 110 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c 111 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040 112 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044 113 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048 114 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c 115 #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050 116 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054 117 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058 118 #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c 119 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060 120 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064 121 #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068 122 #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c 123 #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070 124 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074 125 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078 126 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c 127 #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080 128 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084 129 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088 130 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c 131 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090 132 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094 133 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098 134 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c 135 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0 136 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4 137 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8 138 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac 139 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0 140 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4 141 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8 142 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc 143 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0 144 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4 145 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8 146 #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc 147 #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0 148 #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4 149 #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8 150 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc 151 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0 152 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4 153 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8 154 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec 155 #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0 156 #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4 157 #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8 158 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc 159 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100 160 #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104 161 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108 162 #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800 163 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804 164 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808 165 #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c 166 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 167 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 168 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 169 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c 170 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820 171 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824 172 #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828 173 #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c 174 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830 175 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834 176 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838 177 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c 178 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840 179 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844 180 #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848 181 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c 182 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850 183 #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854 184 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858 185 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c 186 #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860 187 #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864 188 #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868 189 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c 190 #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870 191 #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874 192 #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878 193 #define CLK_CON_DIV_CLKCMU_HPM 0x187c 194 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880 195 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884 196 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888 197 #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c 198 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890 199 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894 200 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898 201 #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c 202 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0 203 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4 204 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8 205 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac 206 #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0 207 #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4 208 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8 209 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc 210 #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0 211 #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4 212 #define CLK_CON_DIV_CLKCMU_OTP 0x18c8 213 #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc 214 #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0 215 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4 216 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8 217 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc 218 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0 219 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4 220 #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8 221 #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec 222 #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0 223 #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4 224 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8 225 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc 226 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900 227 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904 228 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908 229 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c 230 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910 231 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914 232 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918 233 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c 234 #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920 235 #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000 236 #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004 237 #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008 238 #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c 239 #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010 240 #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014 241 #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018 242 #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c 243 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020 244 #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024 245 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028 246 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c 247 #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030 248 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034 249 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038 250 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c 251 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040 252 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044 253 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048 254 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c 255 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050 256 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054 257 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058 258 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c 259 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060 260 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064 261 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068 262 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c 263 #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070 264 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074 265 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078 266 #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c 267 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080 268 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084 269 #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088 270 #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c 271 #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090 272 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094 273 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098 274 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c 275 #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0 276 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4 277 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8 278 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac 279 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0 280 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4 281 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8 282 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc 283 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0 284 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4 285 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8 286 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc 287 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0 288 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4 289 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8 290 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc 291 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0 292 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4 293 #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8 294 #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec 295 #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0 296 #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4 297 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8 298 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc 299 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100 300 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104 301 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108 302 #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c 303 #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110 304 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114 305 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118 306 #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c 307 #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000 308 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004 309 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008 310 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c 311 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010 312 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014 313 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018 314 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c 315 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020 316 #define DMYQCH_CON_OTP_QCH 0x3024 317 #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00 318 #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10 319 #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14 320 #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18 321 #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c 322 #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20 323 #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24 324 #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28 325 #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c 326 #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00 327 #define MIFMIRROR_QUEUE_ENTRY0 0x3e10 328 #define MIFMIRROR_QUEUE_ENTRY1 0x3e14 329 #define MIFMIRROR_QUEUE_ENTRY2 0x3e18 330 #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c 331 #define MIFMIRROR_QUEUE_ENTRY4 0x3e20 332 #define MIFMIRROR_QUEUE_ENTRY5 0x3e24 333 #define MIFMIRROR_QUEUE_ENTRY6 0x3e28 334 #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c 335 #define MIFMIRROR_QUEUE_BUSY 0x3e30 336 #define GENERALIO_ACD_CHANNEL_0 0x3f00 337 #define GENERALIO_ACD_CHANNEL_1 0x3f04 338 #define GENERALIO_ACD_CHANNEL_2 0x3f08 339 #define GENERALIO_ACD_CHANNEL_3 0x3f0c 340 #define GENERALIO_ACD_MASK 0x3f14 341 342 static const unsigned long top_clk_regs[] __initconst = { 343 PLL_LOCKTIME_PLL_SHARED0, 344 PLL_LOCKTIME_PLL_SHARED1, 345 PLL_LOCKTIME_PLL_SHARED2, 346 PLL_LOCKTIME_PLL_SHARED3, 347 PLL_LOCKTIME_PLL_SPARE, 348 PLL_CON0_PLL_SHARED0, 349 PLL_CON1_PLL_SHARED0, 350 PLL_CON2_PLL_SHARED0, 351 PLL_CON3_PLL_SHARED0, 352 PLL_CON4_PLL_SHARED0, 353 PLL_CON0_PLL_SHARED1, 354 PLL_CON1_PLL_SHARED1, 355 PLL_CON2_PLL_SHARED1, 356 PLL_CON3_PLL_SHARED1, 357 PLL_CON4_PLL_SHARED1, 358 PLL_CON0_PLL_SHARED2, 359 PLL_CON1_PLL_SHARED2, 360 PLL_CON2_PLL_SHARED2, 361 PLL_CON3_PLL_SHARED2, 362 PLL_CON4_PLL_SHARED2, 363 PLL_CON0_PLL_SHARED3, 364 PLL_CON1_PLL_SHARED3, 365 PLL_CON2_PLL_SHARED3, 366 PLL_CON3_PLL_SHARED3, 367 PLL_CON4_PLL_SHARED3, 368 PLL_CON0_PLL_SPARE, 369 PLL_CON1_PLL_SPARE, 370 PLL_CON2_PLL_SPARE, 371 PLL_CON3_PLL_SPARE, 372 PLL_CON4_PLL_SPARE, 373 CMU_CMU_TOP_CONTROLLER_OPTION, 374 CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0, 375 CMU_HCHGEN_CLKMUX_CMU_BOOST, 376 CMU_HCHGEN_CLKMUX_TOP_BOOST, 377 CMU_HCHGEN_CLKMUX, 378 POWER_FAIL_DETECT_PLL, 379 EARLY_WAKEUP_FORCED_0_ENABLE, 380 EARLY_WAKEUP_FORCED_1_ENABLE, 381 EARLY_WAKEUP_APM_CTRL, 382 EARLY_WAKEUP_CLUSTER0_CTRL, 383 EARLY_WAKEUP_DPU_CTRL, 384 EARLY_WAKEUP_CSIS_CTRL, 385 EARLY_WAKEUP_APM_DEST, 386 EARLY_WAKEUP_CLUSTER0_DEST, 387 EARLY_WAKEUP_DPU_DEST, 388 EARLY_WAKEUP_CSIS_DEST, 389 EARLY_WAKEUP_SW_TRIG_APM, 390 EARLY_WAKEUP_SW_TRIG_CLUSTER0, 391 EARLY_WAKEUP_SW_TRIG_DPU, 392 EARLY_WAKEUP_SW_TRIG_CSIS, 393 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 394 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 395 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 396 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 397 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 398 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 399 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 400 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 401 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 402 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 403 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 404 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 405 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 406 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 407 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 408 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 409 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 410 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 411 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 412 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 413 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 414 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 415 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 416 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 417 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 418 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 419 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 420 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 421 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 422 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 423 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 424 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 425 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 426 CLK_CON_MUX_MUX_CLKCMU_HPM, 427 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 428 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 429 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 430 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 431 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 432 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 433 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 434 CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 435 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 436 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 437 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 438 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 439 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 440 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 441 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 442 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 443 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 444 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 445 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 446 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 447 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 448 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 449 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 450 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 451 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 452 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 453 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 454 CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 455 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 456 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 457 CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 458 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 459 CLK_CON_MUX_MUX_CMU_CMUREF, 460 CLK_CON_DIV_CLKCMU_BO_BUS, 461 CLK_CON_DIV_CLKCMU_BUS0_BUS, 462 CLK_CON_DIV_CLKCMU_BUS1_BUS, 463 CLK_CON_DIV_CLKCMU_BUS2_BUS, 464 CLK_CON_DIV_CLKCMU_CIS_CLK0, 465 CLK_CON_DIV_CLKCMU_CIS_CLK1, 466 CLK_CON_DIV_CLKCMU_CIS_CLK2, 467 CLK_CON_DIV_CLKCMU_CIS_CLK3, 468 CLK_CON_DIV_CLKCMU_CIS_CLK4, 469 CLK_CON_DIV_CLKCMU_CIS_CLK5, 470 CLK_CON_DIV_CLKCMU_CIS_CLK6, 471 CLK_CON_DIV_CLKCMU_CIS_CLK7, 472 CLK_CON_DIV_CLKCMU_CORE_BUS, 473 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 474 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 475 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 476 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 477 CLK_CON_DIV_CLKCMU_CSIS_BUS, 478 CLK_CON_DIV_CLKCMU_DISP_BUS, 479 CLK_CON_DIV_CLKCMU_DNS_BUS, 480 CLK_CON_DIV_CLKCMU_DPU_BUS, 481 CLK_CON_DIV_CLKCMU_EH_BUS, 482 CLK_CON_DIV_CLKCMU_G2D_G2D, 483 CLK_CON_DIV_CLKCMU_G2D_MSCL, 484 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 485 CLK_CON_DIV_CLKCMU_G3D_BUSD, 486 CLK_CON_DIV_CLKCMU_G3D_GLB, 487 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 488 CLK_CON_DIV_CLKCMU_GDC_GDC0, 489 CLK_CON_DIV_CLKCMU_GDC_GDC1, 490 CLK_CON_DIV_CLKCMU_GDC_SCSC, 491 CLK_CON_DIV_CLKCMU_HPM, 492 CLK_CON_DIV_CLKCMU_HSI0_BUS, 493 CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 494 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 495 CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 496 CLK_CON_DIV_CLKCMU_HSI1_BUS, 497 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 498 CLK_CON_DIV_CLKCMU_HSI2_BUS, 499 CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 500 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 501 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 502 CLK_CON_DIV_CLKCMU_IPP_BUS, 503 CLK_CON_DIV_CLKCMU_ITP_BUS, 504 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 505 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 506 CLK_CON_DIV_CLKCMU_MFC_MFC, 507 CLK_CON_DIV_CLKCMU_MIF_BUSP, 508 CLK_CON_DIV_CLKCMU_MISC_BUS, 509 CLK_CON_DIV_CLKCMU_MISC_SSS, 510 CLK_CON_DIV_CLKCMU_OTP, 511 CLK_CON_DIV_CLKCMU_PDP_BUS, 512 CLK_CON_DIV_CLKCMU_PDP_VRA, 513 CLK_CON_DIV_CLKCMU_PERIC0_BUS, 514 CLK_CON_DIV_CLKCMU_PERIC0_IP, 515 CLK_CON_DIV_CLKCMU_PERIC1_BUS, 516 CLK_CON_DIV_CLKCMU_PERIC1_IP, 517 CLK_CON_DIV_CLKCMU_TNR_BUS, 518 CLK_CON_DIV_CLKCMU_TPU_BUS, 519 CLK_CON_DIV_CLKCMU_TPU_TPU, 520 CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 521 CLK_CON_DIV_CLKCMU_TPU_UART, 522 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 523 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 524 CLK_CON_DIV_PLL_SHARED0_DIV2, 525 CLK_CON_DIV_PLL_SHARED0_DIV3, 526 CLK_CON_DIV_PLL_SHARED0_DIV4, 527 CLK_CON_DIV_PLL_SHARED0_DIV5, 528 CLK_CON_DIV_PLL_SHARED1_DIV2, 529 CLK_CON_DIV_PLL_SHARED1_DIV3, 530 CLK_CON_DIV_PLL_SHARED1_DIV4, 531 CLK_CON_DIV_PLL_SHARED2_DIV2, 532 CLK_CON_DIV_PLL_SHARED3_DIV2, 533 CLK_CON_GAT_CLKCMU_BUS0_BOOST, 534 CLK_CON_GAT_CLKCMU_BUS1_BOOST, 535 CLK_CON_GAT_CLKCMU_BUS2_BOOST, 536 CLK_CON_GAT_CLKCMU_CORE_BOOST, 537 CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 538 CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 539 CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 540 CLK_CON_GAT_CLKCMU_MIF_BOOST, 541 CLK_CON_GAT_CLKCMU_MIF_SWITCH, 542 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 543 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 544 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 545 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 546 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 547 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 548 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 549 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 550 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 551 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 552 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 553 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 554 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 555 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 556 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 557 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 558 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 559 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 560 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 561 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 562 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 563 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 564 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 565 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 566 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 567 CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, 568 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 569 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 570 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 571 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 572 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 573 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 574 CLK_CON_GAT_GATE_CLKCMU_HPM, 575 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 576 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 577 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 578 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 579 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 580 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 581 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 582 CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 583 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 584 CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 585 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 586 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 587 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 588 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 589 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 590 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 591 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 592 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 593 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 594 CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, 595 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 596 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 597 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 598 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 599 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 600 CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 601 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 602 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 603 CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 604 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 605 DMYQCH_CON_CMU_TOP_CMUREF_QCH, 606 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, 607 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, 608 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, 609 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, 610 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, 611 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, 612 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, 613 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, 614 DMYQCH_CON_OTP_QCH, 615 QUEUE_CTRL_REG_BLK_CMU_CMU_TOP, 616 QUEUE_ENTRY0_BLK_CMU_CMU_TOP, 617 QUEUE_ENTRY1_BLK_CMU_CMU_TOP, 618 QUEUE_ENTRY2_BLK_CMU_CMU_TOP, 619 QUEUE_ENTRY3_BLK_CMU_CMU_TOP, 620 QUEUE_ENTRY4_BLK_CMU_CMU_TOP, 621 QUEUE_ENTRY5_BLK_CMU_CMU_TOP, 622 QUEUE_ENTRY6_BLK_CMU_CMU_TOP, 623 QUEUE_ENTRY7_BLK_CMU_CMU_TOP, 624 MIFMIRROR_QUEUE_CTRL_REG, 625 MIFMIRROR_QUEUE_ENTRY0, 626 MIFMIRROR_QUEUE_ENTRY1, 627 MIFMIRROR_QUEUE_ENTRY2, 628 MIFMIRROR_QUEUE_ENTRY3, 629 MIFMIRROR_QUEUE_ENTRY4, 630 MIFMIRROR_QUEUE_ENTRY5, 631 MIFMIRROR_QUEUE_ENTRY6, 632 MIFMIRROR_QUEUE_ENTRY7, 633 MIFMIRROR_QUEUE_BUSY, 634 GENERALIO_ACD_CHANNEL_0, 635 GENERALIO_ACD_CHANNEL_1, 636 GENERALIO_ACD_CHANNEL_2, 637 GENERALIO_ACD_CHANNEL_3, 638 GENERALIO_ACD_MASK, 639 }; 640 641 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 642 /* CMU_TOP_PURECLKCOMP */ 643 PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 644 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 645 NULL), 646 PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 647 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 648 NULL), 649 PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", 650 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, 651 NULL), 652 PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", 653 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, 654 NULL), 655 PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk", 656 PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE, 657 NULL), 658 }; 659 660 /* List of parent clocks for Muxes in CMU_TOP */ 661 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" }; 662 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" }; 663 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" }; 664 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" }; 665 PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" }; 666 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 667 "fout_shared3_pll", "dout_cmu_shared1_div3", 668 "dout_cmu_shared0_div4", 669 "dout_cmu_shared1_div4", 670 "fout_spare_pll", "oscclk" }; 671 PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4", 672 "dout_cmu_shared1_div4", 673 "dout_cmu_shared2_div2", 674 "dout_cmu_shared3_div2", 675 "fout_spare_pll", "oscclk", 676 "oscclk", "oscclk" }; 677 PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 678 "dout_cmu_shared1_div3", 679 "dout_cmu_shared0_div4", 680 "dout_cmu_shared1_div4", 681 "dout_cmu_shared2_div2", 682 "fout_spare_pll", "oscclk" }; 683 PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2", 684 "dout_cmu_shared1_div2", 685 "fout_shared2_pll", "fout_shared3_pll", 686 "dout_cmu_shared0_div3", 687 "dout_cmu_shared1_div3", 688 "dout_cmu_shared0_div5", "fout_spare_pll" }; 689 PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3", 690 "dout_cmu_shared1_div3", 691 "dout_cmu_shared2_div2", 692 "dout_cmu_shared3_div2", "fout_spare_pll", 693 "oscclk", "oscclk" }; 694 PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4", 695 "dout_cmu_shared1_div4", 696 "dout_cmu_shared2_div2", 697 "dout_cmu_shared3_div2" }; 698 PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost", 699 "gout_cmu_boost_option1" }; 700 PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2", 701 "dout_cmu_shared1_div2", 702 "fout_shared2_pll", "fout_shared3_pll", 703 "dout_cmu_shared0_div3", 704 "dout_cmu_shared1_div3", 705 "dout_cmu_shared0_div5", "fout_spare_pll" }; 706 PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll", 707 "dout_cmu_shared0_div4", 708 "dout_cmu_shared1_div4", 709 "dout_cmu_shared2_div2", "fout_spare_pll", 710 "oscclk", "oscclk" }; 711 PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 712 "dout_cmu_shared1_div2", "fout_shared2_pll", 713 "fout_shared3_pll", "dout_cmu_shared0_div3", 714 "dout_cmu_shared1_div3", "fout_spare_pll" }; 715 PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 716 "dout_cmu_shared1_div2", "fout_shared2_pll", 717 "fout_shared3_pll", "dout_cmu_shared0_div3", 718 "dout_cmu_shared1_div3", "fout_spare_pll" }; 719 PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 720 "dout_cmu_shared1_div2", "fout_shared2_pll", 721 "fout_shared3_pll", "dout_cmu_shared0_div3", 722 "dout_cmu_shared1_div3", "fout_spare_pll" }; 723 PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 724 "dout_cmu_shared1_div3", 725 "dout_cmu_shared0_div4", 726 "dout_cmu_shared1_div4", 727 "dout_cmu_shared2_div2", 728 "fout_spare_pll", "oscclk" }; 729 PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 730 "dout_cmu_shared1_div3", 731 "dout_cmu_shared0_div4", 732 "dout_cmu_shared1_div4", 733 "dout_cmu_shared2_div2", 734 "fout_spare_pll", "oscclk" }; 735 PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 736 "dout_cmu_shared1_div3", 737 "dout_cmu_shared0_div4", 738 "dout_cmu_shared1_div4", 739 "dout_cmu_shared2_div2", 740 "fout_spare_pll", "oscclk" }; 741 PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3", 742 "fout_shared3_pll", 743 "dout_cmu_shared1_div3", 744 "dout_cmu_shared0_div4", 745 "dout_cmu_shared1_div4", 746 "dout_cmu_shared2_div2", 747 "fout_spare_pll", "oscclk" }; 748 PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2", 749 "dout_cmu_shared1_div2", 750 "fout_shared2_pll", "fout_shared3_pll", 751 "dout_cmu_shared0_div3", 752 "dout_cmu_shared1_div3", 753 "dout_cmu_shared0_div5", "fout_spare_pll" }; 754 PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 755 "dout_cmu_shared1_div3", 756 "dout_cmu_shared0_div4", 757 "dout_cmu_shared1_div4", 758 "dout_cmu_shared2_div2", 759 "fout_spare_pll", "oscclk" }; 760 PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4", 761 "dout_cmu_shared1_div4", 762 "dout_cmu_shared2_div2", 763 "dout_cmu_shared3_div2", 764 "fout_spare_pll", "oscclk", 765 "oscclk", "oscclk" }; 766 PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 767 "dout_cmu_shared1_div3", 768 "dout_cmu_shared0_div4", 769 "dout_cmu_shared1_div4", 770 "dout_cmu_shared2_div2", 771 "fout_spare_pll", "oscclk" }; 772 PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2", 773 "dout_cmu_shared1_div2", 774 "fout_shared2_pll", "fout_shared3_pll", 775 "dout_cmu_shared0_div3", 776 "dout_cmu_shared1_div3", 777 "dout_cmu_shared0_div4", "fout_spare_pll" }; 778 PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2", 779 "dout_cmu_shared1_div2", 780 "fout_shared2_pll", "fout_shared3_pll", 781 "dout_cmu_shared0_div3", 782 "dout_cmu_shared1_div3", 783 "dout_cmu_shared0_div4", "fout_spare_pll" }; 784 PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 785 "fout_shared3_pll", "dout_cmu_shared1_div3", 786 "dout_cmu_shared0_div4", 787 "dout_cmu_shared1_div4", 788 "fout_spare_pll", "fout_spare_pll"}; 789 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 790 "dout_cmu_shared1_div3", 791 "dout_cmu_shared0_div4", 792 "dout_cmu_shared1_div4", 793 "dout_cmu_shared2_div2", 794 "fout_spare_pll", "oscclk" }; 795 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 796 "dout_cmu_shared1_div3", 797 "dout_cmu_shared0_div4", 798 "dout_cmu_shared1_div4", 799 "dout_cmu_shared2_div2", 800 "fout_spare_pll", "oscclk" }; 801 PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 802 "dout_cmu_shared1_div3", 803 "dout_cmu_shared0_div4", 804 "dout_cmu_shared1_div4", 805 "dout_cmu_shared2_div2", 806 "fout_spare_pll", "oscclk" }; 807 PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3", 808 "dout_cmu_shared0_div4", 809 "dout_cmu_shared2_div2" }; 810 PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4", 811 "dout_cmu_shared1_div4", 812 "dout_cmu_shared2_div2", 813 "dout_cmu_shared3_div2", 814 "fout_spare_pll", "oscclk", 815 "oscclk", "oscclk" }; 816 PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4", 817 "dout_cmu_shared2_div2", "fout_spare_pll" }; 818 PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" }; 819 PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" }; 820 PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4", 821 "dout_cmu_shared1_div4", 822 "dout_cmu_shared2_div2", 823 "dout_cmu_shared3_div2", 824 "fout_spare_pll" }; 825 PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" }; 826 PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4", 827 "dout_cmu_shared1_div4", 828 "dout_cmu_shared2_div2", 829 "dout_cmu_shared3_div2", 830 "fout_spare_pll", "oscclk", 831 "oscclk", "oscclk" }; 832 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll", 833 "dout_cmu_shared0_div4", "fout_spare_pll" }; 834 PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" }; 835 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4", 836 "dout_cmu_shared2_div2", "fout_spare_pll" }; 837 PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 838 "dout_cmu_shared1_div3", 839 "dout_cmu_shared0_div4", 840 "dout_cmu_shared1_div4", 841 "dout_cmu_shared2_div2", 842 "fout_spare_pll", "oscclk" }; 843 PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 844 "dout_cmu_shared1_div3", 845 "dout_cmu_shared0_div4", 846 "dout_cmu_shared1_div4", 847 "dout_cmu_shared2_div2", 848 "fout_spare_pll", "oscclk" }; 849 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 850 "dout_cmu_shared1_div3", 851 "dout_cmu_shared0_div4", 852 "dout_cmu_shared1_div4", 853 "dout_cmu_shared2_div2", 854 "fout_spare_pll", "oscclk" }; 855 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 856 "dout_cmu_shared1_div3", 857 "dout_cmu_shared0_div4", 858 "dout_cmu_shared1_div4", 859 "dout_cmu_shared2_div2", 860 "fout_spare_pll", "oscclk" }; 861 PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 862 "dout_cmu_shared0_div4", 863 "dout_cmu_shared1_div4", 864 "dout_cmu_shared2_div2", "fout_spare_pll", 865 "oscclk", "oscclk" }; 866 PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4", 867 "dout_cmu_shared1_div4", 868 "dout_cmu_shared0_div5", "fout_spare_pll" }; 869 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", 870 "dout_cmu_shared0_div2", 871 "dout_cmu_shared1_div2", 872 "fout_shared2_pll", "dout_cmu_shared0_div3", 873 "fout_shared3_pll", "fout_spare_pll" }; 874 PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4", 875 "dout_cmu_shared2_div2", 876 "dout_cmu_shared3_div2", "fout_spare_pll" }; 877 PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4", 878 "dout_cmu_shared2_div2", 879 "dout_cmu_shared3_div2", "fout_spare_pll" }; 880 PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 881 "dout_cmu_shared1_div3", 882 "dout_cmu_shared0_div4", 883 "dout_cmu_shared1_div4", 884 "dout_cmu_shared2_div2", 885 "fout_spare_pll", "oscclk" }; 886 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 887 "fout_shared3_pll", "dout_cmu_shared1_div3", 888 "dout_cmu_shared0_div4", 889 "dout_cmu_shared1_div4", 890 "fout_spare_pll", "oscclk" }; 891 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4", 892 "dout_cmu_shared2_div2", 893 "dout_cmu_shared3_div2", "fout_spare_pll" }; 894 PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4", 895 "dout_cmu_shared2_div2", 896 "dout_cmu_shared3_div2", "fout_spare_pll" }; 897 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4", 898 "dout_cmu_shared2_div2", 899 "dout_cmu_shared3_div2", "fout_spare_pll" }; 900 PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4", 901 "dout_cmu_shared2_div2", 902 "dout_cmu_shared3_div2", "fout_spare_pll" }; 903 PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 904 "dout_cmu_shared1_div3", 905 "dout_cmu_shared0_div4", 906 "dout_cmu_shared1_div4", 907 "dout_cmu_shared2_div2", 908 "fout_spare_pll", "oscclk" }; 909 PNAME(mout_cmu_top_boost_option1_p) = { "oscclk", 910 "gout_cmu_boost_option1" }; 911 PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4", 912 "dout_cmu_shared1_div4", 913 "dout_cmu_shared2_div2", 914 "dout_cmu_shared3_div2" }; 915 PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2", 916 "dout_cmu_shared1_div2", 917 "fout_shared2_pll", 918 "fout_shared3_pll", 919 "dout_cmu_shared0_div3", 920 "dout_cmu_shared1_div3", 921 "dout_cmu_shared0_div4", 922 "fout_spare_pll" }; 923 PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2", 924 "dout_cmu_shared1_div2", 925 "fout_shared2_pll", 926 "fout_shared3_pll", 927 "dout_cmu_shared0_div3", 928 "dout_cmu_shared1_div3", 929 "dout_cmu_shared0_div4", "fout_spare_pll" }; 930 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2", 931 "dout_cmu_shared1_div2", 932 "fout_shared2_pll", "fout_shared3_pll", 933 "dout_cmu_shared0_div3", 934 "dout_cmu_shared1_div3", 935 "dout_cmu_shared0_div4", "fout_spare_pll" }; 936 PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4", 937 "dout_cmu_shared2_div2", 938 "dout_cmu_shared3_div2", "fout_spare_pll" }; 939 PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1", 940 "dout_cmu_cmuref" }; 941 942 /* 943 * Register name to clock name mangling strategy used in this file 944 * 945 * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll 946 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu 947 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 948 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 949 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu 950 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu 951 * 952 * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC 953 */ 954 955 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 956 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, 957 PLL_CON0_PLL_SHARED0, 4, 1), 958 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, 959 PLL_CON0_PLL_SHARED1, 4, 1), 960 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, 961 PLL_CON0_PLL_SHARED2, 4, 1), 962 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, 963 PLL_CON0_PLL_SHARED3, 4, 1), 964 MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p, 965 PLL_CON0_PLL_SPARE, 4, 1), 966 MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p, 967 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3), 968 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p, 969 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3), 970 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p, 971 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3), 972 MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p, 973 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3), 974 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p, 975 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3), 976 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p, 977 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3), 978 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p, 979 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3), 980 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p, 981 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3), 982 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p, 983 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3), 984 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p, 985 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3), 986 MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p, 987 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3), 988 MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p, 989 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3), 990 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p, 991 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), 992 MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1", 993 mout_cmu_cmu_boost_option1_p, 994 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1), 995 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, 996 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3), 997 MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", 998 mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3), 999 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", 1000 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 1001 0, 3), 1002 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", 1003 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 1004 0, 3), 1005 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", 1006 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 1007 0, 3), 1008 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p, 1009 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3), 1010 MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p, 1011 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3), 1012 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p, 1013 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3), 1014 MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p, 1015 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3), 1016 MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p, 1017 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3), 1018 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, 1019 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3), 1020 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, 1021 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3), 1022 MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p, 1023 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3), 1024 MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p, 1025 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3), 1026 MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p, 1027 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3), 1028 MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch", 1029 mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3), 1030 MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p, 1031 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3), 1032 MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p, 1033 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3), 1034 MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p, 1035 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3), 1036 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, 1037 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), 1038 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, 1039 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), 1040 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", 1041 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2), 1042 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", 1043 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 1044 0, 1), 1045 MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg", 1046 mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 1047 0, 1), 1048 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, 1049 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), 1050 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p, 1051 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1), 1052 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, 1053 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3), 1054 MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", 1055 mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 1056 0, 2), 1057 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p, 1058 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1), 1059 MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", 1060 mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 1061 0, 2), 1062 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p, 1063 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3), 1064 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p, 1065 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3), 1066 MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p, 1067 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3), 1068 MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, 1069 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3), 1070 MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, 1071 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3), 1072 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, 1073 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), 1074 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch", 1075 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), 1076 MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p, 1077 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2), 1078 MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p, 1079 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2), 1080 MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p, 1081 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3), 1082 MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p, 1083 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3), 1084 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus", 1085 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), 1086 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p, 1087 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), 1088 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus", 1089 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2), 1090 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p, 1091 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2), 1092 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p, 1093 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), 1094 MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1", 1095 mout_cmu_top_boost_option1_p, 1096 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1), 1097 MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref", 1098 mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2), 1099 MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p, 1100 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3), 1101 MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p, 1102 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3), 1103 MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", 1104 mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3), 1105 MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p, 1106 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2), 1107 MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p, 1108 CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), 1109 }; 1110 1111 static const struct samsung_div_clock top_div_clks[] __initconst = { 1112 DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", 1113 CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), 1114 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", 1115 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4), 1116 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus", 1117 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4), 1118 DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus", 1119 CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4), 1120 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0", 1121 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), 1122 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1", 1123 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), 1124 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2", 1125 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), 1126 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3", 1127 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), 1128 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4", 1129 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5), 1130 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5", 1131 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5), 1132 DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6", 1133 CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5), 1134 DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7", 1135 CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5), 1136 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", 1137 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 1138 DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", 1139 "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), 1140 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", 1141 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), 1142 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", 1143 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), 1144 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", 1145 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), 1146 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus", 1147 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4), 1148 DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus", 1149 CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4), 1150 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus", 1151 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4), 1152 DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus", 1153 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4), 1154 DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus", 1155 CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4), 1156 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", 1157 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), 1158 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", 1159 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), 1160 DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa", 1161 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4), 1162 DIV(CLK_DOUT_CMU_G3D_BUSD, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd", 1163 CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4), 1164 DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb", 1165 CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4), 1166 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch", 1167 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 1168 DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0", 1169 CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4), 1170 DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1", 1171 CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4), 1172 DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc", 1173 CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4), 1174 DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", 1175 CLK_CON_DIV_CLKCMU_HPM, 0, 2), 1176 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus", 1177 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4), 1178 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", 1179 "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4), 1180 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", 1181 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5), 1182 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", 1183 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4), 1184 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", 1185 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3), 1186 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", 1187 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), 1188 DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", 1189 "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9), 1190 DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", 1191 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3), 1192 DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", 1193 "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4), 1194 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", 1195 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), 1196 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", 1197 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4), 1198 DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc", 1199 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4), 1200 DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc", 1201 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4), 1202 DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", 1203 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), 1204 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", 1205 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), 1206 DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", 1207 CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), 1208 DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", 1209 CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), 1210 DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", 1211 CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), 1212 DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra", 1213 CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4), 1214 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", 1215 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), 1216 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip", 1217 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), 1218 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", 1219 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), 1220 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip", 1221 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), 1222 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus", 1223 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), 1224 DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus", 1225 CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4), 1226 DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu", 1227 CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4), 1228 DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", 1229 "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4), 1230 DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart", 1231 CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4), 1232 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost", 1233 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), 1234 DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref", 1235 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), 1236 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", 1237 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 1238 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", 1239 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 1240 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", 1241 "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 1242 DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5", 1243 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), 1244 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", 1245 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 1246 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", 1247 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 1248 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", 1249 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 1250 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", 1251 "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), 1252 DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2", 1253 "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), 1254 }; 1255 1256 static const struct samsung_fixed_factor_clock top_ffactor_clks[] __initconst = { 1257 FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg", 1258 "gout_cmu_hsi0_usbdpdbg", 1, 4, 0), 1259 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), 1260 }; 1261 1262 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 1263 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost", 1264 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), 1265 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost", 1266 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), 1267 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost", 1268 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), 1269 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost", 1270 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), 1271 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", 1272 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 1273 21, 0, 0), 1274 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", 1275 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 1276 21, 0, 0), 1277 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", 1278 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 1279 21, 0, 0), 1280 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost", 1281 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST, 1282 21, 0, 0), 1283 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch", 1284 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), 1285 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", 1286 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), 1287 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", 1288 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), 1289 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", 1290 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), 1291 GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", 1292 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), 1293 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", 1294 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), 1295 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", 1296 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), 1297 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", 1298 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), 1299 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", 1300 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), 1301 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", 1302 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0), 1303 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", 1304 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0), 1305 GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", 1306 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0), 1307 GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", 1308 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0), 1309 GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", 1310 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), 1311 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", 1312 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 1313 GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", 1314 "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 1315 21, 0, 0), 1316 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", 1317 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 1318 21, 0, 0), 1319 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", 1320 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 1321 21, 0, 0), 1322 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", 1323 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 1324 21, 0, 0), 1325 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", 1326 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), 1327 GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", 1328 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), 1329 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", 1330 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), 1331 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", 1332 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), 1333 GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", 1334 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), 1335 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", 1336 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), 1337 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", 1338 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), 1339 GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", 1340 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), 1341 GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", 1342 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), 1343 GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", 1344 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), 1345 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch", 1346 "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 1347 21, 0, 0), 1348 GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", 1349 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), 1350 GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", 1351 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), 1352 GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", 1353 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), 1354 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", 1355 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), 1356 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", 1357 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), 1358 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", 1359 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 1360 21, 0, 0), 1361 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", 1362 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 1363 21, 0, 0), 1364 GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg", 1365 "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 1366 21, 0, 0), 1367 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", 1368 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), 1369 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", 1370 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), 1371 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", 1372 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), 1373 GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", 1374 "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 1375 21, 0, 0), 1376 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", 1377 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), 1378 GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", 1379 "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 1380 21, 0, 0), 1381 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", 1382 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), 1383 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", 1384 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), 1385 GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", 1386 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), 1387 GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", 1388 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), 1389 GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", 1390 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), 1391 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", 1392 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), 1393 GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", 1394 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), 1395 GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", 1396 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), 1397 GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", 1398 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 1399 GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", 1400 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 1401 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus", 1402 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 1403 21, 0, 0), 1404 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", 1405 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), 1406 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus", 1407 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 1408 21, 0, 0), 1409 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", 1410 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), 1411 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", 1412 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), 1413 GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref", 1414 "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 1415 21, 0, 0), 1416 GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", 1417 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), 1418 GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", 1419 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), 1420 GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", 1421 "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 1422 21, 0, 0), 1423 GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", 1424 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), 1425 }; 1426 1427 static const struct samsung_cmu_info top_cmu_info __initconst = { 1428 .pll_clks = top_pll_clks, 1429 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 1430 .mux_clks = top_mux_clks, 1431 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 1432 .div_clks = top_div_clks, 1433 .nr_div_clks = ARRAY_SIZE(top_div_clks), 1434 .fixed_factor_clks = top_ffactor_clks, 1435 .nr_fixed_factor_clks = ARRAY_SIZE(top_ffactor_clks), 1436 .gate_clks = top_gate_clks, 1437 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 1438 .nr_clk_ids = CLKS_NR_TOP, 1439 .clk_regs = top_clk_regs, 1440 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 1441 .auto_clock_gate = true, 1442 .gate_dbg_offset = GS101_GATE_DBG_OFFSET, 1443 .option_offset = CMU_CMU_TOP_CONTROLLER_OPTION, 1444 }; 1445 1446 static void __init gs101_cmu_top_init(struct device_node *np) 1447 { 1448 exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 1449 } 1450 1451 /* Register CMU_TOP early, as it's a dependency for other early domains */ 1452 CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", 1453 gs101_cmu_top_init); 1454 1455 /* ---- CMU_APM ------------------------------------------------------------- */ 1456 1457 /* Register Offset definitions for CMU_APM (0x17400000) */ 1458 #define APM_CMU_APM_CONTROLLER_OPTION 0x0800 1459 #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 1460 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 1461 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 1462 #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 1463 #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 1464 #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 1465 #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c 1466 #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 1467 #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 1468 #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 1469 #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c 1470 #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 1471 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 1472 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 1473 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c 1474 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 1475 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 1476 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 1477 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c 1478 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 1479 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 1480 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 1481 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c 1482 #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 1483 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 1484 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 1485 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c 1486 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 1487 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 1488 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 1489 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c 1490 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 1491 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 1492 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 1493 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c 1494 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 1495 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 1496 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c 1497 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 1498 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 1499 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 1500 #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c 1501 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 1502 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 1503 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 1504 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c 1505 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 1506 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 1507 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 1508 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac 1509 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 1510 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 1511 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 1512 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc 1513 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 1514 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 1515 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc 1516 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 1517 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 1518 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 1519 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc 1520 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 1521 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 1522 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 1523 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec 1524 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 1525 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 1526 #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 1527 #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc 1528 #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 1529 #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 1530 #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 1531 #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c 1532 #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 1533 #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 1534 #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 1535 #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c 1536 #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 1537 #define QCH_CON_APBIF_RTC_QCH 0x3024 1538 #define QCH_CON_APBIF_TRTC_QCH 0x3028 1539 #define QCH_CON_APM_CMU_APM_QCH 0x302c 1540 #define QCH_CON_APM_USI0_UART_QCH 0x3030 1541 #define QCH_CON_APM_USI0_USI_QCH 0x3034 1542 #define QCH_CON_APM_USI1_UART_QCH 0x3038 1543 #define QCH_CON_D_TZPC_APM_QCH 0x303c 1544 #define QCH_CON_GPC_APM_QCH 0x3040 1545 #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 1546 #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 1547 #define QCH_CON_INTMEM_QCH 0x304c 1548 #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 1549 #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 1550 #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 1551 #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c 1552 #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 1553 #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 1554 #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 1555 #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c 1556 #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 1557 #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 1558 #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c 1559 #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 1560 #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 1561 #define QCH_CON_PMU_INTR_GEN_QCH 0x3088 1562 #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c 1563 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 1564 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 1565 #define QCH_CON_SPEEDY_APM_QCH 0x3098 1566 #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c 1567 #define QCH_CON_SSMT_D_APM_QCH 0x30a0 1568 #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 1569 #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 1570 #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac 1571 #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 1572 #define QCH_CON_SYSREG_APM_QCH 0x30b8 1573 #define QCH_CON_UASC_APM_QCH 0x30bc 1574 #define QCH_CON_UASC_DBGCORE_QCH 0x30c0 1575 #define QCH_CON_UASC_G_SWD_QCH 0x30c4 1576 #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 1577 #define QCH_CON_UASC_P_APM_QCH 0x30cc 1578 #define QCH_CON_WDT_APM_QCH 0x30d0 1579 #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 1580 1581 static const unsigned long apm_clk_regs[] __initconst = { 1582 APM_CMU_APM_CONTROLLER_OPTION, 1583 CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, 1584 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 1585 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 1586 CLK_CON_DIV_DIV_CLK_APM_BOOST, 1587 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 1588 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 1589 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 1590 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 1591 CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 1592 CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 1593 CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 1594 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 1595 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 1596 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 1597 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 1598 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 1599 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 1600 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 1601 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 1602 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 1603 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 1604 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 1605 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 1606 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 1607 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 1608 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 1609 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 1610 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 1611 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 1612 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 1613 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, 1614 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1615 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 1616 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 1617 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 1618 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 1619 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 1620 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 1621 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 1622 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 1623 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 1624 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 1625 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 1626 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 1627 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 1628 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1629 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, 1630 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 1631 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 1632 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 1633 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 1634 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 1635 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 1636 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 1637 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 1638 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 1639 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 1640 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 1641 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 1642 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 1643 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 1644 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 1645 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 1646 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 1647 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, 1648 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 1649 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 1650 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 1651 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 1652 }; 1653 1654 PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc", 1655 "pad_clk_apm", "oscclk" }; 1656 PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", 1657 "pll_alv_div16_apm" }; 1658 1659 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 1660 FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000), 1661 FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000), 1662 FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000), 1663 }; 1664 1665 static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 1666 MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, 1667 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), 1668 MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, 1669 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), 1670 }; 1671 1672 static const struct samsung_div_clock apm_div_clks[] __initconst = { 1673 DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", 1674 CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), 1675 DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", 1676 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), 1677 DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", 1678 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), 1679 DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", 1680 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), 1681 }; 1682 1683 static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 1684 GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK, 1685 "gout_apm_apm_cmu_apm_pclk", "mout_apm_func", 1686 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0), 1687 GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1", 1688 "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0), 1689 GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1", 1690 "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0), 1691 GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1", 1692 "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0), 1693 GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", 1694 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), 1695 GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 1696 "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func", 1697 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 1698 21, 0, 0), 1699 GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK, 1700 "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func", 1701 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 1702 21, 0, 0), 1703 GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 1704 "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func", 1705 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 1706 21, 0, 0), 1707 GATE(CLK_GOUT_APM_APBIF_RTC_PCLK, 1708 "gout_apm_apbif_rtc_pclk", "gout_apm_func", 1709 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0), 1710 GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK, 1711 "gout_apm_apbif_trtc_pclk", "gout_apm_func", 1712 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0), 1713 GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK, 1714 "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart", 1715 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 1716 21, 0, 0), 1717 GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK, 1718 "gout_apm_apm_usi0_uart_pclk", "gout_apm_func", 1719 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 1720 21, 0, 0), 1721 GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK, 1722 "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi", 1723 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 1724 21, 0, 0), 1725 GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK, 1726 "gout_apm_apm_usi0_usi_pclk", "gout_apm_func", 1727 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 1728 21, 0, 0), 1729 GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK, 1730 "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart", 1731 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 1732 21, 0, 0), 1733 GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK, 1734 "gout_apm_apm_usi1_uart_pclk", "gout_apm_func", 1735 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 1736 21, 0, 0), 1737 GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK, 1738 "gout_apm_d_tzpc_apm_pclk", "gout_apm_func", 1739 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1740 GATE(CLK_GOUT_APM_GPC_APM_PCLK, 1741 "gout_apm_gpc_apm_pclk", "gout_apm_func", 1742 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1743 GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK, 1744 "gout_apm_grebeintegration_hclk", "gout_apm_func", 1745 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 1746 21, 0, 0), 1747 GATE(CLK_GOUT_APM_INTMEM_ACLK, 1748 "gout_apm_intmem_aclk", "gout_apm_func", 1749 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0), 1750 GATE(CLK_GOUT_APM_INTMEM_PCLK, 1751 "gout_apm_intmem_pclk", "gout_apm_func", 1752 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0), 1753 GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK, 1754 "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func", 1755 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 1756 21, 0, 0), 1757 GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK, 1758 "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func", 1759 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 1760 21, 0, 0), 1761 GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK, 1762 "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func", 1763 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1764 21, 0, 0), 1765 GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK, 1766 "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func", 1767 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1768 21, 0, 0), 1769 GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK, 1770 "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func", 1771 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 1772 21, 0, 0), 1773 GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK, 1774 "gout_apm_lhs_axi_g_scan2dram_i_clk", 1775 "gout_apm_func", 1776 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 1777 21, 0, 0), 1778 GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK, 1779 "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func", 1780 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 1781 21, 0, 0), 1782 GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK, 1783 "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func", 1784 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 1785 21, 0, 0), 1786 GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK, 1787 "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func", 1788 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 1789 21, 0, 0), 1790 GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK, 1791 "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func", 1792 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 1793 21, 0, 0), 1794 GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK, 1795 "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func", 1796 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 1797 21, 0, 0), 1798 GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK, 1799 "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func", 1800 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 1801 21, 0, 0), 1802 GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK, 1803 "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func", 1804 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 1805 21, 0, 0), 1806 GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK, 1807 "gout_apm_pmu_intr_gen_pclk", "gout_apm_func", 1808 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 1809 21, 0, 0), 1810 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK, 1811 "gout_apm_rom_crc32_host_aclk", "gout_apm_func", 1812 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 1813 21, 0, 0), 1814 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK, 1815 "gout_apm_rom_crc32_host_pclk", "gout_apm_func", 1816 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 1817 21, 0, 0), 1818 GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK, 1819 "gout_apm_clk_apm_bus_clk", "gout_apm_func", 1820 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 1821 21, 0, 0), 1822 GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK, 1823 "gout_apm_clk_apm_usi0_uart_clk", 1824 "dout_apm_usi0_uart", 1825 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1826 21, 0, 0), 1827 GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK, 1828 "gout_apm_clk_apm_usi0_usi_clk", 1829 "dout_apm_usi0_usi", 1830 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1831 21, 0, 0), 1832 GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK, 1833 "gout_apm_clk_apm_usi1_uart_clk", 1834 "dout_apm_usi1_uart", 1835 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 1836 21, 0, 0), 1837 GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK, 1838 "gout_apm_speedy_apm_pclk", "gout_apm_func", 1839 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0), 1840 GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK, 1841 "gout_apm_speedy_sub_apm_pclk", "gout_apm_func", 1842 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 1843 21, 0, 0), 1844 GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK, 1845 "gout_apm_ssmt_d_apm_aclk", "gout_apm_func", 1846 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0), 1847 GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK, 1848 "gout_apm_ssmt_d_apm_pclk", "gout_apm_func", 1849 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0), 1850 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK, 1851 "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func", 1852 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 1853 21, 0, 0), 1854 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK, 1855 "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func", 1856 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 1857 21, 0, 0), 1858 GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK, 1859 "gout_apm_ss_dbgcore_ss_dbgcore_hclk", 1860 "gout_apm_func", 1861 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 1862 21, 0, 0), 1863 GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2, 1864 "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func", 1865 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 1866 21, 0, 0), 1867 GATE(CLK_GOUT_APM_SYSREG_APM_PCLK, 1868 "gout_apm_sysreg_apm_pclk", "gout_apm_func", 1869 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0), 1870 GATE(CLK_GOUT_APM_UASC_APM_ACLK, 1871 "gout_apm_uasc_apm_aclk", "gout_apm_func", 1872 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0), 1873 GATE(CLK_GOUT_APM_UASC_APM_PCLK, 1874 "gout_apm_uasc_apm_pclk", "gout_apm_func", 1875 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1876 GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK, 1877 "gout_apm_uasc_dbgcore_aclk", "gout_apm_func", 1878 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 1879 21, 0, 0), 1880 GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK, 1881 "gout_apm_uasc_dbgcore_pclk", "gout_apm_func", 1882 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 1883 21, 0, 0), 1884 GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK, 1885 "gout_apm_uasc_g_swd_aclk", "gout_apm_func", 1886 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0), 1887 GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK, 1888 "gout_apm_uasc_g_swd_pclk", "gout_apm_func", 1889 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 1890 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK, 1891 "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func", 1892 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 1893 21, 0, 0), 1894 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK, 1895 "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func", 1896 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 1897 GATE(CLK_GOUT_APM_UASC_P_APM_ACLK, 1898 "gout_apm_uasc_p_apm_aclk", "gout_apm_func", 1899 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0), 1900 GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, 1901 "gout_apm_uasc_p_apm_pclk", "gout_apm_func", 1902 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_CRITICAL, 0), 1903 GATE(CLK_GOUT_APM_WDT_APM_PCLK, 1904 "gout_apm_wdt_apm_pclk", "gout_apm_func", 1905 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), 1906 GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, 1907 "gout_apm_xiu_dp_apm_aclk", "gout_apm_func", 1908 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0), 1909 }; 1910 1911 static const unsigned long dcrg_memclk_sysreg[] __initconst = { 1912 GS101_DRCG_EN_OFFSET, 1913 GS101_MEMCLK_OFFSET, 1914 }; 1915 1916 static const struct samsung_cmu_info apm_cmu_info __initconst = { 1917 .mux_clks = apm_mux_clks, 1918 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 1919 .div_clks = apm_div_clks, 1920 .nr_div_clks = ARRAY_SIZE(apm_div_clks), 1921 .gate_clks = apm_gate_clks, 1922 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 1923 .fixed_clks = apm_fixed_clks, 1924 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 1925 .nr_clk_ids = CLKS_NR_APM, 1926 .clk_regs = apm_clk_regs, 1927 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 1928 .sysreg_clk_regs = dcrg_memclk_sysreg, 1929 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), 1930 .auto_clock_gate = true, 1931 .gate_dbg_offset = GS101_GATE_DBG_OFFSET, 1932 .drcg_offset = GS101_DRCG_EN_OFFSET, 1933 .memclk_offset = GS101_MEMCLK_OFFSET, 1934 }; 1935 1936 /* ---- CMU_DPU ------------------------------------------------------------- */ 1937 1938 /* Register Offset definitions for CMU_DPU (0x1c000000) */ 1939 #define PLL_CON0_MUX_CLKCMU_DPU_BUS_USER 0x0600 1940 #define PLL_CON1_MUX_CLKCMU_DPU_BUS_USER 0x0604 1941 #define DPU_CMU_DPU_CONTROLLER_OPTION 0x0800 1942 #define CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0 0x0810 1943 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800 1944 #define CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK 0x2000 1945 #define CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK 0x2004 1946 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM 0x2008 1947 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA 0x200c 1948 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP 0x2010 1949 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK 0x2014 1950 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK 0x2018 1951 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK 0x201c 1952 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK 0x2020 1953 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK 0x2024 1954 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK 0x2028 1955 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK 0x202c 1956 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK 0x2030 1957 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK 0x2034 1958 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK 0x2038 1959 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK 0x203c 1960 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK 0x2040 1961 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK 0x2044 1962 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK 0x2048 1963 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK 0x204c 1964 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK 0x2050 1965 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK 0x2054 1966 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK 0x2058 1967 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK 0x205c 1968 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK 0x2060 1969 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1 0x2064 1970 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2 0x2068 1971 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1 0x206c 1972 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2 0x2070 1973 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1 0x2074 1974 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2 0x2078 1975 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK 0x207c 1976 #define PCH_CON_LHM_AXI_P_DPU_PCH 0x3000 1977 #define PCH_CON_LHS_AXI_D0_DPU_PCH 0x3004 1978 #define PCH_CON_LHS_AXI_D1_DPU_PCH 0x3008 1979 #define PCH_CON_LHS_AXI_D2_DPU_PCH 0x300c 1980 #define QCH_CON_DPUF_QCH_DPU_DMA 0x3010 1981 #define QCH_CON_DPUF_QCH_DPU_DPP 0x3014 1982 #define QCH_CON_DPU_CMU_DPU_QCH 0x301c 1983 #define QCH_CON_D_TZPC_DPU_QCH 0x3020 1984 #define QCH_CON_GPC_DPU_QCH 0x3024 1985 #define QCH_CON_LHM_AXI_P_DPU_QCH 0x3028 1986 #define QCH_CON_LHS_AXI_D0_DPU_QCH 0x302c 1987 #define QCH_CON_LHS_AXI_D1_DPU_QCH 0x3030 1988 #define QCH_CON_LHS_AXI_D2_DPU_QCH 0x3034 1989 #define QCH_CON_PPMU_DPUD0_QCH 0x3038 1990 #define QCH_CON_PPMU_DPUD1_QCH 0x303c 1991 #define QCH_CON_PPMU_DPUD2_QCH 0x3040 1992 #define QCH_CON_SSMT_DPU0_QCH 0x3044 1993 #define QCH_CON_SSMT_DPU1_QCH 0x3048 1994 #define QCH_CON_SSMT_DPU2_QCH 0x304c 1995 #define QCH_CON_SYSMMU_DPUD0_QCH_S1 0x3050 1996 #define QCH_CON_SYSMMU_DPUD0_QCH_S2 0x3054 1997 #define QCH_CON_SYSMMU_DPUD1_QCH_S1 0x3058 1998 #define QCH_CON_SYSMMU_DPUD1_QCH_S2 0x305c 1999 #define QCH_CON_SYSMMU_DPUD2_QCH_S1 0x3060 2000 #define QCH_CON_SYSMMU_DPUD2_QCH_S2 0x3064 2001 #define QCH_CON_SYSREG_DPU_QCH 0x3068 2002 #define QUEUE_CTRL_REG_BLK_DPU_CMU_DPU 0x3c00 2003 2004 static const unsigned long dpu_clk_regs[] __initconst = { 2005 PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 2006 PLL_CON1_MUX_CLKCMU_DPU_BUS_USER, 2007 DPU_CMU_DPU_CONTROLLER_OPTION, 2008 CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0, 2009 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 2010 CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 2011 CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, 2012 CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, 2013 CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, 2014 CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, 2015 CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, 2016 CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, 2017 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK, 2018 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK, 2019 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK, 2020 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK, 2021 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, 2022 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, 2023 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, 2024 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, 2025 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, 2026 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, 2027 CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK, 2028 CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, 2029 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, 2030 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, 2031 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, 2032 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, 2033 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, 2034 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, 2035 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, 2036 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, 2037 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, 2038 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, 2039 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, 2040 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, 2041 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 2042 PCH_CON_LHM_AXI_P_DPU_PCH, 2043 PCH_CON_LHS_AXI_D0_DPU_PCH, 2044 PCH_CON_LHS_AXI_D1_DPU_PCH, 2045 PCH_CON_LHS_AXI_D2_DPU_PCH, 2046 QCH_CON_DPUF_QCH_DPU_DMA, 2047 QCH_CON_DPUF_QCH_DPU_DPP, 2048 QCH_CON_DPU_CMU_DPU_QCH, 2049 QCH_CON_D_TZPC_DPU_QCH, 2050 QCH_CON_GPC_DPU_QCH, 2051 QCH_CON_LHM_AXI_P_DPU_QCH, 2052 QCH_CON_LHS_AXI_D0_DPU_QCH, 2053 QCH_CON_LHS_AXI_D1_DPU_QCH, 2054 QCH_CON_LHS_AXI_D2_DPU_QCH, 2055 QCH_CON_PPMU_DPUD0_QCH, 2056 QCH_CON_PPMU_DPUD1_QCH, 2057 QCH_CON_PPMU_DPUD2_QCH, 2058 QCH_CON_SSMT_DPU0_QCH, 2059 QCH_CON_SSMT_DPU1_QCH, 2060 QCH_CON_SSMT_DPU2_QCH, 2061 QCH_CON_SYSMMU_DPUD0_QCH_S1, 2062 QCH_CON_SYSMMU_DPUD0_QCH_S2, 2063 QCH_CON_SYSMMU_DPUD1_QCH_S1, 2064 QCH_CON_SYSMMU_DPUD1_QCH_S2, 2065 QCH_CON_SYSMMU_DPUD2_QCH_S1, 2066 QCH_CON_SYSMMU_DPUD2_QCH_S2, 2067 QCH_CON_SYSREG_DPU_QCH, 2068 QUEUE_CTRL_REG_BLK_DPU_CMU_DPU, 2069 }; 2070 2071 /* List of parent clocks for Muxes in CMU_DPU */ 2072 PNAME(mout_dpu_bus_user_p) = { "oscclk", "dout_cmu_dpu_bus" }; 2073 2074 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = { 2075 MUX(CLK_MOUT_DPU_BUS_USER, "mout_dpu_bus_user", 2076 mout_dpu_bus_user_p, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 4, 1), 2077 }; 2078 2079 static const struct samsung_div_clock dpu_div_clks[] __initconst = { 2080 DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_bus_user", 2081 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3), 2082 }; 2083 2084 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = { 2085 GATE(CLK_GOUT_DPU_PCLK, "gout_dpu_dpu_pclk", 2086 "dout_dpu_busp", 2087 CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 21, 0, 0), 2088 GATE(CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK, "gout_dpu_clk_dpu_oscclk_clk", 2089 "oscclk", 2090 CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, 2091 21, 0, 0), 2092 GATE(CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM, "gout_dpu_ad_apb_dpu_dma_pclkm", 2093 "mout_dpu_bus_user", 2094 CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, 2095 21, 0, 0), 2096 GATE(CLK_GOUT_DPU_DPUF_ACLK_DMA, "gout_dpu_dpuf_aclk_dma", 2097 "mout_dpu_bus_user", 2098 CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, 21, 0, 0), 2099 GATE(CLK_GOUT_DPU_DPUF_ACLK_DPP, "gout_dpu_dpuf_aclk_dpp", 2100 "mout_dpu_bus_user", 2101 CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, 21, 0, 0), 2102 GATE(CLK_GOUT_DPU_D_TZPC_DPU_PCLK, "gout_dpu_d_tzpc_dpu_pclk", 2103 "dout_dpu_busp", 2104 CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, 21, 0, 0), 2105 GATE(CLK_GOUT_DPU_GPC_DPU_PCLK, "gout_dpu_gpc_dpu_pclk", 2106 "dout_dpu_busp", 2107 CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, 21, 0, 0), 2108 GATE(CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK, "gout_dpu_lhm_axi_p_dpu_i_clk", 2109 "dout_dpu_busp", 2110 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK, 2111 21, 0, 0), 2112 GATE(CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK, "gout_dpu_lhs_axi_d0_dpu_i_clk", 2113 "mout_dpu_bus_user", 2114 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK, 2115 21, 0, 0), 2116 GATE(CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK, "gout_dpu_lhs_axi_d1_dpu_i_clk", 2117 "mout_dpu_bus_user", 2118 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK, 2119 21, 0, 0), 2120 GATE(CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK, "gout_dpu_lhs_axi_d2_dpu_i_clk", 2121 "mout_dpu_bus_user", 2122 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK, 2123 21, 0, 0), 2124 GATE(CLK_GOUT_DPU_PPMU_DPUD0_ACLK, "gout_dpu_ppmu_dpud0_aclk", 2125 "mout_dpu_bus_user", 2126 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, 21, 0, 0), 2127 GATE(CLK_GOUT_DPU_PPMU_DPUD0_PCLK, "gout_dpu_ppmu_dpud0_pclk", 2128 "dout_dpu_busp", 2129 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, 21, 0, 0), 2130 GATE(CLK_GOUT_DPU_PPMU_DPUD1_ACLK, "gout_dpu_ppmu_dpud1_aclk", 2131 "mout_dpu_bus_user", 2132 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, 21, 0, 0), 2133 GATE(CLK_GOUT_DPU_PPMU_DPUD1_PCLK, "gout_dpu_ppmu_dpud1_pclk", 2134 "dout_dpu_busp", 2135 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, 21, 0, 0), 2136 GATE(CLK_GOUT_DPU_PPMU_DPUD2_ACLK, "gout_dpu_ppmu_dpud2_aclk", 2137 "mout_dpu_bus_user", 2138 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, 21, 0, 0), 2139 GATE(CLK_GOUT_DPU_PPMU_DPUD2_PCLK, "gout_dpu_ppmu_dpud2_pclk", 2140 "dout_dpu_busp", 2141 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, 21, 0, 0), 2142 GATE(CLK_GOUT_DPU_CLK_DPU_BUSD_CLK, "gout_dpu_clk_dpu_busd_clk", 2143 "mout_dpu_bus_user", 2144 CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK, 2145 21, 0, 0), 2146 GATE(CLK_GOUT_DPU_CLK_DPU_BUSP_CLK, "gout_dpu_clk_dpu_busp_clk", 2147 "dout_dpu_busp", 2148 CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK, 2149 21, 0, 0), 2150 GATE(CLK_GOUT_DPU_SSMT_DPU0_ACLK, "gout_dpu_ssmt_dpu0_aclk", 2151 "mout_dpu_bus_user", 2152 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, 21, 0, 0), 2153 GATE(CLK_GOUT_DPU_SSMT_DPU0_PCLK, "gout_dpu_ssmt_dpu0_pclk", 2154 "dout_dpu_busp", 2155 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, 21, 0, 0), 2156 GATE(CLK_GOUT_DPU_SSMT_DPU1_ACLK, "gout_dpu_ssmt_dpu1_aclk", 2157 "mout_dpu_bus_user", 2158 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, 21, 0, 0), 2159 GATE(CLK_GOUT_DPU_SSMT_DPU1_PCLK, "gout_dpu_ssmt_dpu1_pclk", 2160 "dout_dpu_busp", 2161 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, 21, 0, 0), 2162 GATE(CLK_GOUT_DPU_SSMT_DPU2_ACLK, "gout_dpu_ssmt_dpu2_aclk", 2163 "mout_dpu_bus_user", 2164 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, 21, 0, 0), 2165 GATE(CLK_GOUT_DPU_SSMT_DPU2_PCLK, "gout_dpu_ssmt_dpu2_pclk", 2166 "dout_dpu_busp", 2167 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, 21, 0, 0), 2168 GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1, "gout_dpu_sysmmu_dpud0_clk_s1", 2169 "mout_dpu_bus_user", 2170 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, 2171 21, 0, 0), 2172 GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2, "gout_dpu_sysmmu_dpud0_clk_s2", 2173 "mout_dpu_bus_user", 2174 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, 2175 21, 0, 0), 2176 GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1, "gout_dpu_sysmmu_dpud1_clk_s1", 2177 "mout_dpu_bus_user", 2178 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, 2179 21, 0, 0), 2180 GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2, "gout_dpu_sysmmu_dpud1_clk_s2", 2181 "mout_dpu_bus_user", 2182 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, 2183 21, 0, 0), 2184 GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1, "gout_dpu_sysmmu_dpud2_clk_s1", 2185 "mout_dpu_bus_user", 2186 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, 2187 21, 0, 0), 2188 GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2, "gout_dpu_sysmmu_dpud2_clk_s2", 2189 "mout_dpu_bus_user", 2190 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, 21, 0, 0), 2191 GATE(CLK_GOUT_DPU_SYSREG_DPU_PCLK, "gout_dpu_sysreg_dpu_pclk", 2192 "dout_dpu_busp", 2193 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 21, 0, 0), 2194 }; 2195 2196 static const struct samsung_cmu_info dpu_cmu_info __initconst = { 2197 .mux_clks = dpu_mux_clks, 2198 .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks), 2199 .div_clks = dpu_div_clks, 2200 .nr_div_clks = ARRAY_SIZE(dpu_div_clks), 2201 .gate_clks = dpu_gate_clks, 2202 .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks), 2203 .nr_clk_ids = CLKS_NR_DPU, 2204 .clk_regs = dpu_clk_regs, 2205 .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs), 2206 .sysreg_clk_regs = dcrg_memclk_sysreg, 2207 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), 2208 .clk_name = "bus", 2209 .auto_clock_gate = true, 2210 .gate_dbg_offset = GS101_GATE_DBG_OFFSET, 2211 .option_offset = DPU_CMU_DPU_CONTROLLER_OPTION, 2212 .drcg_offset = GS101_DRCG_EN_OFFSET, 2213 }; 2214 2215 /* ---- CMU_HSI0 ------------------------------------------------------------ */ 2216 2217 /* Register Offset definitions for CMU_HSI0 (0x11000000) */ 2218 #define PLL_LOCKTIME_PLL_USB 0x0004 2219 #define PLL_CON0_PLL_USB 0x0140 2220 #define PLL_CON1_PLL_USB 0x0144 2221 #define PLL_CON2_PLL_USB 0x0148 2222 #define PLL_CON3_PLL_USB 0x014c 2223 #define PLL_CON4_PLL_USB 0x0150 2224 #define PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER 0x0600 2225 #define PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER 0x0604 2226 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0610 2227 #define PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER 0x0614 2228 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0620 2229 #define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x0624 2230 #define PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER 0x0630 2231 #define PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER 0x0634 2232 #define PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER 0x0640 2233 #define PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER 0x0644 2234 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0650 2235 #define PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0654 2236 #define PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0660 2237 #define PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0664 2238 #define HSI0_CMU_HSI0_CONTROLLER_OPTION 0x0800 2239 #define CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0 0x0810 2240 #define CLK_CON_MUX_MUX_CLK_HSI0_BUS 0x1000 2241 #define CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF 0x1004 2242 #define CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD 0x1008 2243 #define CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD 0x1800 2244 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000 2245 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26 0x2004 2246 #define CLK_CON_GAT_CLK_HSI0_ALT 0x2008 2247 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x200c 2248 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2010 2249 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2014 2250 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2018 2251 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x201c 2252 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK 0x2020 2253 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK 0x2024 2254 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK 0x2028 2255 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x202c 2256 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2030 2257 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK 0x2034 2258 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK 0x2038 2259 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK 0x203c 2260 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK 0x2040 2261 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK 0x2044 2262 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2048 2263 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK 0x204c 2264 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK 0x2050 2265 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2054 2266 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2058 2267 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK 0x205c 2268 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK 0x2060 2269 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK 0x2064 2270 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK 0x2068 2271 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x206c 2272 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2070 2273 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26 0x2074 2274 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2078 2275 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x207c 2276 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x2080 2277 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2084 2278 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK 0x2088 2279 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK 0x208c 2280 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK 0x2090 2281 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK 0x2094 2282 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK 0x2098 2283 #define DMYQCH_CON_USB31DRD_QCH 0x3000 2284 #define DMYQCH_CON_USB31DRD_QCH_REF 0x3004 2285 #define PCH_CON_LHM_AXI_G_ETR_HSI0_PCH 0x3008 2286 #define PCH_CON_LHM_AXI_P_AOCHSI0_PCH 0x300c 2287 #define PCH_CON_LHM_AXI_P_HSI0_PCH 0x3010 2288 #define PCH_CON_LHS_ACEL_D_HSI0_PCH 0x3014 2289 #define PCH_CON_LHS_AXI_D_HSI0AOC_PCH 0x3018 2290 #define QCH_CON_DP_LINK_QCH_GTC_CLK 0x301c 2291 #define QCH_CON_DP_LINK_QCH_PCLK 0x3020 2292 #define QCH_CON_D_TZPC_HSI0_QCH 0x3024 2293 #define QCH_CON_ETR_MIU_QCH_ACLK 0x3028 2294 #define QCH_CON_ETR_MIU_QCH_PCLK 0x302c 2295 #define QCH_CON_GPC_HSI0_QCH 0x3030 2296 #define QCH_CON_HSI0_CMU_HSI0_QCH 0x3034 2297 #define QCH_CON_LHM_AXI_G_ETR_HSI0_QCH 0x3038 2298 #define QCH_CON_LHM_AXI_P_AOCHSI0_QCH 0x303c 2299 #define QCH_CON_LHM_AXI_P_HSI0_QCH 0x3040 2300 #define QCH_CON_LHS_ACEL_D_HSI0_QCH 0x3044 2301 #define QCH_CON_LHS_AXI_D_HSI0AOC_QCH 0x3048 2302 #define QCH_CON_PPMU_HSI0_AOC_QCH 0x304c 2303 #define QCH_CON_PPMU_HSI0_BUS0_QCH 0x3050 2304 #define QCH_CON_SSMT_USB_QCH 0x3054 2305 #define QCH_CON_SYSMMU_USB_QCH 0x3058 2306 #define QCH_CON_SYSREG_HSI0_QCH 0x305c 2307 #define QCH_CON_UASC_HSI0_CTRL_QCH 0x3060 2308 #define QCH_CON_UASC_HSI0_LINK_QCH 0x3064 2309 #define QCH_CON_USB31DRD_QCH_APB 0x3068 2310 #define QCH_CON_USB31DRD_QCH_DBG 0x306c 2311 #define QCH_CON_USB31DRD_QCH_PCS 0x3070 2312 #define QCH_CON_USB31DRD_QCH_SLV_CTRL 0x3074 2313 #define QCH_CON_USB31DRD_QCH_SLV_LINK 0x3078 2314 #define QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0 0x3c00 2315 2316 static const unsigned long hsi0_clk_regs[] __initconst = { 2317 PLL_LOCKTIME_PLL_USB, 2318 PLL_CON0_PLL_USB, 2319 PLL_CON1_PLL_USB, 2320 PLL_CON2_PLL_USB, 2321 PLL_CON3_PLL_USB, 2322 PLL_CON4_PLL_USB, 2323 PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 2324 PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER, 2325 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 2326 PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER, 2327 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 2328 PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER, 2329 PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 2330 PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER, 2331 PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 2332 PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER, 2333 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 2334 PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER, 2335 PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 2336 PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER, 2337 HSI0_CMU_HSI0_CONTROLLER_OPTION, 2338 CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0, 2339 CLK_CON_MUX_MUX_CLK_HSI0_BUS, 2340 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 2341 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 2342 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 2343 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, 2344 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, 2345 CLK_CON_GAT_CLK_HSI0_ALT, 2346 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, 2347 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 2348 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, 2349 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 2350 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 2351 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 2352 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK, 2353 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK, 2354 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK, 2355 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, 2356 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK, 2357 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, 2358 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, 2359 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK, 2360 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK, 2361 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK, 2362 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, 2363 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, 2364 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, 2365 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, 2366 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, 2367 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, 2368 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, 2369 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, 2370 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, 2371 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, 2372 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, 2373 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, 2374 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, 2375 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, 2376 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, 2377 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, 2378 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, 2379 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, 2380 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, 2381 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, 2382 DMYQCH_CON_USB31DRD_QCH, 2383 DMYQCH_CON_USB31DRD_QCH_REF, 2384 PCH_CON_LHM_AXI_G_ETR_HSI0_PCH, 2385 PCH_CON_LHM_AXI_P_AOCHSI0_PCH, 2386 PCH_CON_LHM_AXI_P_HSI0_PCH, 2387 PCH_CON_LHS_ACEL_D_HSI0_PCH, 2388 PCH_CON_LHS_AXI_D_HSI0AOC_PCH, 2389 QCH_CON_DP_LINK_QCH_GTC_CLK, 2390 QCH_CON_DP_LINK_QCH_PCLK, 2391 QCH_CON_D_TZPC_HSI0_QCH, 2392 QCH_CON_ETR_MIU_QCH_ACLK, 2393 QCH_CON_ETR_MIU_QCH_PCLK, 2394 QCH_CON_GPC_HSI0_QCH, 2395 QCH_CON_HSI0_CMU_HSI0_QCH, 2396 QCH_CON_LHM_AXI_G_ETR_HSI0_QCH, 2397 QCH_CON_LHM_AXI_P_AOCHSI0_QCH, 2398 QCH_CON_LHM_AXI_P_HSI0_QCH, 2399 QCH_CON_LHS_ACEL_D_HSI0_QCH, 2400 QCH_CON_LHS_AXI_D_HSI0AOC_QCH, 2401 QCH_CON_PPMU_HSI0_AOC_QCH, 2402 QCH_CON_PPMU_HSI0_BUS0_QCH, 2403 QCH_CON_SSMT_USB_QCH, 2404 QCH_CON_SYSMMU_USB_QCH, 2405 QCH_CON_SYSREG_HSI0_QCH, 2406 QCH_CON_UASC_HSI0_CTRL_QCH, 2407 QCH_CON_UASC_HSI0_LINK_QCH, 2408 QCH_CON_USB31DRD_QCH_APB, 2409 QCH_CON_USB31DRD_QCH_DBG, 2410 QCH_CON_USB31DRD_QCH_PCS, 2411 QCH_CON_USB31DRD_QCH_SLV_CTRL, 2412 QCH_CON_USB31DRD_QCH_SLV_LINK, 2413 QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0, 2414 }; 2415 2416 /* List of parent clocks for Muxes in CMU_HSI0 */ 2417 PNAME(mout_pll_usb_p) = { "oscclk", "fout_usb_pll" }; 2418 PNAME(mout_hsi0_alt_user_p) = { "oscclk", 2419 "gout_hsi0_clk_hsi0_alt" }; 2420 PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" }; 2421 PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" }; 2422 PNAME(mout_hsi0_tcxo_user_p) = { "oscclk", "tcxo_hsi1_hsi0" }; 2423 PNAME(mout_hsi0_usb20_user_p) = { "oscclk", "usb20phy_phy_clock" }; 2424 PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk", 2425 "dout_cmu_hsi0_usb31drd" }; 2426 PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk", 2427 "dout_cmu_hsi0_usbdpdbg" }; 2428 PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user", 2429 "mout_hsi0_alt_user" }; 2430 PNAME(mout_hsi0_usb20_ref_p) = { "mout_pll_usb", 2431 "mout_hsi0_tcxo_user" }; 2432 PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll", 2433 "mout_hsi0_usb31drd_user", 2434 "dout_hsi0_usb31drd", 2435 "fout_usb_pll" }; 2436 2437 static const struct samsung_pll_rate_table hsi0_usb_pll_rates[] __initconst = { 2438 PLL_35XX_RATE(24576000, 19200000, 150, 6, 5), 2439 { /* sentinel */ } 2440 }; 2441 2442 static const struct samsung_pll_clock hsi0_pll_clks[] __initconst = { 2443 PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", 2444 PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB, 2445 hsi0_usb_pll_rates), 2446 }; 2447 2448 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = { 2449 MUX(CLK_MOUT_PLL_USB, 2450 "mout_pll_usb", mout_pll_usb_p, 2451 PLL_CON0_PLL_USB, 4, 1), 2452 MUX(CLK_MOUT_HSI0_ALT_USER, 2453 "mout_hsi0_alt_user", mout_hsi0_alt_user_p, 2454 PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 4, 1), 2455 MUX(CLK_MOUT_HSI0_BUS_USER, 2456 "mout_hsi0_bus_user", mout_hsi0_bus_user_p, 2457 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 4, 1), 2458 MUX(CLK_MOUT_HSI0_DPGTC_USER, 2459 "mout_hsi0_dpgtc_user", mout_hsi0_dpgtc_user_p, 2460 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 4, 1), 2461 MUX(CLK_MOUT_HSI0_TCXO_USER, 2462 "mout_hsi0_tcxo_user", mout_hsi0_tcxo_user_p, 2463 PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 4, 1), 2464 MUX(CLK_MOUT_HSI0_USB20_USER, 2465 "mout_hsi0_usb20_user", mout_hsi0_usb20_user_p, 2466 PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 4, 1), 2467 MUX(CLK_MOUT_HSI0_USB31DRD_USER, 2468 "mout_hsi0_usb31drd_user", mout_hsi0_usb31drd_user_p, 2469 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 4, 1), 2470 MUX(CLK_MOUT_HSI0_USBDPDBG_USER, 2471 "mout_hsi0_usbdpdbg_user", mout_hsi0_usbdpdbg_user_p, 2472 PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 4, 1), 2473 MUX(CLK_MOUT_HSI0_BUS, 2474 "mout_hsi0_bus", mout_hsi0_bus_p, 2475 CLK_CON_MUX_MUX_CLK_HSI0_BUS, 0, 1), 2476 MUX(CLK_MOUT_HSI0_USB20_REF, 2477 "mout_hsi0_usb20_ref", mout_hsi0_usb20_ref_p, 2478 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 0, 1), 2479 MUX(CLK_MOUT_HSI0_USB31DRD, 2480 "mout_hsi0_usb31drd", mout_hsi0_usb31drd_p, 2481 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0, 2), 2482 }; 2483 2484 static const struct samsung_div_clock hsi0_div_clks[] __initconst = { 2485 DIV(CLK_DOUT_HSI0_USB31DRD, 2486 "dout_hsi0_usb31drd", "mout_hsi0_usb20_user", 2487 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0, 3), 2488 }; 2489 2490 static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = { 2491 /* TODO: should have a driver for this */ 2492 GATE(CLK_GOUT_HSI0_PCLK, 2493 "gout_hsi0_hsi0_pclk", "mout_hsi0_bus", 2494 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, 2495 21, CLK_IGNORE_UNUSED, 0), 2496 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26, 2497 "gout_hsi0_usb31drd_i_usb31drd_suspend_clk_26", 2498 "mout_hsi0_usb20_ref", 2499 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, 2500 21, 0, 0), 2501 GATE(CLK_GOUT_HSI0_CLK_HSI0_ALT, 2502 "gout_hsi0_clk_hsi0_alt", "ioclk_clk_hsi0_alt", 2503 CLK_CON_GAT_CLK_HSI0_ALT, 21, 0, 0), 2504 GATE(CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK, 2505 "gout_hsi0_dp_link_i_dp_gtc_clk", "mout_hsi0_dpgtc_user", 2506 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, 2507 21, 0, 0), 2508 GATE(CLK_GOUT_HSI0_DP_LINK_I_PCLK, 2509 "gout_hsi0_dp_link_i_pclk", "mout_hsi0_bus", 2510 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 21, 0, 0), 2511 GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK, 2512 "gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus", 2513 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, 2514 21, 0, 0), 2515 GATE(CLK_GOUT_HSI0_ETR_MIU_I_ACLK, 2516 "gout_hsi0_etr_miu_i_aclk", "mout_hsi0_bus", 2517 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0), 2518 GATE(CLK_GOUT_HSI0_ETR_MIU_I_PCLK, 2519 "gout_hsi0_etr_miu_i_pclk", "mout_hsi0_bus", 2520 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0), 2521 GATE(CLK_GOUT_HSI0_GPC_HSI0_PCLK, 2522 "gout_hsi0_gpc_hsi0_pclk", "mout_hsi0_bus", 2523 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 21, 0, 0), 2524 GATE(CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK, 2525 "gout_hsi0_lhm_axi_g_etr_hsi0_i_clk", "mout_hsi0_bus", 2526 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK, 2527 21, 0, 0), 2528 GATE(CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK, 2529 "gout_hsi0_lhm_axi_p_aochsi0_i_clk", "mout_hsi0_bus", 2530 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK, 2531 21, 0, 0), 2532 /* TODO: should have a driver for this */ 2533 GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK, 2534 "gout_hsi0_lhm_axi_p_hsi0_i_clk", "mout_hsi0_bus", 2535 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK, 2536 21, CLK_IGNORE_UNUSED, 0), 2537 /* TODO: should have a driver for this */ 2538 GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK, 2539 "gout_hsi0_lhs_acel_d_hsi0_i_clk", "mout_hsi0_bus", 2540 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, 2541 21, CLK_IGNORE_UNUSED, 0), 2542 GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK, 2543 "gout_hsi0_lhs_axi_d_hsi0aoc_i_clk", "mout_hsi0_bus", 2544 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK, 2545 21, 0, 0), 2546 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK, 2547 "gout_hsi0_ppmu_hsi0_aoc_aclk", "mout_hsi0_bus", 2548 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, 2549 21, 0, 0), 2550 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK, 2551 "gout_hsi0_ppmu_hsi0_aoc_pclk", "mout_hsi0_bus", 2552 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, 2553 21, 0, 0), 2554 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK, 2555 "gout_hsi0_ppmu_hsi0_bus0_aclk", "mout_hsi0_bus", 2556 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK, 2557 21, 0, 0), 2558 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK, 2559 "gout_hsi0_ppmu_hsi0_bus0_pclk", "mout_hsi0_bus", 2560 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK, 2561 21, 0, 0), 2562 GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK, 2563 "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus", 2564 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK, 2565 21, 0, 0), 2566 /* TODO: should have a driver for this */ 2567 GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK, 2568 "gout_hsi0_ssmt_usb_aclk", "mout_hsi0_bus", 2569 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, 2570 21, CLK_IGNORE_UNUSED, 0), 2571 /* TODO: should have a driver for this */ 2572 GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK, 2573 "gout_hsi0_ssmt_usb_pclk", "mout_hsi0_bus", 2574 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, 2575 21, CLK_IGNORE_UNUSED, 0), 2576 /* TODO: should have a driver for this */ 2577 GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2, 2578 "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus", 2579 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, 2580 21, CLK_IGNORE_UNUSED, 0), 2581 GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK, 2582 "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus", 2583 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, 2584 21, 0, 0), 2585 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK, 2586 "gout_hsi0_uasc_hsi0_ctrl_aclk", "mout_hsi0_bus", 2587 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, 2588 21, 0, 0), 2589 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK, 2590 "gout_hsi0_uasc_hsi0_ctrl_pclk", "mout_hsi0_bus", 2591 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, 2592 21, 0, 0), 2593 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK, 2594 "gout_hsi0_uasc_hsi0_link_aclk", "mout_hsi0_bus", 2595 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, 2596 21, 0, 0), 2597 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK, 2598 "gout_hsi0_uasc_hsi0_link_pclk", "mout_hsi0_bus", 2599 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, 2600 21, 0, 0), 2601 GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL, 2602 "gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus", 2603 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, 2604 21, 0, 0), 2605 GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY, 2606 "gout_hsi0_usb31drd_bus_clk_early", "mout_hsi0_bus", 2607 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, 2608 21, 0, 0), 2609 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26, 2610 "gout_hsi0_usb31drd_i_usb20_phy_refclk_26", "mout_hsi0_usb20_ref", 2611 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, 2612 21, 0, 0), 2613 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40, 2614 "gout_hsi0_usb31drd_i_usb31drd_ref_clk_40", "mout_hsi0_usb31drd", 2615 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, 2616 21, 0, 0), 2617 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL, 2618 "gout_hsi0_usb31drd_i_usbdpphy_ref_soc_pll", 2619 "mout_hsi0_usbdpdbg_user", 2620 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, 2621 21, 0, 0), 2622 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK, 2623 "gout_hsi0_usb31drd_i_usbdpphy_scl_apb_pclk", "mout_hsi0_bus", 2624 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, 2625 21, 0, 0), 2626 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK, 2627 "gout_hsi0_usb31drd_i_usbpcs_apb_clk", "mout_hsi0_bus", 2628 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, 2629 21, 0, 0), 2630 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK, 2631 "gout_hsi0_usb31drd_usbdpphy_i_aclk", "mout_hsi0_bus", 2632 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, 2633 21, 0, 0), 2634 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK, 2635 "gout_hsi0_usb31drd_usbdpphy_udbg_i_apb_pclk", "mout_hsi0_bus", 2636 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, 2637 21, 0, 0), 2638 /* TODO: should have a driver for this */ 2639 GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK, 2640 "gout_hsi0_xiu_d0_hsi0_aclk", "mout_hsi0_bus", 2641 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, 2642 21, CLK_IGNORE_UNUSED, 0), 2643 /* TODO: should have a driver for this */ 2644 GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK, 2645 "gout_hsi0_xiu_d1_hsi0_aclk", "mout_hsi0_bus", 2646 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, 2647 21, CLK_IGNORE_UNUSED, 0), 2648 /* TODO: should have a driver for this */ 2649 GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK, 2650 "gout_hsi0_xiu_p_hsi0_aclk", "mout_hsi0_bus", 2651 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, 2652 21, CLK_IGNORE_UNUSED, 0), 2653 }; 2654 2655 static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = { 2656 FRATE(0, "tcxo_hsi1_hsi0", NULL, 0, 26000000), 2657 FRATE(0, "usb20phy_phy_clock", NULL, 0, 120000000), 2658 /* until we implement APMGSA */ 2659 FRATE(0, "ioclk_clk_hsi0_alt", NULL, 0, 213000000), 2660 }; 2661 2662 static const struct samsung_cmu_info hsi0_cmu_info __initconst = { 2663 .pll_clks = hsi0_pll_clks, 2664 .nr_pll_clks = ARRAY_SIZE(hsi0_pll_clks), 2665 .mux_clks = hsi0_mux_clks, 2666 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks), 2667 .div_clks = hsi0_div_clks, 2668 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks), 2669 .gate_clks = hsi0_gate_clks, 2670 .nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks), 2671 .fixed_clks = hsi0_fixed_clks, 2672 .nr_fixed_clks = ARRAY_SIZE(hsi0_fixed_clks), 2673 .nr_clk_ids = CLKS_NR_HSI0, 2674 .clk_regs = hsi0_clk_regs, 2675 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs), 2676 .sysreg_clk_regs = dcrg_memclk_sysreg, 2677 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), 2678 .clk_name = "bus", 2679 .auto_clock_gate = true, 2680 .gate_dbg_offset = GS101_GATE_DBG_OFFSET, 2681 .option_offset = HSI0_CMU_HSI0_CONTROLLER_OPTION, 2682 .drcg_offset = GS101_DRCG_EN_OFFSET, 2683 .memclk_offset = GS101_MEMCLK_OFFSET, 2684 }; 2685 2686 /* ---- CMU_HSI2 ------------------------------------------------------------ */ 2687 2688 /* Register Offset definitions for CMU_HSI2 (0x14400000) */ 2689 #define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600 2690 #define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604 2691 #define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610 2692 #define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614 2693 #define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620 2694 #define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624 2695 #define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630 2696 #define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634 2697 #define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800 2698 #define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810 2699 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000 2700 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004 2701 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008 2702 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c 2703 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010 2704 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014 2705 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c 2706 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020 2707 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024 2708 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028 2709 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c 2710 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030 2711 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034 2712 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038 2713 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c 2714 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040 2715 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044 2716 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048 2717 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c 2718 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050 2719 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054 2720 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058 2721 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c 2722 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060 2723 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064 2724 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068 2725 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c 2726 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070 2727 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074 2728 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078 2729 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c 2730 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080 2731 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084 2732 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088 2733 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c 2734 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090 2735 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094 2736 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098 2737 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c 2738 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0 2739 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4 2740 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8 2741 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac 2742 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0 2743 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4 2744 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8 2745 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc 2746 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0 2747 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4 2748 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8 2749 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc 2750 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0 2751 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4 2752 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8 2753 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc 2754 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0 2755 #define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000 2756 #define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008 2757 #define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c 2758 #define QCH_CON_D_TZPC_HSI2_QCH 0x3010 2759 #define QCH_CON_GPC_HSI2_QCH 0x3014 2760 #define QCH_CON_GPIO_HSI2_QCH 0x3018 2761 #define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c 2762 #define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020 2763 #define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024 2764 #define QCH_CON_MMC_CARD_QCH 0x3028 2765 #define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c 2766 #define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030 2767 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034 2768 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038 2769 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c 2770 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040 2771 #define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044 2772 #define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048 2773 #define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c 2774 #define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050 2775 #define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054 2776 #define QCH_CON_PPMU_HSI2_QCH 0x3058 2777 #define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c 2778 #define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060 2779 #define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064 2780 #define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068 2781 #define QCH_CON_SSMT_HSI2_QCH 0x306c 2782 #define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070 2783 #define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074 2784 #define QCH_CON_SYSMMU_HSI2_QCH 0x3078 2785 #define QCH_CON_SYSREG_HSI2_QCH 0x307c 2786 #define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080 2787 #define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084 2788 #define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088 2789 #define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c 2790 #define QCH_CON_UFS_EMBD_QCH 0x3090 2791 #define QCH_CON_UFS_EMBD_QCH_FMP 0x3094 2792 #define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00 2793 2794 static const unsigned long hsi2_clk_regs[] __initconst = { 2795 PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 2796 PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER, 2797 PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER, 2798 PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER, 2799 PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER, 2800 PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER, 2801 PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 2802 PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 2803 HSI2_CMU_HSI2_CONTROLLER_OPTION, 2804 CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0, 2805 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 2806 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 2807 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, 2808 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, 2809 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, 2810 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, 2811 CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, 2812 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 2813 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 2814 CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, 2815 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK, 2816 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK, 2817 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, 2818 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 2819 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 2820 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 2821 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 2822 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 2823 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 2824 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 2825 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 2826 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 2827 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, 2828 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, 2829 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 2830 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, 2831 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, 2832 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, 2833 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, 2834 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, 2835 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, 2836 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, 2837 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, 2838 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, 2839 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, 2840 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, 2841 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, 2842 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK, 2843 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, 2844 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, 2845 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, 2846 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, 2847 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, 2848 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, 2849 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, 2850 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, 2851 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, 2852 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, 2853 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, 2854 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, 2855 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, 2856 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 2857 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 2858 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 2859 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, 2860 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, 2861 DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1, 2862 PCH_CON_LHM_AXI_P_HSI2_PCH, 2863 PCH_CON_LHS_ACEL_D_HSI2_PCH, 2864 QCH_CON_D_TZPC_HSI2_QCH, 2865 QCH_CON_GPC_HSI2_QCH, 2866 QCH_CON_GPIO_HSI2_QCH, 2867 QCH_CON_HSI2_CMU_HSI2_QCH, 2868 QCH_CON_LHM_AXI_P_HSI2_QCH, 2869 QCH_CON_LHS_ACEL_D_HSI2_QCH, 2870 QCH_CON_MMC_CARD_QCH, 2871 QCH_CON_PCIE_GEN4_1_QCH_APB_1, 2872 QCH_CON_PCIE_GEN4_1_QCH_APB_2, 2873 QCH_CON_PCIE_GEN4_1_QCH_AXI_1, 2874 QCH_CON_PCIE_GEN4_1_QCH_AXI_2, 2875 QCH_CON_PCIE_GEN4_1_QCH_DBG_1, 2876 QCH_CON_PCIE_GEN4_1_QCH_DBG_2, 2877 QCH_CON_PCIE_GEN4_1_QCH_PCS_APB, 2878 QCH_CON_PCIE_GEN4_1_QCH_PMA_APB, 2879 QCH_CON_PCIE_GEN4_1_QCH_UDBG, 2880 QCH_CON_PCIE_IA_GEN4A_1_QCH, 2881 QCH_CON_PCIE_IA_GEN4B_1_QCH, 2882 QCH_CON_PPMU_HSI2_QCH, 2883 QCH_CON_QE_MMC_CARD_HSI2_QCH, 2884 QCH_CON_QE_PCIE_GEN4A_HSI2_QCH, 2885 QCH_CON_QE_PCIE_GEN4B_HSI2_QCH, 2886 QCH_CON_QE_UFS_EMBD_HSI2_QCH, 2887 QCH_CON_SSMT_HSI2_QCH, 2888 QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH, 2889 QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH, 2890 QCH_CON_SYSMMU_HSI2_QCH, 2891 QCH_CON_SYSREG_HSI2_QCH, 2892 QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH, 2893 QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH, 2894 QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH, 2895 QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH, 2896 QCH_CON_UFS_EMBD_QCH, 2897 QCH_CON_UFS_EMBD_QCH_FMP, 2898 QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2, 2899 }; 2900 2901 PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" }; 2902 PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" }; 2903 PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" }; 2904 PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" }; 2905 2906 static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = { 2907 MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p, 2908 PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1), 2909 MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user", 2910 mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER, 2911 4, 1), 2912 MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user", 2913 mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER, 2914 4, 1), 2915 MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user", 2916 mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 2917 4, 1), 2918 }; 2919 2920 static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { 2921 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN, 2922 "gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in", 2923 "mout_hsi2_pcie_user", 2924 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 2925 21, 0, 0), 2926 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN, 2927 "gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in", 2928 "mout_hsi2_pcie_user", 2929 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 2930 21, 0, 0), 2931 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK, 2932 "gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk", "mout_hsi2_bus_user", 2933 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, 2934 21, 0, 0), 2935 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK, 2936 "gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk", "mout_hsi2_bus_user", 2937 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, 2938 21, 0, 0), 2939 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK, 2940 "gout_hsi2_ssmt_pcie_ia_gen4b_1_aclk", "mout_hsi2_bus_user", 2941 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, 2942 21, 0, 0), 2943 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK, 2944 "gout_hsi2_ssmt_pcie_ia_gen4b_1_pclk", "mout_hsi2_bus_user", 2945 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, 2946 21, 0, 0), 2947 GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK, 2948 "gout_hsi2_d_tzpc_hsi2_pclk", "mout_hsi2_bus_user", 2949 CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, 2950 21, 0, 0), 2951 GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK, 2952 "gout_hsi2_gpc_hsi2_pclk", "mout_hsi2_bus_user", 2953 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0), 2954 GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK, 2955 "gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user", 2956 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21, 2957 CLK_IGNORE_UNUSED, 0), 2958 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2959 GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK, 2960 "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user", 2961 CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, 2962 21, CLK_IS_CRITICAL, 0), 2963 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2964 GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK, 2965 "gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user", 2966 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK, 2967 21, CLK_IS_CRITICAL, 0), 2968 /* TODO: should have a driver for this */ 2969 GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK, 2970 "gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user", 2971 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK, 2972 21, CLK_IGNORE_UNUSED, 0), 2973 GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK, 2974 "gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user", 2975 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, 2976 21, 0, 0), 2977 GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN, 2978 "gout_hsi2_mmc_card_sdclkin", "mout_hsi2_mmc_card_user", 2979 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 2980 21, 0, 0), 2981 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG, 2982 "gout_hsi2_pcie_gen4_1_pcie_003_dbi_aclk_ug", "mout_hsi2_bus_user", 2983 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 2984 21, 0, 0), 2985 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG, 2986 "gout_hsi2_pcie_gen4_1_pcie_003_mstr_aclk_ug", 2987 "mout_hsi2_bus_user", 2988 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 2989 21, 0, 0), 2990 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG, 2991 "gout_hsi2_pcie_gen4_1_pcie_003_slv_aclk_ug", "mout_hsi2_bus_user", 2992 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 2993 21, 0, 0), 2994 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK, 2995 "gout_hsi2_pcie_gen4_1_pcie_003_i_driver_apb_clk", 2996 "mout_hsi2_bus_user", 2997 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 2998 21, 0, 0), 2999 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG, 3000 "gout_hsi2_pcie_gen4_1_pcie_004_dbi_aclk_ug", "mout_hsi2_bus_user", 3001 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 3002 21, 0, 0), 3003 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG, 3004 "gout_hsi2_pcie_gen4_1_pcie_004_mstr_aclk_ug", 3005 "mout_hsi2_bus_user", 3006 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 3007 21, 0, 0), 3008 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG, 3009 "gout_hsi2_pcie_gen4_1_pcie_004_slv_aclk_ug", "mout_hsi2_bus_user", 3010 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 3011 21, 0, 0), 3012 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK, 3013 "gout_hsi2_pcie_gen4_1_pcie_004_i_driver_apb_clk", 3014 "mout_hsi2_bus_user", 3015 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 3016 21, 0, 0), 3017 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK, 3018 "gout_hsi2_pcie_gen4_1_pcs_pma_phy_udbg_i_apb_pclk", 3019 "mout_hsi2_bus_user", 3020 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, 3021 21, 0, 0), 3022 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK, 3023 "gout_hsi2_pcie_gen4_1_pcs_pma_pipe_pal_pcie_i_apb_pclk", 3024 "mout_hsi2_bus_user", 3025 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, 3026 21, 0, 0), 3027 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK, 3028 "gout_hsi2_pcie_gen4_1_pcs_pma_pciephy210x2_qch_i_apb_pclk", 3029 "mout_hsi2_bus_user", 3030 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 3031 21, 0, 0), 3032 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK, 3033 "gout_hsi2_pcie_ia_gen4a_1_i_clk", "mout_hsi2_bus_user", 3034 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, 3035 21, 0, 0), 3036 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK, 3037 "gout_hsi2_pcie_ia_gen4b_1_i_clk", "mout_hsi2_bus_user", 3038 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, 3039 21, 0, 0), 3040 GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK, 3041 "gout_hsi2_ppmu_hsi2_aclk", "mout_hsi2_bus_user", 3042 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, 3043 21, 0, 0), 3044 GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK, 3045 "gout_hsi2_ppmu_hsi2_pclk", "mout_hsi2_bus_user", 3046 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, 3047 21, 0, 0), 3048 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK, 3049 "gout_hsi2_qe_mmc_card_hsi2_aclk", "mout_hsi2_bus_user", 3050 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, 3051 21, 0, 0), 3052 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK, 3053 "gout_hsi2_qe_mmc_card_hsi2_pclk", "mout_hsi2_bus_user", 3054 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, 3055 21, 0, 0), 3056 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK, 3057 "gout_hsi2_qe_pcie_gen4a_hsi2_aclk", "mout_hsi2_bus_user", 3058 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, 3059 21, 0, 0), 3060 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK, 3061 "gout_hsi2_qe_pcie_gen4a_hsi2_pclk", "mout_hsi2_bus_user", 3062 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, 3063 21, 0, 0), 3064 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK, 3065 "gout_hsi2_qe_pcie_gen4b_hsi2_aclk", "mout_hsi2_bus_user", 3066 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, 3067 21, 0, 0), 3068 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK, 3069 "gout_hsi2_qe_pcie_gen4b_hsi2_pclk", "mout_hsi2_bus_user", 3070 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, 3071 21, 0, 0), 3072 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK, 3073 "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user", 3074 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, 3075 21, CLK_IS_CRITICAL, 0), 3076 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK, 3077 "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user", 3078 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, 3079 21, CLK_IS_CRITICAL, 0), 3080 GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK, 3081 "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user", 3082 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK, 3083 21, CLK_IS_CRITICAL, 0), 3084 GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK, 3085 "gout_hsi2_clk_hsi2_oscclk_clk", "oscclk", 3086 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, 3087 21, 0, 0), 3088 /* TODO: should have a driver for this */ 3089 GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK, 3090 "gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user", 3091 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, 3092 21, CLK_IGNORE_UNUSED, 0), 3093 /* TODO: should have a driver for this */ 3094 GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK, 3095 "gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user", 3096 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, 3097 21, CLK_IGNORE_UNUSED, 0), 3098 /* TODO: should have a driver for this */ 3099 GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2, 3100 "gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user", 3101 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, 3102 21, CLK_IGNORE_UNUSED, 0), 3103 GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK, 3104 "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user", 3105 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, 3106 21, CLK_IS_CRITICAL, 0), 3107 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK, 3108 "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user", 3109 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, 3110 21, 0, 0), 3111 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK, 3112 "gout_hsi2_uasc_pcie_gen4a_dbi_1_pclk", "mout_hsi2_bus_user", 3113 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, 3114 21, 0, 0), 3115 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK, 3116 "gout_hsi2_uasc_pcie_gen4a_slv_1_aclk", "mout_hsi2_bus_user", 3117 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, 3118 21, 0, 0), 3119 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK, 3120 "gout_hsi2_uasc_pcie_gen4a_slv_1_pclk", "mout_hsi2_bus_user", 3121 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, 3122 21, 0, 0), 3123 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK, 3124 "gout_hsi2_uasc_pcie_gen4b_dbi_1_aclk", "mout_hsi2_bus_user", 3125 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, 3126 21, 0, 0), 3127 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK, 3128 "gout_hsi2_uasc_pcie_gen4b_dbi_1_pclk", "mout_hsi2_bus_user", 3129 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, 3130 21, 0, 0), 3131 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK, 3132 "gout_hsi2_uasc_pcie_gen4b_slv_1_aclk", "mout_hsi2_bus_user", 3133 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, 3134 21, 0, 0), 3135 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK, 3136 "gout_hsi2_uasc_pcie_gen4b_slv_1_pclk", "mout_hsi2_bus_user", 3137 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, 3138 21, 0, 0), 3139 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK, 3140 "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user", 3141 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 3142 21, CLK_IS_CRITICAL, 0), 3143 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO, 3144 "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user", 3145 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 3146 21, CLK_IS_CRITICAL, 0), 3147 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK, 3148 "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user", 3149 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 3150 21, CLK_IS_CRITICAL, 0), 3151 /* TODO: should have a driver for this */ 3152 GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK, 3153 "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user", 3154 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, 3155 21, CLK_IGNORE_UNUSED, 0), 3156 /* TODO: should have a driver for this */ 3157 GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK, 3158 "gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user", 3159 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, 3160 21, CLK_IGNORE_UNUSED, 0), 3161 }; 3162 3163 static const struct samsung_cmu_info hsi2_cmu_info __initconst = { 3164 .mux_clks = hsi2_mux_clks, 3165 .nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks), 3166 .gate_clks = hsi2_gate_clks, 3167 .nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks), 3168 .nr_clk_ids = CLKS_NR_HSI2, 3169 .clk_regs = hsi2_clk_regs, 3170 .nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs), 3171 .sysreg_clk_regs = dcrg_memclk_sysreg, 3172 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), 3173 .clk_name = "bus", 3174 .auto_clock_gate = true, 3175 .gate_dbg_offset = GS101_GATE_DBG_OFFSET, 3176 .option_offset = HSI2_CMU_HSI2_CONTROLLER_OPTION, 3177 .drcg_offset = GS101_DRCG_EN_OFFSET, 3178 .memclk_offset = GS101_MEMCLK_OFFSET, 3179 }; 3180 3181 /* ---- CMU_MISC ------------------------------------------------------------ */ 3182 3183 /* Register Offset definitions for CMU_MISC (0x10010000) */ 3184 #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600 3185 #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604 3186 #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610 3187 #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614 3188 #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800 3189 #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810 3190 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 3191 #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800 3192 #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804 3193 #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000 3194 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004 3195 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008 3196 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c 3197 #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010 3198 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014 3199 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018 3200 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c 3201 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020 3202 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024 3203 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028 3204 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c 3205 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030 3206 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034 3207 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038 3208 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c 3209 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040 3210 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044 3211 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048 3212 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c 3213 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050 3214 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054 3215 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058 3216 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c 3217 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060 3218 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064 3219 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068 3220 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c 3221 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070 3222 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074 3223 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078 3224 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c 3225 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080 3226 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084 3227 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088 3228 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c 3229 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090 3230 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094 3231 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098 3232 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c 3233 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0 3234 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4 3235 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8 3236 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac 3237 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0 3238 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4 3239 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8 3240 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc 3241 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0 3242 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4 3243 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8 3244 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc 3245 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0 3246 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4 3247 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8 3248 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc 3249 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0 3250 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4 3251 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8 3252 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec 3253 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0 3254 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4 3255 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8 3256 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc 3257 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100 3258 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104 3259 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108 3260 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c 3261 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110 3262 #define DMYQCH_CON_PPMU_DMA_QCH 0x3000 3263 #define DMYQCH_CON_PUF_QCH 0x3004 3264 #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c 3265 #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010 3266 #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014 3267 #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018 3268 #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c 3269 #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020 3270 #define QCH_CON_ADM_AHB_SSS_QCH 0x3024 3271 #define QCH_CON_DIT_QCH 0x3028 3272 #define QCH_CON_GIC_QCH 0x3030 3273 #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038 3274 #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c 3275 #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040 3276 #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044 3277 #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048 3278 #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c 3279 #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050 3280 #define QCH_CON_MCT_QCH 0x3054 3281 #define QCH_CON_MISC_CMU_MISC_QCH 0x3058 3282 #define QCH_CON_OTP_CON_BIRA_QCH 0x305c 3283 #define QCH_CON_OTP_CON_BISR_QCH 0x3060 3284 #define QCH_CON_OTP_CON_TOP_QCH 0x3064 3285 #define QCH_CON_PDMA_QCH 0x3068 3286 #define QCH_CON_PPMU_MISC_QCH 0x306c 3287 #define QCH_CON_QE_DIT_QCH 0x3070 3288 #define QCH_CON_QE_PDMA_QCH 0x3074 3289 #define QCH_CON_QE_PPMU_DMA_QCH 0x3078 3290 #define QCH_CON_QE_RTIC_QCH 0x307c 3291 #define QCH_CON_QE_SPDMA_QCH 0x3080 3292 #define QCH_CON_QE_SSS_QCH 0x3084 3293 #define QCH_CON_RTIC_QCH 0x3088 3294 #define QCH_CON_SPDMA_QCH 0x308c 3295 #define QCH_CON_SSMT_DIT_QCH 0x3090 3296 #define QCH_CON_SSMT_PDMA_QCH 0x3094 3297 #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098 3298 #define QCH_CON_SSMT_RTIC_QCH 0x309c 3299 #define QCH_CON_SSMT_SPDMA_QCH 0x30a0 3300 #define QCH_CON_SSMT_SSS_QCH 0x30a4 3301 #define QCH_CON_SSS_QCH 0x30a8 3302 #define QCH_CON_SYSMMU_MISC_QCH 0x30ac 3303 #define QCH_CON_SYSMMU_SSS_QCH 0x30b0 3304 #define QCH_CON_SYSREG_MISC_QCH 0x30b4 3305 #define QCH_CON_TMU_SUB_QCH 0x30b8 3306 #define QCH_CON_TMU_TOP_QCH 0x30bc 3307 #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0 3308 #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4 3309 #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00 3310 3311 static const unsigned long misc_clk_regs[] __initconst = { 3312 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 3313 PLL_CON1_MUX_CLKCMU_MISC_BUS_USER, 3314 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 3315 PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, 3316 MISC_CMU_MISC_CONTROLLER_OPTION, 3317 CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0, 3318 CLK_CON_MUX_MUX_CLK_MISC_GIC, 3319 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 3320 CLK_CON_DIV_DIV_CLK_MISC_GIC, 3321 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 3322 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 3323 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 3324 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 3325 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 3326 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 3327 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 3328 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, 3329 CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, 3330 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 3331 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 3332 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 3333 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 3334 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 3335 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 3336 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 3337 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 3338 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 3339 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 3340 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 3341 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 3342 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 3343 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 3344 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 3345 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK, 3346 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 3347 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 3348 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 3349 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 3350 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 3351 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 3352 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 3353 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 3354 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 3355 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 3356 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 3357 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 3358 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 3359 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 3360 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 3361 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 3362 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 3363 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 3364 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 3365 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 3366 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 3367 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 3368 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 3369 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 3370 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 3371 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 3372 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 3373 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 3374 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 3375 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 3376 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 3377 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 3378 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 3379 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 3380 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 3381 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 3382 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 3383 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 3384 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 3385 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 3386 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 3387 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 3388 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 3389 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 3390 DMYQCH_CON_PPMU_DMA_QCH, 3391 DMYQCH_CON_PUF_QCH, 3392 PCH_CON_LHM_AXI_D_SSS_PCH, 3393 PCH_CON_LHM_AXI_P_GIC_PCH, 3394 PCH_CON_LHM_AXI_P_MISC_PCH, 3395 PCH_CON_LHS_ACEL_D_MISC_PCH, 3396 PCH_CON_LHS_AST_IRI_GICCPU_PCH, 3397 PCH_CON_LHS_AXI_D_SSS_PCH, 3398 QCH_CON_ADM_AHB_SSS_QCH, 3399 QCH_CON_DIT_QCH, 3400 QCH_CON_GIC_QCH, 3401 QCH_CON_LHM_AST_ICC_CPUGIC_QCH, 3402 QCH_CON_LHM_AXI_D_SSS_QCH, 3403 QCH_CON_LHM_AXI_P_GIC_QCH, 3404 QCH_CON_LHM_AXI_P_MISC_QCH, 3405 QCH_CON_LHS_ACEL_D_MISC_QCH, 3406 QCH_CON_LHS_AST_IRI_GICCPU_QCH, 3407 QCH_CON_LHS_AXI_D_SSS_QCH, 3408 QCH_CON_MCT_QCH, 3409 QCH_CON_MISC_CMU_MISC_QCH, 3410 QCH_CON_OTP_CON_BIRA_QCH, 3411 QCH_CON_OTP_CON_BISR_QCH, 3412 QCH_CON_OTP_CON_TOP_QCH, 3413 QCH_CON_PDMA_QCH, 3414 QCH_CON_PPMU_MISC_QCH, 3415 QCH_CON_QE_DIT_QCH, 3416 QCH_CON_QE_PDMA_QCH, 3417 QCH_CON_QE_PPMU_DMA_QCH, 3418 QCH_CON_QE_RTIC_QCH, 3419 QCH_CON_QE_SPDMA_QCH, 3420 QCH_CON_QE_SSS_QCH, 3421 QCH_CON_RTIC_QCH, 3422 QCH_CON_SPDMA_QCH, 3423 QCH_CON_SSMT_DIT_QCH, 3424 QCH_CON_SSMT_PDMA_QCH, 3425 QCH_CON_SSMT_PPMU_DMA_QCH, 3426 QCH_CON_SSMT_RTIC_QCH, 3427 QCH_CON_SSMT_SPDMA_QCH, 3428 QCH_CON_SSMT_SSS_QCH, 3429 QCH_CON_SSS_QCH, 3430 QCH_CON_SYSMMU_MISC_QCH, 3431 QCH_CON_SYSMMU_SSS_QCH, 3432 QCH_CON_SYSREG_MISC_QCH, 3433 QCH_CON_TMU_SUB_QCH, 3434 QCH_CON_TMU_TOP_QCH, 3435 QCH_CON_WDT_CLUSTER0_QCH, 3436 QCH_CON_WDT_CLUSTER1_QCH, 3437 QUEUE_CTRL_REG_BLK_MISC_CMU_MISC, 3438 }; 3439 3440 /* List of parent clocks for Muxes in CMU_MISC */ 3441 PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" }; 3442 PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" }; 3443 PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" }; 3444 3445 static const struct samsung_mux_clock misc_mux_clks[] __initconst = { 3446 MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p, 3447 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1), 3448 MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p, 3449 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1), 3450 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p, 3451 CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0), 3452 }; 3453 3454 static const struct samsung_div_clock misc_div_clks[] __initconst = { 3455 DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user", 3456 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3), 3457 DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user", 3458 CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3), 3459 }; 3460 3461 static const struct samsung_gate_clock misc_gate_clks[] __initconst = { 3462 GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK, 3463 "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp", 3464 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 3465 21, 0, 0), 3466 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK, 3467 "gout_misc_otp_con_bira_i_oscclk", "oscclk", 3468 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 3469 21, 0, 0), 3470 GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK, 3471 "gout_misc_otp_con_bisr_i_oscclk", "oscclk", 3472 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 3473 21, 0, 0), 3474 GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK, 3475 "gout_misc_otp_con_top_i_oscclk", "oscclk", 3476 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 3477 21, 0, 0), 3478 GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK, 3479 "gout_misc_clk_misc_oscclk_clk", "oscclk", 3480 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 3481 21, 0, 0), 3482 GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM, 3483 "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user", 3484 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 3485 21, 0, 0), 3486 GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM, 3487 "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user", 3488 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 3489 21, 0, 0), 3490 GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK, 3491 "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp", 3492 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 3493 21, 0, 0), 3494 GATE(CLK_GOUT_MISC_GIC_GICCLK, 3495 "gout_misc_gic_gicclk", "mout_misc_gic", 3496 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 3497 21, 0, 0), 3498 GATE(CLK_GOUT_MISC_GPC_MISC_PCLK, 3499 "gout_misc_gpc_misc_pclk", "dout_misc_busp", 3500 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 3501 21, 0, 0), 3502 GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK, 3503 "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic", 3504 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 3505 21, 0, 0), 3506 GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK, 3507 "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user", 3508 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 3509 21, 0, 0), 3510 GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK, 3511 "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic", 3512 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 3513 21, 0, 0), 3514 GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK, 3515 "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp", 3516 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 3517 21, 0, 0), 3518 GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK, 3519 "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user", 3520 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 3521 21, 0, 0), 3522 GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK, 3523 "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic", 3524 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 3525 21, 0, 0), 3526 GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK, 3527 "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user", 3528 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 3529 21, 0, 0), 3530 GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk", 3531 "dout_misc_busp", 3532 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 3533 21, 0, 0), 3534 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK, 3535 "gout_misc_otp_con_bira_pclk", "dout_misc_busp", 3536 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 3537 21, 0, 0), 3538 GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK, 3539 "gout_misc_otp_con_bisr_pclk", "dout_misc_busp", 3540 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 3541 21, 0, 0), 3542 GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK, 3543 "gout_misc_otp_con_top_pclk", "dout_misc_busp", 3544 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 3545 21, 0, 0), 3546 GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk", 3547 "mout_misc_bus_user", 3548 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 3549 21, 0, 0), 3550 GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK, 3551 "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user", 3552 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 3553 21, 0, 0), 3554 GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK, 3555 "gout_misc_ppmu_misc_pclk", "dout_misc_busp", 3556 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 3557 21, 0, 0), 3558 GATE(CLK_GOUT_MISC_PUF_I_CLK, 3559 "gout_misc_puf_i_clk", "mout_misc_sss_user", 3560 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 3561 21, 0, 0), 3562 GATE(CLK_GOUT_MISC_QE_DIT_ACLK, 3563 "gout_misc_qe_dit_aclk", "mout_misc_bus_user", 3564 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 3565 21, 0, 0), 3566 GATE(CLK_GOUT_MISC_QE_DIT_PCLK, 3567 "gout_misc_qe_dit_pclk", "dout_misc_busp", 3568 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 3569 21, 0, 0), 3570 GATE(CLK_GOUT_MISC_QE_PDMA_ACLK, 3571 "gout_misc_qe_pdma_aclk", "mout_misc_bus_user", 3572 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 3573 21, 0, 0), 3574 GATE(CLK_GOUT_MISC_QE_PDMA_PCLK, 3575 "gout_misc_qe_pdma_pclk", "dout_misc_busp", 3576 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 3577 21, 0, 0), 3578 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK, 3579 "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user", 3580 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 3581 21, 0, 0), 3582 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK, 3583 "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp", 3584 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 3585 21, 0, 0), 3586 GATE(CLK_GOUT_MISC_QE_RTIC_ACLK, 3587 "gout_misc_qe_rtic_aclk", "mout_misc_bus_user", 3588 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 3589 21, 0, 0), 3590 GATE(CLK_GOUT_MISC_QE_RTIC_PCLK, 3591 "gout_misc_qe_rtic_pclk", "dout_misc_busp", 3592 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 3593 21, 0, 0), 3594 GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK, 3595 "gout_misc_qe_spdma_aclk", "mout_misc_bus_user", 3596 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 3597 21, 0, 0), 3598 GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK, 3599 "gout_misc_qe_spdma_pclk", "dout_misc_busp", 3600 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 3601 21, 0, 0), 3602 GATE(CLK_GOUT_MISC_QE_SSS_ACLK, 3603 "gout_misc_qe_sss_aclk", "mout_misc_sss_user", 3604 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 3605 21, 0, 0), 3606 GATE(CLK_GOUT_MISC_QE_SSS_PCLK, 3607 "gout_misc_qe_sss_pclk", "dout_misc_busp", 3608 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 3609 21, 0, 0), 3610 GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK, 3611 "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user", 3612 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 3613 21, 0, 0), 3614 GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK, 3615 "gout_misc_clk_misc_busp_clk", "dout_misc_busp", 3616 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 3617 21, 0, 0), 3618 GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK, 3619 "gout_misc_clk_misc_gic_clk", "mout_misc_gic", 3620 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 3621 21, 0, 0), 3622 GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK, 3623 "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user", 3624 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 3625 21, 0, 0), 3626 GATE(CLK_GOUT_MISC_RTIC_I_ACLK, 3627 "gout_misc_rtic_i_aclk", "mout_misc_bus_user", 3628 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 3629 21, 0, 0), 3630 GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk", 3631 "dout_misc_busp", 3632 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 3633 21, 0, 0), 3634 GATE(CLK_GOUT_MISC_SPDMA_ACLK, 3635 "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user", 3636 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 3637 21, 0, 0), 3638 GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK, 3639 "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user", 3640 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 3641 21, 0, 0), 3642 GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK, 3643 "gout_misc_ssmt_dit_pclk", "dout_misc_busp", 3644 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 3645 21, 0, 0), 3646 GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK, 3647 "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user", 3648 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 3649 21, 0, 0), 3650 GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK, 3651 "gout_misc_ssmt_pdma_pclk", "dout_misc_busp", 3652 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 3653 21, 0, 0), 3654 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK, 3655 "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user", 3656 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 3657 21, 0, 0), 3658 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK, 3659 "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp", 3660 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 3661 21, 0, 0), 3662 GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK, 3663 "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user", 3664 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 3665 21, 0, 0), 3666 GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK, 3667 "gout_misc_ssmt_rtic_pclk", "dout_misc_busp", 3668 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 3669 21, 0, 0), 3670 GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK, 3671 "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user", 3672 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 3673 21, 0, 0), 3674 GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK, 3675 "gout_misc_ssmt_spdma_pclk", "dout_misc_busp", 3676 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 3677 21, 0, 0), 3678 GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK, 3679 "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user", 3680 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 3681 21, 0, 0), 3682 GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK, 3683 "gout_misc_ssmt_sss_pclk", "dout_misc_busp", 3684 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 3685 21, 0, 0), 3686 GATE(CLK_GOUT_MISC_SSS_I_ACLK, 3687 "gout_misc_sss_i_aclk", "mout_misc_bus_user", 3688 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 3689 21, 0, 0), 3690 GATE(CLK_GOUT_MISC_SSS_I_PCLK, 3691 "gout_misc_sss_i_pclk", "dout_misc_busp", 3692 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 3693 21, 0, 0), 3694 GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2, 3695 "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user", 3696 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 3697 21, 0, 0), 3698 GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1, 3699 "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user", 3700 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 3701 21, 0, 0), 3702 GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK, 3703 "gout_misc_sysreg_misc_pclk", "dout_misc_busp", 3704 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 3705 21, 0, 0), 3706 GATE(CLK_GOUT_MISC_TMU_SUB_PCLK, 3707 "gout_misc_tmu_sub_pclk", "dout_misc_busp", 3708 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 3709 21, 0, 0), 3710 GATE(CLK_GOUT_MISC_TMU_TOP_PCLK, 3711 "gout_misc_tmu_top_pclk", "dout_misc_busp", 3712 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 3713 21, 0, 0), 3714 GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK, 3715 "gout_misc_wdt_cluster0_pclk", "dout_misc_busp", 3716 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 3717 21, 0, 0), 3718 GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK, 3719 "gout_misc_wdt_cluster1_pclk", "dout_misc_busp", 3720 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 3721 21, 0, 0), 3722 GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK, 3723 "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user", 3724 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 3725 21, 0, 0), 3726 }; 3727 3728 static const struct samsung_cmu_info misc_cmu_info __initconst = { 3729 .mux_clks = misc_mux_clks, 3730 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), 3731 .div_clks = misc_div_clks, 3732 .nr_div_clks = ARRAY_SIZE(misc_div_clks), 3733 .gate_clks = misc_gate_clks, 3734 .nr_gate_clks = ARRAY_SIZE(misc_gate_clks), 3735 .nr_clk_ids = CLKS_NR_MISC, 3736 .clk_regs = misc_clk_regs, 3737 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), 3738 .sysreg_clk_regs = dcrg_memclk_sysreg, 3739 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg), 3740 .clk_name = "bus", 3741 .auto_clock_gate = true, 3742 .gate_dbg_offset = GS101_GATE_DBG_OFFSET, 3743 .option_offset = MISC_CMU_MISC_CONTROLLER_OPTION, 3744 .drcg_offset = GS101_DRCG_EN_OFFSET, 3745 .memclk_offset = GS101_MEMCLK_OFFSET, 3746 }; 3747 3748 static void __init gs101_cmu_misc_init(struct device_node *np) 3749 { 3750 exynos_arm64_register_cmu(NULL, np, &misc_cmu_info); 3751 } 3752 3753 /* Register CMU_MISC early, as it's needed for MCT timer */ 3754 CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc", 3755 gs101_cmu_misc_init); 3756 3757 /* ---- CMU_PERIC0 ---------------------------------------------------------- */ 3758 3759 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */ 3760 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 3761 #define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 3762 #define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 3763 #define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 3764 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 3765 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 3766 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 3767 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 3768 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 3769 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 3770 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 3771 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 3772 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 3773 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 3774 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 3775 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 3776 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 3777 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 3778 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 3779 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 3780 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 3781 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 3782 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 3783 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 3784 #define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 3785 #define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 3786 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 3787 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 3788 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c 3789 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 3790 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 3791 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 3792 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 3793 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 3794 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c 3795 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 3796 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 3797 #define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 3798 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 3799 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 3800 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c 3801 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 3802 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 3803 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018 3804 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c 3805 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020 3806 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024 3807 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028 3808 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c 3809 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030 3810 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034 3811 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038 3812 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c 3813 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040 3814 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044 3815 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048 3816 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c 3817 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050 3818 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054 3819 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058 3820 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c 3821 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060 3822 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064 3823 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068 3824 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c 3825 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070 3826 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074 3827 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078 3828 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c 3829 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080 3830 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084 3831 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088 3832 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c 3833 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090 3834 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094 3835 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098 3836 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c 3837 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4 3838 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8 3839 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0 3840 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 3841 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8 3842 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc 3843 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4 3844 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8 3845 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc 3846 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0 3847 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4 3848 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8 3849 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc 3850 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0 3851 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4 3852 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8 3853 #define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 3854 #define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 3855 #define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 3856 #define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c 3857 #define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 3858 #define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 3859 #define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 3860 #define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c 3861 #define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 3862 #define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 3863 #define QCH_CON_GPC_PERIC0_QCH 0x3028 3864 #define QCH_CON_GPIO_PERIC0_QCH 0x302c 3865 #define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 3866 #define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 3867 #define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 3868 #define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c 3869 #define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 3870 #define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 3871 #define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 3872 #define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c 3873 #define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 3874 #define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 3875 #define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 3876 #define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c 3877 #define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 3878 #define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 3879 #define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 3880 #define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c 3881 #define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 3882 #define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 3883 #define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 3884 #define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c 3885 #define QCH_CON_SYSREG_PERIC0_QCH 0x3080 3886 #define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 3887 3888 static const unsigned long peric0_clk_regs[] __initconst = { 3889 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 3890 PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, 3891 PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 3892 PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, 3893 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 3894 PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, 3895 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 3896 PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, 3897 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 3898 PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, 3899 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 3900 PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, 3901 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 3902 PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, 3903 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 3904 PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, 3905 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 3906 PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, 3907 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 3908 PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, 3909 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 3910 PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, 3911 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 3912 PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, 3913 PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 3914 CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, 3915 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 3916 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 3917 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 3918 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 3919 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 3920 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 3921 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 3922 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 3923 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 3924 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 3925 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 3926 CLK_CON_BUF_CLKBUF_PERIC0_IP, 3927 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 3928 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 3929 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 3930 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 3931 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 3932 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 3933 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 3934 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 3935 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 3936 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 3937 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 3938 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 3939 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 3940 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 3941 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 3942 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 3943 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 3944 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 3945 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 3946 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 3947 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 3948 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 3949 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 3950 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 3951 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 3952 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 3953 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 3954 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 3955 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 3956 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 3957 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 3958 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 3959 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 3960 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 3961 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 3962 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 3963 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 3964 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 3965 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 3966 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 3967 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 3968 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, 3969 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 3970 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 3971 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 3972 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 3973 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 3974 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 3975 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 3976 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 3977 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 3978 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 3979 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 3980 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 3981 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 3982 DMYQCH_CON_PERIC0_TOP0_QCH_S1, 3983 DMYQCH_CON_PERIC0_TOP0_QCH_S2, 3984 DMYQCH_CON_PERIC0_TOP0_QCH_S3, 3985 DMYQCH_CON_PERIC0_TOP0_QCH_S4, 3986 DMYQCH_CON_PERIC0_TOP0_QCH_S5, 3987 DMYQCH_CON_PERIC0_TOP0_QCH_S6, 3988 DMYQCH_CON_PERIC0_TOP0_QCH_S7, 3989 DMYQCH_CON_PERIC0_TOP0_QCH_S8, 3990 PCH_CON_LHM_AXI_P_PERIC0_PCH, 3991 QCH_CON_D_TZPC_PERIC0_QCH, 3992 QCH_CON_GPC_PERIC0_QCH, 3993 QCH_CON_GPIO_PERIC0_QCH, 3994 QCH_CON_LHM_AXI_P_PERIC0_QCH, 3995 QCH_CON_PERIC0_CMU_PERIC0_QCH, 3996 QCH_CON_PERIC0_TOP0_QCH_I3C1, 3997 QCH_CON_PERIC0_TOP0_QCH_I3C2, 3998 QCH_CON_PERIC0_TOP0_QCH_I3C3, 3999 QCH_CON_PERIC0_TOP0_QCH_I3C4, 4000 QCH_CON_PERIC0_TOP0_QCH_I3C5, 4001 QCH_CON_PERIC0_TOP0_QCH_I3C6, 4002 QCH_CON_PERIC0_TOP0_QCH_I3C7, 4003 QCH_CON_PERIC0_TOP0_QCH_I3C8, 4004 QCH_CON_PERIC0_TOP0_QCH_USI1_USI, 4005 QCH_CON_PERIC0_TOP0_QCH_USI2_USI, 4006 QCH_CON_PERIC0_TOP0_QCH_USI3_USI, 4007 QCH_CON_PERIC0_TOP0_QCH_USI4_USI, 4008 QCH_CON_PERIC0_TOP0_QCH_USI5_USI, 4009 QCH_CON_PERIC0_TOP0_QCH_USI6_USI, 4010 QCH_CON_PERIC0_TOP0_QCH_USI7_USI, 4011 QCH_CON_PERIC0_TOP0_QCH_USI8_USI, 4012 QCH_CON_PERIC0_TOP1_QCH_USI0_UART, 4013 QCH_CON_PERIC0_TOP1_QCH_USI14_UART, 4014 QCH_CON_SYSREG_PERIC0_QCH, 4015 QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, 4016 }; 4017 4018 /* List of parent clocks for Muxes in CMU_PERIC0 */ 4019 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; 4020 PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 4021 PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 4022 PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 4023 4024 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { 4025 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", 4026 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), 4027 MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", 4028 mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), 4029 MUX(CLK_MOUT_PERIC0_USI0_UART_USER, 4030 "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, 4031 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), 4032 nMUX(CLK_MOUT_PERIC0_USI14_USI_USER, 4033 "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, 4034 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), 4035 nMUX(CLK_MOUT_PERIC0_USI1_USI_USER, 4036 "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, 4037 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), 4038 nMUX(CLK_MOUT_PERIC0_USI2_USI_USER, 4039 "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, 4040 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), 4041 nMUX(CLK_MOUT_PERIC0_USI3_USI_USER, 4042 "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, 4043 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), 4044 nMUX(CLK_MOUT_PERIC0_USI4_USI_USER, 4045 "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, 4046 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), 4047 nMUX(CLK_MOUT_PERIC0_USI5_USI_USER, 4048 "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, 4049 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), 4050 nMUX(CLK_MOUT_PERIC0_USI6_USI_USER, 4051 "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, 4052 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), 4053 nMUX(CLK_MOUT_PERIC0_USI7_USI_USER, 4054 "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, 4055 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), 4056 nMUX(CLK_MOUT_PERIC0_USI8_USI_USER, 4057 "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, 4058 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), 4059 }; 4060 4061 static const struct samsung_div_clock peric0_div_clks[] __initconst = { 4062 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", 4063 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4), 4064 DIV(CLK_DOUT_PERIC0_USI0_UART, 4065 "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", 4066 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4), 4067 DIV_F(CLK_DOUT_PERIC0_USI14_USI, 4068 "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", 4069 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4, 4070 CLK_SET_RATE_PARENT, 0), 4071 DIV_F(CLK_DOUT_PERIC0_USI1_USI, 4072 "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", 4073 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4, 4074 CLK_SET_RATE_PARENT, 0), 4075 DIV_F(CLK_DOUT_PERIC0_USI2_USI, 4076 "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", 4077 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4, 4078 CLK_SET_RATE_PARENT, 0), 4079 DIV_F(CLK_DOUT_PERIC0_USI3_USI, 4080 "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", 4081 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4, 4082 CLK_SET_RATE_PARENT, 0), 4083 DIV_F(CLK_DOUT_PERIC0_USI4_USI, 4084 "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", 4085 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4, 4086 CLK_SET_RATE_PARENT, 0), 4087 DIV_F(CLK_DOUT_PERIC0_USI5_USI, 4088 "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", 4089 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4, 4090 CLK_SET_RATE_PARENT, 0), 4091 DIV_F(CLK_DOUT_PERIC0_USI6_USI, 4092 "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", 4093 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4, 4094 CLK_SET_RATE_PARENT, 0), 4095 DIV_F(CLK_DOUT_PERIC0_USI7_USI, 4096 "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", 4097 CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4, 4098 CLK_SET_RATE_PARENT, 0), 4099 DIV_F(CLK_DOUT_PERIC0_USI8_USI, 4100 "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", 4101 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4, 4102 CLK_SET_RATE_PARENT, 0), 4103 }; 4104 4105 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { 4106 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 4107 GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, 4108 "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", 4109 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 4110 21, CLK_IS_CRITICAL, 0), 4111 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, 4112 "gout_peric0_clk_peric0_oscclk_clk", "oscclk", 4113 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 4114 21, 0, 0), 4115 GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, 4116 "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", 4117 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 4118 21, 0, 0), 4119 GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, 4120 "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", 4121 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 4122 21, 0, 0), 4123 GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, 4124 "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", 4125 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 4126 21, CLK_IGNORE_UNUSED, 0), 4127 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 4128 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, 4129 "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", 4130 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 4131 21, CLK_IS_CRITICAL, 0), 4132 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, 4133 "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", 4134 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 4135 21, CLK_SET_RATE_PARENT, 0), 4136 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, 4137 "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", 4138 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 4139 21, CLK_SET_RATE_PARENT, 0), 4140 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, 4141 "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", 4142 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 4143 21, 0, 0), 4144 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, 4145 "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", 4146 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 4147 21, 0, 0), 4148 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, 4149 "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", 4150 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 4151 21, 0, 0), 4152 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, 4153 "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", 4154 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 4155 21, 0, 0), 4156 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, 4157 "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", 4158 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 4159 21, 0, 0), 4160 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, 4161 "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", 4162 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 4163 21, 0, 0), 4164 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, 4165 "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", 4166 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 4167 21, CLK_SET_RATE_PARENT, 0), 4168 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, 4169 "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", 4170 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 4171 21, CLK_SET_RATE_PARENT, 0), 4172 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, 4173 "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", 4174 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 4175 21, CLK_SET_RATE_PARENT, 0), 4176 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, 4177 "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", 4178 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 4179 21, CLK_SET_RATE_PARENT, 0), 4180 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, 4181 "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", 4182 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 4183 21, CLK_SET_RATE_PARENT, 0), 4184 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, 4185 "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", 4186 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 4187 21, CLK_SET_RATE_PARENT, 0), 4188 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, 4189 "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", 4190 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 4191 21, 0, 0), 4192 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, 4193 "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", 4194 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 4195 21, 0, 0), 4196 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, 4197 "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", 4198 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 4199 21, 0, 0), 4200 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, 4201 "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", 4202 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 4203 21, 0, 0), 4204 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, 4205 "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", 4206 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 4207 21, 0, 0), 4208 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, 4209 "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", 4210 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 4211 21, 0, 0), 4212 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, 4213 "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", 4214 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 4215 21, 0, 0), 4216 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, 4217 "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", 4218 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 4219 21, 0, 0), 4220 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, 4221 "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", 4222 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 4223 21, 0, 0), 4224 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, 4225 "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", 4226 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 4227 21, 0, 0), 4228 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, 4229 "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", 4230 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 4231 21, 0, 0), 4232 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, 4233 "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", 4234 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 4235 21, 0, 0), 4236 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, 4237 "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", 4238 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 4239 21, 0, 0), 4240 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, 4241 "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", 4242 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 4243 21, 0, 0), 4244 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, 4245 "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", 4246 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 4247 21, 0, 0), 4248 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, 4249 "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", 4250 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 4251 21, 0, 0), 4252 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, 4253 "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", 4254 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 4255 21, 0, 0), 4256 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, 4257 "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", 4258 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 4259 21, 0, 0), 4260 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 4261 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, 4262 "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", 4263 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 4264 21, CLK_IS_CRITICAL, 0), 4265 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, 4266 "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", 4267 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 4268 21, CLK_SET_RATE_PARENT, 0), 4269 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 4270 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, 4271 "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", 4272 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 4273 21, CLK_IS_CRITICAL, 0), 4274 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, 4275 "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", 4276 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, 4277 21, 0, 0), 4278 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, 4279 "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", 4280 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 4281 21, 0, 0), 4282 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, 4283 "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", 4284 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 4285 21, 0, 0), 4286 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, 4287 "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", 4288 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 4289 21, 0, 0), 4290 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, 4291 "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", 4292 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 4293 21, 0, 0), 4294 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, 4295 "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", 4296 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 4297 21, 0, 0), 4298 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, 4299 "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", 4300 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 4301 21, 0, 0), 4302 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, 4303 "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", 4304 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 4305 21, 0, 0), 4306 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, 4307 "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", 4308 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 4309 21, 0, 0), 4310 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, 4311 "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", 4312 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 4313 21, 0, 0), 4314 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, 4315 "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", 4316 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 4317 21, 0, 0), 4318 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, 4319 "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", 4320 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 4321 21, 0, 0), 4322 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, 4323 "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", 4324 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 4325 21, 0, 0), 4326 GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, 4327 "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", 4328 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 4329 21, 0, 0), 4330 }; 4331 4332 static const unsigned long dcrg_sysreg[] __initconst = { 4333 GS101_DRCG_EN_OFFSET, 4334 }; 4335 4336 static const struct samsung_cmu_info peric0_cmu_info __initconst = { 4337 .mux_clks = peric0_mux_clks, 4338 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 4339 .div_clks = peric0_div_clks, 4340 .nr_div_clks = ARRAY_SIZE(peric0_div_clks), 4341 .gate_clks = peric0_gate_clks, 4342 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 4343 .nr_clk_ids = CLKS_NR_PERIC0, 4344 .clk_regs = peric0_clk_regs, 4345 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 4346 .sysreg_clk_regs = dcrg_sysreg, 4347 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_sysreg), 4348 .clk_name = "bus", 4349 .auto_clock_gate = true, 4350 .gate_dbg_offset = GS101_GATE_DBG_OFFSET, 4351 .option_offset = PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 4352 .drcg_offset = GS101_DRCG_EN_OFFSET, 4353 }; 4354 4355 /* ---- CMU_PERIC1 ---------------------------------------------------------- */ 4356 4357 /* Register Offset definitions for CMU_PERIC1 (0x10c00000) */ 4358 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 4359 #define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 4360 #define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610 4361 #define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614 4362 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620 4363 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624 4364 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630 4365 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634 4366 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640 4367 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644 4368 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650 4369 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654 4370 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660 4371 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664 4372 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670 4373 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674 4374 #define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800 4375 #define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810 4376 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 4377 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804 4378 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 4379 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c 4380 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 4381 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 4382 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818 4383 #define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000 4384 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004 4385 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008 4386 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c 4387 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010 4388 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014 4389 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 4390 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c 4391 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020 4392 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024 4393 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028 4394 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c 4395 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030 4396 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034 4397 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038 4398 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c 4399 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040 4400 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044 4401 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048 4402 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c 4403 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050 4404 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054 4405 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058 4406 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c 4407 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060 4408 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064 4409 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068 4410 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c 4411 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070 4412 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074 4413 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078 4414 #define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000 4415 #define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004 4416 #define QCH_CON_D_TZPC_PERIC1_QCH 0x3008 4417 #define QCH_CON_GPC_PERIC1_QCH 0x300c 4418 #define QCH_CON_GPIO_PERIC1_QCH 0x3010 4419 #define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014 4420 #define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018 4421 #define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c 4422 #define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020 4423 #define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024 4424 #define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028 4425 #define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c 4426 #define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030 4427 #define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034 4428 #define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038 4429 #define QCH_CON_SYSREG_PERIC1_QCH 0x303c 4430 #define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00 4431 4432 static const unsigned long peric1_clk_regs[] __initconst = { 4433 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4434 PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, 4435 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4436 PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER, 4437 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4438 PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4439 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4440 PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4441 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4442 PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4443 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4444 PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4445 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4446 PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4447 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4448 PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4449 PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 4450 CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0, 4451 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 4452 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 4453 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 4454 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 4455 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 4456 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 4457 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 4458 CLK_CON_BUF_CLKBUF_PERIC1_IP, 4459 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 4460 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 4461 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 4462 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 4463 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 4464 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 4465 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 4466 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 4467 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 4468 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 4469 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 4470 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 4471 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 4472 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 4473 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 4474 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, 4475 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 4476 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 4477 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 4478 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 4479 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 4480 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 4481 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 4482 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 4483 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 4484 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 4485 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 4486 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 4487 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 4488 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 4489 DMYQCH_CON_PERIC1_TOP0_QCH_S, 4490 PCH_CON_LHM_AXI_P_PERIC1_PCH, 4491 QCH_CON_D_TZPC_PERIC1_QCH, 4492 QCH_CON_GPC_PERIC1_QCH, 4493 QCH_CON_GPIO_PERIC1_QCH, 4494 QCH_CON_LHM_AXI_P_PERIC1_QCH, 4495 QCH_CON_PERIC1_CMU_PERIC1_QCH, 4496 QCH_CON_PERIC1_TOP0_QCH_I3C0, 4497 QCH_CON_PERIC1_TOP0_QCH_PWM, 4498 QCH_CON_PERIC1_TOP0_QCH_USI0_USI, 4499 QCH_CON_PERIC1_TOP0_QCH_USI10_USI, 4500 QCH_CON_PERIC1_TOP0_QCH_USI11_USI, 4501 QCH_CON_PERIC1_TOP0_QCH_USI12_USI, 4502 QCH_CON_PERIC1_TOP0_QCH_USI13_USI, 4503 QCH_CON_PERIC1_TOP0_QCH_USI9_USI, 4504 QCH_CON_SYSREG_PERIC1_QCH, 4505 QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1, 4506 }; 4507 4508 /* List of parent clocks for Muxes in CMU_PERIC1 */ 4509 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" }; 4510 PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" }; 4511 4512 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { 4513 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", 4514 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), 4515 MUX(CLK_MOUT_PERIC1_I3C_USER, 4516 "mout_peric1_i3c_user", mout_peric1_nonbususer_p, 4517 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1), 4518 nMUX(CLK_MOUT_PERIC1_USI0_USI_USER, 4519 "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, 4520 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), 4521 nMUX(CLK_MOUT_PERIC1_USI10_USI_USER, 4522 "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, 4523 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), 4524 nMUX(CLK_MOUT_PERIC1_USI11_USI_USER, 4525 "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, 4526 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), 4527 nMUX(CLK_MOUT_PERIC1_USI12_USI_USER, 4528 "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, 4529 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), 4530 nMUX(CLK_MOUT_PERIC1_USI13_USI_USER, 4531 "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, 4532 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), 4533 nMUX(CLK_MOUT_PERIC1_USI9_USI_USER, 4534 "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, 4535 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), 4536 }; 4537 4538 static const struct samsung_div_clock peric1_div_clks[] __initconst = { 4539 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user", 4540 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), 4541 DIV_F(CLK_DOUT_PERIC1_USI0_USI, 4542 "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", 4543 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4, 4544 CLK_SET_RATE_PARENT, 0), 4545 DIV_F(CLK_DOUT_PERIC1_USI10_USI, 4546 "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", 4547 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4, 4548 CLK_SET_RATE_PARENT, 0), 4549 DIV_F(CLK_DOUT_PERIC1_USI11_USI, 4550 "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", 4551 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4, 4552 CLK_SET_RATE_PARENT, 0), 4553 DIV_F(CLK_DOUT_PERIC1_USI12_USI, 4554 "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", 4555 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4, 4556 CLK_SET_RATE_PARENT, 0), 4557 DIV_F(CLK_DOUT_PERIC1_USI13_USI, 4558 "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", 4559 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4, 4560 CLK_SET_RATE_PARENT, 0), 4561 DIV_F(CLK_DOUT_PERIC1_USI9_USI, 4562 "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", 4563 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4, 4564 CLK_SET_RATE_PARENT, 0), 4565 }; 4566 4567 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { 4568 GATE(CLK_GOUT_PERIC1_PCLK, 4569 "gout_peric1_peric1_pclk", "mout_peric1_bus_user", 4570 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 4571 21, CLK_IS_CRITICAL, 0), 4572 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK, 4573 "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c", 4574 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 4575 21, 0, 0), 4576 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK, 4577 "gout_peric1_clk_peric1_oscclk_clk", "oscclk", 4578 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 4579 21, 0, 0), 4580 GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK, 4581 "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user", 4582 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 4583 21, 0, 0), 4584 GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK, 4585 "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user", 4586 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 4587 21, 0, 0), 4588 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK, 4589 "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user", 4590 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 4591 21, CLK_IGNORE_UNUSED, 0), 4592 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK, 4593 "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user", 4594 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 4595 21, CLK_IS_CRITICAL, 0), 4596 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, 4597 "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", 4598 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 4599 21, CLK_SET_RATE_PARENT, 0), 4600 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2, 4601 "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi", 4602 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 4603 21, CLK_SET_RATE_PARENT, 0), 4604 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3, 4605 "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi", 4606 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 4607 21, CLK_SET_RATE_PARENT, 0), 4608 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4, 4609 "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi", 4610 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 4611 21, CLK_SET_RATE_PARENT, 0), 4612 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5, 4613 "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi", 4614 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 4615 21, CLK_SET_RATE_PARENT, 0), 4616 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6, 4617 "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi", 4618 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 4619 21, CLK_SET_RATE_PARENT, 0), 4620 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8, 4621 "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c", 4622 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 4623 21, 0, 0), 4624 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1, 4625 "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user", 4626 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 4627 21, 0, 0), 4628 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15, 4629 "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user", 4630 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, 4631 21, 0, 0), 4632 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2, 4633 "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user", 4634 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 4635 21, 0, 0), 4636 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3, 4637 "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user", 4638 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 4639 21, 0, 0), 4640 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4, 4641 "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user", 4642 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 4643 21, 0, 0), 4644 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5, 4645 "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user", 4646 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 4647 21, 0, 0), 4648 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6, 4649 "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user", 4650 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 4651 21, 0, 0), 4652 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8, 4653 "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user", 4654 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 4655 21, 0, 0), 4656 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK, 4657 "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user", 4658 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 4659 21, 0, 0), 4660 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK, 4661 "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi", 4662 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 4663 21, 0, 0), 4664 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK, 4665 "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi", 4666 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 4667 21, 0, 0), 4668 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK, 4669 "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi", 4670 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 4671 21, 0, 0), 4672 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK, 4673 "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi", 4674 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 4675 21, 0, 0), 4676 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK, 4677 "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi", 4678 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 4679 21, 0, 0), 4680 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK, 4681 "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi", 4682 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 4683 21, 0, 0), 4684 GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK, 4685 "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user", 4686 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 4687 21, 0, 0), 4688 }; 4689 4690 static const struct samsung_cmu_info peric1_cmu_info __initconst = { 4691 .mux_clks = peric1_mux_clks, 4692 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 4693 .div_clks = peric1_div_clks, 4694 .nr_div_clks = ARRAY_SIZE(peric1_div_clks), 4695 .gate_clks = peric1_gate_clks, 4696 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 4697 .nr_clk_ids = CLKS_NR_PERIC1, 4698 .clk_regs = peric1_clk_regs, 4699 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 4700 .sysreg_clk_regs = dcrg_sysreg, 4701 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_sysreg), 4702 .clk_name = "bus", 4703 .auto_clock_gate = true, 4704 .gate_dbg_offset = GS101_GATE_DBG_OFFSET, 4705 .option_offset = PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 4706 .drcg_offset = GS101_DRCG_EN_OFFSET, 4707 }; 4708 4709 /* ---- platform_driver ----------------------------------------------------- */ 4710 4711 static int __init gs101_cmu_probe(struct platform_device *pdev) 4712 { 4713 const struct samsung_cmu_info *info; 4714 struct device *dev = &pdev->dev; 4715 4716 info = of_device_get_match_data(dev); 4717 exynos_arm64_register_cmu(dev, dev->of_node, info); 4718 4719 return 0; 4720 } 4721 4722 static const struct of_device_id gs101_cmu_of_match[] = { 4723 { 4724 .compatible = "google,gs101-cmu-apm", 4725 .data = &apm_cmu_info, 4726 }, { 4727 .compatible = "google,gs101-cmu-dpu", 4728 .data = &dpu_cmu_info, 4729 }, { 4730 .compatible = "google,gs101-cmu-hsi0", 4731 .data = &hsi0_cmu_info, 4732 }, { 4733 .compatible = "google,gs101-cmu-hsi2", 4734 .data = &hsi2_cmu_info, 4735 }, { 4736 .compatible = "google,gs101-cmu-peric0", 4737 .data = &peric0_cmu_info, 4738 }, { 4739 .compatible = "google,gs101-cmu-peric1", 4740 .data = &peric1_cmu_info, 4741 }, { 4742 }, 4743 }; 4744 4745 static struct platform_driver gs101_cmu_driver __refdata = { 4746 .driver = { 4747 .name = "gs101-cmu", 4748 .of_match_table = gs101_cmu_of_match, 4749 .suppress_bind_attrs = true, 4750 }, 4751 .probe = gs101_cmu_probe, 4752 }; 4753 4754 static int __init gs101_cmu_init(void) 4755 { 4756 return platform_driver_register(&gs101_cmu_driver); 4757 } 4758 core_initcall(gs101_cmu_init); 4759