1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2023 Linaro Ltd. 4 * Author: Peter Griffin <peter.griffin@linaro.org> 5 * 6 * Common Clock Framework support for GS101. 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 14 #include <dt-bindings/clock/google,gs101.h> 15 16 #include "clk.h" 17 #include "clk-exynos-arm64.h" 18 #include "clk-pll.h" 19 20 /* NOTE: Must be equal to the last clock ID increased by one */ 21 #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) 22 #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) 23 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1) 24 #define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1) 25 #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) 26 #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) 27 #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) 28 29 /* ---- CMU_TOP ------------------------------------------------------------- */ 30 31 /* Register Offset definitions for CMU_TOP (0x1e080000) */ 32 #define PLL_LOCKTIME_PLL_SHARED0 0x0000 33 #define PLL_LOCKTIME_PLL_SHARED1 0x0004 34 #define PLL_LOCKTIME_PLL_SHARED2 0x0008 35 #define PLL_LOCKTIME_PLL_SHARED3 0x000c 36 #define PLL_LOCKTIME_PLL_SPARE 0x0010 37 #define PLL_CON0_PLL_SHARED0 0x0100 38 #define PLL_CON1_PLL_SHARED0 0x0104 39 #define PLL_CON2_PLL_SHARED0 0x0108 40 #define PLL_CON3_PLL_SHARED0 0x010c 41 #define PLL_CON4_PLL_SHARED0 0x0110 42 #define PLL_CON0_PLL_SHARED1 0x0140 43 #define PLL_CON1_PLL_SHARED1 0x0144 44 #define PLL_CON2_PLL_SHARED1 0x0148 45 #define PLL_CON3_PLL_SHARED1 0x014c 46 #define PLL_CON4_PLL_SHARED1 0x0150 47 #define PLL_CON0_PLL_SHARED2 0x0180 48 #define PLL_CON1_PLL_SHARED2 0x0184 49 #define PLL_CON2_PLL_SHARED2 0x0188 50 #define PLL_CON3_PLL_SHARED2 0x018c 51 #define PLL_CON4_PLL_SHARED2 0x0190 52 #define PLL_CON0_PLL_SHARED3 0x01c0 53 #define PLL_CON1_PLL_SHARED3 0x01c4 54 #define PLL_CON2_PLL_SHARED3 0x01c8 55 #define PLL_CON3_PLL_SHARED3 0x01cc 56 #define PLL_CON4_PLL_SHARED3 0x01d0 57 #define PLL_CON0_PLL_SPARE 0x0200 58 #define PLL_CON1_PLL_SPARE 0x0204 59 #define PLL_CON2_PLL_SPARE 0x0208 60 #define PLL_CON3_PLL_SPARE 0x020c 61 #define PLL_CON4_PLL_SPARE 0x0210 62 #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800 63 #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810 64 #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840 65 #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844 66 #define CMU_HCHGEN_CLKMUX 0x0850 67 #define POWER_FAIL_DETECT_PLL 0x0864 68 #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870 69 #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874 70 #define EARLY_WAKEUP_APM_CTRL 0x0878 71 #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c 72 #define EARLY_WAKEUP_DPU_CTRL 0x0880 73 #define EARLY_WAKEUP_CSIS_CTRL 0x0884 74 #define EARLY_WAKEUP_APM_DEST 0x0890 75 #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894 76 #define EARLY_WAKEUP_DPU_DEST 0x0898 77 #define EARLY_WAKEUP_CSIS_DEST 0x089c 78 #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0 79 #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4 80 #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8 81 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0 82 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4 83 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8 84 #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0 85 #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4 86 #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8 87 #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0 88 #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4 89 #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8 90 #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000 91 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004 92 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008 93 #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c 94 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010 95 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014 96 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018 97 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c 98 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020 99 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024 100 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028 101 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c 102 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030 103 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034 104 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038 105 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c 106 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040 107 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044 108 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048 109 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c 110 #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050 111 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054 112 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058 113 #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c 114 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060 115 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064 116 #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068 117 #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c 118 #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070 119 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074 120 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078 121 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c 122 #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080 123 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084 124 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088 125 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c 126 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090 127 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094 128 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098 129 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c 130 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0 131 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4 132 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8 133 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac 134 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0 135 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4 136 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8 137 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc 138 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0 139 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4 140 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8 141 #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc 142 #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0 143 #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4 144 #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8 145 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc 146 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0 147 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4 148 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8 149 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec 150 #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0 151 #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4 152 #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8 153 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc 154 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100 155 #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104 156 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108 157 #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800 158 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804 159 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808 160 #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c 161 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 162 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 163 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 164 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c 165 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820 166 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824 167 #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828 168 #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c 169 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830 170 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834 171 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838 172 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c 173 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840 174 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844 175 #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848 176 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c 177 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850 178 #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854 179 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858 180 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c 181 #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860 182 #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864 183 #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868 184 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c 185 #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870 186 #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874 187 #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878 188 #define CLK_CON_DIV_CLKCMU_HPM 0x187c 189 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880 190 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884 191 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888 192 #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c 193 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890 194 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894 195 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898 196 #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c 197 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0 198 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4 199 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8 200 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac 201 #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0 202 #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4 203 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8 204 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc 205 #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0 206 #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4 207 #define CLK_CON_DIV_CLKCMU_OTP 0x18c8 208 #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc 209 #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0 210 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4 211 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8 212 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc 213 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0 214 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4 215 #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8 216 #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec 217 #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0 218 #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4 219 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8 220 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc 221 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900 222 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904 223 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908 224 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c 225 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910 226 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914 227 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918 228 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c 229 #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920 230 #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000 231 #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004 232 #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008 233 #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c 234 #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010 235 #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014 236 #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018 237 #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c 238 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020 239 #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024 240 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028 241 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c 242 #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030 243 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034 244 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038 245 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c 246 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040 247 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044 248 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048 249 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c 250 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050 251 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054 252 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058 253 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c 254 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060 255 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064 256 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068 257 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c 258 #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070 259 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074 260 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078 261 #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c 262 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080 263 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084 264 #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088 265 #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c 266 #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090 267 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094 268 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098 269 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c 270 #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0 271 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4 272 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8 273 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac 274 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0 275 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4 276 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8 277 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc 278 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0 279 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4 280 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8 281 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc 282 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0 283 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4 284 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8 285 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc 286 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0 287 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4 288 #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8 289 #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec 290 #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0 291 #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4 292 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8 293 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc 294 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100 295 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104 296 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108 297 #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c 298 #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110 299 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114 300 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118 301 #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c 302 #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000 303 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004 304 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008 305 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c 306 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010 307 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014 308 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018 309 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c 310 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020 311 #define DMYQCH_CON_OTP_QCH 0x3024 312 #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00 313 #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10 314 #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14 315 #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18 316 #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c 317 #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20 318 #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24 319 #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28 320 #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c 321 #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00 322 #define MIFMIRROR_QUEUE_ENTRY0 0x3e10 323 #define MIFMIRROR_QUEUE_ENTRY1 0x3e14 324 #define MIFMIRROR_QUEUE_ENTRY2 0x3e18 325 #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c 326 #define MIFMIRROR_QUEUE_ENTRY4 0x3e20 327 #define MIFMIRROR_QUEUE_ENTRY5 0x3e24 328 #define MIFMIRROR_QUEUE_ENTRY6 0x3e28 329 #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c 330 #define MIFMIRROR_QUEUE_BUSY 0x3e30 331 #define GENERALIO_ACD_CHANNEL_0 0x3f00 332 #define GENERALIO_ACD_CHANNEL_1 0x3f04 333 #define GENERALIO_ACD_CHANNEL_2 0x3f08 334 #define GENERALIO_ACD_CHANNEL_3 0x3f0c 335 #define GENERALIO_ACD_MASK 0x3f14 336 337 static const unsigned long cmu_top_clk_regs[] __initconst = { 338 PLL_LOCKTIME_PLL_SHARED0, 339 PLL_LOCKTIME_PLL_SHARED1, 340 PLL_LOCKTIME_PLL_SHARED2, 341 PLL_LOCKTIME_PLL_SHARED3, 342 PLL_LOCKTIME_PLL_SPARE, 343 PLL_CON0_PLL_SHARED0, 344 PLL_CON1_PLL_SHARED0, 345 PLL_CON2_PLL_SHARED0, 346 PLL_CON3_PLL_SHARED0, 347 PLL_CON4_PLL_SHARED0, 348 PLL_CON0_PLL_SHARED1, 349 PLL_CON1_PLL_SHARED1, 350 PLL_CON2_PLL_SHARED1, 351 PLL_CON3_PLL_SHARED1, 352 PLL_CON4_PLL_SHARED1, 353 PLL_CON0_PLL_SHARED2, 354 PLL_CON1_PLL_SHARED2, 355 PLL_CON2_PLL_SHARED2, 356 PLL_CON3_PLL_SHARED2, 357 PLL_CON4_PLL_SHARED2, 358 PLL_CON0_PLL_SHARED3, 359 PLL_CON1_PLL_SHARED3, 360 PLL_CON2_PLL_SHARED3, 361 PLL_CON3_PLL_SHARED3, 362 PLL_CON4_PLL_SHARED3, 363 PLL_CON0_PLL_SPARE, 364 PLL_CON1_PLL_SPARE, 365 PLL_CON2_PLL_SPARE, 366 PLL_CON3_PLL_SPARE, 367 PLL_CON4_PLL_SPARE, 368 CMU_CMU_TOP_CONTROLLER_OPTION, 369 CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0, 370 CMU_HCHGEN_CLKMUX_CMU_BOOST, 371 CMU_HCHGEN_CLKMUX_TOP_BOOST, 372 CMU_HCHGEN_CLKMUX, 373 POWER_FAIL_DETECT_PLL, 374 EARLY_WAKEUP_FORCED_0_ENABLE, 375 EARLY_WAKEUP_FORCED_1_ENABLE, 376 EARLY_WAKEUP_APM_CTRL, 377 EARLY_WAKEUP_CLUSTER0_CTRL, 378 EARLY_WAKEUP_DPU_CTRL, 379 EARLY_WAKEUP_CSIS_CTRL, 380 EARLY_WAKEUP_APM_DEST, 381 EARLY_WAKEUP_CLUSTER0_DEST, 382 EARLY_WAKEUP_DPU_DEST, 383 EARLY_WAKEUP_CSIS_DEST, 384 EARLY_WAKEUP_SW_TRIG_APM, 385 EARLY_WAKEUP_SW_TRIG_CLUSTER0, 386 EARLY_WAKEUP_SW_TRIG_DPU, 387 EARLY_WAKEUP_SW_TRIG_CSIS, 388 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 389 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 390 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 391 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 392 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 393 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 394 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 395 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 396 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 397 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 398 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 399 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 400 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 401 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 402 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 403 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 404 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 405 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 406 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 407 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 408 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 409 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 410 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 411 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 412 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 413 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 414 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 415 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 416 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 417 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 418 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 419 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 420 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 421 CLK_CON_MUX_MUX_CLKCMU_HPM, 422 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 423 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 424 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 425 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 426 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 427 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 428 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 429 CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 430 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 431 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 432 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 433 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 434 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 435 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 436 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 437 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 438 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 439 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 440 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 441 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 442 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 443 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 444 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 445 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 446 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 447 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 448 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 449 CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 450 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 451 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 452 CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 453 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 454 CLK_CON_MUX_MUX_CMU_CMUREF, 455 CLK_CON_DIV_CLKCMU_BO_BUS, 456 CLK_CON_DIV_CLKCMU_BUS0_BUS, 457 CLK_CON_DIV_CLKCMU_BUS1_BUS, 458 CLK_CON_DIV_CLKCMU_BUS2_BUS, 459 CLK_CON_DIV_CLKCMU_CIS_CLK0, 460 CLK_CON_DIV_CLKCMU_CIS_CLK1, 461 CLK_CON_DIV_CLKCMU_CIS_CLK2, 462 CLK_CON_DIV_CLKCMU_CIS_CLK3, 463 CLK_CON_DIV_CLKCMU_CIS_CLK4, 464 CLK_CON_DIV_CLKCMU_CIS_CLK5, 465 CLK_CON_DIV_CLKCMU_CIS_CLK6, 466 CLK_CON_DIV_CLKCMU_CIS_CLK7, 467 CLK_CON_DIV_CLKCMU_CORE_BUS, 468 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 469 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 470 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 471 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 472 CLK_CON_DIV_CLKCMU_CSIS_BUS, 473 CLK_CON_DIV_CLKCMU_DISP_BUS, 474 CLK_CON_DIV_CLKCMU_DNS_BUS, 475 CLK_CON_DIV_CLKCMU_DPU_BUS, 476 CLK_CON_DIV_CLKCMU_EH_BUS, 477 CLK_CON_DIV_CLKCMU_G2D_G2D, 478 CLK_CON_DIV_CLKCMU_G2D_MSCL, 479 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 480 CLK_CON_DIV_CLKCMU_G3D_BUSD, 481 CLK_CON_DIV_CLKCMU_G3D_GLB, 482 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 483 CLK_CON_DIV_CLKCMU_GDC_GDC0, 484 CLK_CON_DIV_CLKCMU_GDC_GDC1, 485 CLK_CON_DIV_CLKCMU_GDC_SCSC, 486 CLK_CON_DIV_CLKCMU_HPM, 487 CLK_CON_DIV_CLKCMU_HSI0_BUS, 488 CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 489 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 490 CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 491 CLK_CON_DIV_CLKCMU_HSI1_BUS, 492 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 493 CLK_CON_DIV_CLKCMU_HSI2_BUS, 494 CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 495 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 496 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 497 CLK_CON_DIV_CLKCMU_IPP_BUS, 498 CLK_CON_DIV_CLKCMU_ITP_BUS, 499 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 500 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 501 CLK_CON_DIV_CLKCMU_MFC_MFC, 502 CLK_CON_DIV_CLKCMU_MIF_BUSP, 503 CLK_CON_DIV_CLKCMU_MISC_BUS, 504 CLK_CON_DIV_CLKCMU_MISC_SSS, 505 CLK_CON_DIV_CLKCMU_OTP, 506 CLK_CON_DIV_CLKCMU_PDP_BUS, 507 CLK_CON_DIV_CLKCMU_PDP_VRA, 508 CLK_CON_DIV_CLKCMU_PERIC0_BUS, 509 CLK_CON_DIV_CLKCMU_PERIC0_IP, 510 CLK_CON_DIV_CLKCMU_PERIC1_BUS, 511 CLK_CON_DIV_CLKCMU_PERIC1_IP, 512 CLK_CON_DIV_CLKCMU_TNR_BUS, 513 CLK_CON_DIV_CLKCMU_TPU_BUS, 514 CLK_CON_DIV_CLKCMU_TPU_TPU, 515 CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 516 CLK_CON_DIV_CLKCMU_TPU_UART, 517 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 518 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 519 CLK_CON_DIV_PLL_SHARED0_DIV2, 520 CLK_CON_DIV_PLL_SHARED0_DIV3, 521 CLK_CON_DIV_PLL_SHARED0_DIV4, 522 CLK_CON_DIV_PLL_SHARED0_DIV5, 523 CLK_CON_DIV_PLL_SHARED1_DIV2, 524 CLK_CON_DIV_PLL_SHARED1_DIV3, 525 CLK_CON_DIV_PLL_SHARED1_DIV4, 526 CLK_CON_DIV_PLL_SHARED2_DIV2, 527 CLK_CON_DIV_PLL_SHARED3_DIV2, 528 CLK_CON_GAT_CLKCMU_BUS0_BOOST, 529 CLK_CON_GAT_CLKCMU_BUS1_BOOST, 530 CLK_CON_GAT_CLKCMU_BUS2_BOOST, 531 CLK_CON_GAT_CLKCMU_CORE_BOOST, 532 CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 533 CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 534 CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 535 CLK_CON_GAT_CLKCMU_MIF_BOOST, 536 CLK_CON_GAT_CLKCMU_MIF_SWITCH, 537 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 538 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 539 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 540 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 541 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 542 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 543 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 544 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 545 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 546 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 547 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 548 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 549 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 550 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 551 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 552 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 553 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 554 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 555 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 556 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 557 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 558 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 559 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 560 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 561 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 562 CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, 563 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 564 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 565 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 566 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 567 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 568 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 569 CLK_CON_GAT_GATE_CLKCMU_HPM, 570 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 571 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 572 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 573 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 574 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 575 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 576 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 577 CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 578 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 579 CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 580 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 581 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 582 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 583 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 584 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 585 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 586 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 587 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 588 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 589 CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, 590 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 591 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 592 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 593 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 594 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 595 CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 596 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 597 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 598 CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 599 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 600 DMYQCH_CON_CMU_TOP_CMUREF_QCH, 601 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, 602 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, 603 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, 604 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, 605 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, 606 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, 607 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, 608 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, 609 DMYQCH_CON_OTP_QCH, 610 QUEUE_CTRL_REG_BLK_CMU_CMU_TOP, 611 QUEUE_ENTRY0_BLK_CMU_CMU_TOP, 612 QUEUE_ENTRY1_BLK_CMU_CMU_TOP, 613 QUEUE_ENTRY2_BLK_CMU_CMU_TOP, 614 QUEUE_ENTRY3_BLK_CMU_CMU_TOP, 615 QUEUE_ENTRY4_BLK_CMU_CMU_TOP, 616 QUEUE_ENTRY5_BLK_CMU_CMU_TOP, 617 QUEUE_ENTRY6_BLK_CMU_CMU_TOP, 618 QUEUE_ENTRY7_BLK_CMU_CMU_TOP, 619 MIFMIRROR_QUEUE_CTRL_REG, 620 MIFMIRROR_QUEUE_ENTRY0, 621 MIFMIRROR_QUEUE_ENTRY1, 622 MIFMIRROR_QUEUE_ENTRY2, 623 MIFMIRROR_QUEUE_ENTRY3, 624 MIFMIRROR_QUEUE_ENTRY4, 625 MIFMIRROR_QUEUE_ENTRY5, 626 MIFMIRROR_QUEUE_ENTRY6, 627 MIFMIRROR_QUEUE_ENTRY7, 628 MIFMIRROR_QUEUE_BUSY, 629 GENERALIO_ACD_CHANNEL_0, 630 GENERALIO_ACD_CHANNEL_1, 631 GENERALIO_ACD_CHANNEL_2, 632 GENERALIO_ACD_CHANNEL_3, 633 GENERALIO_ACD_MASK, 634 }; 635 636 static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = { 637 /* CMU_TOP_PURECLKCOMP */ 638 PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 639 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 640 NULL), 641 PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 642 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 643 NULL), 644 PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", 645 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, 646 NULL), 647 PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", 648 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, 649 NULL), 650 PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk", 651 PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE, 652 NULL), 653 }; 654 655 /* List of parent clocks for Muxes in CMU_TOP */ 656 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" }; 657 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" }; 658 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" }; 659 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" }; 660 PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" }; 661 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 662 "fout_shared3_pll", "dout_cmu_shared1_div3", 663 "dout_cmu_shared0_div4", 664 "dout_cmu_shared1_div4", 665 "fout_spare_pll", "oscclk" }; 666 PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4", 667 "dout_cmu_shared1_div4", 668 "dout_cmu_shared2_div2", 669 "dout_cmu_shared3_div2", 670 "fout_spare_pll", "oscclk", 671 "oscclk", "oscclk" }; 672 PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 673 "dout_cmu_shared1_div3", 674 "dout_cmu_shared0_div4", 675 "dout_cmu_shared1_div4", 676 "dout_cmu_shared2_div2", 677 "fout_spare_pll", "oscclk" }; 678 PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2", 679 "dout_cmu_shared1_div2", 680 "fout_shared2_pll", "fout_shared3_pll", 681 "dout_cmu_shared0_div3", 682 "dout_cmu_shared1_div3", 683 "dout_cmu_shared0_div5", "fout_spare_pll" }; 684 PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3", 685 "dout_cmu_shared1_div3", 686 "dout_cmu_shared2_div2", 687 "dout_cmu_shared3_div2", "fout_spare_pll", 688 "oscclk", "oscclk" }; 689 PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4", 690 "dout_cmu_shared1_div4", 691 "dout_cmu_shared2_div2", 692 "dout_cmu_shared3_div2" }; 693 PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost", 694 "gout_cmu_boost_option1" }; 695 PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2", 696 "dout_cmu_shared1_div2", 697 "fout_shared2_pll", "fout_shared3_pll", 698 "dout_cmu_shared0_div3", 699 "dout_cmu_shared1_div3", 700 "dout_cmu_shared0_div5", "fout_spare_pll" }; 701 PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll", 702 "dout_cmu_shared0_div4", 703 "dout_cmu_shared1_div4", 704 "dout_cmu_shared2_div2", "fout_spare_pll", 705 "oscclk", "oscclk" }; 706 PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 707 "dout_cmu_shared1_div2", "fout_shared2_pll", 708 "fout_shared3_pll", "dout_cmu_shared0_div3", 709 "dout_cmu_shared1_div3", "fout_spare_pll" }; 710 PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 711 "dout_cmu_shared1_div2", "fout_shared2_pll", 712 "fout_shared3_pll", "dout_cmu_shared0_div3", 713 "dout_cmu_shared1_div3", "fout_spare_pll" }; 714 PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 715 "dout_cmu_shared1_div2", "fout_shared2_pll", 716 "fout_shared3_pll", "dout_cmu_shared0_div3", 717 "dout_cmu_shared1_div3", "fout_spare_pll" }; 718 PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 719 "dout_cmu_shared1_div3", 720 "dout_cmu_shared0_div4", 721 "dout_cmu_shared1_div4", 722 "dout_cmu_shared2_div2", 723 "fout_spare_pll", "oscclk" }; 724 PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 725 "dout_cmu_shared1_div3", 726 "dout_cmu_shared0_div4", 727 "dout_cmu_shared1_div4", 728 "dout_cmu_shared2_div2", 729 "fout_spare_pll", "oscclk" }; 730 PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 731 "dout_cmu_shared1_div3", 732 "dout_cmu_shared0_div4", 733 "dout_cmu_shared1_div4", 734 "dout_cmu_shared2_div2", 735 "fout_spare_pll", "oscclk" }; 736 PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3", 737 "fout_shared3_pll", 738 "dout_cmu_shared1_div3", 739 "dout_cmu_shared0_div4", 740 "dout_cmu_shared1_div4", 741 "dout_cmu_shared2_div2", 742 "fout_spare_pll", "oscclk" }; 743 PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2", 744 "dout_cmu_shared1_div2", 745 "fout_shared2_pll", "fout_shared3_pll", 746 "dout_cmu_shared0_div3", 747 "dout_cmu_shared1_div3", 748 "dout_cmu_shared0_div5", "fout_spare_pll" }; 749 PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 750 "dout_cmu_shared1_div3", 751 "dout_cmu_shared0_div4", 752 "dout_cmu_shared1_div4", 753 "dout_cmu_shared2_div2", 754 "fout_spare_pll", "oscclk" }; 755 PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4", 756 "dout_cmu_shared1_div4", 757 "dout_cmu_shared2_div2", 758 "dout_cmu_shared3_div2", 759 "fout_spare_pll", "oscclk", 760 "oscclk", "oscclk" }; 761 PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 762 "dout_cmu_shared1_div3", 763 "dout_cmu_shared0_div4", 764 "dout_cmu_shared1_div4", 765 "dout_cmu_shared2_div2", 766 "fout_spare_pll", "oscclk" }; 767 PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2", 768 "dout_cmu_shared1_div2", 769 "fout_shared2_pll", "fout_shared3_pll", 770 "dout_cmu_shared0_div3", 771 "dout_cmu_shared1_div3", 772 "dout_cmu_shared0_div4", "fout_spare_pll" }; 773 PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2", 774 "dout_cmu_shared1_div2", 775 "fout_shared2_pll", "fout_shared3_pll", 776 "dout_cmu_shared0_div3", 777 "dout_cmu_shared1_div3", 778 "dout_cmu_shared0_div4", "fout_spare_pll" }; 779 PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 780 "fout_shared3_pll", "dout_cmu_shared1_div3", 781 "dout_cmu_shared0_div4", 782 "dout_cmu_shared1_div4", 783 "fout_spare_pll", "fout_spare_pll"}; 784 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 785 "dout_cmu_shared1_div3", 786 "dout_cmu_shared0_div4", 787 "dout_cmu_shared1_div4", 788 "dout_cmu_shared2_div2", 789 "fout_spare_pll", "oscclk" }; 790 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 791 "dout_cmu_shared1_div3", 792 "dout_cmu_shared0_div4", 793 "dout_cmu_shared1_div4", 794 "dout_cmu_shared2_div2", 795 "fout_spare_pll", "oscclk" }; 796 PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 797 "dout_cmu_shared1_div3", 798 "dout_cmu_shared0_div4", 799 "dout_cmu_shared1_div4", 800 "dout_cmu_shared2_div2", 801 "fout_spare_pll", "oscclk" }; 802 PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3", 803 "dout_cmu_shared0_div4", 804 "dout_cmu_shared2_div2" }; 805 PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4", 806 "dout_cmu_shared1_div4", 807 "dout_cmu_shared2_div2", 808 "dout_cmu_shared3_div2", 809 "fout_spare_pll", "oscclk", 810 "oscclk", "oscclk" }; 811 PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4", 812 "dout_cmu_shared2_div2", "fout_spare_pll" }; 813 PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" }; 814 PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" }; 815 PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4", 816 "dout_cmu_shared1_div4", 817 "dout_cmu_shared2_div2", 818 "dout_cmu_shared3_div2", 819 "fout_spare_pll" }; 820 PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" }; 821 PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4", 822 "dout_cmu_shared1_div4", 823 "dout_cmu_shared2_div2", 824 "dout_cmu_shared3_div2", 825 "fout_spare_pll", "oscclk", 826 "oscclk", "oscclk" }; 827 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll", 828 "dout_cmu_shared0_div4", "fout_spare_pll" }; 829 PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" }; 830 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4", 831 "dout_cmu_shared2_div2", "fout_spare_pll" }; 832 PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 833 "dout_cmu_shared1_div3", 834 "dout_cmu_shared0_div4", 835 "dout_cmu_shared1_div4", 836 "dout_cmu_shared2_div2", 837 "fout_spare_pll", "oscclk" }; 838 PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 839 "dout_cmu_shared1_div3", 840 "dout_cmu_shared0_div4", 841 "dout_cmu_shared1_div4", 842 "dout_cmu_shared2_div2", 843 "fout_spare_pll", "oscclk" }; 844 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 845 "dout_cmu_shared1_div3", 846 "dout_cmu_shared0_div4", 847 "dout_cmu_shared1_div4", 848 "dout_cmu_shared2_div2", 849 "fout_spare_pll", "oscclk" }; 850 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 851 "dout_cmu_shared1_div3", 852 "dout_cmu_shared0_div4", 853 "dout_cmu_shared1_div4", 854 "dout_cmu_shared2_div2", 855 "fout_spare_pll", "oscclk" }; 856 PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 857 "dout_cmu_shared0_div4", 858 "dout_cmu_shared1_div4", 859 "dout_cmu_shared2_div2", "fout_spare_pll", 860 "oscclk", "oscclk" }; 861 PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4", 862 "dout_cmu_shared1_div4", 863 "dout_cmu_shared0_div5", "fout_spare_pll" }; 864 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", 865 "dout_cmu_shared0_div2", 866 "dout_cmu_shared1_div2", 867 "fout_shared2_pll", "dout_cmu_shared0_div3", 868 "fout_shared3_pll", "fout_spare_pll" }; 869 PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4", 870 "dout_cmu_shared2_div2", 871 "dout_cmu_shared3_div2", "fout_spare_pll" }; 872 PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4", 873 "dout_cmu_shared2_div2", 874 "dout_cmu_shared3_div2", "fout_spare_pll" }; 875 PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 876 "dout_cmu_shared1_div3", 877 "dout_cmu_shared0_div4", 878 "dout_cmu_shared1_div4", 879 "dout_cmu_shared2_div2", 880 "fout_spare_pll", "oscclk" }; 881 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 882 "fout_shared3_pll", "dout_cmu_shared1_div3", 883 "dout_cmu_shared0_div4", 884 "dout_cmu_shared1_div4", 885 "fout_spare_pll", "oscclk" }; 886 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4", 887 "dout_cmu_shared2_div2", 888 "dout_cmu_shared3_div2", "fout_spare_pll" }; 889 PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4", 890 "dout_cmu_shared2_div2", 891 "dout_cmu_shared3_div2", "fout_spare_pll" }; 892 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4", 893 "dout_cmu_shared2_div2", 894 "dout_cmu_shared3_div2", "fout_spare_pll" }; 895 PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4", 896 "dout_cmu_shared2_div2", 897 "dout_cmu_shared3_div2", "fout_spare_pll" }; 898 PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 899 "dout_cmu_shared1_div3", 900 "dout_cmu_shared0_div4", 901 "dout_cmu_shared1_div4", 902 "dout_cmu_shared2_div2", 903 "fout_spare_pll", "oscclk" }; 904 PNAME(mout_cmu_top_boost_option1_p) = { "oscclk", 905 "gout_cmu_boost_option1" }; 906 PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4", 907 "dout_cmu_shared1_div4", 908 "dout_cmu_shared2_div2", 909 "dout_cmu_shared3_div2" }; 910 PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2", 911 "dout_cmu_shared1_div2", 912 "fout_shared2_pll", 913 "fout_shared3_pll", 914 "dout_cmu_shared0_div3", 915 "dout_cmu_shared1_div3", 916 "dout_cmu_shared0_div4", 917 "fout_spare_pll" }; 918 PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2", 919 "dout_cmu_shared1_div2", 920 "fout_shared2_pll", 921 "fout_shared3_pll", 922 "dout_cmu_shared0_div3", 923 "dout_cmu_shared1_div3", 924 "dout_cmu_shared0_div4", "fout_spare_pll" }; 925 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2", 926 "dout_cmu_shared1_div2", 927 "fout_shared2_pll", "fout_shared3_pll", 928 "dout_cmu_shared0_div3", 929 "dout_cmu_shared1_div3", 930 "dout_cmu_shared0_div4", "fout_spare_pll" }; 931 PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4", 932 "dout_cmu_shared2_div2", 933 "dout_cmu_shared3_div2", "fout_spare_pll" }; 934 PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1", 935 "dout_cmu_cmuref" }; 936 937 /* 938 * Register name to clock name mangling strategy used in this file 939 * 940 * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll 941 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu 942 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 943 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 944 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu 945 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu 946 * 947 * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC 948 */ 949 950 static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { 951 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, 952 PLL_CON0_PLL_SHARED0, 4, 1), 953 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, 954 PLL_CON0_PLL_SHARED1, 4, 1), 955 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, 956 PLL_CON0_PLL_SHARED2, 4, 1), 957 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, 958 PLL_CON0_PLL_SHARED3, 4, 1), 959 MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p, 960 PLL_CON0_PLL_SPARE, 4, 1), 961 MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p, 962 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3), 963 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p, 964 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3), 965 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p, 966 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3), 967 MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p, 968 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3), 969 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p, 970 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3), 971 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p, 972 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3), 973 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p, 974 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3), 975 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p, 976 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3), 977 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p, 978 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3), 979 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p, 980 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3), 981 MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p, 982 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3), 983 MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p, 984 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3), 985 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p, 986 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), 987 MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1", 988 mout_cmu_cmu_boost_option1_p, 989 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1), 990 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, 991 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3), 992 MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", 993 mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3), 994 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", 995 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 996 0, 3), 997 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", 998 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 999 0, 3), 1000 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", 1001 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 1002 0, 3), 1003 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p, 1004 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3), 1005 MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p, 1006 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3), 1007 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p, 1008 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3), 1009 MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p, 1010 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3), 1011 MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p, 1012 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3), 1013 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, 1014 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3), 1015 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, 1016 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3), 1017 MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p, 1018 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3), 1019 MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p, 1020 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3), 1021 MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p, 1022 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3), 1023 MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch", 1024 mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3), 1025 MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p, 1026 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3), 1027 MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p, 1028 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3), 1029 MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p, 1030 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3), 1031 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, 1032 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), 1033 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, 1034 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), 1035 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", 1036 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2), 1037 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", 1038 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 1039 0, 1), 1040 MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg", 1041 mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 1042 0, 1), 1043 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, 1044 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), 1045 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p, 1046 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1), 1047 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, 1048 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3), 1049 MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", 1050 mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 1051 0, 2), 1052 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p, 1053 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1), 1054 MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", 1055 mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 1056 0, 2), 1057 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p, 1058 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3), 1059 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p, 1060 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3), 1061 MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p, 1062 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3), 1063 MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, 1064 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3), 1065 MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, 1066 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3), 1067 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, 1068 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), 1069 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch", 1070 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), 1071 MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p, 1072 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2), 1073 MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p, 1074 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2), 1075 MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p, 1076 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3), 1077 MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p, 1078 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3), 1079 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus", 1080 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), 1081 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p, 1082 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), 1083 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus", 1084 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2), 1085 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p, 1086 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2), 1087 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p, 1088 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), 1089 MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1", 1090 mout_cmu_top_boost_option1_p, 1091 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1), 1092 MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref", 1093 mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2), 1094 MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p, 1095 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3), 1096 MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p, 1097 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3), 1098 MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", 1099 mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3), 1100 MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p, 1101 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2), 1102 MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p, 1103 CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), 1104 }; 1105 1106 static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { 1107 DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", 1108 CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), 1109 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", 1110 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4), 1111 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus", 1112 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4), 1113 DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus", 1114 CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4), 1115 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0", 1116 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), 1117 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1", 1118 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), 1119 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2", 1120 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), 1121 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3", 1122 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), 1123 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4", 1124 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5), 1125 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5", 1126 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5), 1127 DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6", 1128 CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5), 1129 DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7", 1130 CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5), 1131 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", 1132 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 1133 DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", 1134 "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), 1135 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", 1136 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), 1137 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", 1138 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), 1139 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", 1140 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), 1141 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus", 1142 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4), 1143 DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus", 1144 CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4), 1145 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus", 1146 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4), 1147 DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus", 1148 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4), 1149 DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus", 1150 CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4), 1151 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", 1152 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), 1153 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", 1154 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), 1155 DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa", 1156 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4), 1157 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd", 1158 CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4), 1159 DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb", 1160 CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4), 1161 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch", 1162 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 1163 DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0", 1164 CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4), 1165 DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1", 1166 CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4), 1167 DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc", 1168 CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4), 1169 DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", 1170 CLK_CON_DIV_CLKCMU_HPM, 0, 2), 1171 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus", 1172 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4), 1173 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", 1174 "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4), 1175 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", 1176 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5), 1177 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", 1178 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4), 1179 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", 1180 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3), 1181 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", 1182 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), 1183 DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", 1184 "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9), 1185 DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", 1186 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3), 1187 DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", 1188 "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4), 1189 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", 1190 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), 1191 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", 1192 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4), 1193 DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc", 1194 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4), 1195 DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc", 1196 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4), 1197 DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", 1198 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), 1199 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", 1200 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), 1201 DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", 1202 CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), 1203 DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", 1204 CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), 1205 DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", 1206 CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), 1207 DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra", 1208 CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4), 1209 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", 1210 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), 1211 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip", 1212 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), 1213 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", 1214 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), 1215 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip", 1216 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), 1217 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus", 1218 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), 1219 DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus", 1220 CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4), 1221 DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu", 1222 CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4), 1223 DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", 1224 "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4), 1225 DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart", 1226 CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4), 1227 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost", 1228 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), 1229 DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref", 1230 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), 1231 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", 1232 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 1233 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", 1234 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 1235 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", 1236 "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 1237 DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5", 1238 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), 1239 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", 1240 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 1241 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", 1242 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 1243 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", 1244 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 1245 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", 1246 "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), 1247 DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2", 1248 "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), 1249 }; 1250 1251 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { 1252 FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg", 1253 "gout_cmu_hsi0_usbdpdbg", 1, 4, 0), 1254 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), 1255 }; 1256 1257 static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { 1258 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost", 1259 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), 1260 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost", 1261 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), 1262 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost", 1263 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), 1264 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost", 1265 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), 1266 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", 1267 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 1268 21, 0, 0), 1269 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", 1270 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 1271 21, 0, 0), 1272 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", 1273 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 1274 21, 0, 0), 1275 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost", 1276 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST, 1277 21, 0, 0), 1278 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch", 1279 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), 1280 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", 1281 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), 1282 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", 1283 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), 1284 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", 1285 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), 1286 GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", 1287 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), 1288 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", 1289 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), 1290 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", 1291 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), 1292 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", 1293 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), 1294 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", 1295 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), 1296 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", 1297 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0), 1298 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", 1299 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0), 1300 GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", 1301 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0), 1302 GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", 1303 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0), 1304 GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", 1305 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), 1306 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", 1307 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 1308 GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", 1309 "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 1310 21, 0, 0), 1311 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", 1312 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 1313 21, 0, 0), 1314 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", 1315 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 1316 21, 0, 0), 1317 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", 1318 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 1319 21, 0, 0), 1320 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", 1321 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), 1322 GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", 1323 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), 1324 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", 1325 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), 1326 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", 1327 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), 1328 GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", 1329 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), 1330 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", 1331 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), 1332 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", 1333 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), 1334 GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", 1335 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), 1336 GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", 1337 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), 1338 GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", 1339 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), 1340 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch", 1341 "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 1342 21, 0, 0), 1343 GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", 1344 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), 1345 GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", 1346 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), 1347 GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", 1348 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), 1349 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", 1350 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), 1351 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", 1352 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), 1353 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", 1354 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 1355 21, 0, 0), 1356 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", 1357 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 1358 21, 0, 0), 1359 GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg", 1360 "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 1361 21, 0, 0), 1362 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", 1363 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), 1364 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", 1365 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), 1366 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", 1367 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), 1368 GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", 1369 "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 1370 21, 0, 0), 1371 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", 1372 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), 1373 GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", 1374 "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 1375 21, 0, 0), 1376 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", 1377 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), 1378 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", 1379 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), 1380 GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", 1381 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), 1382 GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", 1383 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), 1384 GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", 1385 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), 1386 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", 1387 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), 1388 GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", 1389 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), 1390 GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", 1391 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), 1392 GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", 1393 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 1394 GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", 1395 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 1396 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus", 1397 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 1398 21, 0, 0), 1399 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", 1400 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), 1401 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus", 1402 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 1403 21, 0, 0), 1404 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", 1405 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), 1406 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", 1407 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), 1408 GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref", 1409 "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 1410 21, 0, 0), 1411 GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", 1412 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), 1413 GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", 1414 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), 1415 GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", 1416 "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 1417 21, 0, 0), 1418 GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", 1419 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), 1420 }; 1421 1422 static const struct samsung_cmu_info top_cmu_info __initconst = { 1423 .pll_clks = cmu_top_pll_clks, 1424 .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks), 1425 .mux_clks = cmu_top_mux_clks, 1426 .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks), 1427 .div_clks = cmu_top_div_clks, 1428 .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks), 1429 .fixed_factor_clks = cmu_top_ffactor, 1430 .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor), 1431 .gate_clks = cmu_top_gate_clks, 1432 .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks), 1433 .nr_clk_ids = CLKS_NR_TOP, 1434 .clk_regs = cmu_top_clk_regs, 1435 .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs), 1436 }; 1437 1438 static void __init gs101_cmu_top_init(struct device_node *np) 1439 { 1440 exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 1441 } 1442 1443 /* Register CMU_TOP early, as it's a dependency for other early domains */ 1444 CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", 1445 gs101_cmu_top_init); 1446 1447 /* ---- CMU_APM ------------------------------------------------------------- */ 1448 1449 /* Register Offset definitions for CMU_APM (0x17400000) */ 1450 #define APM_CMU_APM_CONTROLLER_OPTION 0x0800 1451 #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 1452 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 1453 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 1454 #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 1455 #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 1456 #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 1457 #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c 1458 #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 1459 #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 1460 #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 1461 #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c 1462 #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 1463 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 1464 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 1465 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c 1466 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 1467 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 1468 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 1469 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c 1470 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 1471 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 1472 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 1473 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c 1474 #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 1475 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 1476 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 1477 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c 1478 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 1479 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 1480 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 1481 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c 1482 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 1483 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 1484 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 1485 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c 1486 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 1487 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 1488 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c 1489 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 1490 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 1491 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 1492 #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c 1493 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 1494 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 1495 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 1496 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c 1497 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 1498 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 1499 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 1500 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac 1501 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 1502 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 1503 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 1504 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc 1505 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 1506 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 1507 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc 1508 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 1509 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 1510 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 1511 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc 1512 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 1513 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 1514 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 1515 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec 1516 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 1517 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 1518 #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 1519 #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc 1520 #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 1521 #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 1522 #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 1523 #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c 1524 #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 1525 #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 1526 #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 1527 #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c 1528 #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 1529 #define QCH_CON_APBIF_RTC_QCH 0x3024 1530 #define QCH_CON_APBIF_TRTC_QCH 0x3028 1531 #define QCH_CON_APM_CMU_APM_QCH 0x302c 1532 #define QCH_CON_APM_USI0_UART_QCH 0x3030 1533 #define QCH_CON_APM_USI0_USI_QCH 0x3034 1534 #define QCH_CON_APM_USI1_UART_QCH 0x3038 1535 #define QCH_CON_D_TZPC_APM_QCH 0x303c 1536 #define QCH_CON_GPC_APM_QCH 0x3040 1537 #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 1538 #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 1539 #define QCH_CON_INTMEM_QCH 0x304c 1540 #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 1541 #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 1542 #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 1543 #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c 1544 #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 1545 #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 1546 #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 1547 #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c 1548 #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 1549 #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 1550 #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c 1551 #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 1552 #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 1553 #define QCH_CON_PMU_INTR_GEN_QCH 0x3088 1554 #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c 1555 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 1556 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 1557 #define QCH_CON_SPEEDY_APM_QCH 0x3098 1558 #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c 1559 #define QCH_CON_SSMT_D_APM_QCH 0x30a0 1560 #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 1561 #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 1562 #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac 1563 #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 1564 #define QCH_CON_SYSREG_APM_QCH 0x30b8 1565 #define QCH_CON_UASC_APM_QCH 0x30bc 1566 #define QCH_CON_UASC_DBGCORE_QCH 0x30c0 1567 #define QCH_CON_UASC_G_SWD_QCH 0x30c4 1568 #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 1569 #define QCH_CON_UASC_P_APM_QCH 0x30cc 1570 #define QCH_CON_WDT_APM_QCH 0x30d0 1571 #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 1572 1573 static const unsigned long apm_clk_regs[] __initconst = { 1574 APM_CMU_APM_CONTROLLER_OPTION, 1575 CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, 1576 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 1577 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 1578 CLK_CON_DIV_DIV_CLK_APM_BOOST, 1579 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 1580 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 1581 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 1582 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 1583 CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 1584 CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 1585 CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 1586 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 1587 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 1588 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 1589 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 1590 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 1591 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 1592 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 1593 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 1594 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 1595 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 1596 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 1597 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 1598 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 1599 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 1600 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 1601 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 1602 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 1603 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 1604 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 1605 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, 1606 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1607 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 1608 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 1609 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 1610 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 1611 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 1612 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 1613 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 1614 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 1615 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 1616 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 1617 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 1618 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 1619 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 1620 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1621 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, 1622 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 1623 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 1624 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 1625 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 1626 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 1627 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 1628 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 1629 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 1630 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 1631 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 1632 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 1633 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 1634 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 1635 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 1636 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 1637 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 1638 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 1639 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, 1640 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 1641 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 1642 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 1643 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 1644 }; 1645 1646 PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc", 1647 "pad_clk_apm", "oscclk" }; 1648 PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", 1649 "pll_alv_div16_apm" }; 1650 1651 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 1652 FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000), 1653 FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000), 1654 FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000), 1655 }; 1656 1657 static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 1658 MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, 1659 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), 1660 MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, 1661 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), 1662 }; 1663 1664 static const struct samsung_div_clock apm_div_clks[] __initconst = { 1665 DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", 1666 CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), 1667 DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", 1668 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), 1669 DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", 1670 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), 1671 DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", 1672 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), 1673 }; 1674 1675 static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 1676 GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK, 1677 "gout_apm_apm_cmu_apm_pclk", "mout_apm_func", 1678 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0), 1679 GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1", 1680 "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0), 1681 GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1", 1682 "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0), 1683 GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1", 1684 "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0), 1685 GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", 1686 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), 1687 GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 1688 "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func", 1689 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 1690 21, 0, 0), 1691 GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK, 1692 "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func", 1693 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 1694 21, 0, 0), 1695 GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 1696 "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func", 1697 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 1698 21, 0, 0), 1699 GATE(CLK_GOUT_APM_APBIF_RTC_PCLK, 1700 "gout_apm_apbif_rtc_pclk", "gout_apm_func", 1701 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0), 1702 GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK, 1703 "gout_apm_apbif_trtc_pclk", "gout_apm_func", 1704 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0), 1705 GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK, 1706 "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart", 1707 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 1708 21, 0, 0), 1709 GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK, 1710 "gout_apm_apm_usi0_uart_pclk", "gout_apm_func", 1711 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 1712 21, 0, 0), 1713 GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK, 1714 "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi", 1715 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 1716 21, 0, 0), 1717 GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK, 1718 "gout_apm_apm_usi0_usi_pclk", "gout_apm_func", 1719 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 1720 21, 0, 0), 1721 GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK, 1722 "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart", 1723 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 1724 21, 0, 0), 1725 GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK, 1726 "gout_apm_apm_usi1_uart_pclk", "gout_apm_func", 1727 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 1728 21, 0, 0), 1729 GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK, 1730 "gout_apm_d_tzpc_apm_pclk", "gout_apm_func", 1731 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1732 GATE(CLK_GOUT_APM_GPC_APM_PCLK, 1733 "gout_apm_gpc_apm_pclk", "gout_apm_func", 1734 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1735 GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK, 1736 "gout_apm_grebeintegration_hclk", "gout_apm_func", 1737 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 1738 21, 0, 0), 1739 GATE(CLK_GOUT_APM_INTMEM_ACLK, 1740 "gout_apm_intmem_aclk", "gout_apm_func", 1741 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0), 1742 GATE(CLK_GOUT_APM_INTMEM_PCLK, 1743 "gout_apm_intmem_pclk", "gout_apm_func", 1744 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0), 1745 GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK, 1746 "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func", 1747 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 1748 21, 0, 0), 1749 GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK, 1750 "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func", 1751 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 1752 21, 0, 0), 1753 GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK, 1754 "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func", 1755 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1756 21, 0, 0), 1757 GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK, 1758 "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func", 1759 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 1760 21, 0, 0), 1761 GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK, 1762 "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func", 1763 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 1764 21, 0, 0), 1765 GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK, 1766 "gout_apm_lhs_axi_g_scan2dram_i_clk", 1767 "gout_apm_func", 1768 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 1769 21, 0, 0), 1770 GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK, 1771 "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func", 1772 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 1773 21, 0, 0), 1774 GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK, 1775 "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func", 1776 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 1777 21, 0, 0), 1778 GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK, 1779 "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func", 1780 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 1781 21, 0, 0), 1782 GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK, 1783 "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func", 1784 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 1785 21, 0, 0), 1786 GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK, 1787 "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func", 1788 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 1789 21, 0, 0), 1790 GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK, 1791 "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func", 1792 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 1793 21, 0, 0), 1794 GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK, 1795 "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func", 1796 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 1797 21, 0, 0), 1798 GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK, 1799 "gout_apm_pmu_intr_gen_pclk", "gout_apm_func", 1800 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 1801 21, 0, 0), 1802 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK, 1803 "gout_apm_rom_crc32_host_aclk", "gout_apm_func", 1804 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 1805 21, 0, 0), 1806 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK, 1807 "gout_apm_rom_crc32_host_pclk", "gout_apm_func", 1808 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 1809 21, 0, 0), 1810 GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK, 1811 "gout_apm_clk_apm_bus_clk", "gout_apm_func", 1812 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 1813 21, 0, 0), 1814 GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK, 1815 "gout_apm_clk_apm_usi0_uart_clk", 1816 "dout_apm_usi0_uart", 1817 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1818 21, 0, 0), 1819 GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK, 1820 "gout_apm_clk_apm_usi0_usi_clk", 1821 "dout_apm_usi0_usi", 1822 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 1823 21, 0, 0), 1824 GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK, 1825 "gout_apm_clk_apm_usi1_uart_clk", 1826 "dout_apm_usi1_uart", 1827 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 1828 21, 0, 0), 1829 GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK, 1830 "gout_apm_speedy_apm_pclk", "gout_apm_func", 1831 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0), 1832 GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK, 1833 "gout_apm_speedy_sub_apm_pclk", "gout_apm_func", 1834 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 1835 21, 0, 0), 1836 GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK, 1837 "gout_apm_ssmt_d_apm_aclk", "gout_apm_func", 1838 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0), 1839 GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK, 1840 "gout_apm_ssmt_d_apm_pclk", "gout_apm_func", 1841 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0), 1842 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK, 1843 "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func", 1844 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 1845 21, 0, 0), 1846 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK, 1847 "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func", 1848 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 1849 21, 0, 0), 1850 GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK, 1851 "gout_apm_ss_dbgcore_ss_dbgcore_hclk", 1852 "gout_apm_func", 1853 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 1854 21, 0, 0), 1855 GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2, 1856 "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func", 1857 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 1858 21, 0, 0), 1859 GATE(CLK_GOUT_APM_SYSREG_APM_PCLK, 1860 "gout_apm_sysreg_apm_pclk", "gout_apm_func", 1861 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0), 1862 GATE(CLK_GOUT_APM_UASC_APM_ACLK, 1863 "gout_apm_uasc_apm_aclk", "gout_apm_func", 1864 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0), 1865 GATE(CLK_GOUT_APM_UASC_APM_PCLK, 1866 "gout_apm_uasc_apm_pclk", "gout_apm_func", 1867 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0), 1868 GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK, 1869 "gout_apm_uasc_dbgcore_aclk", "gout_apm_func", 1870 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 1871 21, 0, 0), 1872 GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK, 1873 "gout_apm_uasc_dbgcore_pclk", "gout_apm_func", 1874 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 1875 21, 0, 0), 1876 GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK, 1877 "gout_apm_uasc_g_swd_aclk", "gout_apm_func", 1878 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0), 1879 GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK, 1880 "gout_apm_uasc_g_swd_pclk", "gout_apm_func", 1881 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 1882 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK, 1883 "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func", 1884 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 1885 21, 0, 0), 1886 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK, 1887 "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func", 1888 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 1889 GATE(CLK_GOUT_APM_UASC_P_APM_ACLK, 1890 "gout_apm_uasc_p_apm_aclk", "gout_apm_func", 1891 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0), 1892 GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, 1893 "gout_apm_uasc_p_apm_pclk", "gout_apm_func", 1894 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_CRITICAL, 0), 1895 GATE(CLK_GOUT_APM_WDT_APM_PCLK, 1896 "gout_apm_wdt_apm_pclk", "gout_apm_func", 1897 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), 1898 GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, 1899 "gout_apm_xiu_dp_apm_aclk", "gout_apm_func", 1900 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0), 1901 }; 1902 1903 static const struct samsung_cmu_info apm_cmu_info __initconst = { 1904 .mux_clks = apm_mux_clks, 1905 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 1906 .div_clks = apm_div_clks, 1907 .nr_div_clks = ARRAY_SIZE(apm_div_clks), 1908 .gate_clks = apm_gate_clks, 1909 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 1910 .fixed_clks = apm_fixed_clks, 1911 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 1912 .nr_clk_ids = CLKS_NR_APM, 1913 .clk_regs = apm_clk_regs, 1914 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 1915 }; 1916 1917 /* ---- CMU_HSI0 ------------------------------------------------------------ */ 1918 1919 /* Register Offset definitions for CMU_HSI0 (0x11000000) */ 1920 #define PLL_LOCKTIME_PLL_USB 0x0004 1921 #define PLL_CON0_PLL_USB 0x0140 1922 #define PLL_CON1_PLL_USB 0x0144 1923 #define PLL_CON2_PLL_USB 0x0148 1924 #define PLL_CON3_PLL_USB 0x014c 1925 #define PLL_CON4_PLL_USB 0x0150 1926 #define PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER 0x0600 1927 #define PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER 0x0604 1928 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0610 1929 #define PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER 0x0614 1930 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0620 1931 #define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x0624 1932 #define PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER 0x0630 1933 #define PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER 0x0634 1934 #define PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER 0x0640 1935 #define PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER 0x0644 1936 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0650 1937 #define PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0654 1938 #define PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0660 1939 #define PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0664 1940 #define HSI0_CMU_HSI0_CONTROLLER_OPTION 0x0800 1941 #define CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0 0x0810 1942 #define CLK_CON_MUX_MUX_CLK_HSI0_BUS 0x1000 1943 #define CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF 0x1004 1944 #define CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD 0x1008 1945 #define CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD 0x1800 1946 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000 1947 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26 0x2004 1948 #define CLK_CON_GAT_CLK_HSI0_ALT 0x2008 1949 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x200c 1950 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2010 1951 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2014 1952 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2018 1953 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x201c 1954 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK 0x2020 1955 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK 0x2024 1956 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK 0x2028 1957 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x202c 1958 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2030 1959 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK 0x2034 1960 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK 0x2038 1961 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK 0x203c 1962 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK 0x2040 1963 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK 0x2044 1964 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2048 1965 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK 0x204c 1966 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK 0x2050 1967 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2054 1968 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2058 1969 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK 0x205c 1970 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK 0x2060 1971 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK 0x2064 1972 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK 0x2068 1973 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x206c 1974 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2070 1975 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26 0x2074 1976 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2078 1977 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x207c 1978 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x2080 1979 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2084 1980 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK 0x2088 1981 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK 0x208c 1982 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK 0x2090 1983 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK 0x2094 1984 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK 0x2098 1985 #define DMYQCH_CON_USB31DRD_QCH 0x3000 1986 #define DMYQCH_CON_USB31DRD_QCH_REF 0x3004 1987 #define PCH_CON_LHM_AXI_G_ETR_HSI0_PCH 0x3008 1988 #define PCH_CON_LHM_AXI_P_AOCHSI0_PCH 0x300c 1989 #define PCH_CON_LHM_AXI_P_HSI0_PCH 0x3010 1990 #define PCH_CON_LHS_ACEL_D_HSI0_PCH 0x3014 1991 #define PCH_CON_LHS_AXI_D_HSI0AOC_PCH 0x3018 1992 #define QCH_CON_DP_LINK_QCH_GTC_CLK 0x301c 1993 #define QCH_CON_DP_LINK_QCH_PCLK 0x3020 1994 #define QCH_CON_D_TZPC_HSI0_QCH 0x3024 1995 #define QCH_CON_ETR_MIU_QCH_ACLK 0x3028 1996 #define QCH_CON_ETR_MIU_QCH_PCLK 0x302c 1997 #define QCH_CON_GPC_HSI0_QCH 0x3030 1998 #define QCH_CON_HSI0_CMU_HSI0_QCH 0x3034 1999 #define QCH_CON_LHM_AXI_G_ETR_HSI0_QCH 0x3038 2000 #define QCH_CON_LHM_AXI_P_AOCHSI0_QCH 0x303c 2001 #define QCH_CON_LHM_AXI_P_HSI0_QCH 0x3040 2002 #define QCH_CON_LHS_ACEL_D_HSI0_QCH 0x3044 2003 #define QCH_CON_LHS_AXI_D_HSI0AOC_QCH 0x3048 2004 #define QCH_CON_PPMU_HSI0_AOC_QCH 0x304c 2005 #define QCH_CON_PPMU_HSI0_BUS0_QCH 0x3050 2006 #define QCH_CON_SSMT_USB_QCH 0x3054 2007 #define QCH_CON_SYSMMU_USB_QCH 0x3058 2008 #define QCH_CON_SYSREG_HSI0_QCH 0x305c 2009 #define QCH_CON_UASC_HSI0_CTRL_QCH 0x3060 2010 #define QCH_CON_UASC_HSI0_LINK_QCH 0x3064 2011 #define QCH_CON_USB31DRD_QCH_APB 0x3068 2012 #define QCH_CON_USB31DRD_QCH_DBG 0x306c 2013 #define QCH_CON_USB31DRD_QCH_PCS 0x3070 2014 #define QCH_CON_USB31DRD_QCH_SLV_CTRL 0x3074 2015 #define QCH_CON_USB31DRD_QCH_SLV_LINK 0x3078 2016 #define QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0 0x3c00 2017 2018 static const unsigned long hsi0_clk_regs[] __initconst = { 2019 PLL_LOCKTIME_PLL_USB, 2020 PLL_CON0_PLL_USB, 2021 PLL_CON1_PLL_USB, 2022 PLL_CON2_PLL_USB, 2023 PLL_CON3_PLL_USB, 2024 PLL_CON4_PLL_USB, 2025 PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 2026 PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER, 2027 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 2028 PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER, 2029 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 2030 PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER, 2031 PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 2032 PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER, 2033 PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 2034 PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER, 2035 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 2036 PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER, 2037 PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 2038 PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER, 2039 HSI0_CMU_HSI0_CONTROLLER_OPTION, 2040 CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0, 2041 CLK_CON_MUX_MUX_CLK_HSI0_BUS, 2042 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 2043 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 2044 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 2045 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, 2046 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, 2047 CLK_CON_GAT_CLK_HSI0_ALT, 2048 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, 2049 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 2050 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, 2051 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 2052 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 2053 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 2054 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK, 2055 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK, 2056 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK, 2057 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, 2058 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK, 2059 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, 2060 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, 2061 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK, 2062 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK, 2063 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK, 2064 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, 2065 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, 2066 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, 2067 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, 2068 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, 2069 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, 2070 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, 2071 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, 2072 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, 2073 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, 2074 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, 2075 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, 2076 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, 2077 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, 2078 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, 2079 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, 2080 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, 2081 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, 2082 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, 2083 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, 2084 DMYQCH_CON_USB31DRD_QCH, 2085 DMYQCH_CON_USB31DRD_QCH_REF, 2086 PCH_CON_LHM_AXI_G_ETR_HSI0_PCH, 2087 PCH_CON_LHM_AXI_P_AOCHSI0_PCH, 2088 PCH_CON_LHM_AXI_P_HSI0_PCH, 2089 PCH_CON_LHS_ACEL_D_HSI0_PCH, 2090 PCH_CON_LHS_AXI_D_HSI0AOC_PCH, 2091 QCH_CON_DP_LINK_QCH_GTC_CLK, 2092 QCH_CON_DP_LINK_QCH_PCLK, 2093 QCH_CON_D_TZPC_HSI0_QCH, 2094 QCH_CON_ETR_MIU_QCH_ACLK, 2095 QCH_CON_ETR_MIU_QCH_PCLK, 2096 QCH_CON_GPC_HSI0_QCH, 2097 QCH_CON_HSI0_CMU_HSI0_QCH, 2098 QCH_CON_LHM_AXI_G_ETR_HSI0_QCH, 2099 QCH_CON_LHM_AXI_P_AOCHSI0_QCH, 2100 QCH_CON_LHM_AXI_P_HSI0_QCH, 2101 QCH_CON_LHS_ACEL_D_HSI0_QCH, 2102 QCH_CON_LHS_AXI_D_HSI0AOC_QCH, 2103 QCH_CON_PPMU_HSI0_AOC_QCH, 2104 QCH_CON_PPMU_HSI0_BUS0_QCH, 2105 QCH_CON_SSMT_USB_QCH, 2106 QCH_CON_SYSMMU_USB_QCH, 2107 QCH_CON_SYSREG_HSI0_QCH, 2108 QCH_CON_UASC_HSI0_CTRL_QCH, 2109 QCH_CON_UASC_HSI0_LINK_QCH, 2110 QCH_CON_USB31DRD_QCH_APB, 2111 QCH_CON_USB31DRD_QCH_DBG, 2112 QCH_CON_USB31DRD_QCH_PCS, 2113 QCH_CON_USB31DRD_QCH_SLV_CTRL, 2114 QCH_CON_USB31DRD_QCH_SLV_LINK, 2115 QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0, 2116 }; 2117 2118 /* List of parent clocks for Muxes in CMU_HSI0 */ 2119 PNAME(mout_pll_usb_p) = { "oscclk", "fout_usb_pll" }; 2120 PNAME(mout_hsi0_alt_user_p) = { "oscclk", 2121 "gout_hsi0_clk_hsi0_alt" }; 2122 PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" }; 2123 PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" }; 2124 PNAME(mout_hsi0_tcxo_user_p) = { "oscclk", "tcxo_hsi1_hsi0" }; 2125 PNAME(mout_hsi0_usb20_user_p) = { "oscclk", "usb20phy_phy_clock" }; 2126 PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk", 2127 "dout_cmu_hsi0_usb31drd" }; 2128 PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk", 2129 "dout_cmu_hsi0_usbdpdbg" }; 2130 PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user", 2131 "mout_hsi0_alt_user" }; 2132 PNAME(mout_hsi0_usb20_ref_p) = { "fout_usb_pll", 2133 "mout_hsi0_tcxo_user" }; 2134 PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll", 2135 "mout_hsi0_usb31drd_user", 2136 "dout_hsi0_usb31drd", 2137 "fout_usb_pll" }; 2138 2139 static const struct samsung_pll_rate_table cmu_hsi0_usb_pll_rates[] __initconst = { 2140 PLL_35XX_RATE(24576000, 19200000, 150, 6, 5), 2141 { /* sentinel */ } 2142 }; 2143 2144 static const struct samsung_pll_clock cmu_hsi0_pll_clks[] __initconst = { 2145 PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk", 2146 PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB, 2147 cmu_hsi0_usb_pll_rates), 2148 }; 2149 2150 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = { 2151 MUX(CLK_MOUT_PLL_USB, 2152 "mout_pll_usb", mout_pll_usb_p, 2153 PLL_CON0_PLL_USB, 4, 1), 2154 MUX(CLK_MOUT_HSI0_ALT_USER, 2155 "mout_hsi0_alt_user", mout_hsi0_alt_user_p, 2156 PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 4, 1), 2157 MUX(CLK_MOUT_HSI0_BUS_USER, 2158 "mout_hsi0_bus_user", mout_hsi0_bus_user_p, 2159 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 4, 1), 2160 MUX(CLK_MOUT_HSI0_DPGTC_USER, 2161 "mout_hsi0_dpgtc_user", mout_hsi0_dpgtc_user_p, 2162 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 4, 1), 2163 MUX(CLK_MOUT_HSI0_TCXO_USER, 2164 "mout_hsi0_tcxo_user", mout_hsi0_tcxo_user_p, 2165 PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 4, 1), 2166 MUX(CLK_MOUT_HSI0_USB20_USER, 2167 "mout_hsi0_usb20_user", mout_hsi0_usb20_user_p, 2168 PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 4, 1), 2169 MUX(CLK_MOUT_HSI0_USB31DRD_USER, 2170 "mout_hsi0_usb31drd_user", mout_hsi0_usb31drd_user_p, 2171 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 4, 1), 2172 MUX(CLK_MOUT_HSI0_USBDPDBG_USER, 2173 "mout_hsi0_usbdpdbg_user", mout_hsi0_usbdpdbg_user_p, 2174 PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 4, 1), 2175 MUX(CLK_MOUT_HSI0_BUS, 2176 "mout_hsi0_bus", mout_hsi0_bus_p, 2177 CLK_CON_MUX_MUX_CLK_HSI0_BUS, 0, 1), 2178 MUX(CLK_MOUT_HSI0_USB20_REF, 2179 "mout_hsi0_usb20_ref", mout_hsi0_usb20_ref_p, 2180 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 0, 1), 2181 MUX(CLK_MOUT_HSI0_USB31DRD, 2182 "mout_hsi0_usb31drd", mout_hsi0_usb31drd_p, 2183 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0, 2), 2184 }; 2185 2186 static const struct samsung_div_clock hsi0_div_clks[] __initconst = { 2187 DIV(CLK_DOUT_HSI0_USB31DRD, 2188 "dout_hsi0_usb31drd", "mout_hsi0_usb20_user", 2189 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0, 3), 2190 }; 2191 2192 static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = { 2193 /* TODO: should have a driver for this */ 2194 GATE(CLK_GOUT_HSI0_PCLK, 2195 "gout_hsi0_hsi0_pclk", "mout_hsi0_bus", 2196 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, 2197 21, CLK_IGNORE_UNUSED, 0), 2198 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26, 2199 "gout_hsi0_usb31drd_i_usb31drd_suspend_clk_26", 2200 "mout_hsi0_usb20_ref", 2201 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, 2202 21, 0, 0), 2203 GATE(CLK_GOUT_HSI0_CLK_HSI0_ALT, 2204 "gout_hsi0_clk_hsi0_alt", "ioclk_clk_hsi0_alt", 2205 CLK_CON_GAT_CLK_HSI0_ALT, 21, 0, 0), 2206 GATE(CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK, 2207 "gout_hsi0_dp_link_i_dp_gtc_clk", "mout_hsi0_dpgtc_user", 2208 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, 2209 21, 0, 0), 2210 GATE(CLK_GOUT_HSI0_DP_LINK_I_PCLK, 2211 "gout_hsi0_dp_link_i_pclk", "mout_hsi0_bus", 2212 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 21, 0, 0), 2213 GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK, 2214 "gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus", 2215 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, 2216 21, 0, 0), 2217 GATE(CLK_GOUT_HSI0_ETR_MIU_I_ACLK, 2218 "gout_hsi0_etr_miu_i_aclk", "mout_hsi0_bus", 2219 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0), 2220 GATE(CLK_GOUT_HSI0_ETR_MIU_I_PCLK, 2221 "gout_hsi0_etr_miu_i_pclk", "mout_hsi0_bus", 2222 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0), 2223 GATE(CLK_GOUT_HSI0_GPC_HSI0_PCLK, 2224 "gout_hsi0_gpc_hsi0_pclk", "mout_hsi0_bus", 2225 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 21, 0, 0), 2226 GATE(CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK, 2227 "gout_hsi0_lhm_axi_g_etr_hsi0_i_clk", "mout_hsi0_bus", 2228 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK, 2229 21, 0, 0), 2230 GATE(CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK, 2231 "gout_hsi0_lhm_axi_p_aochsi0_i_clk", "mout_hsi0_bus", 2232 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK, 2233 21, 0, 0), 2234 /* TODO: should have a driver for this */ 2235 GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK, 2236 "gout_hsi0_lhm_axi_p_hsi0_i_clk", "mout_hsi0_bus", 2237 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK, 2238 21, CLK_IGNORE_UNUSED, 0), 2239 /* TODO: should have a driver for this */ 2240 GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK, 2241 "gout_hsi0_lhs_acel_d_hsi0_i_clk", "mout_hsi0_bus", 2242 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK, 2243 21, CLK_IGNORE_UNUSED, 0), 2244 GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK, 2245 "gout_hsi0_lhs_axi_d_hsi0aoc_i_clk", "mout_hsi0_bus", 2246 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK, 2247 21, 0, 0), 2248 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK, 2249 "gout_hsi0_ppmu_hsi0_aoc_aclk", "mout_hsi0_bus", 2250 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, 2251 21, 0, 0), 2252 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK, 2253 "gout_hsi0_ppmu_hsi0_aoc_pclk", "mout_hsi0_bus", 2254 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, 2255 21, 0, 0), 2256 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK, 2257 "gout_hsi0_ppmu_hsi0_bus0_aclk", "mout_hsi0_bus", 2258 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK, 2259 21, 0, 0), 2260 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK, 2261 "gout_hsi0_ppmu_hsi0_bus0_pclk", "mout_hsi0_bus", 2262 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK, 2263 21, 0, 0), 2264 GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK, 2265 "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus", 2266 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK, 2267 21, 0, 0), 2268 /* TODO: should have a driver for this */ 2269 GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK, 2270 "gout_hsi0_ssmt_usb_aclk", "mout_hsi0_bus", 2271 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, 2272 21, CLK_IGNORE_UNUSED, 0), 2273 /* TODO: should have a driver for this */ 2274 GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK, 2275 "gout_hsi0_ssmt_usb_pclk", "mout_hsi0_bus", 2276 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, 2277 21, CLK_IGNORE_UNUSED, 0), 2278 /* TODO: should have a driver for this */ 2279 GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2, 2280 "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus", 2281 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, 2282 21, CLK_IGNORE_UNUSED, 0), 2283 GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK, 2284 "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus", 2285 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, 2286 21, 0, 0), 2287 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK, 2288 "gout_hsi0_uasc_hsi0_ctrl_aclk", "mout_hsi0_bus", 2289 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, 2290 21, 0, 0), 2291 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK, 2292 "gout_hsi0_uasc_hsi0_ctrl_pclk", "mout_hsi0_bus", 2293 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, 2294 21, 0, 0), 2295 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK, 2296 "gout_hsi0_uasc_hsi0_link_aclk", "mout_hsi0_bus", 2297 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, 2298 21, 0, 0), 2299 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK, 2300 "gout_hsi0_uasc_hsi0_link_pclk", "mout_hsi0_bus", 2301 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, 2302 21, 0, 0), 2303 GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL, 2304 "gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus", 2305 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, 2306 21, 0, 0), 2307 GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY, 2308 "gout_hsi0_usb31drd_bus_clk_early", "mout_hsi0_bus", 2309 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, 2310 21, 0, 0), 2311 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26, 2312 "gout_hsi0_usb31drd_i_usb20_phy_refclk_26", "mout_hsi0_usb20_ref", 2313 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, 2314 21, 0, 0), 2315 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40, 2316 "gout_hsi0_usb31drd_i_usb31drd_ref_clk_40", "mout_hsi0_usb31drd", 2317 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, 2318 21, 0, 0), 2319 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL, 2320 "gout_hsi0_usb31drd_i_usbdpphy_ref_soc_pll", 2321 "mout_hsi0_usbdpdbg_user", 2322 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, 2323 21, 0, 0), 2324 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK, 2325 "gout_hsi0_usb31drd_i_usbdpphy_scl_apb_pclk", "mout_hsi0_bus", 2326 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, 2327 21, 0, 0), 2328 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK, 2329 "gout_hsi0_usb31drd_i_usbpcs_apb_clk", "mout_hsi0_bus", 2330 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, 2331 21, 0, 0), 2332 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK, 2333 "gout_hsi0_usb31drd_usbdpphy_i_aclk", "mout_hsi0_bus", 2334 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, 2335 21, 0, 0), 2336 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK, 2337 "gout_hsi0_usb31drd_usbdpphy_udbg_i_apb_pclk", "mout_hsi0_bus", 2338 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, 2339 21, 0, 0), 2340 /* TODO: should have a driver for this */ 2341 GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK, 2342 "gout_hsi0_xiu_d0_hsi0_aclk", "mout_hsi0_bus", 2343 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, 2344 21, CLK_IGNORE_UNUSED, 0), 2345 /* TODO: should have a driver for this */ 2346 GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK, 2347 "gout_hsi0_xiu_d1_hsi0_aclk", "mout_hsi0_bus", 2348 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, 2349 21, CLK_IGNORE_UNUSED, 0), 2350 /* TODO: should have a driver for this */ 2351 GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK, 2352 "gout_hsi0_xiu_p_hsi0_aclk", "mout_hsi0_bus", 2353 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, 2354 21, CLK_IGNORE_UNUSED, 0), 2355 }; 2356 2357 static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = { 2358 FRATE(0, "tcxo_hsi1_hsi0", NULL, 0, 26000000), 2359 FRATE(0, "usb20phy_phy_clock", NULL, 0, 120000000), 2360 /* until we implement APMGSA */ 2361 FRATE(0, "ioclk_clk_hsi0_alt", NULL, 0, 213000000), 2362 }; 2363 2364 static const struct samsung_cmu_info hsi0_cmu_info __initconst = { 2365 .pll_clks = cmu_hsi0_pll_clks, 2366 .nr_pll_clks = ARRAY_SIZE(cmu_hsi0_pll_clks), 2367 .mux_clks = hsi0_mux_clks, 2368 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks), 2369 .div_clks = hsi0_div_clks, 2370 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks), 2371 .gate_clks = hsi0_gate_clks, 2372 .nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks), 2373 .fixed_clks = hsi0_fixed_clks, 2374 .nr_fixed_clks = ARRAY_SIZE(hsi0_fixed_clks), 2375 .nr_clk_ids = CLKS_NR_HSI0, 2376 .clk_regs = hsi0_clk_regs, 2377 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs), 2378 .clk_name = "bus", 2379 }; 2380 2381 /* ---- CMU_HSI2 ------------------------------------------------------------ */ 2382 2383 /* Register Offset definitions for CMU_HSI2 (0x14400000) */ 2384 #define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600 2385 #define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604 2386 #define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610 2387 #define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614 2388 #define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620 2389 #define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624 2390 #define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630 2391 #define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634 2392 #define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800 2393 #define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810 2394 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000 2395 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004 2396 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008 2397 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c 2398 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010 2399 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014 2400 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c 2401 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020 2402 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024 2403 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028 2404 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c 2405 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030 2406 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034 2407 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038 2408 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c 2409 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040 2410 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044 2411 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048 2412 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c 2413 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050 2414 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054 2415 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058 2416 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c 2417 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060 2418 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064 2419 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068 2420 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c 2421 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070 2422 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074 2423 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078 2424 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c 2425 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080 2426 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084 2427 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088 2428 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c 2429 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090 2430 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094 2431 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098 2432 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c 2433 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0 2434 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4 2435 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8 2436 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac 2437 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0 2438 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4 2439 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8 2440 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc 2441 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0 2442 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4 2443 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8 2444 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc 2445 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0 2446 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4 2447 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8 2448 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc 2449 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0 2450 #define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000 2451 #define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008 2452 #define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c 2453 #define QCH_CON_D_TZPC_HSI2_QCH 0x3010 2454 #define QCH_CON_GPC_HSI2_QCH 0x3014 2455 #define QCH_CON_GPIO_HSI2_QCH 0x3018 2456 #define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c 2457 #define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020 2458 #define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024 2459 #define QCH_CON_MMC_CARD_QCH 0x3028 2460 #define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c 2461 #define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030 2462 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034 2463 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038 2464 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c 2465 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040 2466 #define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044 2467 #define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048 2468 #define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c 2469 #define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050 2470 #define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054 2471 #define QCH_CON_PPMU_HSI2_QCH 0x3058 2472 #define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c 2473 #define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060 2474 #define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064 2475 #define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068 2476 #define QCH_CON_SSMT_HSI2_QCH 0x306c 2477 #define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070 2478 #define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074 2479 #define QCH_CON_SYSMMU_HSI2_QCH 0x3078 2480 #define QCH_CON_SYSREG_HSI2_QCH 0x307c 2481 #define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080 2482 #define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084 2483 #define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088 2484 #define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c 2485 #define QCH_CON_UFS_EMBD_QCH 0x3090 2486 #define QCH_CON_UFS_EMBD_QCH_FMP 0x3094 2487 #define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00 2488 2489 static const unsigned long cmu_hsi2_clk_regs[] __initconst = { 2490 PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 2491 PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER, 2492 PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER, 2493 PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER, 2494 PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER, 2495 PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER, 2496 PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 2497 PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 2498 HSI2_CMU_HSI2_CONTROLLER_OPTION, 2499 CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0, 2500 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 2501 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 2502 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, 2503 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, 2504 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, 2505 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, 2506 CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, 2507 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 2508 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 2509 CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, 2510 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK, 2511 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK, 2512 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, 2513 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 2514 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 2515 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 2516 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 2517 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 2518 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 2519 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 2520 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 2521 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 2522 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, 2523 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, 2524 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 2525 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, 2526 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, 2527 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, 2528 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, 2529 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, 2530 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, 2531 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, 2532 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, 2533 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, 2534 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, 2535 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, 2536 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, 2537 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK, 2538 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, 2539 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, 2540 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, 2541 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, 2542 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, 2543 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, 2544 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, 2545 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, 2546 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, 2547 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, 2548 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, 2549 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, 2550 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, 2551 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 2552 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 2553 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 2554 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, 2555 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, 2556 DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1, 2557 PCH_CON_LHM_AXI_P_HSI2_PCH, 2558 PCH_CON_LHS_ACEL_D_HSI2_PCH, 2559 QCH_CON_D_TZPC_HSI2_QCH, 2560 QCH_CON_GPC_HSI2_QCH, 2561 QCH_CON_GPIO_HSI2_QCH, 2562 QCH_CON_HSI2_CMU_HSI2_QCH, 2563 QCH_CON_LHM_AXI_P_HSI2_QCH, 2564 QCH_CON_LHS_ACEL_D_HSI2_QCH, 2565 QCH_CON_MMC_CARD_QCH, 2566 QCH_CON_PCIE_GEN4_1_QCH_APB_1, 2567 QCH_CON_PCIE_GEN4_1_QCH_APB_2, 2568 QCH_CON_PCIE_GEN4_1_QCH_AXI_1, 2569 QCH_CON_PCIE_GEN4_1_QCH_AXI_2, 2570 QCH_CON_PCIE_GEN4_1_QCH_DBG_1, 2571 QCH_CON_PCIE_GEN4_1_QCH_DBG_2, 2572 QCH_CON_PCIE_GEN4_1_QCH_PCS_APB, 2573 QCH_CON_PCIE_GEN4_1_QCH_PMA_APB, 2574 QCH_CON_PCIE_GEN4_1_QCH_UDBG, 2575 QCH_CON_PCIE_IA_GEN4A_1_QCH, 2576 QCH_CON_PCIE_IA_GEN4B_1_QCH, 2577 QCH_CON_PPMU_HSI2_QCH, 2578 QCH_CON_QE_MMC_CARD_HSI2_QCH, 2579 QCH_CON_QE_PCIE_GEN4A_HSI2_QCH, 2580 QCH_CON_QE_PCIE_GEN4B_HSI2_QCH, 2581 QCH_CON_QE_UFS_EMBD_HSI2_QCH, 2582 QCH_CON_SSMT_HSI2_QCH, 2583 QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH, 2584 QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH, 2585 QCH_CON_SYSMMU_HSI2_QCH, 2586 QCH_CON_SYSREG_HSI2_QCH, 2587 QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH, 2588 QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH, 2589 QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH, 2590 QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH, 2591 QCH_CON_UFS_EMBD_QCH, 2592 QCH_CON_UFS_EMBD_QCH_FMP, 2593 QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2, 2594 }; 2595 2596 PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" }; 2597 PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" }; 2598 PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" }; 2599 PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" }; 2600 2601 static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = { 2602 MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p, 2603 PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1), 2604 MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user", 2605 mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER, 2606 4, 1), 2607 MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user", 2608 mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER, 2609 4, 1), 2610 MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user", 2611 mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 2612 4, 1), 2613 }; 2614 2615 static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = { 2616 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN, 2617 "gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in", 2618 "mout_hsi2_pcie_user", 2619 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 2620 21, 0, 0), 2621 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN, 2622 "gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in", 2623 "mout_hsi2_pcie_user", 2624 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 2625 21, 0, 0), 2626 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK, 2627 "gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk", "mout_hsi2_bus_user", 2628 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, 2629 21, 0, 0), 2630 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK, 2631 "gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk", "mout_hsi2_bus_user", 2632 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, 2633 21, 0, 0), 2634 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK, 2635 "gout_hsi2_ssmt_pcie_ia_gen4b_1_aclk", "mout_hsi2_bus_user", 2636 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, 2637 21, 0, 0), 2638 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK, 2639 "gout_hsi2_ssmt_pcie_ia_gen4b_1_pclk", "mout_hsi2_bus_user", 2640 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, 2641 21, 0, 0), 2642 GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK, 2643 "gout_hsi2_d_tzpc_hsi2_pclk", "mout_hsi2_bus_user", 2644 CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, 2645 21, 0, 0), 2646 GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK, 2647 "gout_hsi2_gpc_hsi2_pclk", "mout_hsi2_bus_user", 2648 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0), 2649 GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK, 2650 "gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user", 2651 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21, 2652 CLK_IGNORE_UNUSED, 0), 2653 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2654 GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK, 2655 "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user", 2656 CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, 2657 21, CLK_IS_CRITICAL, 0), 2658 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2659 GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK, 2660 "gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user", 2661 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK, 2662 21, CLK_IS_CRITICAL, 0), 2663 /* TODO: should have a driver for this */ 2664 GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK, 2665 "gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user", 2666 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK, 2667 21, CLK_IGNORE_UNUSED, 0), 2668 GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK, 2669 "gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user", 2670 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, 2671 21, 0, 0), 2672 GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN, 2673 "gout_hsi2_mmc_card_sdclkin", "mout_hsi2_mmc_card_user", 2674 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 2675 21, 0, 0), 2676 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG, 2677 "gout_hsi2_pcie_gen4_1_pcie_003_dbi_aclk_ug", "mout_hsi2_bus_user", 2678 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 2679 21, 0, 0), 2680 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG, 2681 "gout_hsi2_pcie_gen4_1_pcie_003_mstr_aclk_ug", 2682 "mout_hsi2_bus_user", 2683 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 2684 21, 0, 0), 2685 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG, 2686 "gout_hsi2_pcie_gen4_1_pcie_003_slv_aclk_ug", "mout_hsi2_bus_user", 2687 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 2688 21, 0, 0), 2689 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK, 2690 "gout_hsi2_pcie_gen4_1_pcie_003_i_driver_apb_clk", 2691 "mout_hsi2_bus_user", 2692 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 2693 21, 0, 0), 2694 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG, 2695 "gout_hsi2_pcie_gen4_1_pcie_004_dbi_aclk_ug", "mout_hsi2_bus_user", 2696 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 2697 21, 0, 0), 2698 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG, 2699 "gout_hsi2_pcie_gen4_1_pcie_004_mstr_aclk_ug", 2700 "mout_hsi2_bus_user", 2701 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 2702 21, 0, 0), 2703 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG, 2704 "gout_hsi2_pcie_gen4_1_pcie_004_slv_aclk_ug", "mout_hsi2_bus_user", 2705 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 2706 21, 0, 0), 2707 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK, 2708 "gout_hsi2_pcie_gen4_1_pcie_004_i_driver_apb_clk", 2709 "mout_hsi2_bus_user", 2710 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 2711 21, 0, 0), 2712 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK, 2713 "gout_hsi2_pcie_gen4_1_pcs_pma_phy_udbg_i_apb_pclk", 2714 "mout_hsi2_bus_user", 2715 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, 2716 21, 0, 0), 2717 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK, 2718 "gout_hsi2_pcie_gen4_1_pcs_pma_pipe_pal_pcie_i_apb_pclk", 2719 "mout_hsi2_bus_user", 2720 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, 2721 21, 0, 0), 2722 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK, 2723 "gout_hsi2_pcie_gen4_1_pcs_pma_pciephy210x2_qch_i_apb_pclk", 2724 "mout_hsi2_bus_user", 2725 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 2726 21, 0, 0), 2727 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK, 2728 "gout_hsi2_pcie_ia_gen4a_1_i_clk", "mout_hsi2_bus_user", 2729 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, 2730 21, 0, 0), 2731 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK, 2732 "gout_hsi2_pcie_ia_gen4b_1_i_clk", "mout_hsi2_bus_user", 2733 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, 2734 21, 0, 0), 2735 GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK, 2736 "gout_hsi2_ppmu_hsi2_aclk", "mout_hsi2_bus_user", 2737 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, 2738 21, 0, 0), 2739 GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK, 2740 "gout_hsi2_ppmu_hsi2_pclk", "mout_hsi2_bus_user", 2741 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, 2742 21, 0, 0), 2743 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK, 2744 "gout_hsi2_qe_mmc_card_hsi2_aclk", "mout_hsi2_bus_user", 2745 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, 2746 21, 0, 0), 2747 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK, 2748 "gout_hsi2_qe_mmc_card_hsi2_pclk", "mout_hsi2_bus_user", 2749 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, 2750 21, 0, 0), 2751 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK, 2752 "gout_hsi2_qe_pcie_gen4a_hsi2_aclk", "mout_hsi2_bus_user", 2753 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, 2754 21, 0, 0), 2755 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK, 2756 "gout_hsi2_qe_pcie_gen4a_hsi2_pclk", "mout_hsi2_bus_user", 2757 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, 2758 21, 0, 0), 2759 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK, 2760 "gout_hsi2_qe_pcie_gen4b_hsi2_aclk", "mout_hsi2_bus_user", 2761 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, 2762 21, 0, 0), 2763 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK, 2764 "gout_hsi2_qe_pcie_gen4b_hsi2_pclk", "mout_hsi2_bus_user", 2765 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, 2766 21, 0, 0), 2767 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK, 2768 "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user", 2769 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, 2770 21, CLK_IS_CRITICAL, 0), 2771 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK, 2772 "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user", 2773 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, 2774 21, CLK_IS_CRITICAL, 0), 2775 GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK, 2776 "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user", 2777 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK, 2778 21, CLK_IS_CRITICAL, 0), 2779 GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK, 2780 "gout_hsi2_clk_hsi2_oscclk_clk", "oscclk", 2781 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, 2782 21, 0, 0), 2783 /* TODO: should have a driver for this */ 2784 GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK, 2785 "gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user", 2786 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, 2787 21, CLK_IGNORE_UNUSED, 0), 2788 /* TODO: should have a driver for this */ 2789 GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK, 2790 "gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user", 2791 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, 2792 21, CLK_IGNORE_UNUSED, 0), 2793 /* TODO: should have a driver for this */ 2794 GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2, 2795 "gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user", 2796 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, 2797 21, CLK_IGNORE_UNUSED, 0), 2798 GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK, 2799 "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user", 2800 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, 2801 21, CLK_IS_CRITICAL, 0), 2802 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK, 2803 "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user", 2804 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, 2805 21, 0, 0), 2806 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK, 2807 "gout_hsi2_uasc_pcie_gen4a_dbi_1_pclk", "mout_hsi2_bus_user", 2808 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, 2809 21, 0, 0), 2810 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK, 2811 "gout_hsi2_uasc_pcie_gen4a_slv_1_aclk", "mout_hsi2_bus_user", 2812 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, 2813 21, 0, 0), 2814 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK, 2815 "gout_hsi2_uasc_pcie_gen4a_slv_1_pclk", "mout_hsi2_bus_user", 2816 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, 2817 21, 0, 0), 2818 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK, 2819 "gout_hsi2_uasc_pcie_gen4b_dbi_1_aclk", "mout_hsi2_bus_user", 2820 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, 2821 21, 0, 0), 2822 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK, 2823 "gout_hsi2_uasc_pcie_gen4b_dbi_1_pclk", "mout_hsi2_bus_user", 2824 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, 2825 21, 0, 0), 2826 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK, 2827 "gout_hsi2_uasc_pcie_gen4b_slv_1_aclk", "mout_hsi2_bus_user", 2828 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, 2829 21, 0, 0), 2830 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK, 2831 "gout_hsi2_uasc_pcie_gen4b_slv_1_pclk", "mout_hsi2_bus_user", 2832 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, 2833 21, 0, 0), 2834 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK, 2835 "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user", 2836 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 2837 21, CLK_IS_CRITICAL, 0), 2838 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO, 2839 "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user", 2840 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 2841 21, CLK_IS_CRITICAL, 0), 2842 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK, 2843 "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user", 2844 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 2845 21, CLK_IS_CRITICAL, 0), 2846 /* TODO: should have a driver for this */ 2847 GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK, 2848 "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user", 2849 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, 2850 21, CLK_IGNORE_UNUSED, 0), 2851 /* TODO: should have a driver for this */ 2852 GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK, 2853 "gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user", 2854 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, 2855 21, CLK_IGNORE_UNUSED, 0), 2856 }; 2857 2858 static const struct samsung_cmu_info hsi2_cmu_info __initconst = { 2859 .mux_clks = hsi2_mux_clks, 2860 .nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks), 2861 .gate_clks = hsi2_gate_clks, 2862 .nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks), 2863 .nr_clk_ids = CLKS_NR_HSI2, 2864 .clk_regs = cmu_hsi2_clk_regs, 2865 .nr_clk_regs = ARRAY_SIZE(cmu_hsi2_clk_regs), 2866 .clk_name = "bus", 2867 }; 2868 2869 /* ---- CMU_MISC ------------------------------------------------------------ */ 2870 2871 /* Register Offset definitions for CMU_MISC (0x10010000) */ 2872 #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600 2873 #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604 2874 #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610 2875 #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614 2876 #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800 2877 #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810 2878 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 2879 #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800 2880 #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804 2881 #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000 2882 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004 2883 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008 2884 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c 2885 #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010 2886 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014 2887 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018 2888 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c 2889 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020 2890 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024 2891 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028 2892 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c 2893 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030 2894 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034 2895 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038 2896 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c 2897 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040 2898 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044 2899 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048 2900 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c 2901 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050 2902 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054 2903 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058 2904 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c 2905 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060 2906 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064 2907 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068 2908 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c 2909 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070 2910 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074 2911 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078 2912 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c 2913 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080 2914 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084 2915 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088 2916 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c 2917 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090 2918 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094 2919 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098 2920 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c 2921 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0 2922 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4 2923 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8 2924 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac 2925 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0 2926 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4 2927 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8 2928 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc 2929 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0 2930 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4 2931 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8 2932 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc 2933 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0 2934 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4 2935 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8 2936 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc 2937 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0 2938 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4 2939 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8 2940 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec 2941 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0 2942 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4 2943 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8 2944 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc 2945 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100 2946 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104 2947 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108 2948 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c 2949 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110 2950 #define DMYQCH_CON_PPMU_DMA_QCH 0x3000 2951 #define DMYQCH_CON_PUF_QCH 0x3004 2952 #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c 2953 #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010 2954 #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014 2955 #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018 2956 #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c 2957 #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020 2958 #define QCH_CON_ADM_AHB_SSS_QCH 0x3024 2959 #define QCH_CON_DIT_QCH 0x3028 2960 #define QCH_CON_GIC_QCH 0x3030 2961 #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038 2962 #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c 2963 #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040 2964 #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044 2965 #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048 2966 #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c 2967 #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050 2968 #define QCH_CON_MCT_QCH 0x3054 2969 #define QCH_CON_MISC_CMU_MISC_QCH 0x3058 2970 #define QCH_CON_OTP_CON_BIRA_QCH 0x305c 2971 #define QCH_CON_OTP_CON_BISR_QCH 0x3060 2972 #define QCH_CON_OTP_CON_TOP_QCH 0x3064 2973 #define QCH_CON_PDMA_QCH 0x3068 2974 #define QCH_CON_PPMU_MISC_QCH 0x306c 2975 #define QCH_CON_QE_DIT_QCH 0x3070 2976 #define QCH_CON_QE_PDMA_QCH 0x3074 2977 #define QCH_CON_QE_PPMU_DMA_QCH 0x3078 2978 #define QCH_CON_QE_RTIC_QCH 0x307c 2979 #define QCH_CON_QE_SPDMA_QCH 0x3080 2980 #define QCH_CON_QE_SSS_QCH 0x3084 2981 #define QCH_CON_RTIC_QCH 0x3088 2982 #define QCH_CON_SPDMA_QCH 0x308c 2983 #define QCH_CON_SSMT_DIT_QCH 0x3090 2984 #define QCH_CON_SSMT_PDMA_QCH 0x3094 2985 #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098 2986 #define QCH_CON_SSMT_RTIC_QCH 0x309c 2987 #define QCH_CON_SSMT_SPDMA_QCH 0x30a0 2988 #define QCH_CON_SSMT_SSS_QCH 0x30a4 2989 #define QCH_CON_SSS_QCH 0x30a8 2990 #define QCH_CON_SYSMMU_MISC_QCH 0x30ac 2991 #define QCH_CON_SYSMMU_SSS_QCH 0x30b0 2992 #define QCH_CON_SYSREG_MISC_QCH 0x30b4 2993 #define QCH_CON_TMU_SUB_QCH 0x30b8 2994 #define QCH_CON_TMU_TOP_QCH 0x30bc 2995 #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0 2996 #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4 2997 #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00 2998 2999 static const unsigned long misc_clk_regs[] __initconst = { 3000 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 3001 PLL_CON1_MUX_CLKCMU_MISC_BUS_USER, 3002 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 3003 PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, 3004 MISC_CMU_MISC_CONTROLLER_OPTION, 3005 CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0, 3006 CLK_CON_MUX_MUX_CLK_MISC_GIC, 3007 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 3008 CLK_CON_DIV_DIV_CLK_MISC_GIC, 3009 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 3010 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 3011 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 3012 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 3013 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 3014 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 3015 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 3016 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, 3017 CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, 3018 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 3019 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 3020 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 3021 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 3022 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 3023 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 3024 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 3025 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 3026 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 3027 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 3028 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 3029 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 3030 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 3031 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 3032 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 3033 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK, 3034 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 3035 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 3036 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 3037 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 3038 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 3039 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 3040 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 3041 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 3042 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 3043 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 3044 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 3045 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 3046 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 3047 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 3048 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 3049 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 3050 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 3051 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 3052 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 3053 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 3054 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 3055 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 3056 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 3057 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 3058 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 3059 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 3060 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 3061 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 3062 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 3063 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 3064 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 3065 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 3066 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 3067 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 3068 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 3069 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 3070 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 3071 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 3072 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 3073 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 3074 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 3075 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 3076 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 3077 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 3078 DMYQCH_CON_PPMU_DMA_QCH, 3079 DMYQCH_CON_PUF_QCH, 3080 PCH_CON_LHM_AXI_D_SSS_PCH, 3081 PCH_CON_LHM_AXI_P_GIC_PCH, 3082 PCH_CON_LHM_AXI_P_MISC_PCH, 3083 PCH_CON_LHS_ACEL_D_MISC_PCH, 3084 PCH_CON_LHS_AST_IRI_GICCPU_PCH, 3085 PCH_CON_LHS_AXI_D_SSS_PCH, 3086 QCH_CON_ADM_AHB_SSS_QCH, 3087 QCH_CON_DIT_QCH, 3088 QCH_CON_GIC_QCH, 3089 QCH_CON_LHM_AST_ICC_CPUGIC_QCH, 3090 QCH_CON_LHM_AXI_D_SSS_QCH, 3091 QCH_CON_LHM_AXI_P_GIC_QCH, 3092 QCH_CON_LHM_AXI_P_MISC_QCH, 3093 QCH_CON_LHS_ACEL_D_MISC_QCH, 3094 QCH_CON_LHS_AST_IRI_GICCPU_QCH, 3095 QCH_CON_LHS_AXI_D_SSS_QCH, 3096 QCH_CON_MCT_QCH, 3097 QCH_CON_MISC_CMU_MISC_QCH, 3098 QCH_CON_OTP_CON_BIRA_QCH, 3099 QCH_CON_OTP_CON_BISR_QCH, 3100 QCH_CON_OTP_CON_TOP_QCH, 3101 QCH_CON_PDMA_QCH, 3102 QCH_CON_PPMU_MISC_QCH, 3103 QCH_CON_QE_DIT_QCH, 3104 QCH_CON_QE_PDMA_QCH, 3105 QCH_CON_QE_PPMU_DMA_QCH, 3106 QCH_CON_QE_RTIC_QCH, 3107 QCH_CON_QE_SPDMA_QCH, 3108 QCH_CON_QE_SSS_QCH, 3109 QCH_CON_RTIC_QCH, 3110 QCH_CON_SPDMA_QCH, 3111 QCH_CON_SSMT_DIT_QCH, 3112 QCH_CON_SSMT_PDMA_QCH, 3113 QCH_CON_SSMT_PPMU_DMA_QCH, 3114 QCH_CON_SSMT_RTIC_QCH, 3115 QCH_CON_SSMT_SPDMA_QCH, 3116 QCH_CON_SSMT_SSS_QCH, 3117 QCH_CON_SSS_QCH, 3118 QCH_CON_SYSMMU_MISC_QCH, 3119 QCH_CON_SYSMMU_SSS_QCH, 3120 QCH_CON_SYSREG_MISC_QCH, 3121 QCH_CON_TMU_SUB_QCH, 3122 QCH_CON_TMU_TOP_QCH, 3123 QCH_CON_WDT_CLUSTER0_QCH, 3124 QCH_CON_WDT_CLUSTER1_QCH, 3125 QUEUE_CTRL_REG_BLK_MISC_CMU_MISC, 3126 }; 3127 3128 /* List of parent clocks for Muxes in CMU_MISC */ 3129 PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" }; 3130 PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" }; 3131 PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" }; 3132 3133 static const struct samsung_mux_clock misc_mux_clks[] __initconst = { 3134 MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p, 3135 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1), 3136 MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p, 3137 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1), 3138 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p, 3139 CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0), 3140 }; 3141 3142 static const struct samsung_div_clock misc_div_clks[] __initconst = { 3143 DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user", 3144 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3), 3145 DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user", 3146 CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3), 3147 }; 3148 3149 static const struct samsung_gate_clock misc_gate_clks[] __initconst = { 3150 GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK, 3151 "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp", 3152 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 3153 21, 0, 0), 3154 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK, 3155 "gout_misc_otp_con_bira_i_oscclk", "oscclk", 3156 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 3157 21, 0, 0), 3158 GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK, 3159 "gout_misc_otp_con_bisr_i_oscclk", "oscclk", 3160 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 3161 21, 0, 0), 3162 GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK, 3163 "gout_misc_otp_con_top_i_oscclk", "oscclk", 3164 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 3165 21, 0, 0), 3166 GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK, 3167 "gout_misc_clk_misc_oscclk_clk", "oscclk", 3168 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 3169 21, 0, 0), 3170 GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM, 3171 "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user", 3172 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 3173 21, 0, 0), 3174 GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM, 3175 "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user", 3176 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 3177 21, 0, 0), 3178 GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK, 3179 "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp", 3180 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 3181 21, 0, 0), 3182 GATE(CLK_GOUT_MISC_GIC_GICCLK, 3183 "gout_misc_gic_gicclk", "mout_misc_gic", 3184 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 3185 21, 0, 0), 3186 GATE(CLK_GOUT_MISC_GPC_MISC_PCLK, 3187 "gout_misc_gpc_misc_pclk", "dout_misc_busp", 3188 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 3189 21, 0, 0), 3190 GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK, 3191 "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic", 3192 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 3193 21, 0, 0), 3194 GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK, 3195 "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user", 3196 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 3197 21, 0, 0), 3198 GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK, 3199 "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic", 3200 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 3201 21, 0, 0), 3202 GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK, 3203 "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp", 3204 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 3205 21, 0, 0), 3206 GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK, 3207 "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user", 3208 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 3209 21, 0, 0), 3210 GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK, 3211 "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic", 3212 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 3213 21, 0, 0), 3214 GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK, 3215 "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user", 3216 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 3217 21, 0, 0), 3218 GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk", 3219 "dout_misc_busp", 3220 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 3221 21, 0, 0), 3222 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK, 3223 "gout_misc_otp_con_bira_pclk", "dout_misc_busp", 3224 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 3225 21, 0, 0), 3226 GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK, 3227 "gout_misc_otp_con_bisr_pclk", "dout_misc_busp", 3228 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 3229 21, 0, 0), 3230 GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK, 3231 "gout_misc_otp_con_top_pclk", "dout_misc_busp", 3232 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 3233 21, 0, 0), 3234 GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk", 3235 "mout_misc_bus_user", 3236 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 3237 21, 0, 0), 3238 GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK, 3239 "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user", 3240 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 3241 21, 0, 0), 3242 GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK, 3243 "gout_misc_ppmu_misc_pclk", "dout_misc_busp", 3244 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 3245 21, 0, 0), 3246 GATE(CLK_GOUT_MISC_PUF_I_CLK, 3247 "gout_misc_puf_i_clk", "mout_misc_sss_user", 3248 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 3249 21, 0, 0), 3250 GATE(CLK_GOUT_MISC_QE_DIT_ACLK, 3251 "gout_misc_qe_dit_aclk", "mout_misc_bus_user", 3252 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 3253 21, 0, 0), 3254 GATE(CLK_GOUT_MISC_QE_DIT_PCLK, 3255 "gout_misc_qe_dit_pclk", "dout_misc_busp", 3256 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 3257 21, 0, 0), 3258 GATE(CLK_GOUT_MISC_QE_PDMA_ACLK, 3259 "gout_misc_qe_pdma_aclk", "mout_misc_bus_user", 3260 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 3261 21, 0, 0), 3262 GATE(CLK_GOUT_MISC_QE_PDMA_PCLK, 3263 "gout_misc_qe_pdma_pclk", "dout_misc_busp", 3264 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 3265 21, 0, 0), 3266 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK, 3267 "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user", 3268 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 3269 21, 0, 0), 3270 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK, 3271 "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp", 3272 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 3273 21, 0, 0), 3274 GATE(CLK_GOUT_MISC_QE_RTIC_ACLK, 3275 "gout_misc_qe_rtic_aclk", "mout_misc_bus_user", 3276 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 3277 21, 0, 0), 3278 GATE(CLK_GOUT_MISC_QE_RTIC_PCLK, 3279 "gout_misc_qe_rtic_pclk", "dout_misc_busp", 3280 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 3281 21, 0, 0), 3282 GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK, 3283 "gout_misc_qe_spdma_aclk", "mout_misc_bus_user", 3284 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 3285 21, 0, 0), 3286 GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK, 3287 "gout_misc_qe_spdma_pclk", "dout_misc_busp", 3288 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 3289 21, 0, 0), 3290 GATE(CLK_GOUT_MISC_QE_SSS_ACLK, 3291 "gout_misc_qe_sss_aclk", "mout_misc_sss_user", 3292 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 3293 21, 0, 0), 3294 GATE(CLK_GOUT_MISC_QE_SSS_PCLK, 3295 "gout_misc_qe_sss_pclk", "dout_misc_busp", 3296 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 3297 21, 0, 0), 3298 GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK, 3299 "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user", 3300 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 3301 21, 0, 0), 3302 GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK, 3303 "gout_misc_clk_misc_busp_clk", "dout_misc_busp", 3304 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 3305 21, 0, 0), 3306 GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK, 3307 "gout_misc_clk_misc_gic_clk", "mout_misc_gic", 3308 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 3309 21, 0, 0), 3310 GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK, 3311 "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user", 3312 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 3313 21, 0, 0), 3314 GATE(CLK_GOUT_MISC_RTIC_I_ACLK, 3315 "gout_misc_rtic_i_aclk", "mout_misc_bus_user", 3316 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 3317 21, 0, 0), 3318 GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk", 3319 "dout_misc_busp", 3320 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 3321 21, 0, 0), 3322 GATE(CLK_GOUT_MISC_SPDMA_ACLK, 3323 "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user", 3324 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 3325 21, 0, 0), 3326 GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK, 3327 "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user", 3328 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 3329 21, 0, 0), 3330 GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK, 3331 "gout_misc_ssmt_dit_pclk", "dout_misc_busp", 3332 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 3333 21, 0, 0), 3334 GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK, 3335 "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user", 3336 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 3337 21, 0, 0), 3338 GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK, 3339 "gout_misc_ssmt_pdma_pclk", "dout_misc_busp", 3340 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 3341 21, 0, 0), 3342 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK, 3343 "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user", 3344 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 3345 21, 0, 0), 3346 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK, 3347 "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp", 3348 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 3349 21, 0, 0), 3350 GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK, 3351 "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user", 3352 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 3353 21, 0, 0), 3354 GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK, 3355 "gout_misc_ssmt_rtic_pclk", "dout_misc_busp", 3356 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 3357 21, 0, 0), 3358 GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK, 3359 "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user", 3360 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 3361 21, 0, 0), 3362 GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK, 3363 "gout_misc_ssmt_spdma_pclk", "dout_misc_busp", 3364 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 3365 21, 0, 0), 3366 GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK, 3367 "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user", 3368 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 3369 21, 0, 0), 3370 GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK, 3371 "gout_misc_ssmt_sss_pclk", "dout_misc_busp", 3372 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 3373 21, 0, 0), 3374 GATE(CLK_GOUT_MISC_SSS_I_ACLK, 3375 "gout_misc_sss_i_aclk", "mout_misc_bus_user", 3376 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 3377 21, 0, 0), 3378 GATE(CLK_GOUT_MISC_SSS_I_PCLK, 3379 "gout_misc_sss_i_pclk", "dout_misc_busp", 3380 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 3381 21, 0, 0), 3382 GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2, 3383 "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user", 3384 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 3385 21, 0, 0), 3386 GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1, 3387 "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user", 3388 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 3389 21, 0, 0), 3390 GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK, 3391 "gout_misc_sysreg_misc_pclk", "dout_misc_busp", 3392 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 3393 21, 0, 0), 3394 GATE(CLK_GOUT_MISC_TMU_SUB_PCLK, 3395 "gout_misc_tmu_sub_pclk", "dout_misc_busp", 3396 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 3397 21, 0, 0), 3398 GATE(CLK_GOUT_MISC_TMU_TOP_PCLK, 3399 "gout_misc_tmu_top_pclk", "dout_misc_busp", 3400 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 3401 21, 0, 0), 3402 GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK, 3403 "gout_misc_wdt_cluster0_pclk", "dout_misc_busp", 3404 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 3405 21, 0, 0), 3406 GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK, 3407 "gout_misc_wdt_cluster1_pclk", "dout_misc_busp", 3408 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 3409 21, 0, 0), 3410 GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK, 3411 "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user", 3412 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 3413 21, 0, 0), 3414 }; 3415 3416 static const struct samsung_cmu_info misc_cmu_info __initconst = { 3417 .mux_clks = misc_mux_clks, 3418 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), 3419 .div_clks = misc_div_clks, 3420 .nr_div_clks = ARRAY_SIZE(misc_div_clks), 3421 .gate_clks = misc_gate_clks, 3422 .nr_gate_clks = ARRAY_SIZE(misc_gate_clks), 3423 .nr_clk_ids = CLKS_NR_MISC, 3424 .clk_regs = misc_clk_regs, 3425 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), 3426 .clk_name = "bus", 3427 }; 3428 3429 static void __init gs101_cmu_misc_init(struct device_node *np) 3430 { 3431 exynos_arm64_register_cmu(NULL, np, &misc_cmu_info); 3432 } 3433 3434 /* Register CMU_MISC early, as it's needed for MCT timer */ 3435 CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc", 3436 gs101_cmu_misc_init); 3437 3438 /* ---- CMU_PERIC0 ---------------------------------------------------------- */ 3439 3440 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */ 3441 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 3442 #define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 3443 #define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 3444 #define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 3445 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 3446 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 3447 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 3448 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 3449 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 3450 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 3451 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 3452 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 3453 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 3454 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 3455 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 3456 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 3457 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 3458 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 3459 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 3460 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 3461 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 3462 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 3463 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 3464 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 3465 #define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 3466 #define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 3467 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 3468 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 3469 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c 3470 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 3471 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 3472 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 3473 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 3474 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 3475 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c 3476 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 3477 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 3478 #define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 3479 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 3480 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 3481 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c 3482 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 3483 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 3484 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018 3485 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c 3486 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020 3487 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024 3488 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028 3489 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c 3490 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030 3491 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034 3492 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038 3493 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c 3494 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040 3495 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044 3496 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048 3497 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c 3498 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050 3499 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054 3500 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058 3501 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c 3502 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060 3503 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064 3504 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068 3505 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c 3506 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070 3507 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074 3508 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078 3509 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c 3510 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080 3511 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084 3512 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088 3513 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c 3514 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090 3515 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094 3516 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098 3517 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c 3518 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4 3519 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8 3520 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0 3521 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 3522 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8 3523 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc 3524 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4 3525 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8 3526 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc 3527 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0 3528 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4 3529 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8 3530 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc 3531 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0 3532 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4 3533 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8 3534 #define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 3535 #define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 3536 #define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 3537 #define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c 3538 #define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 3539 #define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 3540 #define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 3541 #define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c 3542 #define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 3543 #define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 3544 #define QCH_CON_GPC_PERIC0_QCH 0x3028 3545 #define QCH_CON_GPIO_PERIC0_QCH 0x302c 3546 #define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 3547 #define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 3548 #define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 3549 #define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c 3550 #define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 3551 #define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 3552 #define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 3553 #define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c 3554 #define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 3555 #define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 3556 #define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 3557 #define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c 3558 #define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 3559 #define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 3560 #define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 3561 #define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c 3562 #define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 3563 #define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 3564 #define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 3565 #define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c 3566 #define QCH_CON_SYSREG_PERIC0_QCH 0x3080 3567 #define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 3568 3569 static const unsigned long peric0_clk_regs[] __initconst = { 3570 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 3571 PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, 3572 PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 3573 PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, 3574 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 3575 PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, 3576 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 3577 PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, 3578 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 3579 PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, 3580 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 3581 PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, 3582 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 3583 PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, 3584 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 3585 PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, 3586 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 3587 PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, 3588 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 3589 PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, 3590 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 3591 PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, 3592 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 3593 PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, 3594 PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 3595 CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, 3596 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 3597 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 3598 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 3599 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 3600 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 3601 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 3602 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 3603 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 3604 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 3605 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 3606 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 3607 CLK_CON_BUF_CLKBUF_PERIC0_IP, 3608 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 3609 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 3610 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 3611 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 3612 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 3613 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 3614 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 3615 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 3616 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 3617 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 3618 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 3619 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 3620 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 3621 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 3622 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 3623 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 3624 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 3625 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 3626 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 3627 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 3628 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 3629 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 3630 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 3631 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 3632 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 3633 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 3634 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 3635 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 3636 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 3637 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 3638 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 3639 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 3640 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 3641 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 3642 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 3643 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 3644 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 3645 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 3646 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 3647 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 3648 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 3649 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, 3650 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 3651 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 3652 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 3653 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 3654 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 3655 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 3656 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 3657 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 3658 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 3659 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 3660 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 3661 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 3662 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 3663 DMYQCH_CON_PERIC0_TOP0_QCH_S1, 3664 DMYQCH_CON_PERIC0_TOP0_QCH_S2, 3665 DMYQCH_CON_PERIC0_TOP0_QCH_S3, 3666 DMYQCH_CON_PERIC0_TOP0_QCH_S4, 3667 DMYQCH_CON_PERIC0_TOP0_QCH_S5, 3668 DMYQCH_CON_PERIC0_TOP0_QCH_S6, 3669 DMYQCH_CON_PERIC0_TOP0_QCH_S7, 3670 DMYQCH_CON_PERIC0_TOP0_QCH_S8, 3671 PCH_CON_LHM_AXI_P_PERIC0_PCH, 3672 QCH_CON_D_TZPC_PERIC0_QCH, 3673 QCH_CON_GPC_PERIC0_QCH, 3674 QCH_CON_GPIO_PERIC0_QCH, 3675 QCH_CON_LHM_AXI_P_PERIC0_QCH, 3676 QCH_CON_PERIC0_CMU_PERIC0_QCH, 3677 QCH_CON_PERIC0_TOP0_QCH_I3C1, 3678 QCH_CON_PERIC0_TOP0_QCH_I3C2, 3679 QCH_CON_PERIC0_TOP0_QCH_I3C3, 3680 QCH_CON_PERIC0_TOP0_QCH_I3C4, 3681 QCH_CON_PERIC0_TOP0_QCH_I3C5, 3682 QCH_CON_PERIC0_TOP0_QCH_I3C6, 3683 QCH_CON_PERIC0_TOP0_QCH_I3C7, 3684 QCH_CON_PERIC0_TOP0_QCH_I3C8, 3685 QCH_CON_PERIC0_TOP0_QCH_USI1_USI, 3686 QCH_CON_PERIC0_TOP0_QCH_USI2_USI, 3687 QCH_CON_PERIC0_TOP0_QCH_USI3_USI, 3688 QCH_CON_PERIC0_TOP0_QCH_USI4_USI, 3689 QCH_CON_PERIC0_TOP0_QCH_USI5_USI, 3690 QCH_CON_PERIC0_TOP0_QCH_USI6_USI, 3691 QCH_CON_PERIC0_TOP0_QCH_USI7_USI, 3692 QCH_CON_PERIC0_TOP0_QCH_USI8_USI, 3693 QCH_CON_PERIC0_TOP1_QCH_USI0_UART, 3694 QCH_CON_PERIC0_TOP1_QCH_USI14_UART, 3695 QCH_CON_SYSREG_PERIC0_QCH, 3696 QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, 3697 }; 3698 3699 /* List of parent clocks for Muxes in CMU_PERIC0 */ 3700 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; 3701 PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 3702 PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 3703 PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 3704 3705 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { 3706 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", 3707 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), 3708 MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", 3709 mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), 3710 MUX(CLK_MOUT_PERIC0_USI0_UART_USER, 3711 "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, 3712 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), 3713 nMUX(CLK_MOUT_PERIC0_USI14_USI_USER, 3714 "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, 3715 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), 3716 nMUX(CLK_MOUT_PERIC0_USI1_USI_USER, 3717 "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, 3718 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), 3719 nMUX(CLK_MOUT_PERIC0_USI2_USI_USER, 3720 "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, 3721 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), 3722 nMUX(CLK_MOUT_PERIC0_USI3_USI_USER, 3723 "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, 3724 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), 3725 nMUX(CLK_MOUT_PERIC0_USI4_USI_USER, 3726 "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, 3727 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), 3728 nMUX(CLK_MOUT_PERIC0_USI5_USI_USER, 3729 "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, 3730 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), 3731 nMUX(CLK_MOUT_PERIC0_USI6_USI_USER, 3732 "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, 3733 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), 3734 nMUX(CLK_MOUT_PERIC0_USI7_USI_USER, 3735 "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, 3736 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), 3737 nMUX(CLK_MOUT_PERIC0_USI8_USI_USER, 3738 "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, 3739 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), 3740 }; 3741 3742 static const struct samsung_div_clock peric0_div_clks[] __initconst = { 3743 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", 3744 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4), 3745 DIV(CLK_DOUT_PERIC0_USI0_UART, 3746 "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", 3747 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4), 3748 DIV_F(CLK_DOUT_PERIC0_USI14_USI, 3749 "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", 3750 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4, 3751 CLK_SET_RATE_PARENT, 0), 3752 DIV_F(CLK_DOUT_PERIC0_USI1_USI, 3753 "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", 3754 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4, 3755 CLK_SET_RATE_PARENT, 0), 3756 DIV_F(CLK_DOUT_PERIC0_USI2_USI, 3757 "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", 3758 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4, 3759 CLK_SET_RATE_PARENT, 0), 3760 DIV_F(CLK_DOUT_PERIC0_USI3_USI, 3761 "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", 3762 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4, 3763 CLK_SET_RATE_PARENT, 0), 3764 DIV_F(CLK_DOUT_PERIC0_USI4_USI, 3765 "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", 3766 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4, 3767 CLK_SET_RATE_PARENT, 0), 3768 DIV_F(CLK_DOUT_PERIC0_USI5_USI, 3769 "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", 3770 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4, 3771 CLK_SET_RATE_PARENT, 0), 3772 DIV_F(CLK_DOUT_PERIC0_USI6_USI, 3773 "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", 3774 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4, 3775 CLK_SET_RATE_PARENT, 0), 3776 DIV_F(CLK_DOUT_PERIC0_USI7_USI, 3777 "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", 3778 CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4, 3779 CLK_SET_RATE_PARENT, 0), 3780 DIV_F(CLK_DOUT_PERIC0_USI8_USI, 3781 "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", 3782 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4, 3783 CLK_SET_RATE_PARENT, 0), 3784 }; 3785 3786 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { 3787 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 3788 GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, 3789 "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", 3790 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 3791 21, CLK_IS_CRITICAL, 0), 3792 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, 3793 "gout_peric0_clk_peric0_oscclk_clk", "oscclk", 3794 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 3795 21, 0, 0), 3796 GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, 3797 "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", 3798 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 3799 21, 0, 0), 3800 GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, 3801 "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", 3802 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 3803 21, 0, 0), 3804 GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, 3805 "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", 3806 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 3807 21, CLK_IGNORE_UNUSED, 0), 3808 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 3809 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, 3810 "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", 3811 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 3812 21, CLK_IS_CRITICAL, 0), 3813 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, 3814 "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", 3815 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 3816 21, CLK_SET_RATE_PARENT, 0), 3817 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, 3818 "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", 3819 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 3820 21, CLK_SET_RATE_PARENT, 0), 3821 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, 3822 "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", 3823 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 3824 21, 0, 0), 3825 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, 3826 "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", 3827 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 3828 21, 0, 0), 3829 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, 3830 "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", 3831 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 3832 21, 0, 0), 3833 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, 3834 "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", 3835 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 3836 21, 0, 0), 3837 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, 3838 "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", 3839 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 3840 21, 0, 0), 3841 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, 3842 "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", 3843 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 3844 21, 0, 0), 3845 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, 3846 "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", 3847 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 3848 21, CLK_SET_RATE_PARENT, 0), 3849 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, 3850 "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", 3851 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 3852 21, CLK_SET_RATE_PARENT, 0), 3853 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, 3854 "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", 3855 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 3856 21, CLK_SET_RATE_PARENT, 0), 3857 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, 3858 "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", 3859 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 3860 21, CLK_SET_RATE_PARENT, 0), 3861 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, 3862 "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", 3863 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 3864 21, CLK_SET_RATE_PARENT, 0), 3865 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, 3866 "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", 3867 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 3868 21, CLK_SET_RATE_PARENT, 0), 3869 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, 3870 "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", 3871 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 3872 21, 0, 0), 3873 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, 3874 "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", 3875 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 3876 21, 0, 0), 3877 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, 3878 "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", 3879 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 3880 21, 0, 0), 3881 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, 3882 "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", 3883 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 3884 21, 0, 0), 3885 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, 3886 "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", 3887 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 3888 21, 0, 0), 3889 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, 3890 "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", 3891 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 3892 21, 0, 0), 3893 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, 3894 "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", 3895 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 3896 21, 0, 0), 3897 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, 3898 "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", 3899 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 3900 21, 0, 0), 3901 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, 3902 "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", 3903 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 3904 21, 0, 0), 3905 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, 3906 "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", 3907 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 3908 21, 0, 0), 3909 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, 3910 "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", 3911 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 3912 21, 0, 0), 3913 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, 3914 "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", 3915 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 3916 21, 0, 0), 3917 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, 3918 "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", 3919 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 3920 21, 0, 0), 3921 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, 3922 "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", 3923 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 3924 21, 0, 0), 3925 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, 3926 "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", 3927 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 3928 21, 0, 0), 3929 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, 3930 "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", 3931 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 3932 21, 0, 0), 3933 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, 3934 "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", 3935 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 3936 21, 0, 0), 3937 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, 3938 "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", 3939 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 3940 21, 0, 0), 3941 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 3942 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, 3943 "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", 3944 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 3945 21, CLK_IS_CRITICAL, 0), 3946 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, 3947 "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", 3948 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 3949 21, CLK_SET_RATE_PARENT, 0), 3950 /* Disabling this clock makes the system hang. Mark the clock as critical. */ 3951 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, 3952 "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", 3953 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 3954 21, CLK_IS_CRITICAL, 0), 3955 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, 3956 "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", 3957 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, 3958 21, 0, 0), 3959 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, 3960 "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", 3961 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 3962 21, 0, 0), 3963 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, 3964 "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", 3965 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 3966 21, 0, 0), 3967 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, 3968 "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", 3969 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 3970 21, 0, 0), 3971 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, 3972 "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", 3973 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 3974 21, 0, 0), 3975 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, 3976 "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", 3977 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 3978 21, 0, 0), 3979 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, 3980 "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", 3981 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 3982 21, 0, 0), 3983 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, 3984 "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", 3985 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 3986 21, 0, 0), 3987 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, 3988 "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", 3989 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 3990 21, 0, 0), 3991 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, 3992 "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", 3993 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 3994 21, 0, 0), 3995 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, 3996 "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", 3997 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 3998 21, 0, 0), 3999 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, 4000 "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", 4001 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 4002 21, 0, 0), 4003 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, 4004 "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", 4005 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 4006 21, 0, 0), 4007 GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, 4008 "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", 4009 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 4010 21, 0, 0), 4011 }; 4012 4013 static const struct samsung_cmu_info peric0_cmu_info __initconst = { 4014 .mux_clks = peric0_mux_clks, 4015 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 4016 .div_clks = peric0_div_clks, 4017 .nr_div_clks = ARRAY_SIZE(peric0_div_clks), 4018 .gate_clks = peric0_gate_clks, 4019 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 4020 .nr_clk_ids = CLKS_NR_PERIC0, 4021 .clk_regs = peric0_clk_regs, 4022 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 4023 .clk_name = "bus", 4024 }; 4025 4026 /* ---- CMU_PERIC1 ---------------------------------------------------------- */ 4027 4028 /* Register Offset definitions for CMU_PERIC1 (0x10c00000) */ 4029 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 4030 #define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 4031 #define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610 4032 #define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614 4033 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620 4034 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624 4035 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630 4036 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634 4037 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640 4038 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644 4039 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650 4040 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654 4041 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660 4042 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664 4043 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670 4044 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674 4045 #define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800 4046 #define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810 4047 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 4048 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804 4049 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 4050 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c 4051 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 4052 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 4053 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818 4054 #define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000 4055 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004 4056 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008 4057 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c 4058 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010 4059 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014 4060 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 4061 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c 4062 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020 4063 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024 4064 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028 4065 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c 4066 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030 4067 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034 4068 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038 4069 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c 4070 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040 4071 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044 4072 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048 4073 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c 4074 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050 4075 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054 4076 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058 4077 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c 4078 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060 4079 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064 4080 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068 4081 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c 4082 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070 4083 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074 4084 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078 4085 #define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000 4086 #define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004 4087 #define QCH_CON_D_TZPC_PERIC1_QCH 0x3008 4088 #define QCH_CON_GPC_PERIC1_QCH 0x300c 4089 #define QCH_CON_GPIO_PERIC1_QCH 0x3010 4090 #define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014 4091 #define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018 4092 #define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c 4093 #define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020 4094 #define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024 4095 #define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028 4096 #define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c 4097 #define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030 4098 #define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034 4099 #define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038 4100 #define QCH_CON_SYSREG_PERIC1_QCH 0x303c 4101 #define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00 4102 4103 static const unsigned long peric1_clk_regs[] __initconst = { 4104 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4105 PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, 4106 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4107 PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER, 4108 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4109 PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4110 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4111 PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4112 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4113 PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4114 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4115 PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4116 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4117 PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4118 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4119 PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4120 PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 4121 CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0, 4122 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 4123 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 4124 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 4125 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 4126 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 4127 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 4128 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 4129 CLK_CON_BUF_CLKBUF_PERIC1_IP, 4130 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 4131 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 4132 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 4133 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 4134 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 4135 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 4136 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 4137 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 4138 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 4139 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 4140 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 4141 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 4142 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 4143 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 4144 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 4145 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, 4146 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 4147 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 4148 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 4149 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 4150 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 4151 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 4152 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 4153 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 4154 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 4155 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 4156 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 4157 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 4158 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 4159 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 4160 DMYQCH_CON_PERIC1_TOP0_QCH_S, 4161 PCH_CON_LHM_AXI_P_PERIC1_PCH, 4162 QCH_CON_D_TZPC_PERIC1_QCH, 4163 QCH_CON_GPC_PERIC1_QCH, 4164 QCH_CON_GPIO_PERIC1_QCH, 4165 QCH_CON_LHM_AXI_P_PERIC1_QCH, 4166 QCH_CON_PERIC1_CMU_PERIC1_QCH, 4167 QCH_CON_PERIC1_TOP0_QCH_I3C0, 4168 QCH_CON_PERIC1_TOP0_QCH_PWM, 4169 QCH_CON_PERIC1_TOP0_QCH_USI0_USI, 4170 QCH_CON_PERIC1_TOP0_QCH_USI10_USI, 4171 QCH_CON_PERIC1_TOP0_QCH_USI11_USI, 4172 QCH_CON_PERIC1_TOP0_QCH_USI12_USI, 4173 QCH_CON_PERIC1_TOP0_QCH_USI13_USI, 4174 QCH_CON_PERIC1_TOP0_QCH_USI9_USI, 4175 QCH_CON_SYSREG_PERIC1_QCH, 4176 QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1, 4177 }; 4178 4179 /* List of parent clocks for Muxes in CMU_PERIC1 */ 4180 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" }; 4181 PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" }; 4182 4183 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { 4184 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", 4185 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), 4186 MUX(CLK_MOUT_PERIC1_I3C_USER, 4187 "mout_peric1_i3c_user", mout_peric1_nonbususer_p, 4188 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1), 4189 nMUX(CLK_MOUT_PERIC1_USI0_USI_USER, 4190 "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, 4191 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), 4192 nMUX(CLK_MOUT_PERIC1_USI10_USI_USER, 4193 "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, 4194 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), 4195 nMUX(CLK_MOUT_PERIC1_USI11_USI_USER, 4196 "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, 4197 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), 4198 nMUX(CLK_MOUT_PERIC1_USI12_USI_USER, 4199 "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, 4200 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), 4201 nMUX(CLK_MOUT_PERIC1_USI13_USI_USER, 4202 "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, 4203 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), 4204 nMUX(CLK_MOUT_PERIC1_USI9_USI_USER, 4205 "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, 4206 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), 4207 }; 4208 4209 static const struct samsung_div_clock peric1_div_clks[] __initconst = { 4210 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user", 4211 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), 4212 DIV_F(CLK_DOUT_PERIC1_USI0_USI, 4213 "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", 4214 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4, 4215 CLK_SET_RATE_PARENT, 0), 4216 DIV_F(CLK_DOUT_PERIC1_USI10_USI, 4217 "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", 4218 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4, 4219 CLK_SET_RATE_PARENT, 0), 4220 DIV_F(CLK_DOUT_PERIC1_USI11_USI, 4221 "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", 4222 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4, 4223 CLK_SET_RATE_PARENT, 0), 4224 DIV_F(CLK_DOUT_PERIC1_USI12_USI, 4225 "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", 4226 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4, 4227 CLK_SET_RATE_PARENT, 0), 4228 DIV_F(CLK_DOUT_PERIC1_USI13_USI, 4229 "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", 4230 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4, 4231 CLK_SET_RATE_PARENT, 0), 4232 DIV_F(CLK_DOUT_PERIC1_USI9_USI, 4233 "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", 4234 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4, 4235 CLK_SET_RATE_PARENT, 0), 4236 }; 4237 4238 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { 4239 GATE(CLK_GOUT_PERIC1_PCLK, 4240 "gout_peric1_peric1_pclk", "mout_peric1_bus_user", 4241 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 4242 21, CLK_IS_CRITICAL, 0), 4243 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK, 4244 "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c", 4245 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 4246 21, 0, 0), 4247 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK, 4248 "gout_peric1_clk_peric1_oscclk_clk", "oscclk", 4249 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 4250 21, 0, 0), 4251 GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK, 4252 "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user", 4253 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 4254 21, 0, 0), 4255 GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK, 4256 "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user", 4257 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 4258 21, 0, 0), 4259 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK, 4260 "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user", 4261 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 4262 21, CLK_IGNORE_UNUSED, 0), 4263 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK, 4264 "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user", 4265 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 4266 21, CLK_IS_CRITICAL, 0), 4267 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, 4268 "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", 4269 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 4270 21, CLK_SET_RATE_PARENT, 0), 4271 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2, 4272 "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi", 4273 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 4274 21, CLK_SET_RATE_PARENT, 0), 4275 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3, 4276 "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi", 4277 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 4278 21, CLK_SET_RATE_PARENT, 0), 4279 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4, 4280 "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi", 4281 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 4282 21, CLK_SET_RATE_PARENT, 0), 4283 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5, 4284 "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi", 4285 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 4286 21, CLK_SET_RATE_PARENT, 0), 4287 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6, 4288 "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi", 4289 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 4290 21, CLK_SET_RATE_PARENT, 0), 4291 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8, 4292 "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c", 4293 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 4294 21, 0, 0), 4295 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1, 4296 "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user", 4297 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 4298 21, 0, 0), 4299 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15, 4300 "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user", 4301 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, 4302 21, 0, 0), 4303 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2, 4304 "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user", 4305 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 4306 21, 0, 0), 4307 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3, 4308 "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user", 4309 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 4310 21, 0, 0), 4311 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4, 4312 "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user", 4313 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 4314 21, 0, 0), 4315 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5, 4316 "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user", 4317 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 4318 21, 0, 0), 4319 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6, 4320 "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user", 4321 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 4322 21, 0, 0), 4323 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8, 4324 "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user", 4325 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 4326 21, 0, 0), 4327 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK, 4328 "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user", 4329 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 4330 21, 0, 0), 4331 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK, 4332 "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi", 4333 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 4334 21, 0, 0), 4335 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK, 4336 "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi", 4337 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 4338 21, 0, 0), 4339 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK, 4340 "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi", 4341 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 4342 21, 0, 0), 4343 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK, 4344 "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi", 4345 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 4346 21, 0, 0), 4347 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK, 4348 "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi", 4349 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 4350 21, 0, 0), 4351 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK, 4352 "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi", 4353 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 4354 21, 0, 0), 4355 GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK, 4356 "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user", 4357 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 4358 21, 0, 0), 4359 }; 4360 4361 static const struct samsung_cmu_info peric1_cmu_info __initconst = { 4362 .mux_clks = peric1_mux_clks, 4363 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 4364 .div_clks = peric1_div_clks, 4365 .nr_div_clks = ARRAY_SIZE(peric1_div_clks), 4366 .gate_clks = peric1_gate_clks, 4367 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 4368 .nr_clk_ids = CLKS_NR_PERIC1, 4369 .clk_regs = peric1_clk_regs, 4370 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 4371 .clk_name = "bus", 4372 }; 4373 4374 /* ---- platform_driver ----------------------------------------------------- */ 4375 4376 static int __init gs101_cmu_probe(struct platform_device *pdev) 4377 { 4378 const struct samsung_cmu_info *info; 4379 struct device *dev = &pdev->dev; 4380 4381 info = of_device_get_match_data(dev); 4382 exynos_arm64_register_cmu(dev, dev->of_node, info); 4383 4384 return 0; 4385 } 4386 4387 static const struct of_device_id gs101_cmu_of_match[] = { 4388 { 4389 .compatible = "google,gs101-cmu-apm", 4390 .data = &apm_cmu_info, 4391 }, { 4392 .compatible = "google,gs101-cmu-hsi0", 4393 .data = &hsi0_cmu_info, 4394 }, { 4395 .compatible = "google,gs101-cmu-hsi2", 4396 .data = &hsi2_cmu_info, 4397 }, { 4398 .compatible = "google,gs101-cmu-peric0", 4399 .data = &peric0_cmu_info, 4400 }, { 4401 .compatible = "google,gs101-cmu-peric1", 4402 .data = &peric1_cmu_info, 4403 }, { 4404 }, 4405 }; 4406 4407 static struct platform_driver gs101_cmu_driver __refdata = { 4408 .driver = { 4409 .name = "gs101-cmu", 4410 .of_match_table = gs101_cmu_of_match, 4411 .suppress_bind_attrs = true, 4412 }, 4413 .probe = gs101_cmu_probe, 4414 }; 4415 4416 static int __init gs101_cmu_init(void) 4417 { 4418 return platform_driver_register(&gs101_cmu_driver); 4419 } 4420 core_initcall(gs101_cmu_init); 4421