12c597bb7SPeter Griffin // SPDX-License-Identifier: GPL-2.0-only 22c597bb7SPeter Griffin /* 32c597bb7SPeter Griffin * Copyright (C) 2023 Linaro Ltd. 42c597bb7SPeter Griffin * Author: Peter Griffin <peter.griffin@linaro.org> 52c597bb7SPeter Griffin * 62c597bb7SPeter Griffin * Common Clock Framework support for GS101. 72c597bb7SPeter Griffin */ 82c597bb7SPeter Griffin 92c597bb7SPeter Griffin #include <linux/clk.h> 102c597bb7SPeter Griffin #include <linux/clk-provider.h> 112c597bb7SPeter Griffin #include <linux/of.h> 122c597bb7SPeter Griffin #include <linux/platform_device.h> 132c597bb7SPeter Griffin 142c597bb7SPeter Griffin #include <dt-bindings/clock/google,gs101.h> 152c597bb7SPeter Griffin 162c597bb7SPeter Griffin #include "clk.h" 172c597bb7SPeter Griffin #include "clk-exynos-arm64.h" 182c597bb7SPeter Griffin 192c597bb7SPeter Griffin /* NOTE: Must be equal to the last clock ID increased by one */ 2035f32e39STudor Ambarus #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1) 212c597bb7SPeter Griffin #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1) 222c597bb7SPeter Griffin #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1) 23893f133aSTudor Ambarus #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1) 242999e786SAndré Draszik #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1) 252c597bb7SPeter Griffin 262c597bb7SPeter Griffin /* ---- CMU_TOP ------------------------------------------------------------- */ 272c597bb7SPeter Griffin 282c597bb7SPeter Griffin /* Register Offset definitions for CMU_TOP (0x1e080000) */ 292c597bb7SPeter Griffin #define PLL_LOCKTIME_PLL_SHARED0 0x0000 302c597bb7SPeter Griffin #define PLL_LOCKTIME_PLL_SHARED1 0x0004 312c597bb7SPeter Griffin #define PLL_LOCKTIME_PLL_SHARED2 0x0008 322c597bb7SPeter Griffin #define PLL_LOCKTIME_PLL_SHARED3 0x000c 332c597bb7SPeter Griffin #define PLL_LOCKTIME_PLL_SPARE 0x0010 342c597bb7SPeter Griffin #define PLL_CON0_PLL_SHARED0 0x0100 352c597bb7SPeter Griffin #define PLL_CON1_PLL_SHARED0 0x0104 362c597bb7SPeter Griffin #define PLL_CON2_PLL_SHARED0 0x0108 372c597bb7SPeter Griffin #define PLL_CON3_PLL_SHARED0 0x010c 382c597bb7SPeter Griffin #define PLL_CON4_PLL_SHARED0 0x0110 392c597bb7SPeter Griffin #define PLL_CON0_PLL_SHARED1 0x0140 402c597bb7SPeter Griffin #define PLL_CON1_PLL_SHARED1 0x0144 412c597bb7SPeter Griffin #define PLL_CON2_PLL_SHARED1 0x0148 422c597bb7SPeter Griffin #define PLL_CON3_PLL_SHARED1 0x014c 432c597bb7SPeter Griffin #define PLL_CON4_PLL_SHARED1 0x0150 442c597bb7SPeter Griffin #define PLL_CON0_PLL_SHARED2 0x0180 452c597bb7SPeter Griffin #define PLL_CON1_PLL_SHARED2 0x0184 462c597bb7SPeter Griffin #define PLL_CON2_PLL_SHARED2 0x0188 472c597bb7SPeter Griffin #define PLL_CON3_PLL_SHARED2 0x018c 482c597bb7SPeter Griffin #define PLL_CON4_PLL_SHARED2 0x0190 492c597bb7SPeter Griffin #define PLL_CON0_PLL_SHARED3 0x01c0 502c597bb7SPeter Griffin #define PLL_CON1_PLL_SHARED3 0x01c4 512c597bb7SPeter Griffin #define PLL_CON2_PLL_SHARED3 0x01c8 522c597bb7SPeter Griffin #define PLL_CON3_PLL_SHARED3 0x01cc 532c597bb7SPeter Griffin #define PLL_CON4_PLL_SHARED3 0x01d0 542c597bb7SPeter Griffin #define PLL_CON0_PLL_SPARE 0x0200 552c597bb7SPeter Griffin #define PLL_CON1_PLL_SPARE 0x0204 562c597bb7SPeter Griffin #define PLL_CON2_PLL_SPARE 0x0208 572c597bb7SPeter Griffin #define PLL_CON3_PLL_SPARE 0x020c 582c597bb7SPeter Griffin #define PLL_CON4_PLL_SPARE 0x0210 592c597bb7SPeter Griffin #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800 602c597bb7SPeter Griffin #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810 612c597bb7SPeter Griffin #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840 622c597bb7SPeter Griffin #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844 632c597bb7SPeter Griffin #define CMU_HCHGEN_CLKMUX 0x0850 642c597bb7SPeter Griffin #define POWER_FAIL_DETECT_PLL 0x0864 652c597bb7SPeter Griffin #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870 662c597bb7SPeter Griffin #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874 672c597bb7SPeter Griffin #define EARLY_WAKEUP_APM_CTRL 0x0878 682c597bb7SPeter Griffin #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c 692c597bb7SPeter Griffin #define EARLY_WAKEUP_DPU_CTRL 0x0880 702c597bb7SPeter Griffin #define EARLY_WAKEUP_CSIS_CTRL 0x0884 712c597bb7SPeter Griffin #define EARLY_WAKEUP_APM_DEST 0x0890 722c597bb7SPeter Griffin #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894 732c597bb7SPeter Griffin #define EARLY_WAKEUP_DPU_DEST 0x0898 742c597bb7SPeter Griffin #define EARLY_WAKEUP_CSIS_DEST 0x089c 752c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0 762c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4 772c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8 782c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0 792c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4 802c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8 812c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0 822c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4 832c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8 842c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0 852c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4 862c597bb7SPeter Griffin #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8 872c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000 882c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004 892c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008 902c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c 912c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010 922c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014 932c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018 942c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c 952c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020 962c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024 972c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028 982c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c 992c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030 1002c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034 1012c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038 1022c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c 1032c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040 1042c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044 1052c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048 1062c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c 1072c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050 1082c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054 1092c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058 1102c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c 1112c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060 1122c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064 1132c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068 1142c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c 1152c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070 1162c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074 1172c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078 1182c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c 1192c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080 1202c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084 1212c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088 1222c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c 1232c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090 1242c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094 1252c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098 1262c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c 1272c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0 1282c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4 1292c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8 1302c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac 1312c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0 1322c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4 1332c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8 1342c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc 1352c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0 1362c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4 1372c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8 1382c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc 1392c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0 1402c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4 1412c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8 1422c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc 1432c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0 1442c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4 1452c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8 1462c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec 1472c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0 1482c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4 1492c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8 1502c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc 1512c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100 1522c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104 1532c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108 1542c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800 1552c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804 1562c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808 1572c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c 1582c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 1592c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 1602c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 1612c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c 1622c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820 1632c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824 1642c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828 1652c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c 1662c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830 1672c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834 1682c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838 1692c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c 1702c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840 1712c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844 1722c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848 1732c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c 1742c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850 1752c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854 1762c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858 1772c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c 1782c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860 1792c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864 1802c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868 1812c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c 1822c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870 1832c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874 1842c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878 1852c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HPM 0x187c 1862c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880 1872c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884 1882c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888 1892c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c 1902c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890 1912c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894 1922c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898 1932c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c 1942c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0 1952c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4 1962c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8 1972c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac 1982c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0 1992c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4 2002c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8 2012c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc 2022c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0 2032c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4 2042c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_OTP 0x18c8 2052c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc 2062c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0 2072c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4 2082c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8 2092c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc 2102c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0 2112c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4 2122c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8 2132c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec 2142c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0 2152c597bb7SPeter Griffin #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4 2162c597bb7SPeter Griffin #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8 2172c597bb7SPeter Griffin #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc 2182c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900 2192c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904 2202c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908 2212c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c 2222c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910 2232c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914 2242c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918 2252c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c 2262c597bb7SPeter Griffin #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920 2272c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000 2282c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004 2292c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008 2302c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c 2312c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010 2322c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014 2332c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018 2342c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c 2352c597bb7SPeter Griffin #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020 2362c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024 2372c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028 2382c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c 2392c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030 2402c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034 2412c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038 2422c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c 2432c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040 2442c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044 2452c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048 2462c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c 2472c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050 2482c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054 2492c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058 2502c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c 2512c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060 2522c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064 2532c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068 2542c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c 2552c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070 2562c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074 2572c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078 2582c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c 2592c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080 2602c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084 2612c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088 2622c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c 2632c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090 2642c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094 2652c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098 2662c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c 2672c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0 2682c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4 2692c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8 2702c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac 2712c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0 2722c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4 2732c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8 2742c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc 2752c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0 2762c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4 2772c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8 2782c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc 2792c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0 2802c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4 2812c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8 2822c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc 2832c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0 2842c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4 2852c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8 2862c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec 2872c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0 2882c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4 2892c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8 2902c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc 2912c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100 2922c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104 2932c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108 2942c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c 2952c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110 2962c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114 2972c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118 2982c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c 2992c597bb7SPeter Griffin #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000 3002c597bb7SPeter Griffin #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004 3012c597bb7SPeter Griffin #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008 3022c597bb7SPeter Griffin #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c 3032c597bb7SPeter Griffin #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010 3042c597bb7SPeter Griffin #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014 3052c597bb7SPeter Griffin #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018 3062c597bb7SPeter Griffin #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c 3072c597bb7SPeter Griffin #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020 3082c597bb7SPeter Griffin #define DMYQCH_CON_OTP_QCH 0x3024 3092c597bb7SPeter Griffin #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00 3102c597bb7SPeter Griffin #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10 3112c597bb7SPeter Griffin #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14 3122c597bb7SPeter Griffin #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18 3132c597bb7SPeter Griffin #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c 3142c597bb7SPeter Griffin #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20 3152c597bb7SPeter Griffin #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24 3162c597bb7SPeter Griffin #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28 3172c597bb7SPeter Griffin #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c 3182c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00 3192c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_ENTRY0 0x3e10 3202c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_ENTRY1 0x3e14 3212c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_ENTRY2 0x3e18 3222c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c 3232c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_ENTRY4 0x3e20 3242c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_ENTRY5 0x3e24 3252c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_ENTRY6 0x3e28 3262c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c 3272c597bb7SPeter Griffin #define MIFMIRROR_QUEUE_BUSY 0x3e30 3282c597bb7SPeter Griffin #define GENERALIO_ACD_CHANNEL_0 0x3f00 3292c597bb7SPeter Griffin #define GENERALIO_ACD_CHANNEL_1 0x3f04 3302c597bb7SPeter Griffin #define GENERALIO_ACD_CHANNEL_2 0x3f08 3312c597bb7SPeter Griffin #define GENERALIO_ACD_CHANNEL_3 0x3f0c 3322c597bb7SPeter Griffin #define GENERALIO_ACD_MASK 0x3f14 3332c597bb7SPeter Griffin 3342c597bb7SPeter Griffin static const unsigned long cmu_top_clk_regs[] __initconst = { 3352c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SHARED0, 3362c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SHARED1, 3372c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SHARED2, 3382c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SHARED3, 3392c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SPARE, 3402c597bb7SPeter Griffin PLL_CON0_PLL_SHARED0, 3412c597bb7SPeter Griffin PLL_CON1_PLL_SHARED0, 3422c597bb7SPeter Griffin PLL_CON2_PLL_SHARED0, 3432c597bb7SPeter Griffin PLL_CON3_PLL_SHARED0, 3442c597bb7SPeter Griffin PLL_CON4_PLL_SHARED0, 3452c597bb7SPeter Griffin PLL_CON0_PLL_SHARED1, 3462c597bb7SPeter Griffin PLL_CON1_PLL_SHARED1, 3472c597bb7SPeter Griffin PLL_CON2_PLL_SHARED1, 3482c597bb7SPeter Griffin PLL_CON3_PLL_SHARED1, 3492c597bb7SPeter Griffin PLL_CON4_PLL_SHARED1, 3502c597bb7SPeter Griffin PLL_CON0_PLL_SHARED2, 3512c597bb7SPeter Griffin PLL_CON1_PLL_SHARED2, 3522c597bb7SPeter Griffin PLL_CON2_PLL_SHARED2, 3532c597bb7SPeter Griffin PLL_CON3_PLL_SHARED2, 3542c597bb7SPeter Griffin PLL_CON4_PLL_SHARED2, 3552c597bb7SPeter Griffin PLL_CON0_PLL_SHARED3, 3562c597bb7SPeter Griffin PLL_CON1_PLL_SHARED3, 3572c597bb7SPeter Griffin PLL_CON2_PLL_SHARED3, 3582c597bb7SPeter Griffin PLL_CON3_PLL_SHARED3, 3592c597bb7SPeter Griffin PLL_CON4_PLL_SHARED3, 3602c597bb7SPeter Griffin PLL_CON0_PLL_SPARE, 3612c597bb7SPeter Griffin PLL_CON1_PLL_SPARE, 3622c597bb7SPeter Griffin PLL_CON2_PLL_SPARE, 3632c597bb7SPeter Griffin PLL_CON3_PLL_SPARE, 3642c597bb7SPeter Griffin PLL_CON4_PLL_SPARE, 3652c597bb7SPeter Griffin CMU_CMU_TOP_CONTROLLER_OPTION, 3662c597bb7SPeter Griffin CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0, 3672c597bb7SPeter Griffin CMU_HCHGEN_CLKMUX_CMU_BOOST, 3682c597bb7SPeter Griffin CMU_HCHGEN_CLKMUX_TOP_BOOST, 3692c597bb7SPeter Griffin CMU_HCHGEN_CLKMUX, 3702c597bb7SPeter Griffin POWER_FAIL_DETECT_PLL, 3712c597bb7SPeter Griffin EARLY_WAKEUP_FORCED_0_ENABLE, 3722c597bb7SPeter Griffin EARLY_WAKEUP_FORCED_1_ENABLE, 3732c597bb7SPeter Griffin EARLY_WAKEUP_APM_CTRL, 3742c597bb7SPeter Griffin EARLY_WAKEUP_CLUSTER0_CTRL, 3752c597bb7SPeter Griffin EARLY_WAKEUP_DPU_CTRL, 3762c597bb7SPeter Griffin EARLY_WAKEUP_CSIS_CTRL, 3772c597bb7SPeter Griffin EARLY_WAKEUP_APM_DEST, 3782c597bb7SPeter Griffin EARLY_WAKEUP_CLUSTER0_DEST, 3792c597bb7SPeter Griffin EARLY_WAKEUP_DPU_DEST, 3802c597bb7SPeter Griffin EARLY_WAKEUP_CSIS_DEST, 3812c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_APM, 3822c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_APM_SET, 3832c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_APM_CLEAR, 3842c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_CLUSTER0, 3852c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET, 3862c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR, 3872c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_DPU, 3882c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_DPU_SET, 3892c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_DPU_CLEAR, 3902c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_CSIS, 3912c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_CSIS_SET, 3922c597bb7SPeter Griffin EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR, 3932c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 3942c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 3952c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 3962c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 3972c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 3982c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 3992c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 4002c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 4012c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 4022c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 4032c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 4042c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 4052c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 4062c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 4072c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 4082c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 4092c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 4102c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 4112c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 4122c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 4132c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 4142c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 4152c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 4162c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 4172c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 4182c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 4192c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 4202c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 4212c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 4222c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 4232c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 4242c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 4252c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 4262c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HPM, 4272c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 4282c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 4292c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 4302c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 4312c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 4322c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 4332c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 4342c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 4352c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 4362c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 4372c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 4382c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 4392c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 4402c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 4412c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 4422c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 4432c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 4442c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 4452c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 4462c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 4472c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 4482c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 4492c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 4502c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 4512c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 4522c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 4532c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 4542c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 4552c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 4562c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 4572c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 4582c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 4592c597bb7SPeter Griffin CLK_CON_MUX_MUX_CMU_CMUREF, 4602c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_BO_BUS, 4612c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_BUS0_BUS, 4622c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_BUS1_BUS, 4632c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_BUS2_BUS, 4642c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK0, 4652c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK1, 4662c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK2, 4672c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK3, 4682c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK4, 4692c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK5, 4702c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK6, 4712c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK7, 4722c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CORE_BUS, 4732c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 4742c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 4752c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 4762c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 4772c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CSIS_BUS, 4782c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_DISP_BUS, 4792c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_DNS_BUS, 4802c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_DPU_BUS, 4812c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_EH_BUS, 4822c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G2D_G2D, 4832c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G2D_MSCL, 4842c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G3AA_G3AA, 4852c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G3D_BUSD, 4862c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G3D_GLB, 4872c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G3D_SWITCH, 4882c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_GDC_GDC0, 4892c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_GDC_GDC1, 4902c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_GDC_SCSC, 4912c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HPM, 4922c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI0_BUS, 4932c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 4942c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 4952c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 4962c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI1_BUS, 4972c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI1_PCIE, 4982c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI2_BUS, 4992c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 5002c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI2_PCIE, 5012c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 5022c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_IPP_BUS, 5032c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_ITP_BUS, 5042c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MCSC_ITSC, 5052c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MCSC_MCSC, 5062c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MFC_MFC, 5072c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MIF_BUSP, 5082c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MISC_BUS, 5092c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MISC_SSS, 5102c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_OTP, 5112c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PDP_BUS, 5122c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PDP_VRA, 5132c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PERIC0_BUS, 5142c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PERIC0_IP, 5152c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PERIC1_BUS, 5162c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PERIC1_IP, 5172c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TNR_BUS, 5182c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TPU_BUS, 5192c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TPU_TPU, 5202c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 5212c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TPU_UART, 5222c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 5232c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 5242c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED0_DIV2, 5252c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED0_DIV3, 5262c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED0_DIV4, 5272c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED0_DIV5, 5282c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED1_DIV2, 5292c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED1_DIV3, 5302c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED1_DIV4, 5312c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED2_DIV2, 5322c597bb7SPeter Griffin CLK_CON_DIV_PLL_SHARED3_DIV2, 5332c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_BUS0_BOOST, 5342c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_BUS1_BOOST, 5352c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_BUS2_BOOST, 5362c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_CORE_BOOST, 5372c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 5382c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 5392c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 5402c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_MIF_BOOST, 5412c597bb7SPeter Griffin CLK_CON_GAT_CLKCMU_MIF_SWITCH, 5422c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 5432c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 5442c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 5452c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 5462c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 5472c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 5482c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 5492c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 5502c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 5512c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 5522c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 5532c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 5542c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 5552c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 5562c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 5572c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 5582c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 5592c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 5602c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 5612c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 5622c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 5632c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 5642c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 5652c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 5662c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 5672c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, 5682c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 5692c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 5702c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 5712c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 5722c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 5732c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 5742c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HPM, 5752c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 5762c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 5772c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 5782c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 5792c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 5802c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 5812c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 5822c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 5832c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 5842c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 5852c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 5862c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 5872c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 5882c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 5892c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 5902c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 5912c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 5922c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 5932c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 5942c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, 5952c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 5962c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 5972c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 5982c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 5992c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 6002c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 6012c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 6022c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 6032c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 6042c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 6052c597bb7SPeter Griffin DMYQCH_CON_CMU_TOP_CMUREF_QCH, 6062c597bb7SPeter Griffin DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, 6072c597bb7SPeter Griffin DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, 6082c597bb7SPeter Griffin DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, 6092c597bb7SPeter Griffin DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, 6102c597bb7SPeter Griffin DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, 6112c597bb7SPeter Griffin DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, 6122c597bb7SPeter Griffin DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, 6132c597bb7SPeter Griffin DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, 6142c597bb7SPeter Griffin DMYQCH_CON_OTP_QCH, 6152c597bb7SPeter Griffin QUEUE_CTRL_REG_BLK_CMU_CMU_TOP, 6162c597bb7SPeter Griffin QUEUE_ENTRY0_BLK_CMU_CMU_TOP, 6172c597bb7SPeter Griffin QUEUE_ENTRY1_BLK_CMU_CMU_TOP, 6182c597bb7SPeter Griffin QUEUE_ENTRY2_BLK_CMU_CMU_TOP, 6192c597bb7SPeter Griffin QUEUE_ENTRY3_BLK_CMU_CMU_TOP, 6202c597bb7SPeter Griffin QUEUE_ENTRY4_BLK_CMU_CMU_TOP, 6212c597bb7SPeter Griffin QUEUE_ENTRY5_BLK_CMU_CMU_TOP, 6222c597bb7SPeter Griffin QUEUE_ENTRY6_BLK_CMU_CMU_TOP, 6232c597bb7SPeter Griffin QUEUE_ENTRY7_BLK_CMU_CMU_TOP, 6242c597bb7SPeter Griffin MIFMIRROR_QUEUE_CTRL_REG, 6252c597bb7SPeter Griffin MIFMIRROR_QUEUE_ENTRY0, 6262c597bb7SPeter Griffin MIFMIRROR_QUEUE_ENTRY1, 6272c597bb7SPeter Griffin MIFMIRROR_QUEUE_ENTRY2, 6282c597bb7SPeter Griffin MIFMIRROR_QUEUE_ENTRY3, 6292c597bb7SPeter Griffin MIFMIRROR_QUEUE_ENTRY4, 6302c597bb7SPeter Griffin MIFMIRROR_QUEUE_ENTRY5, 6312c597bb7SPeter Griffin MIFMIRROR_QUEUE_ENTRY6, 6322c597bb7SPeter Griffin MIFMIRROR_QUEUE_ENTRY7, 6332c597bb7SPeter Griffin MIFMIRROR_QUEUE_BUSY, 6342c597bb7SPeter Griffin GENERALIO_ACD_CHANNEL_0, 6352c597bb7SPeter Griffin GENERALIO_ACD_CHANNEL_1, 6362c597bb7SPeter Griffin GENERALIO_ACD_CHANNEL_2, 6372c597bb7SPeter Griffin GENERALIO_ACD_CHANNEL_3, 6382c597bb7SPeter Griffin GENERALIO_ACD_MASK, 6392c597bb7SPeter Griffin }; 6402c597bb7SPeter Griffin 6412c597bb7SPeter Griffin static const struct samsung_pll_clock cmu_top_pll_clks[] __initconst = { 6422c597bb7SPeter Griffin /* CMU_TOP_PURECLKCOMP */ 6432c597bb7SPeter Griffin PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 6442c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, 6452c597bb7SPeter Griffin NULL), 6462c597bb7SPeter Griffin PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 6472c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, 6482c597bb7SPeter Griffin NULL), 6492c597bb7SPeter Griffin PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", 6502c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, 6512c597bb7SPeter Griffin NULL), 6522c597bb7SPeter Griffin PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", 6532c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, 6542c597bb7SPeter Griffin NULL), 6552c597bb7SPeter Griffin PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk", 6562c597bb7SPeter Griffin PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE, 6572c597bb7SPeter Griffin NULL), 6582c597bb7SPeter Griffin }; 6592c597bb7SPeter Griffin 6602c597bb7SPeter Griffin /* List of parent clocks for Muxes in CMU_TOP */ 6612c597bb7SPeter Griffin PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" }; 6622c597bb7SPeter Griffin PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" }; 6632c597bb7SPeter Griffin PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" }; 6642c597bb7SPeter Griffin PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" }; 6652c597bb7SPeter Griffin PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" }; 6662c597bb7SPeter Griffin PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 6672c597bb7SPeter Griffin "fout_shared3_pll", "dout_cmu_shared1_div3", 6682c597bb7SPeter Griffin "dout_cmu_shared0_div4", 6692c597bb7SPeter Griffin "dout_cmu_shared1_div4", 6702c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 6712c597bb7SPeter Griffin PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4", 6722c597bb7SPeter Griffin "dout_cmu_shared1_div4", 6732c597bb7SPeter Griffin "dout_cmu_shared2_div2", 6742c597bb7SPeter Griffin "dout_cmu_shared3_div2", 6752c597bb7SPeter Griffin "fout_spare_pll", "oscclk", 6762c597bb7SPeter Griffin "oscclk", "oscclk" }; 6772c597bb7SPeter Griffin PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 6782c597bb7SPeter Griffin "dout_cmu_shared1_div3", 6792c597bb7SPeter Griffin "dout_cmu_shared0_div4", 6802c597bb7SPeter Griffin "dout_cmu_shared1_div4", 6812c597bb7SPeter Griffin "dout_cmu_shared2_div2", 6822c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 6832c597bb7SPeter Griffin PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2", 6842c597bb7SPeter Griffin "dout_cmu_shared1_div2", 6852c597bb7SPeter Griffin "fout_shared2_pll", "fout_shared3_pll", 6862c597bb7SPeter Griffin "dout_cmu_shared0_div3", 6872c597bb7SPeter Griffin "dout_cmu_shared1_div3", 6882c597bb7SPeter Griffin "dout_cmu_shared0_div5", "fout_spare_pll" }; 6892c597bb7SPeter Griffin PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3", 6902c597bb7SPeter Griffin "dout_cmu_shared1_div3", 6912c597bb7SPeter Griffin "dout_cmu_shared2_div2", 6922c597bb7SPeter Griffin "dout_cmu_shared3_div2", "fout_spare_pll", 6932c597bb7SPeter Griffin "oscclk", "oscclk" }; 6942c597bb7SPeter Griffin PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4", 6952c597bb7SPeter Griffin "dout_cmu_shared1_div4", 6962c597bb7SPeter Griffin "dout_cmu_shared2_div2", 6972c597bb7SPeter Griffin "dout_cmu_shared3_div2" }; 6982c597bb7SPeter Griffin PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost", 6992c597bb7SPeter Griffin "gout_cmu_boost_option1" }; 7002c597bb7SPeter Griffin PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2", 7012c597bb7SPeter Griffin "dout_cmu_shared1_div2", 7022c597bb7SPeter Griffin "fout_shared2_pll", "fout_shared3_pll", 7032c597bb7SPeter Griffin "dout_cmu_shared0_div3", 7042c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7052c597bb7SPeter Griffin "dout_cmu_shared0_div5", "fout_spare_pll" }; 7062c597bb7SPeter Griffin PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll", 7072c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7082c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7092c597bb7SPeter Griffin "dout_cmu_shared2_div2", "fout_spare_pll", 7102c597bb7SPeter Griffin "oscclk", "oscclk" }; 7112c597bb7SPeter Griffin PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 7122c597bb7SPeter Griffin "dout_cmu_shared1_div2", "fout_shared2_pll", 7132c597bb7SPeter Griffin "fout_shared3_pll", "dout_cmu_shared0_div3", 7142c597bb7SPeter Griffin "dout_cmu_shared1_div3", "fout_spare_pll" }; 7152c597bb7SPeter Griffin PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 7162c597bb7SPeter Griffin "dout_cmu_shared1_div2", "fout_shared2_pll", 7172c597bb7SPeter Griffin "fout_shared3_pll", "dout_cmu_shared0_div3", 7182c597bb7SPeter Griffin "dout_cmu_shared1_div3", "fout_spare_pll" }; 7192c597bb7SPeter Griffin PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2", 7202c597bb7SPeter Griffin "dout_cmu_shared1_div2", "fout_shared2_pll", 7212c597bb7SPeter Griffin "fout_shared3_pll", "dout_cmu_shared0_div3", 7222c597bb7SPeter Griffin "dout_cmu_shared1_div3", "fout_spare_pll" }; 7232c597bb7SPeter Griffin PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 7242c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7252c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7262c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7272c597bb7SPeter Griffin "dout_cmu_shared2_div2", 7282c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 7292c597bb7SPeter Griffin PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 7302c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7312c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7322c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7332c597bb7SPeter Griffin "dout_cmu_shared2_div2", 7342c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 7352c597bb7SPeter Griffin PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 7362c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7372c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7382c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7392c597bb7SPeter Griffin "dout_cmu_shared2_div2", 7402c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 7412c597bb7SPeter Griffin PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3", 7422c597bb7SPeter Griffin "fout_shared3_pll", 7432c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7442c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7452c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7462c597bb7SPeter Griffin "dout_cmu_shared2_div2", 7472c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 7482c597bb7SPeter Griffin PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2", 7492c597bb7SPeter Griffin "dout_cmu_shared1_div2", 7502c597bb7SPeter Griffin "fout_shared2_pll", "fout_shared3_pll", 7512c597bb7SPeter Griffin "dout_cmu_shared0_div3", 7522c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7532c597bb7SPeter Griffin "dout_cmu_shared0_div5", "fout_spare_pll" }; 7542c597bb7SPeter Griffin PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 7552c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7562c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7572c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7582c597bb7SPeter Griffin "dout_cmu_shared2_div2", 7592c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 7602c597bb7SPeter Griffin PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4", 7612c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7622c597bb7SPeter Griffin "dout_cmu_shared2_div2", 7632c597bb7SPeter Griffin "dout_cmu_shared3_div2", 7642c597bb7SPeter Griffin "fout_spare_pll", "oscclk", 7652c597bb7SPeter Griffin "oscclk", "oscclk" }; 7662c597bb7SPeter Griffin PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 7672c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7682c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7692c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7702c597bb7SPeter Griffin "dout_cmu_shared2_div2", 7712c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 7722c597bb7SPeter Griffin PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2", 7732c597bb7SPeter Griffin "dout_cmu_shared1_div2", 7742c597bb7SPeter Griffin "fout_shared2_pll", "fout_shared3_pll", 7752c597bb7SPeter Griffin "dout_cmu_shared0_div3", 7762c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7772c597bb7SPeter Griffin "dout_cmu_shared0_div4", "fout_spare_pll" }; 7782c597bb7SPeter Griffin PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2", 7792c597bb7SPeter Griffin "dout_cmu_shared1_div2", 7802c597bb7SPeter Griffin "fout_shared2_pll", "fout_shared3_pll", 7812c597bb7SPeter Griffin "dout_cmu_shared0_div3", 7822c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7832c597bb7SPeter Griffin "dout_cmu_shared0_div4", "fout_spare_pll" }; 7842c597bb7SPeter Griffin PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 7852c597bb7SPeter Griffin "fout_shared3_pll", "dout_cmu_shared1_div3", 7862c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7872c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7882c597bb7SPeter Griffin "fout_spare_pll", "fout_spare_pll"}; 7892c597bb7SPeter Griffin PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 7902c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7912c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7922c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7932c597bb7SPeter Griffin "dout_cmu_shared2_div2", 7942c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 7952c597bb7SPeter Griffin PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 7962c597bb7SPeter Griffin "dout_cmu_shared1_div3", 7972c597bb7SPeter Griffin "dout_cmu_shared0_div4", 7982c597bb7SPeter Griffin "dout_cmu_shared1_div4", 7992c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8002c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 8012c597bb7SPeter Griffin PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 8022c597bb7SPeter Griffin "dout_cmu_shared1_div3", 8032c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8042c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8052c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8062c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 8072c597bb7SPeter Griffin PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3", 8082c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8092c597bb7SPeter Griffin "dout_cmu_shared2_div2" }; 8102c597bb7SPeter Griffin PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4", 8112c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8122c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8132c597bb7SPeter Griffin "dout_cmu_shared3_div2", 8142c597bb7SPeter Griffin "fout_spare_pll", "oscclk", 8152c597bb7SPeter Griffin "oscclk", "oscclk" }; 8162c597bb7SPeter Griffin PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4", 8172c597bb7SPeter Griffin "dout_cmu_shared2_div2", "fout_spare_pll" }; 8182c597bb7SPeter Griffin PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" }; 8192c597bb7SPeter Griffin PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" }; 8202c597bb7SPeter Griffin PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4", 8212c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8222c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8232c597bb7SPeter Griffin "dout_cmu_shared3_div2", 8242c597bb7SPeter Griffin "fout_spare_pll" }; 8252c597bb7SPeter Griffin PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" }; 8262c597bb7SPeter Griffin PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4", 8272c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8282c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8292c597bb7SPeter Griffin "dout_cmu_shared3_div2", 8302c597bb7SPeter Griffin "fout_spare_pll", "oscclk", 8312c597bb7SPeter Griffin "oscclk", "oscclk" }; 8322c597bb7SPeter Griffin PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll", 8332c597bb7SPeter Griffin "dout_cmu_shared0_div4", "fout_spare_pll" }; 8342c597bb7SPeter Griffin PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" }; 8352c597bb7SPeter Griffin PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4", 8362c597bb7SPeter Griffin "dout_cmu_shared2_div2", "fout_spare_pll" }; 8372c597bb7SPeter Griffin PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 8382c597bb7SPeter Griffin "dout_cmu_shared1_div3", 8392c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8402c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8412c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8422c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 8432c597bb7SPeter Griffin PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 8442c597bb7SPeter Griffin "dout_cmu_shared1_div3", 8452c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8462c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8472c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8482c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 8492c597bb7SPeter Griffin PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 8502c597bb7SPeter Griffin "dout_cmu_shared1_div3", 8512c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8522c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8532c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8542c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 8552c597bb7SPeter Griffin PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 8562c597bb7SPeter Griffin "dout_cmu_shared1_div3", 8572c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8582c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8592c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8602c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 8612c597bb7SPeter Griffin PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 8622c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8632c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8642c597bb7SPeter Griffin "dout_cmu_shared2_div2", "fout_spare_pll", 8652c597bb7SPeter Griffin "oscclk", "oscclk" }; 8662c597bb7SPeter Griffin PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4", 8672c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8682c597bb7SPeter Griffin "dout_cmu_shared0_div5", "fout_spare_pll" }; 8692c597bb7SPeter Griffin PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", 8702c597bb7SPeter Griffin "dout_cmu_shared0_div2", 8712c597bb7SPeter Griffin "dout_cmu_shared1_div2", 8722c597bb7SPeter Griffin "fout_shared2_pll", "dout_cmu_shared0_div3", 8732c597bb7SPeter Griffin "fout_shared3_pll", "fout_spare_pll" }; 8742c597bb7SPeter Griffin PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4", 8752c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8762c597bb7SPeter Griffin "dout_cmu_shared3_div2", "fout_spare_pll" }; 8772c597bb7SPeter Griffin PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4", 8782c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8792c597bb7SPeter Griffin "dout_cmu_shared3_div2", "fout_spare_pll" }; 8802c597bb7SPeter Griffin PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 8812c597bb7SPeter Griffin "dout_cmu_shared1_div3", 8822c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8832c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8842c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8852c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 8862c597bb7SPeter Griffin PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3", 8872c597bb7SPeter Griffin "fout_shared3_pll", "dout_cmu_shared1_div3", 8882c597bb7SPeter Griffin "dout_cmu_shared0_div4", 8892c597bb7SPeter Griffin "dout_cmu_shared1_div4", 8902c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 8912c597bb7SPeter Griffin PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4", 8922c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8932c597bb7SPeter Griffin "dout_cmu_shared3_div2", "fout_spare_pll" }; 8942c597bb7SPeter Griffin PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4", 8952c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8962c597bb7SPeter Griffin "dout_cmu_shared3_div2", "fout_spare_pll" }; 8972c597bb7SPeter Griffin PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4", 8982c597bb7SPeter Griffin "dout_cmu_shared2_div2", 8992c597bb7SPeter Griffin "dout_cmu_shared3_div2", "fout_spare_pll" }; 9002c597bb7SPeter Griffin PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4", 9012c597bb7SPeter Griffin "dout_cmu_shared2_div2", 9022c597bb7SPeter Griffin "dout_cmu_shared3_div2", "fout_spare_pll" }; 9032c597bb7SPeter Griffin PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll", 9042c597bb7SPeter Griffin "dout_cmu_shared1_div3", 9052c597bb7SPeter Griffin "dout_cmu_shared0_div4", 9062c597bb7SPeter Griffin "dout_cmu_shared1_div4", 9072c597bb7SPeter Griffin "dout_cmu_shared2_div2", 9082c597bb7SPeter Griffin "fout_spare_pll", "oscclk" }; 9092c597bb7SPeter Griffin PNAME(mout_cmu_top_boost_option1_p) = { "oscclk", 9102c597bb7SPeter Griffin "gout_cmu_boost_option1" }; 9112c597bb7SPeter Griffin PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4", 9122c597bb7SPeter Griffin "dout_cmu_shared1_div4", 9132c597bb7SPeter Griffin "dout_cmu_shared2_div2", 9142c597bb7SPeter Griffin "dout_cmu_shared3_div2" }; 9152c597bb7SPeter Griffin PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2", 9162c597bb7SPeter Griffin "dout_cmu_shared1_div2", 9172c597bb7SPeter Griffin "fout_shared2_pll", 9182c597bb7SPeter Griffin "fout_shared3_pll", 9192c597bb7SPeter Griffin "dout_cmu_shared0_div3", 9202c597bb7SPeter Griffin "dout_cmu_shared1_div3", 9212c597bb7SPeter Griffin "dout_cmu_shared0_div4", 9222c597bb7SPeter Griffin "fout_spare_pll" }; 9232c597bb7SPeter Griffin PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2", 9242c597bb7SPeter Griffin "dout_cmu_shared1_div2", 9252c597bb7SPeter Griffin "fout_shared2_pll", 9262c597bb7SPeter Griffin "fout_shared3_pll", 9272c597bb7SPeter Griffin "dout_cmu_shared0_div3", 9282c597bb7SPeter Griffin "dout_cmu_shared1_div3", 9292c597bb7SPeter Griffin "dout_cmu_shared0_div4", "fout_spare_pll" }; 9302c597bb7SPeter Griffin PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2", 9312c597bb7SPeter Griffin "dout_cmu_shared1_div2", 9322c597bb7SPeter Griffin "fout_shared2_pll", "fout_shared3_pll", 9332c597bb7SPeter Griffin "dout_cmu_shared0_div3", 9342c597bb7SPeter Griffin "dout_cmu_shared1_div3", 9352c597bb7SPeter Griffin "dout_cmu_shared0_div4", "fout_spare_pll" }; 9362c597bb7SPeter Griffin PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4", 9372c597bb7SPeter Griffin "dout_cmu_shared2_div2", 9382c597bb7SPeter Griffin "dout_cmu_shared3_div2", "fout_spare_pll" }; 9392c597bb7SPeter Griffin PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1", 9402c597bb7SPeter Griffin "dout_cmu_cmuref" }; 9412c597bb7SPeter Griffin 9422c597bb7SPeter Griffin /* 9432c597bb7SPeter Griffin * Register name to clock name mangling strategy used in this file 9442c597bb7SPeter Griffin * 9452c597bb7SPeter Griffin * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll 9462c597bb7SPeter Griffin * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu 9472c597bb7SPeter Griffin * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 9482c597bb7SPeter Griffin * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu 9492c597bb7SPeter Griffin * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu 9502c597bb7SPeter Griffin * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu 9512c597bb7SPeter Griffin * 9522c597bb7SPeter Griffin * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC 9532c597bb7SPeter Griffin */ 9542c597bb7SPeter Griffin 9552c597bb7SPeter Griffin static const struct samsung_mux_clock cmu_top_mux_clks[] __initconst = { 9562c597bb7SPeter Griffin MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, 9572c597bb7SPeter Griffin PLL_CON0_PLL_SHARED0, 4, 1), 9582c597bb7SPeter Griffin MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, 9592c597bb7SPeter Griffin PLL_CON0_PLL_SHARED1, 4, 1), 9602c597bb7SPeter Griffin MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, 9612c597bb7SPeter Griffin PLL_CON0_PLL_SHARED2, 4, 1), 9622c597bb7SPeter Griffin MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, 9632c597bb7SPeter Griffin PLL_CON0_PLL_SHARED3, 4, 1), 9642c597bb7SPeter Griffin MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p, 9652c597bb7SPeter Griffin PLL_CON0_PLL_SPARE, 4, 1), 9662c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p, 9672c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3), 9682c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p, 9692c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3), 9702c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p, 9712c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3), 9722c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p, 9732c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3), 9742c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p, 9752c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3), 9762c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p, 9772c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3), 9782c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p, 9792c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3), 9802c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p, 9812c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3), 9822c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p, 9832c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3), 9842c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p, 9852c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3), 9862c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p, 9872c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3), 9882c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p, 9892c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3), 9902c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p, 9912c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), 9922c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1", 9932c597bb7SPeter Griffin mout_cmu_cmu_boost_option1_p, 9942c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1), 9952c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, 9962c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3), 9972c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", 9982c597bb7SPeter Griffin mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3), 9992c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", 10002c597bb7SPeter Griffin mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 10012c597bb7SPeter Griffin 0, 3), 10022c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", 10032c597bb7SPeter Griffin mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 10042c597bb7SPeter Griffin 0, 3), 10052c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch", 10062c597bb7SPeter Griffin mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 10072c597bb7SPeter Griffin 0, 3), 10082c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p, 10092c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3), 10102c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p, 10112c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3), 10122c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p, 10132c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3), 10142c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p, 10152c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3), 10162c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p, 10172c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3), 10182c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, 10192c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3), 10202c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, 10212c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3), 10222c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p, 10232c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3), 10242c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p, 10252c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3), 10262c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p, 10272c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3), 10282c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch", 10292c597bb7SPeter Griffin mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3), 10302c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p, 10312c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3), 10322c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p, 10332c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3), 10342c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p, 10352c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3), 10362c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, 10372c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), 10382c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p, 10392c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3), 10402c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc", 10412c597bb7SPeter Griffin mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2), 10422c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd", 10432c597bb7SPeter Griffin mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 10442c597bb7SPeter Griffin 0, 1), 10452c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg", 10462c597bb7SPeter Griffin mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 10472c597bb7SPeter Griffin 0, 1), 10482c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, 10492c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), 10502c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p, 10512c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1), 10522c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, 10532c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3), 10542c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card", 10552c597bb7SPeter Griffin mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 10562c597bb7SPeter Griffin 0, 2), 10572c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p, 10582c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1), 10592c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd", 10602c597bb7SPeter Griffin mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 10612c597bb7SPeter Griffin 0, 2), 10622c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p, 10632c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3), 10642c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p, 10652c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3), 10662c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p, 10672c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3), 10682c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p, 10692c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3), 10702c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, 10712c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3), 10722c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, 10732c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), 10742c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch", 10752c597bb7SPeter Griffin mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), 10762c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p, 10772c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2), 10782c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p, 10792c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2), 10802c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p, 10812c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3), 10822c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p, 10832c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3), 10842c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus", 10852c597bb7SPeter Griffin mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2), 10862c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p, 10872c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2), 10882c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus", 10892c597bb7SPeter Griffin mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2), 10902c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p, 10912c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2), 10922c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p, 10932c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), 10942c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1", 10952c597bb7SPeter Griffin mout_cmu_top_boost_option1_p, 10962c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1), 10972c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref", 10982c597bb7SPeter Griffin mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2), 10992c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p, 11002c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3), 11012c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p, 11022c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3), 11032c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl", 11042c597bb7SPeter Griffin mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3), 11052c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p, 11062c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2), 11072c597bb7SPeter Griffin MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p, 11082c597bb7SPeter Griffin CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), 11092c597bb7SPeter Griffin }; 11102c597bb7SPeter Griffin 11112c597bb7SPeter Griffin static const struct samsung_div_clock cmu_top_div_clks[] __initconst = { 11122c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus", 11132c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4), 11142c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", 11152c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4), 11162c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus", 11172c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4), 11182c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus", 11192c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4), 11202c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0", 11212c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), 11222c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1", 11232c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), 11242c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2", 11252c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), 11262c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3", 11272c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), 11282c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4", 11292c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5), 11302c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5", 11312c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5), 11322c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6", 11332c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5), 11342c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7", 11352c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5), 11362c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", 11372c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), 11382c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", 11392c597bb7SPeter Griffin "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), 11402c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", 11412c597bb7SPeter Griffin "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), 11422c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", 11432c597bb7SPeter Griffin "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), 11442c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch", 11452c597bb7SPeter Griffin "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), 11462c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus", 11472c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4), 11482c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus", 11492c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4), 11502c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus", 11512c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4), 11522c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus", 11532c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4), 11542c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus", 11552c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4), 11562c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", 11572c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), 11582c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", 11592c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), 11602c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa", 11612c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4), 11622c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd", 11632c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4), 11642c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb", 11652c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4), 11662c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch", 11672c597bb7SPeter Griffin "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 11682c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0", 11692c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4), 11702c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1", 11712c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4), 11722c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc", 11732c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4), 11742c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", 11752c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HPM, 0, 2), 11762c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus", 11772c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4), 11782c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", 11792c597bb7SPeter Griffin "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4), 11802c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", 11812c597bb7SPeter Griffin "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5), 11822c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", 11832c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4), 11842c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", 11852c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3), 11862c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", 11872c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), 11882c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card", 11892c597bb7SPeter Griffin "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9), 11902c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", 11912c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3), 11922c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd", 11932c597bb7SPeter Griffin "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4), 11942c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", 11952c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), 11962c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", 11972c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4), 11982c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc", 11992c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4), 12002c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc", 12012c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4), 12022c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", 12032c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), 12042c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", 12052c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4), 12062c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus", 12072c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4), 12082c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss", 12092c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4), 12102c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus", 12112c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4), 12122c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra", 12132c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4), 12142c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", 12152c597bb7SPeter Griffin "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4), 12162c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip", 12172c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), 12182c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", 12192c597bb7SPeter Griffin "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4), 12202c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip", 12212c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), 12222c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus", 12232c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), 12242c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus", 12252c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4), 12262c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu", 12272c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4), 12282c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl", 12292c597bb7SPeter Griffin "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4), 12302c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart", 12312c597bb7SPeter Griffin CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4), 12322c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost", 12332c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), 12342c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref", 12352c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), 12362c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", 12372c597bb7SPeter Griffin "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), 12382c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", 12392c597bb7SPeter Griffin "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), 12402c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", 12412c597bb7SPeter Griffin "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), 12422c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5", 12432c597bb7SPeter Griffin "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3), 12442c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", 12452c597bb7SPeter Griffin "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), 12462c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", 12472c597bb7SPeter Griffin "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), 12482c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", 12492c597bb7SPeter Griffin "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), 12502c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", 12512c597bb7SPeter Griffin "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), 12522c597bb7SPeter Griffin DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2", 12532c597bb7SPeter Griffin "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1), 12542c597bb7SPeter Griffin }; 12552c597bb7SPeter Griffin 12562c597bb7SPeter Griffin static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initconst = { 12572c597bb7SPeter Griffin FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg", 12582c597bb7SPeter Griffin "gout_cmu_hsi0_usbdpdbg", 1, 4, 0), 12592c597bb7SPeter Griffin FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), 12602c597bb7SPeter Griffin }; 12612c597bb7SPeter Griffin 12622c597bb7SPeter Griffin static const struct samsung_gate_clock cmu_top_gate_clks[] __initconst = { 126335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost", 12642c597bb7SPeter Griffin "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0), 126535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost", 12662c597bb7SPeter Griffin "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0), 126735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost", 12682c597bb7SPeter Griffin "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0), 126935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost", 12702c597bb7SPeter Griffin "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0), 127135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost", 12722c597bb7SPeter Griffin "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 12732c597bb7SPeter Griffin 21, 0, 0), 127435f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost", 12752c597bb7SPeter Griffin "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 12762c597bb7SPeter Griffin 21, 0, 0), 127735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost", 12782c597bb7SPeter Griffin "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 12792c597bb7SPeter Griffin 21, 0, 0), 128035f32e39STudor Ambarus GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost", 12812c597bb7SPeter Griffin "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST, 12822c597bb7SPeter Griffin 21, 0, 0), 128335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch", 128435f32e39STudor Ambarus "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0), 128535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus", 12862c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0), 128735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus", 12882c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0), 128935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus", 12902c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0), 129135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus", 12922c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0), 129335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", 12942c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), 129535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", 12962c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), 129735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", 12982c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), 129935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", 13002c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), 130135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4", 13022c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0), 130335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5", 13042c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0), 130535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6", 13062c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0), 130735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7", 13082c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0), 130935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost", 13102c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0), 131135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", 13122c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0), 131335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", 131435f32e39STudor Ambarus "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS, 131535f32e39STudor Ambarus 21, 0, 0), 131635f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", 13172c597bb7SPeter Griffin "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 13182c597bb7SPeter Griffin 21, 0, 0), 131935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", 13202c597bb7SPeter Griffin "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 13212c597bb7SPeter Griffin 21, 0, 0), 132235f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch", 13232c597bb7SPeter Griffin "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 13242c597bb7SPeter Griffin 21, 0, 0), 132535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus", 13262c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0), 132735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus", 13282c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0), 132935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus", 13302c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0), 133135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus", 13322c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0), 133335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus", 13342c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0), 133535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", 13362c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), 133735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", 13382c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), 133935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa", 13402c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0), 134135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd", 13422c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0), 134335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb", 13442c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0), 134535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch", 134635f32e39STudor Ambarus "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 134735f32e39STudor Ambarus 21, 0, 0), 134835f32e39STudor Ambarus GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0", 13492c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0), 135035f32e39STudor Ambarus GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1", 13512c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0), 135235f32e39STudor Ambarus GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc", 13532c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0), 13542c597bb7SPeter Griffin GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", 13552c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), 135635f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus", 13572c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0), 135835f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc", 135935f32e39STudor Ambarus "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 136035f32e39STudor Ambarus 21, 0, 0), 136135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd", 13622c597bb7SPeter Griffin "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 13632c597bb7SPeter Griffin 21, 0, 0), 136435f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg", 13652c597bb7SPeter Griffin "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 13662c597bb7SPeter Griffin 21, 0, 0), 136735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus", 13682c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0), 136935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie", 13702c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0), 137135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus", 13722c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0), 137335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card", 13742c597bb7SPeter Griffin "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 13752c597bb7SPeter Griffin 21, 0, 0), 137635f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie", 13772c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0), 137835f32e39STudor Ambarus GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd", 13792c597bb7SPeter Griffin "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 13802c597bb7SPeter Griffin 21, 0, 0), 138135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus", 13822c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0), 138335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus", 13842c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0), 138535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc", 13862c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0), 138735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc", 13882c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0), 138935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", 13902c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0), 139135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", 13922c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0), 139335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus", 13942c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0), 139535f32e39STudor Ambarus GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss", 13962c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0), 139735f32e39STudor Ambarus GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus", 13982c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 139935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra", 14002c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0), 140135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus", 140235f32e39STudor Ambarus "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 140335f32e39STudor Ambarus 21, 0, 0), 140435f32e39STudor Ambarus GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip", 14052c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0), 140635f32e39STudor Ambarus GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus", 140735f32e39STudor Ambarus "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 140835f32e39STudor Ambarus 21, 0, 0), 140935f32e39STudor Ambarus GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip", 14102c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0), 141135f32e39STudor Ambarus GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus", 14122c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0), 141335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref", 141435f32e39STudor Ambarus "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 141535f32e39STudor Ambarus 21, 0, 0), 141635f32e39STudor Ambarus GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus", 14172c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0), 141835f32e39STudor Ambarus GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu", 14192c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0), 142035f32e39STudor Ambarus GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl", 142135f32e39STudor Ambarus "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 142235f32e39STudor Ambarus 21, 0, 0), 142335f32e39STudor Ambarus GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart", 14242c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0), 14252c597bb7SPeter Griffin }; 14262c597bb7SPeter Griffin 14272c597bb7SPeter Griffin static const struct samsung_cmu_info top_cmu_info __initconst = { 14282c597bb7SPeter Griffin .pll_clks = cmu_top_pll_clks, 14292c597bb7SPeter Griffin .nr_pll_clks = ARRAY_SIZE(cmu_top_pll_clks), 14302c597bb7SPeter Griffin .mux_clks = cmu_top_mux_clks, 14312c597bb7SPeter Griffin .nr_mux_clks = ARRAY_SIZE(cmu_top_mux_clks), 14322c597bb7SPeter Griffin .div_clks = cmu_top_div_clks, 14332c597bb7SPeter Griffin .nr_div_clks = ARRAY_SIZE(cmu_top_div_clks), 14342c597bb7SPeter Griffin .fixed_factor_clks = cmu_top_ffactor, 14352c597bb7SPeter Griffin .nr_fixed_factor_clks = ARRAY_SIZE(cmu_top_ffactor), 14362c597bb7SPeter Griffin .gate_clks = cmu_top_gate_clks, 14372c597bb7SPeter Griffin .nr_gate_clks = ARRAY_SIZE(cmu_top_gate_clks), 14382c597bb7SPeter Griffin .nr_clk_ids = CLKS_NR_TOP, 14392c597bb7SPeter Griffin .clk_regs = cmu_top_clk_regs, 14402c597bb7SPeter Griffin .nr_clk_regs = ARRAY_SIZE(cmu_top_clk_regs), 14412c597bb7SPeter Griffin }; 14422c597bb7SPeter Griffin 14432c597bb7SPeter Griffin static void __init gs101_cmu_top_init(struct device_node *np) 14442c597bb7SPeter Griffin { 14452c597bb7SPeter Griffin exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 14462c597bb7SPeter Griffin } 14472c597bb7SPeter Griffin 14482c597bb7SPeter Griffin /* Register CMU_TOP early, as it's a dependency for other early domains */ 14492c597bb7SPeter Griffin CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top", 14502c597bb7SPeter Griffin gs101_cmu_top_init); 14512c597bb7SPeter Griffin 14522c597bb7SPeter Griffin /* ---- CMU_APM ------------------------------------------------------------- */ 14532c597bb7SPeter Griffin 14542c597bb7SPeter Griffin /* Register Offset definitions for CMU_APM (0x17400000) */ 14552c597bb7SPeter Griffin #define APM_CMU_APM_CONTROLLER_OPTION 0x0800 14562c597bb7SPeter Griffin #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810 14572c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000 14582c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004 14592c597bb7SPeter Griffin #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800 14602c597bb7SPeter Griffin #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804 14612c597bb7SPeter Griffin #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808 14622c597bb7SPeter Griffin #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c 14632c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000 14642c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004 14652c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008 14662c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c 14672c597bb7SPeter Griffin #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010 14682c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014 14692c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018 14702c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c 14712c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020 14722c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024 14732c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028 14742c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c 14752c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030 14762c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034 14772c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038 14782c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c 14792c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040 14802c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044 14812c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048 14822c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c 14832c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050 14842c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054 14852c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058 14862c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c 14872c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060 14882c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064 14892c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068 14902c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c 14912c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070 14922c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074 14932c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c 14942c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080 14952c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084 14962c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088 14972c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c 14982c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090 14992c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094 15002c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098 15012c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c 15022c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0 15032c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4 15042c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8 15052c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac 15062c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0 15072c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4 15082c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8 15092c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc 15102c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0 15112c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4 15122c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc 15132c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0 15142c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4 15152c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8 15162c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc 15172c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0 15182c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4 15192c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8 15202c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec 15212c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0 15222c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4 15232c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8 15242c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc 15252c597bb7SPeter Griffin #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000 15262c597bb7SPeter Griffin #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004 15272c597bb7SPeter Griffin #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008 15282c597bb7SPeter Griffin #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c 15292c597bb7SPeter Griffin #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010 15302c597bb7SPeter Griffin #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014 15312c597bb7SPeter Griffin #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018 15322c597bb7SPeter Griffin #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c 15332c597bb7SPeter Griffin #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020 15342c597bb7SPeter Griffin #define QCH_CON_APBIF_RTC_QCH 0x3024 15352c597bb7SPeter Griffin #define QCH_CON_APBIF_TRTC_QCH 0x3028 15362c597bb7SPeter Griffin #define QCH_CON_APM_CMU_APM_QCH 0x302c 15372c597bb7SPeter Griffin #define QCH_CON_APM_USI0_UART_QCH 0x3030 15382c597bb7SPeter Griffin #define QCH_CON_APM_USI0_USI_QCH 0x3034 15392c597bb7SPeter Griffin #define QCH_CON_APM_USI1_UART_QCH 0x3038 15402c597bb7SPeter Griffin #define QCH_CON_D_TZPC_APM_QCH 0x303c 15412c597bb7SPeter Griffin #define QCH_CON_GPC_APM_QCH 0x3040 15422c597bb7SPeter Griffin #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044 15432c597bb7SPeter Griffin #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048 15442c597bb7SPeter Griffin #define QCH_CON_INTMEM_QCH 0x304c 15452c597bb7SPeter Griffin #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050 15462c597bb7SPeter Griffin #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054 15472c597bb7SPeter Griffin #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058 15482c597bb7SPeter Griffin #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c 15492c597bb7SPeter Griffin #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060 15502c597bb7SPeter Griffin #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064 15512c597bb7SPeter Griffin #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068 15522c597bb7SPeter Griffin #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c 15532c597bb7SPeter Griffin #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070 15542c597bb7SPeter Griffin #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078 15552c597bb7SPeter Griffin #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c 15562c597bb7SPeter Griffin #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080 15572c597bb7SPeter Griffin #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084 15582c597bb7SPeter Griffin #define QCH_CON_PMU_INTR_GEN_QCH 0x3088 15592c597bb7SPeter Griffin #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c 15602c597bb7SPeter Griffin #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090 15612c597bb7SPeter Griffin #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094 15622c597bb7SPeter Griffin #define QCH_CON_SPEEDY_APM_QCH 0x3098 15632c597bb7SPeter Griffin #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c 15642c597bb7SPeter Griffin #define QCH_CON_SSMT_D_APM_QCH 0x30a0 15652c597bb7SPeter Griffin #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4 15662c597bb7SPeter Griffin #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8 15672c597bb7SPeter Griffin #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac 15682c597bb7SPeter Griffin #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0 15692c597bb7SPeter Griffin #define QCH_CON_SYSREG_APM_QCH 0x30b8 15702c597bb7SPeter Griffin #define QCH_CON_UASC_APM_QCH 0x30bc 15712c597bb7SPeter Griffin #define QCH_CON_UASC_DBGCORE_QCH 0x30c0 15722c597bb7SPeter Griffin #define QCH_CON_UASC_G_SWD_QCH 0x30c4 15732c597bb7SPeter Griffin #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8 15742c597bb7SPeter Griffin #define QCH_CON_UASC_P_APM_QCH 0x30cc 15752c597bb7SPeter Griffin #define QCH_CON_WDT_APM_QCH 0x30d0 15762c597bb7SPeter Griffin #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00 15772c597bb7SPeter Griffin 15782c597bb7SPeter Griffin static const unsigned long apm_clk_regs[] __initconst = { 15792c597bb7SPeter Griffin APM_CMU_APM_CONTROLLER_OPTION, 15802c597bb7SPeter Griffin CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0, 15812c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 15822c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 15832c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_APM_BOOST, 15842c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 15852c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 15862c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 15872c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 15882c597bb7SPeter Griffin CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 15892c597bb7SPeter Griffin CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 15902c597bb7SPeter Griffin CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 15912c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 15922c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 15932c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 15942c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 15952c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 15962c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 15972c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 15982c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 15992c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 16002c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 16012c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 16022c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 16032c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 16042c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 16052c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 16062c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 16072c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 16082c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 16092c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 16102c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK, 16112c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 16122c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 16132c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 16142c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 16152c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 16162c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 16172c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 16182c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 16192c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 16202c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 16212c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 16222c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 16232c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 16242c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 16252c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 16262c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, 16272c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 16282c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 16292c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 16302c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 16312c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 16322c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 16332c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 16342c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 16352c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 16362c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 16372c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 16382c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 16392c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 16402c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 16412c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 16422c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 16432c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 16442c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK, 16452c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 16462c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 16472c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 16482c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 16492c597bb7SPeter Griffin }; 16502c597bb7SPeter Griffin 16512c597bb7SPeter Griffin PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc", 16522c597bb7SPeter Griffin "pad_clk_apm", "oscclk" }; 16532c597bb7SPeter Griffin PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm", 16542c597bb7SPeter Griffin "pll_alv_div16_apm" }; 16552c597bb7SPeter Griffin 16562c597bb7SPeter Griffin static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = { 16572c597bb7SPeter Griffin FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000), 16582c597bb7SPeter Griffin FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000), 16592c597bb7SPeter Griffin FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000), 16602c597bb7SPeter Griffin }; 16612c597bb7SPeter Griffin 16622c597bb7SPeter Griffin static const struct samsung_mux_clock apm_mux_clks[] __initconst = { 16632c597bb7SPeter Griffin MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p, 16642c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1), 16652c597bb7SPeter Griffin MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p, 16662c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1), 16672c597bb7SPeter Griffin }; 16682c597bb7SPeter Griffin 16692c597bb7SPeter Griffin static const struct samsung_div_clock apm_div_clks[] __initconst = { 16702c597bb7SPeter Griffin DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func", 16712c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1), 16722c597bb7SPeter Griffin DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func", 16732c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7), 16742c597bb7SPeter Griffin DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func", 16752c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7), 16762c597bb7SPeter Griffin DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func", 16772c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7), 16782c597bb7SPeter Griffin }; 16792c597bb7SPeter Griffin 16802c597bb7SPeter Griffin static const struct samsung_gate_clock apm_gate_clks[] __initconst = { 16812c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK, 16822c597bb7SPeter Griffin "gout_apm_apm_cmu_apm_pclk", "mout_apm_func", 16832c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0), 16842c597bb7SPeter Griffin GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1", 16852c597bb7SPeter Griffin "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0), 16862c597bb7SPeter Griffin GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1", 16872c597bb7SPeter Griffin "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0), 16882c597bb7SPeter Griffin GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1", 16892c597bb7SPeter Griffin "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0), 16902c597bb7SPeter Griffin GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func", 16912c597bb7SPeter Griffin CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0), 16922c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 16932c597bb7SPeter Griffin "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func", 16942c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 16952c597bb7SPeter Griffin 21, 0, 0), 16962c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK, 16972c597bb7SPeter Griffin "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func", 16982c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 16992c597bb7SPeter Griffin 21, 0, 0), 17002c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 17012c597bb7SPeter Griffin "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func", 17022c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 17032c597bb7SPeter Griffin 21, 0, 0), 17042c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APBIF_RTC_PCLK, 17052c597bb7SPeter Griffin "gout_apm_apbif_rtc_pclk", "gout_apm_func", 17062c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0), 17072c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK, 17082c597bb7SPeter Griffin "gout_apm_apbif_trtc_pclk", "gout_apm_func", 17092c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0), 17102c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK, 17112c597bb7SPeter Griffin "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart", 17122c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 17132c597bb7SPeter Griffin 21, 0, 0), 17142c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK, 17152c597bb7SPeter Griffin "gout_apm_apm_usi0_uart_pclk", "gout_apm_func", 17162c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 17172c597bb7SPeter Griffin 21, 0, 0), 17182c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK, 17192c597bb7SPeter Griffin "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi", 17202c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 17212c597bb7SPeter Griffin 21, 0, 0), 17222c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK, 17232c597bb7SPeter Griffin "gout_apm_apm_usi0_usi_pclk", "gout_apm_func", 17242c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 17252c597bb7SPeter Griffin 21, 0, 0), 17262c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK, 17272c597bb7SPeter Griffin "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart", 17282c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 17292c597bb7SPeter Griffin 21, 0, 0), 17302c597bb7SPeter Griffin GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK, 17312c597bb7SPeter Griffin "gout_apm_apm_usi1_uart_pclk", "gout_apm_func", 17322c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 17332c597bb7SPeter Griffin 21, 0, 0), 17342c597bb7SPeter Griffin GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK, 17352c597bb7SPeter Griffin "gout_apm_d_tzpc_apm_pclk", "gout_apm_func", 17362c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 17372c597bb7SPeter Griffin GATE(CLK_GOUT_APM_GPC_APM_PCLK, 17382c597bb7SPeter Griffin "gout_apm_gpc_apm_pclk", "gout_apm_func", 17392c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0), 17402c597bb7SPeter Griffin GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK, 17412c597bb7SPeter Griffin "gout_apm_grebeintegration_hclk", "gout_apm_func", 17422c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 17432c597bb7SPeter Griffin 21, 0, 0), 17442c597bb7SPeter Griffin GATE(CLK_GOUT_APM_INTMEM_ACLK, 17452c597bb7SPeter Griffin "gout_apm_intmem_aclk", "gout_apm_func", 17462c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0), 17472c597bb7SPeter Griffin GATE(CLK_GOUT_APM_INTMEM_PCLK, 17482c597bb7SPeter Griffin "gout_apm_intmem_pclk", "gout_apm_func", 17492c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0), 17502c597bb7SPeter Griffin GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK, 17512c597bb7SPeter Griffin "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func", 17522c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK, 17532c597bb7SPeter Griffin 21, 0, 0), 17542c597bb7SPeter Griffin GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK, 17552c597bb7SPeter Griffin "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func", 17562c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK, 17572c597bb7SPeter Griffin 21, 0, 0), 17582c597bb7SPeter Griffin GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK, 17592c597bb7SPeter Griffin "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func", 17602c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 17612c597bb7SPeter Griffin 21, 0, 0), 17622c597bb7SPeter Griffin GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK, 17632c597bb7SPeter Griffin "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func", 17642c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK, 17652c597bb7SPeter Griffin 21, 0, 0), 17662c597bb7SPeter Griffin GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK, 17672c597bb7SPeter Griffin "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func", 17682c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK, 17692c597bb7SPeter Griffin 21, 0, 0), 17702c597bb7SPeter Griffin GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK, 17712c597bb7SPeter Griffin "gout_apm_lhs_axi_g_scan2dram_i_clk", 17722c597bb7SPeter Griffin "gout_apm_func", 17732c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK, 17742c597bb7SPeter Griffin 21, 0, 0), 17752c597bb7SPeter Griffin GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK, 17762c597bb7SPeter Griffin "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func", 17772c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 17782c597bb7SPeter Griffin 21, 0, 0), 17792c597bb7SPeter Griffin GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK, 17802c597bb7SPeter Griffin "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func", 17812c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 17822c597bb7SPeter Griffin 21, 0, 0), 17832c597bb7SPeter Griffin GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK, 17842c597bb7SPeter Griffin "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func", 17852c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 17862c597bb7SPeter Griffin 21, 0, 0), 17872c597bb7SPeter Griffin GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK, 17882c597bb7SPeter Griffin "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func", 17892c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 17902c597bb7SPeter Griffin 21, 0, 0), 17912c597bb7SPeter Griffin GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK, 17922c597bb7SPeter Griffin "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func", 17932c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 17942c597bb7SPeter Griffin 21, 0, 0), 17952c597bb7SPeter Griffin GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK, 17962c597bb7SPeter Griffin "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func", 17972c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK, 17982c597bb7SPeter Griffin 21, 0, 0), 17992c597bb7SPeter Griffin GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK, 18002c597bb7SPeter Griffin "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func", 18012c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 18022c597bb7SPeter Griffin 21, 0, 0), 18032c597bb7SPeter Griffin GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK, 18042c597bb7SPeter Griffin "gout_apm_pmu_intr_gen_pclk", "gout_apm_func", 18052c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 18062c597bb7SPeter Griffin 21, 0, 0), 18072c597bb7SPeter Griffin GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK, 18082c597bb7SPeter Griffin "gout_apm_rom_crc32_host_aclk", "gout_apm_func", 18092c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 18102c597bb7SPeter Griffin 21, 0, 0), 18112c597bb7SPeter Griffin GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK, 18122c597bb7SPeter Griffin "gout_apm_rom_crc32_host_pclk", "gout_apm_func", 18132c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 18142c597bb7SPeter Griffin 21, 0, 0), 18152c597bb7SPeter Griffin GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK, 18162c597bb7SPeter Griffin "gout_apm_clk_apm_bus_clk", "gout_apm_func", 18172c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 18182c597bb7SPeter Griffin 21, 0, 0), 18192c597bb7SPeter Griffin GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK, 18202c597bb7SPeter Griffin "gout_apm_clk_apm_usi0_uart_clk", 18212c597bb7SPeter Griffin "dout_apm_usi0_uart", 18222c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 18232c597bb7SPeter Griffin 21, 0, 0), 18242c597bb7SPeter Griffin GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK, 18252c597bb7SPeter Griffin "gout_apm_clk_apm_usi0_usi_clk", 18262c597bb7SPeter Griffin "dout_apm_usi0_usi", 18272c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 18282c597bb7SPeter Griffin 21, 0, 0), 18292c597bb7SPeter Griffin GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK, 18302c597bb7SPeter Griffin "gout_apm_clk_apm_usi1_uart_clk", 18312c597bb7SPeter Griffin "dout_apm_usi1_uart", 18322c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 18332c597bb7SPeter Griffin 21, 0, 0), 18342c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK, 18352c597bb7SPeter Griffin "gout_apm_speedy_apm_pclk", "gout_apm_func", 18362c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0), 18372c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK, 18382c597bb7SPeter Griffin "gout_apm_speedy_sub_apm_pclk", "gout_apm_func", 18392c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK, 18402c597bb7SPeter Griffin 21, 0, 0), 18412c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK, 18422c597bb7SPeter Griffin "gout_apm_ssmt_d_apm_aclk", "gout_apm_func", 18432c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0), 18442c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK, 18452c597bb7SPeter Griffin "gout_apm_ssmt_d_apm_pclk", "gout_apm_func", 18462c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0), 18472c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK, 18482c597bb7SPeter Griffin "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func", 18492c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK, 18502c597bb7SPeter Griffin 21, 0, 0), 18512c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK, 18522c597bb7SPeter Griffin "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func", 18532c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK, 18542c597bb7SPeter Griffin 21, 0, 0), 18552c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK, 18562c597bb7SPeter Griffin "gout_apm_ss_dbgcore_ss_dbgcore_hclk", 18572c597bb7SPeter Griffin "gout_apm_func", 18582c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 18592c597bb7SPeter Griffin 21, 0, 0), 18602c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2, 18612c597bb7SPeter Griffin "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func", 18622c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 18632c597bb7SPeter Griffin 21, 0, 0), 18642c597bb7SPeter Griffin GATE(CLK_GOUT_APM_SYSREG_APM_PCLK, 18652c597bb7SPeter Griffin "gout_apm_sysreg_apm_pclk", "gout_apm_func", 18662c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0), 18672c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_APM_ACLK, 18682c597bb7SPeter Griffin "gout_apm_uasc_apm_aclk", "gout_apm_func", 18692c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0), 18702c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_APM_PCLK, 18712c597bb7SPeter Griffin "gout_apm_uasc_apm_pclk", "gout_apm_func", 18722c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0), 18732c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK, 18742c597bb7SPeter Griffin "gout_apm_uasc_dbgcore_aclk", "gout_apm_func", 18752c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 18762c597bb7SPeter Griffin 21, 0, 0), 18772c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK, 18782c597bb7SPeter Griffin "gout_apm_uasc_dbgcore_pclk", "gout_apm_func", 18792c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 18802c597bb7SPeter Griffin 21, 0, 0), 18812c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK, 18822c597bb7SPeter Griffin "gout_apm_uasc_g_swd_aclk", "gout_apm_func", 18832c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0), 18842c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK, 18852c597bb7SPeter Griffin "gout_apm_uasc_g_swd_pclk", "gout_apm_func", 18862c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 18872c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK, 18882c597bb7SPeter Griffin "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func", 18892c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK, 18902c597bb7SPeter Griffin 21, 0, 0), 18912c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK, 18922c597bb7SPeter Griffin "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func", 18932c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0), 18942c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_P_APM_ACLK, 18952c597bb7SPeter Griffin "gout_apm_uasc_p_apm_aclk", "gout_apm_func", 18962c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, 0, 0), 18972c597bb7SPeter Griffin GATE(CLK_GOUT_APM_UASC_P_APM_PCLK, 18982c597bb7SPeter Griffin "gout_apm_uasc_p_apm_pclk", "gout_apm_func", 18992c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, 0, 0), 19002c597bb7SPeter Griffin GATE(CLK_GOUT_APM_WDT_APM_PCLK, 19012c597bb7SPeter Griffin "gout_apm_wdt_apm_pclk", "gout_apm_func", 19022c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0), 19032c597bb7SPeter Griffin GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK, 19042c597bb7SPeter Griffin "gout_apm_xiu_dp_apm_aclk", "gout_apm_func", 19052c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, 0, 0), 19062c597bb7SPeter Griffin }; 19072c597bb7SPeter Griffin 19082c597bb7SPeter Griffin static const struct samsung_cmu_info apm_cmu_info __initconst = { 19092c597bb7SPeter Griffin .mux_clks = apm_mux_clks, 19102c597bb7SPeter Griffin .nr_mux_clks = ARRAY_SIZE(apm_mux_clks), 19112c597bb7SPeter Griffin .div_clks = apm_div_clks, 19122c597bb7SPeter Griffin .nr_div_clks = ARRAY_SIZE(apm_div_clks), 19132c597bb7SPeter Griffin .gate_clks = apm_gate_clks, 19142c597bb7SPeter Griffin .nr_gate_clks = ARRAY_SIZE(apm_gate_clks), 19152c597bb7SPeter Griffin .fixed_clks = apm_fixed_clks, 19162c597bb7SPeter Griffin .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks), 19172c597bb7SPeter Griffin .nr_clk_ids = CLKS_NR_APM, 19182c597bb7SPeter Griffin .clk_regs = apm_clk_regs, 19192c597bb7SPeter Griffin .nr_clk_regs = ARRAY_SIZE(apm_clk_regs), 19202c597bb7SPeter Griffin }; 19212c597bb7SPeter Griffin 19222c597bb7SPeter Griffin /* ---- CMU_MISC ------------------------------------------------------------ */ 19232c597bb7SPeter Griffin 19242c597bb7SPeter Griffin /* Register Offset definitions for CMU_MISC (0x10010000) */ 19252c597bb7SPeter Griffin #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600 19262c597bb7SPeter Griffin #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604 19272c597bb7SPeter Griffin #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610 19282c597bb7SPeter Griffin #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614 19292c597bb7SPeter Griffin #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800 19302c597bb7SPeter Griffin #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810 19312c597bb7SPeter Griffin #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 19322c597bb7SPeter Griffin #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800 19332c597bb7SPeter Griffin #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804 19342c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000 19352c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004 19362c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008 19372c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c 19382c597bb7SPeter Griffin #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010 19392c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014 19402c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018 19412c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c 19422c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020 19432c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024 19442c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028 19452c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c 19462c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030 19472c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034 19482c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038 19492c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c 19502c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040 19512c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044 19522c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048 19532c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c 19542c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050 19552c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054 19562c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058 19572c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c 19582c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060 19592c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064 19602c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068 19612c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c 19622c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070 19632c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074 19642c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078 19652c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c 19662c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080 19672c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084 19682c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088 19692c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c 19702c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090 19712c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094 19722c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098 19732c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c 19742c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0 19752c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4 19762c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8 19772c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac 19782c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0 19792c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4 19802c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8 19812c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc 19822c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0 19832c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4 19842c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8 19852c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc 19862c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0 19872c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4 19882c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8 19892c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc 19902c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0 19912c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4 19922c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8 19932c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec 19942c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0 19952c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4 19962c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8 19972c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc 19982c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100 19992c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104 20002c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108 20012c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c 20022c597bb7SPeter Griffin #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110 20032c597bb7SPeter Griffin #define DMYQCH_CON_PPMU_DMA_QCH 0x3000 20042c597bb7SPeter Griffin #define DMYQCH_CON_PUF_QCH 0x3004 20052c597bb7SPeter Griffin #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c 20062c597bb7SPeter Griffin #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010 20072c597bb7SPeter Griffin #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014 20082c597bb7SPeter Griffin #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018 20092c597bb7SPeter Griffin #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c 20102c597bb7SPeter Griffin #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020 20112c597bb7SPeter Griffin #define QCH_CON_ADM_AHB_SSS_QCH 0x3024 20122c597bb7SPeter Griffin #define QCH_CON_DIT_QCH 0x3028 20132c597bb7SPeter Griffin #define QCH_CON_GIC_QCH 0x3030 20142c597bb7SPeter Griffin #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038 20152c597bb7SPeter Griffin #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c 20162c597bb7SPeter Griffin #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040 20172c597bb7SPeter Griffin #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044 20182c597bb7SPeter Griffin #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048 20192c597bb7SPeter Griffin #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c 20202c597bb7SPeter Griffin #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050 20212c597bb7SPeter Griffin #define QCH_CON_MCT_QCH 0x3054 20222c597bb7SPeter Griffin #define QCH_CON_MISC_CMU_MISC_QCH 0x3058 20232c597bb7SPeter Griffin #define QCH_CON_OTP_CON_BIRA_QCH 0x305c 20242c597bb7SPeter Griffin #define QCH_CON_OTP_CON_BISR_QCH 0x3060 20252c597bb7SPeter Griffin #define QCH_CON_OTP_CON_TOP_QCH 0x3064 20262c597bb7SPeter Griffin #define QCH_CON_PDMA_QCH 0x3068 20272c597bb7SPeter Griffin #define QCH_CON_PPMU_MISC_QCH 0x306c 20282c597bb7SPeter Griffin #define QCH_CON_QE_DIT_QCH 0x3070 20292c597bb7SPeter Griffin #define QCH_CON_QE_PDMA_QCH 0x3074 20302c597bb7SPeter Griffin #define QCH_CON_QE_PPMU_DMA_QCH 0x3078 20312c597bb7SPeter Griffin #define QCH_CON_QE_RTIC_QCH 0x307c 20322c597bb7SPeter Griffin #define QCH_CON_QE_SPDMA_QCH 0x3080 20332c597bb7SPeter Griffin #define QCH_CON_QE_SSS_QCH 0x3084 20342c597bb7SPeter Griffin #define QCH_CON_RTIC_QCH 0x3088 20352c597bb7SPeter Griffin #define QCH_CON_SPDMA_QCH 0x308c 20362c597bb7SPeter Griffin #define QCH_CON_SSMT_DIT_QCH 0x3090 20372c597bb7SPeter Griffin #define QCH_CON_SSMT_PDMA_QCH 0x3094 20382c597bb7SPeter Griffin #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098 20392c597bb7SPeter Griffin #define QCH_CON_SSMT_RTIC_QCH 0x309c 20402c597bb7SPeter Griffin #define QCH_CON_SSMT_SPDMA_QCH 0x30a0 20412c597bb7SPeter Griffin #define QCH_CON_SSMT_SSS_QCH 0x30a4 20422c597bb7SPeter Griffin #define QCH_CON_SSS_QCH 0x30a8 20432c597bb7SPeter Griffin #define QCH_CON_SYSMMU_MISC_QCH 0x30ac 20442c597bb7SPeter Griffin #define QCH_CON_SYSMMU_SSS_QCH 0x30b0 20452c597bb7SPeter Griffin #define QCH_CON_SYSREG_MISC_QCH 0x30b4 20462c597bb7SPeter Griffin #define QCH_CON_TMU_SUB_QCH 0x30b8 20472c597bb7SPeter Griffin #define QCH_CON_TMU_TOP_QCH 0x30bc 20482c597bb7SPeter Griffin #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0 20492c597bb7SPeter Griffin #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4 20502c597bb7SPeter Griffin #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00 20512c597bb7SPeter Griffin 20522c597bb7SPeter Griffin static const unsigned long misc_clk_regs[] __initconst = { 20532c597bb7SPeter Griffin PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 20542c597bb7SPeter Griffin PLL_CON1_MUX_CLKCMU_MISC_BUS_USER, 20552c597bb7SPeter Griffin PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 20562c597bb7SPeter Griffin PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, 20572c597bb7SPeter Griffin MISC_CMU_MISC_CONTROLLER_OPTION, 20582c597bb7SPeter Griffin CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0, 20592c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLK_MISC_GIC, 20602c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_MISC_BUSP, 20612c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_MISC_GIC, 20622c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 20632c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 20642c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 20652c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 20662c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 20672c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 20682c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 20692c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, 20702c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, 20712c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 20722c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 20732c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 20742c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 20752c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 20762c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 20772c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 20782c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 20792c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 20802c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 20812c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 20822c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 20832c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 20842c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 20852c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 20862c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK, 20872c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 20882c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 20892c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 20902c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 20912c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 20922c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 20932c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 20942c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 20952c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 20962c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 20972c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 20982c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 20992c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 21002c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 21012c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 21022c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 21032c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 21042c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 21052c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 21062c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 21072c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 21082c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 21092c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 21102c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 21112c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 21122c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 21132c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 21142c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 21152c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 21162c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 21172c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 21182c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 21192c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 21202c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 21212c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 21222c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 21232c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 21242c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 21252c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 21262c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 21272c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 21282c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 21292c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 21302c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 21312c597bb7SPeter Griffin DMYQCH_CON_PPMU_DMA_QCH, 21322c597bb7SPeter Griffin DMYQCH_CON_PUF_QCH, 21332c597bb7SPeter Griffin PCH_CON_LHM_AXI_D_SSS_PCH, 21342c597bb7SPeter Griffin PCH_CON_LHM_AXI_P_GIC_PCH, 21352c597bb7SPeter Griffin PCH_CON_LHM_AXI_P_MISC_PCH, 21362c597bb7SPeter Griffin PCH_CON_LHS_ACEL_D_MISC_PCH, 21372c597bb7SPeter Griffin PCH_CON_LHS_AST_IRI_GICCPU_PCH, 21382c597bb7SPeter Griffin PCH_CON_LHS_AXI_D_SSS_PCH, 21392c597bb7SPeter Griffin QCH_CON_ADM_AHB_SSS_QCH, 21402c597bb7SPeter Griffin QCH_CON_DIT_QCH, 21412c597bb7SPeter Griffin QCH_CON_GIC_QCH, 21422c597bb7SPeter Griffin QCH_CON_LHM_AST_ICC_CPUGIC_QCH, 21432c597bb7SPeter Griffin QCH_CON_LHM_AXI_D_SSS_QCH, 21442c597bb7SPeter Griffin QCH_CON_LHM_AXI_P_GIC_QCH, 21452c597bb7SPeter Griffin QCH_CON_LHM_AXI_P_MISC_QCH, 21462c597bb7SPeter Griffin QCH_CON_LHS_ACEL_D_MISC_QCH, 21472c597bb7SPeter Griffin QCH_CON_LHS_AST_IRI_GICCPU_QCH, 21482c597bb7SPeter Griffin QCH_CON_LHS_AXI_D_SSS_QCH, 21492c597bb7SPeter Griffin QCH_CON_MCT_QCH, 21502c597bb7SPeter Griffin QCH_CON_MISC_CMU_MISC_QCH, 21512c597bb7SPeter Griffin QCH_CON_OTP_CON_BIRA_QCH, 21522c597bb7SPeter Griffin QCH_CON_OTP_CON_BISR_QCH, 21532c597bb7SPeter Griffin QCH_CON_OTP_CON_TOP_QCH, 21542c597bb7SPeter Griffin QCH_CON_PDMA_QCH, 21552c597bb7SPeter Griffin QCH_CON_PPMU_MISC_QCH, 21562c597bb7SPeter Griffin QCH_CON_QE_DIT_QCH, 21572c597bb7SPeter Griffin QCH_CON_QE_PDMA_QCH, 21582c597bb7SPeter Griffin QCH_CON_QE_PPMU_DMA_QCH, 21592c597bb7SPeter Griffin QCH_CON_QE_RTIC_QCH, 21602c597bb7SPeter Griffin QCH_CON_QE_SPDMA_QCH, 21612c597bb7SPeter Griffin QCH_CON_QE_SSS_QCH, 21622c597bb7SPeter Griffin QCH_CON_RTIC_QCH, 21632c597bb7SPeter Griffin QCH_CON_SPDMA_QCH, 21642c597bb7SPeter Griffin QCH_CON_SSMT_DIT_QCH, 21652c597bb7SPeter Griffin QCH_CON_SSMT_PDMA_QCH, 21662c597bb7SPeter Griffin QCH_CON_SSMT_PPMU_DMA_QCH, 21672c597bb7SPeter Griffin QCH_CON_SSMT_RTIC_QCH, 21682c597bb7SPeter Griffin QCH_CON_SSMT_SPDMA_QCH, 21692c597bb7SPeter Griffin QCH_CON_SSMT_SSS_QCH, 21702c597bb7SPeter Griffin QCH_CON_SSS_QCH, 21712c597bb7SPeter Griffin QCH_CON_SYSMMU_MISC_QCH, 21722c597bb7SPeter Griffin QCH_CON_SYSMMU_SSS_QCH, 21732c597bb7SPeter Griffin QCH_CON_SYSREG_MISC_QCH, 21742c597bb7SPeter Griffin QCH_CON_TMU_SUB_QCH, 21752c597bb7SPeter Griffin QCH_CON_TMU_TOP_QCH, 21762c597bb7SPeter Griffin QCH_CON_WDT_CLUSTER0_QCH, 21772c597bb7SPeter Griffin QCH_CON_WDT_CLUSTER1_QCH, 21782c597bb7SPeter Griffin QUEUE_CTRL_REG_BLK_MISC_CMU_MISC, 21792c597bb7SPeter Griffin }; 21802c597bb7SPeter Griffin 21812c597bb7SPeter Griffin /* List of parent clocks for Muxes in CMU_MISC */ 21822c597bb7SPeter Griffin PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" }; 21832c597bb7SPeter Griffin PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" }; 21842c597bb7SPeter Griffin PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" }; 21852c597bb7SPeter Griffin 21862c597bb7SPeter Griffin static const struct samsung_mux_clock misc_mux_clks[] __initconst = { 21872c597bb7SPeter Griffin MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p, 21882c597bb7SPeter Griffin PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1), 21892c597bb7SPeter Griffin MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p, 21902c597bb7SPeter Griffin PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1), 21912c597bb7SPeter Griffin MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p, 21922c597bb7SPeter Griffin CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0), 21932c597bb7SPeter Griffin }; 21942c597bb7SPeter Griffin 21952c597bb7SPeter Griffin static const struct samsung_div_clock misc_div_clks[] __initconst = { 21962c597bb7SPeter Griffin DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user", 21972c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3), 21982c597bb7SPeter Griffin DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user", 21992c597bb7SPeter Griffin CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3), 22002c597bb7SPeter Griffin }; 22012c597bb7SPeter Griffin 22022c597bb7SPeter Griffin static const struct samsung_gate_clock misc_gate_clks[] __initconst = { 22032c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK, 22042c597bb7SPeter Griffin "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp", 22052c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 22062c597bb7SPeter Griffin 21, 0, 0), 22072c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK, 22082c597bb7SPeter Griffin "gout_misc_otp_con_bira_i_oscclk", "oscclk", 22092c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 22102c597bb7SPeter Griffin 21, 0, 0), 22112c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK, 22122c597bb7SPeter Griffin "gout_misc_otp_con_bisr_i_oscclk", "oscclk", 22132c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 22142c597bb7SPeter Griffin 21, 0, 0), 22152c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK, 22162c597bb7SPeter Griffin "gout_misc_otp_con_top_i_oscclk", "oscclk", 22172c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 22182c597bb7SPeter Griffin 21, 0, 0), 22192c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK, 22202c597bb7SPeter Griffin "gout_misc_clk_misc_oscclk_clk", "oscclk", 22212c597bb7SPeter Griffin CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 22222c597bb7SPeter Griffin 21, 0, 0), 22232c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM, 22242c597bb7SPeter Griffin "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user", 22252c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 22262c597bb7SPeter Griffin 21, 0, 0), 22272c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM, 22282c597bb7SPeter Griffin "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user", 22292c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 22302c597bb7SPeter Griffin 21, 0, 0), 22312c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK, 22322c597bb7SPeter Griffin "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp", 22332c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 22342c597bb7SPeter Griffin 21, 0, 0), 22352c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_GIC_GICCLK, 22362c597bb7SPeter Griffin "gout_misc_gic_gicclk", "mout_misc_gic", 22372c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 22382c597bb7SPeter Griffin 21, 0, 0), 22392c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_GPC_MISC_PCLK, 22402c597bb7SPeter Griffin "gout_misc_gpc_misc_pclk", "dout_misc_busp", 22412c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 22422c597bb7SPeter Griffin 21, 0, 0), 22432c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK, 22442c597bb7SPeter Griffin "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic", 22452c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK, 22462c597bb7SPeter Griffin 21, 0, 0), 22472c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK, 22482c597bb7SPeter Griffin "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user", 22492c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK, 22502c597bb7SPeter Griffin 21, 0, 0), 22512c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK, 22522c597bb7SPeter Griffin "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic", 22532c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK, 22542c597bb7SPeter Griffin 21, 0, 0), 22552c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK, 22562c597bb7SPeter Griffin "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp", 22572c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK, 22582c597bb7SPeter Griffin 21, 0, 0), 22592c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK, 22602c597bb7SPeter Griffin "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user", 22612c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK, 22622c597bb7SPeter Griffin 21, 0, 0), 22632c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK, 22642c597bb7SPeter Griffin "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic", 22652c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK, 22662c597bb7SPeter Griffin 21, 0, 0), 22672c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK, 22682c597bb7SPeter Griffin "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user", 22692c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK, 22702c597bb7SPeter Griffin 21, 0, 0), 22712c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk", 22722c597bb7SPeter Griffin "dout_misc_busp", 22732c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 22742c597bb7SPeter Griffin 21, 0, 0), 22752c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK, 22762c597bb7SPeter Griffin "gout_misc_otp_con_bira_pclk", "dout_misc_busp", 22772c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 22782c597bb7SPeter Griffin 21, 0, 0), 22792c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK, 22802c597bb7SPeter Griffin "gout_misc_otp_con_bisr_pclk", "dout_misc_busp", 22812c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 22822c597bb7SPeter Griffin 21, 0, 0), 22832c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK, 22842c597bb7SPeter Griffin "gout_misc_otp_con_top_pclk", "dout_misc_busp", 22852c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 22862c597bb7SPeter Griffin 21, 0, 0), 22872c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk", 22882c597bb7SPeter Griffin "mout_misc_bus_user", 22892c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK, 22902c597bb7SPeter Griffin 21, 0, 0), 22912c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK, 22922c597bb7SPeter Griffin "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user", 22932c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 22942c597bb7SPeter Griffin 21, 0, 0), 22952c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK, 22962c597bb7SPeter Griffin "gout_misc_ppmu_misc_pclk", "dout_misc_busp", 22972c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 22982c597bb7SPeter Griffin 21, 0, 0), 22992c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_PUF_I_CLK, 23002c597bb7SPeter Griffin "gout_misc_puf_i_clk", "mout_misc_sss_user", 23012c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 23022c597bb7SPeter Griffin 21, 0, 0), 23032c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_DIT_ACLK, 23042c597bb7SPeter Griffin "gout_misc_qe_dit_aclk", "mout_misc_bus_user", 23052c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 23062c597bb7SPeter Griffin 21, 0, 0), 23072c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_DIT_PCLK, 23082c597bb7SPeter Griffin "gout_misc_qe_dit_pclk", "dout_misc_busp", 23092c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 23102c597bb7SPeter Griffin 21, 0, 0), 23112c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_PDMA_ACLK, 23122c597bb7SPeter Griffin "gout_misc_qe_pdma_aclk", "mout_misc_bus_user", 23132c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK, 23142c597bb7SPeter Griffin 21, 0, 0), 23152c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_PDMA_PCLK, 23162c597bb7SPeter Griffin "gout_misc_qe_pdma_pclk", "dout_misc_busp", 23172c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK, 23182c597bb7SPeter Griffin 21, 0, 0), 23192c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK, 23202c597bb7SPeter Griffin "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user", 23212c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK, 23222c597bb7SPeter Griffin 21, 0, 0), 23232c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK, 23242c597bb7SPeter Griffin "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp", 23252c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK, 23262c597bb7SPeter Griffin 21, 0, 0), 23272c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_RTIC_ACLK, 23282c597bb7SPeter Griffin "gout_misc_qe_rtic_aclk", "mout_misc_bus_user", 23292c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 23302c597bb7SPeter Griffin 21, 0, 0), 23312c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_RTIC_PCLK, 23322c597bb7SPeter Griffin "gout_misc_qe_rtic_pclk", "dout_misc_busp", 23332c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 23342c597bb7SPeter Griffin 21, 0, 0), 23352c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK, 23362c597bb7SPeter Griffin "gout_misc_qe_spdma_aclk", "mout_misc_bus_user", 23372c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK, 23382c597bb7SPeter Griffin 21, 0, 0), 23392c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK, 23402c597bb7SPeter Griffin "gout_misc_qe_spdma_pclk", "dout_misc_busp", 23412c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK, 23422c597bb7SPeter Griffin 21, 0, 0), 23432c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_SSS_ACLK, 23442c597bb7SPeter Griffin "gout_misc_qe_sss_aclk", "mout_misc_sss_user", 23452c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 23462c597bb7SPeter Griffin 21, 0, 0), 23472c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_QE_SSS_PCLK, 23482c597bb7SPeter Griffin "gout_misc_qe_sss_pclk", "dout_misc_busp", 23492c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 23502c597bb7SPeter Griffin 21, 0, 0), 23512c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK, 23522c597bb7SPeter Griffin "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user", 23532c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK, 23542c597bb7SPeter Griffin 21, 0, 0), 23552c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK, 23562c597bb7SPeter Griffin "gout_misc_clk_misc_busp_clk", "dout_misc_busp", 23572c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK, 23582c597bb7SPeter Griffin 21, 0, 0), 23592c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK, 23602c597bb7SPeter Griffin "gout_misc_clk_misc_gic_clk", "mout_misc_gic", 23612c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 23622c597bb7SPeter Griffin 21, 0, 0), 23632c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK, 23642c597bb7SPeter Griffin "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user", 23652c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 23662c597bb7SPeter Griffin 21, 0, 0), 23672c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_RTIC_I_ACLK, 23682c597bb7SPeter Griffin "gout_misc_rtic_i_aclk", "mout_misc_bus_user", 23692c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 23702c597bb7SPeter Griffin 21, 0, 0), 23712c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk", 23722c597bb7SPeter Griffin "dout_misc_busp", 23732c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 23742c597bb7SPeter Griffin 21, 0, 0), 23752c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SPDMA_ACLK, 23762c597bb7SPeter Griffin "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user", 23772c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK, 23782c597bb7SPeter Griffin 21, 0, 0), 23792c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK, 23802c597bb7SPeter Griffin "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user", 23812c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 23822c597bb7SPeter Griffin 21, 0, 0), 23832c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK, 23842c597bb7SPeter Griffin "gout_misc_ssmt_dit_pclk", "dout_misc_busp", 23852c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 23862c597bb7SPeter Griffin 21, 0, 0), 23872c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK, 23882c597bb7SPeter Griffin "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user", 23892c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK, 23902c597bb7SPeter Griffin 21, 0, 0), 23912c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK, 23922c597bb7SPeter Griffin "gout_misc_ssmt_pdma_pclk", "dout_misc_busp", 23932c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK, 23942c597bb7SPeter Griffin 21, 0, 0), 23952c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK, 23962c597bb7SPeter Griffin "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user", 23972c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK, 23982c597bb7SPeter Griffin 21, 0, 0), 23992c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK, 24002c597bb7SPeter Griffin "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp", 24012c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK, 24022c597bb7SPeter Griffin 21, 0, 0), 24032c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK, 24042c597bb7SPeter Griffin "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user", 24052c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 24062c597bb7SPeter Griffin 21, 0, 0), 24072c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK, 24082c597bb7SPeter Griffin "gout_misc_ssmt_rtic_pclk", "dout_misc_busp", 24092c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 24102c597bb7SPeter Griffin 21, 0, 0), 24112c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK, 24122c597bb7SPeter Griffin "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user", 24132c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK, 24142c597bb7SPeter Griffin 21, 0, 0), 24152c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK, 24162c597bb7SPeter Griffin "gout_misc_ssmt_spdma_pclk", "dout_misc_busp", 24172c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK, 24182c597bb7SPeter Griffin 21, 0, 0), 24192c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK, 24202c597bb7SPeter Griffin "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user", 24212c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 24222c597bb7SPeter Griffin 21, 0, 0), 24232c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK, 24242c597bb7SPeter Griffin "gout_misc_ssmt_sss_pclk", "dout_misc_busp", 24252c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 24262c597bb7SPeter Griffin 21, 0, 0), 24272c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSS_I_ACLK, 24282c597bb7SPeter Griffin "gout_misc_sss_i_aclk", "mout_misc_bus_user", 24292c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 24302c597bb7SPeter Griffin 21, 0, 0), 24312c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SSS_I_PCLK, 24322c597bb7SPeter Griffin "gout_misc_sss_i_pclk", "dout_misc_busp", 24332c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 24342c597bb7SPeter Griffin 21, 0, 0), 24352c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2, 24362c597bb7SPeter Griffin "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user", 24372c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 24382c597bb7SPeter Griffin 21, 0, 0), 24392c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1, 24402c597bb7SPeter Griffin "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user", 24412c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 24422c597bb7SPeter Griffin 21, 0, 0), 24432c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK, 24442c597bb7SPeter Griffin "gout_misc_sysreg_misc_pclk", "dout_misc_busp", 24452c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 24462c597bb7SPeter Griffin 21, 0, 0), 24472c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_TMU_SUB_PCLK, 24482c597bb7SPeter Griffin "gout_misc_tmu_sub_pclk", "dout_misc_busp", 24492c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 24502c597bb7SPeter Griffin 21, 0, 0), 24512c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_TMU_TOP_PCLK, 24522c597bb7SPeter Griffin "gout_misc_tmu_top_pclk", "dout_misc_busp", 24532c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 24542c597bb7SPeter Griffin 21, 0, 0), 24552c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK, 24562c597bb7SPeter Griffin "gout_misc_wdt_cluster0_pclk", "dout_misc_busp", 24572c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 24582c597bb7SPeter Griffin 21, 0, 0), 24592c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK, 24602c597bb7SPeter Griffin "gout_misc_wdt_cluster1_pclk", "dout_misc_busp", 24612c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 24622c597bb7SPeter Griffin 21, 0, 0), 24632c597bb7SPeter Griffin GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK, 24642c597bb7SPeter Griffin "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user", 24652c597bb7SPeter Griffin CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 24662c597bb7SPeter Griffin 21, 0, 0), 24672c597bb7SPeter Griffin }; 24682c597bb7SPeter Griffin 24692c597bb7SPeter Griffin static const struct samsung_cmu_info misc_cmu_info __initconst = { 24702c597bb7SPeter Griffin .mux_clks = misc_mux_clks, 24712c597bb7SPeter Griffin .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), 24722c597bb7SPeter Griffin .div_clks = misc_div_clks, 24732c597bb7SPeter Griffin .nr_div_clks = ARRAY_SIZE(misc_div_clks), 24742c597bb7SPeter Griffin .gate_clks = misc_gate_clks, 24752c597bb7SPeter Griffin .nr_gate_clks = ARRAY_SIZE(misc_gate_clks), 24762c597bb7SPeter Griffin .nr_clk_ids = CLKS_NR_MISC, 24772c597bb7SPeter Griffin .clk_regs = misc_clk_regs, 24782c597bb7SPeter Griffin .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), 2479d76c762eSTudor Ambarus .clk_name = "bus", 24802c597bb7SPeter Griffin }; 24812c597bb7SPeter Griffin 2482163cd42fSPeter Griffin static void __init gs101_cmu_misc_init(struct device_node *np) 2483163cd42fSPeter Griffin { 2484163cd42fSPeter Griffin exynos_arm64_register_cmu(NULL, np, &misc_cmu_info); 2485163cd42fSPeter Griffin } 2486163cd42fSPeter Griffin 2487163cd42fSPeter Griffin /* Register CMU_MISC early, as it's needed for MCT timer */ 2488163cd42fSPeter Griffin CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc", 2489163cd42fSPeter Griffin gs101_cmu_misc_init); 2490163cd42fSPeter Griffin 2491893f133aSTudor Ambarus /* ---- CMU_PERIC0 ---------------------------------------------------------- */ 2492893f133aSTudor Ambarus 2493893f133aSTudor Ambarus /* Register Offset definitions for CMU_PERIC0 (0x10800000) */ 2494893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600 2495893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604 2496893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610 2497893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614 2498893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620 2499893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624 2500893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640 2501893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644 2502893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650 2503893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654 2504893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660 2505893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664 2506893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670 2507893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674 2508893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680 2509893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684 2510893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690 2511893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694 2512893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0 2513893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4 2514893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0 2515893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4 2516893f133aSTudor Ambarus #define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0 2517893f133aSTudor Ambarus #define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4 2518893f133aSTudor Ambarus #define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800 2519893f133aSTudor Ambarus #define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810 2520893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 2521893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804 2522893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c 2523893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810 2524893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814 2525893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820 2526893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824 2527893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828 2528893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c 2529893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830 2530893f133aSTudor Ambarus #define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834 2531893f133aSTudor Ambarus #define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000 2532893f133aSTudor Ambarus #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004 2533893f133aSTudor Ambarus #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008 2534893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c 2535893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010 2536893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014 2537893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018 2538893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c 2539893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020 2540893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024 2541893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028 2542893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c 2543893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030 2544893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034 2545893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038 2546893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c 2547893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040 2548893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044 2549893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048 2550893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c 2551893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050 2552893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054 2553893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058 2554893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c 2555893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060 2556893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064 2557893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068 2558893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c 2559893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070 2560893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074 2561893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078 2562893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c 2563893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080 2564893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084 2565893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088 2566893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c 2567893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090 2568893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094 2569893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098 2570893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c 2571893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4 2572893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8 2573893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0 2574893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4 2575893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8 2576893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc 2577893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4 2578893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8 2579893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc 2580893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0 2581893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4 2582893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8 2583893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc 2584893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0 2585893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4 2586893f133aSTudor Ambarus #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8 2587893f133aSTudor Ambarus #define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000 2588893f133aSTudor Ambarus #define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004 2589893f133aSTudor Ambarus #define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008 2590893f133aSTudor Ambarus #define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c 2591893f133aSTudor Ambarus #define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010 2592893f133aSTudor Ambarus #define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014 2593893f133aSTudor Ambarus #define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018 2594893f133aSTudor Ambarus #define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c 2595893f133aSTudor Ambarus #define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020 2596893f133aSTudor Ambarus #define QCH_CON_D_TZPC_PERIC0_QCH 0x3024 2597893f133aSTudor Ambarus #define QCH_CON_GPC_PERIC0_QCH 0x3028 2598893f133aSTudor Ambarus #define QCH_CON_GPIO_PERIC0_QCH 0x302c 2599893f133aSTudor Ambarus #define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030 2600893f133aSTudor Ambarus #define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034 2601893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038 2602893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c 2603893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040 2604893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044 2605893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048 2606893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c 2607893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050 2608893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054 2609893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058 2610893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c 2611893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060 2612893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064 2613893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068 2614893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c 2615893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070 2616893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074 2617893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078 2618893f133aSTudor Ambarus #define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c 2619893f133aSTudor Ambarus #define QCH_CON_SYSREG_PERIC0_QCH 0x3080 2620893f133aSTudor Ambarus #define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00 2621893f133aSTudor Ambarus 2622893f133aSTudor Ambarus static const unsigned long peric0_clk_regs[] __initconst = { 2623893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 2624893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER, 2625893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 2626893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, 2627893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 2628893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, 2629893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 2630893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, 2631893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 2632893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, 2633893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 2634893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, 2635893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 2636893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, 2637893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 2638893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, 2639893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 2640893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, 2641893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 2642893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, 2643893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 2644893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, 2645893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 2646893f133aSTudor Ambarus PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, 2647893f133aSTudor Ambarus PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 2648893f133aSTudor Ambarus CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0, 2649893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 2650893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 2651893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 2652893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 2653893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 2654893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 2655893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 2656893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 2657893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 2658893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 2659893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 2660893f133aSTudor Ambarus CLK_CON_BUF_CLKBUF_PERIC0_IP, 2661893f133aSTudor Ambarus CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 2662893f133aSTudor Ambarus CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 2663893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 2664893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 2665893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 2666893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 2667893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 2668893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 2669893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 2670893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 2671893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 2672893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 2673893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 2674893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 2675893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 2676893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 2677893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 2678893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 2679893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 2680893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 2681893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 2682893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 2683893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 2684893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 2685893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 2686893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 2687893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 2688893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 2689893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 2690893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 2691893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 2692893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 2693893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 2694893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 2695893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 2696893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 2697893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 2698893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 2699893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 2700893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 2701893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 2702893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, 2703893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 2704893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 2705893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 2706893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 2707893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 2708893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 2709893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 2710893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 2711893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 2712893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 2713893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 2714893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 2715893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 2716893f133aSTudor Ambarus DMYQCH_CON_PERIC0_TOP0_QCH_S1, 2717893f133aSTudor Ambarus DMYQCH_CON_PERIC0_TOP0_QCH_S2, 2718893f133aSTudor Ambarus DMYQCH_CON_PERIC0_TOP0_QCH_S3, 2719893f133aSTudor Ambarus DMYQCH_CON_PERIC0_TOP0_QCH_S4, 2720893f133aSTudor Ambarus DMYQCH_CON_PERIC0_TOP0_QCH_S5, 2721893f133aSTudor Ambarus DMYQCH_CON_PERIC0_TOP0_QCH_S6, 2722893f133aSTudor Ambarus DMYQCH_CON_PERIC0_TOP0_QCH_S7, 2723893f133aSTudor Ambarus DMYQCH_CON_PERIC0_TOP0_QCH_S8, 2724893f133aSTudor Ambarus PCH_CON_LHM_AXI_P_PERIC0_PCH, 2725893f133aSTudor Ambarus QCH_CON_D_TZPC_PERIC0_QCH, 2726893f133aSTudor Ambarus QCH_CON_GPC_PERIC0_QCH, 2727893f133aSTudor Ambarus QCH_CON_GPIO_PERIC0_QCH, 2728893f133aSTudor Ambarus QCH_CON_LHM_AXI_P_PERIC0_QCH, 2729893f133aSTudor Ambarus QCH_CON_PERIC0_CMU_PERIC0_QCH, 2730893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_I3C1, 2731893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_I3C2, 2732893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_I3C3, 2733893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_I3C4, 2734893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_I3C5, 2735893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_I3C6, 2736893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_I3C7, 2737893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_I3C8, 2738893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_USI1_USI, 2739893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_USI2_USI, 2740893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_USI3_USI, 2741893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_USI4_USI, 2742893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_USI5_USI, 2743893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_USI6_USI, 2744893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_USI7_USI, 2745893f133aSTudor Ambarus QCH_CON_PERIC0_TOP0_QCH_USI8_USI, 2746893f133aSTudor Ambarus QCH_CON_PERIC0_TOP1_QCH_USI0_UART, 2747893f133aSTudor Ambarus QCH_CON_PERIC0_TOP1_QCH_USI14_UART, 2748893f133aSTudor Ambarus QCH_CON_SYSREG_PERIC0_QCH, 2749893f133aSTudor Ambarus QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0, 2750893f133aSTudor Ambarus }; 2751893f133aSTudor Ambarus 2752893f133aSTudor Ambarus /* List of parent clocks for Muxes in CMU_PERIC0 */ 2753893f133aSTudor Ambarus PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" }; 2754893f133aSTudor Ambarus PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 2755893f133aSTudor Ambarus PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 2756893f133aSTudor Ambarus PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" }; 2757893f133aSTudor Ambarus 2758893f133aSTudor Ambarus static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { 2759893f133aSTudor Ambarus MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user", 2760893f133aSTudor Ambarus mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1), 2761893f133aSTudor Ambarus MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user", 2762893f133aSTudor Ambarus mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1), 2763893f133aSTudor Ambarus MUX(CLK_MOUT_PERIC0_USI0_UART_USER, 2764893f133aSTudor Ambarus "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p, 2765893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1), 2766*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI14_USI_USER, 2767893f133aSTudor Ambarus "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p, 2768893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1), 2769*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI1_USI_USER, 2770893f133aSTudor Ambarus "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p, 2771893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1), 2772*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI2_USI_USER, 2773893f133aSTudor Ambarus "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p, 2774893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1), 2775*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI3_USI_USER, 2776893f133aSTudor Ambarus "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p, 2777893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1), 2778*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI4_USI_USER, 2779893f133aSTudor Ambarus "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p, 2780893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1), 2781*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI5_USI_USER, 2782893f133aSTudor Ambarus "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p, 2783893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1), 2784*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI6_USI_USER, 2785893f133aSTudor Ambarus "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p, 2786893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1), 2787*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI7_USI_USER, 2788893f133aSTudor Ambarus "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p, 2789893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1), 2790*7b54d911STudor Ambarus nMUX(CLK_MOUT_PERIC0_USI8_USI_USER, 2791893f133aSTudor Ambarus "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p, 2792893f133aSTudor Ambarus PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1), 2793893f133aSTudor Ambarus }; 2794893f133aSTudor Ambarus 2795893f133aSTudor Ambarus static const struct samsung_div_clock peric0_div_clks[] __initconst = { 2796893f133aSTudor Ambarus DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user", 2797893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4), 2798893f133aSTudor Ambarus DIV(CLK_DOUT_PERIC0_USI0_UART, 2799893f133aSTudor Ambarus "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user", 2800893f133aSTudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4), 2801*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI14_USI, 2802893f133aSTudor Ambarus "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user", 2803*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4, 2804*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2805*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI1_USI, 2806893f133aSTudor Ambarus "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user", 2807*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4, 2808*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2809*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI2_USI, 2810893f133aSTudor Ambarus "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user", 2811*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4, 2812*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2813*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI3_USI, 2814893f133aSTudor Ambarus "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user", 2815*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4, 2816*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2817*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI4_USI, 2818893f133aSTudor Ambarus "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user", 2819*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4, 2820*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2821*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI5_USI, 2822893f133aSTudor Ambarus "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user", 2823*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4, 2824*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2825*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI6_USI, 2826893f133aSTudor Ambarus "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user", 2827*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4, 2828*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2829*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI7_USI, 2830893f133aSTudor Ambarus "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user", 2831*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4, 2832*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2833*7b54d911STudor Ambarus DIV_F(CLK_DOUT_PERIC0_USI8_USI, 2834893f133aSTudor Ambarus "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user", 2835*7b54d911STudor Ambarus CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4, 2836*7b54d911STudor Ambarus CLK_SET_RATE_PARENT, 0), 2837893f133aSTudor Ambarus }; 2838893f133aSTudor Ambarus 2839893f133aSTudor Ambarus static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { 2840893f133aSTudor Ambarus /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2841893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK, 2842893f133aSTudor Ambarus "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user", 2843893f133aSTudor Ambarus CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 2844893f133aSTudor Ambarus 21, CLK_IS_CRITICAL, 0), 2845893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK, 2846893f133aSTudor Ambarus "gout_peric0_clk_peric0_oscclk_clk", "oscclk", 2847893f133aSTudor Ambarus CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 2848893f133aSTudor Ambarus 21, 0, 0), 2849893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK, 2850893f133aSTudor Ambarus "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user", 2851893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 2852893f133aSTudor Ambarus 21, 0, 0), 2853893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK, 2854893f133aSTudor Ambarus "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user", 2855893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 2856893f133aSTudor Ambarus 21, 0, 0), 2857893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK, 2858893f133aSTudor Ambarus "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user", 2859893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 28608a96d270SAndré Draszik 21, CLK_IGNORE_UNUSED, 0), 2861893f133aSTudor Ambarus /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2862893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK, 2863893f133aSTudor Ambarus "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user", 2864893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 2865893f133aSTudor Ambarus 21, CLK_IS_CRITICAL, 0), 2866893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0, 2867893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi", 2868893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0, 2869*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 2870893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1, 2871893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi", 2872893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1, 2873*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 2874893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10, 2875893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c", 2876893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10, 2877893f133aSTudor Ambarus 21, 0, 0), 2878893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11, 2879893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c", 2880893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11, 2881893f133aSTudor Ambarus 21, 0, 0), 2882893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12, 2883893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c", 2884893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12, 2885893f133aSTudor Ambarus 21, 0, 0), 2886893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13, 2887893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c", 2888893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13, 2889893f133aSTudor Ambarus 21, 0, 0), 2890893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14, 2891893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c", 2892893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14, 2893893f133aSTudor Ambarus 21, 0, 0), 2894893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15, 2895893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c", 2896893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15, 2897893f133aSTudor Ambarus 21, 0, 0), 2898893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2, 2899893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi", 2900893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2, 2901*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 2902893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3, 2903893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi", 2904893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3, 2905*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 2906893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4, 2907893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi", 2908893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4, 2909*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 2910893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5, 2911893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi", 2912893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5, 2913*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 2914893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6, 2915893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi", 2916893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6, 2917*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 2918893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7, 2919893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi", 2920893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7, 2921*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 2922893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8, 2923893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c", 2924893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8, 2925893f133aSTudor Ambarus 21, 0, 0), 2926893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9, 2927893f133aSTudor Ambarus "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c", 2928893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9, 2929893f133aSTudor Ambarus 21, 0, 0), 2930893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0, 2931893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user", 2932893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0, 2933893f133aSTudor Ambarus 21, 0, 0), 2934893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1, 2935893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user", 2936893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1, 2937893f133aSTudor Ambarus 21, 0, 0), 2938893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10, 2939893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user", 2940893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10, 2941893f133aSTudor Ambarus 21, 0, 0), 2942893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11, 2943893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user", 2944893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11, 2945893f133aSTudor Ambarus 21, 0, 0), 2946893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12, 2947893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user", 2948893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12, 2949893f133aSTudor Ambarus 21, 0, 0), 2950893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13, 2951893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user", 2952893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13, 2953893f133aSTudor Ambarus 21, 0, 0), 2954893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14, 2955893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user", 2956893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14, 2957893f133aSTudor Ambarus 21, 0, 0), 2958893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15, 2959893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user", 2960893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15, 2961893f133aSTudor Ambarus 21, 0, 0), 2962893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2, 2963893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user", 2964893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2, 2965893f133aSTudor Ambarus 21, 0, 0), 2966893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3, 2967893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user", 2968893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3, 2969893f133aSTudor Ambarus 21, 0, 0), 2970893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4, 2971893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user", 2972893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4, 2973893f133aSTudor Ambarus 21, 0, 0), 2974893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5, 2975893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user", 2976893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5, 2977893f133aSTudor Ambarus 21, 0, 0), 2978893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6, 2979893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user", 2980893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6, 2981893f133aSTudor Ambarus 21, 0, 0), 2982893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7, 2983893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user", 2984893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7, 2985893f133aSTudor Ambarus 21, 0, 0), 2986893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8, 2987893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user", 2988893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8, 2989893f133aSTudor Ambarus 21, 0, 0), 2990893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9, 2991893f133aSTudor Ambarus "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user", 2992893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9, 2993893f133aSTudor Ambarus 21, 0, 0), 2994893f133aSTudor Ambarus /* Disabling this clock makes the system hang. Mark the clock as critical. */ 2995893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0, 2996893f133aSTudor Ambarus "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart", 2997893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0, 2998893f133aSTudor Ambarus 21, CLK_IS_CRITICAL, 0), 2999893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2, 3000893f133aSTudor Ambarus "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi", 3001893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2, 3002*7b54d911STudor Ambarus 21, CLK_SET_RATE_PARENT, 0), 3003893f133aSTudor Ambarus /* Disabling this clock makes the system hang. Mark the clock as critical. */ 3004893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0, 3005893f133aSTudor Ambarus "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user", 3006893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0, 3007893f133aSTudor Ambarus 21, CLK_IS_CRITICAL, 0), 3008893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2, 3009893f133aSTudor Ambarus "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user", 3010893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2, 3011893f133aSTudor Ambarus 21, 0, 0), 3012893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK, 3013893f133aSTudor Ambarus "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user", 3014893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 3015893f133aSTudor Ambarus 21, 0, 0), 3016893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK, 3017893f133aSTudor Ambarus "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c", 3018893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 3019893f133aSTudor Ambarus 21, 0, 0), 3020893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK, 3021893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart", 3022893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 3023893f133aSTudor Ambarus 21, 0, 0), 3024893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK, 3025893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi", 3026893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 3027893f133aSTudor Ambarus 21, 0, 0), 3028893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK, 3029893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi", 3030893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 3031893f133aSTudor Ambarus 21, 0, 0), 3032893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK, 3033893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi", 3034893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 3035893f133aSTudor Ambarus 21, 0, 0), 3036893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK, 3037893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi", 3038893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 3039893f133aSTudor Ambarus 21, 0, 0), 3040893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK, 3041893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi", 3042893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 3043893f133aSTudor Ambarus 21, 0, 0), 3044893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK, 3045893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi", 3046893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 3047893f133aSTudor Ambarus 21, 0, 0), 3048893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK, 3049893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi", 3050893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 3051893f133aSTudor Ambarus 21, 0, 0), 3052893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK, 3053893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi", 3054893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 3055893f133aSTudor Ambarus 21, 0, 0), 3056893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK, 3057893f133aSTudor Ambarus "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi", 3058893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 3059893f133aSTudor Ambarus 21, 0, 0), 3060893f133aSTudor Ambarus GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK, 3061893f133aSTudor Ambarus "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user", 3062893f133aSTudor Ambarus CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 3063893f133aSTudor Ambarus 21, 0, 0), 3064893f133aSTudor Ambarus }; 3065893f133aSTudor Ambarus 3066893f133aSTudor Ambarus static const struct samsung_cmu_info peric0_cmu_info __initconst = { 3067893f133aSTudor Ambarus .mux_clks = peric0_mux_clks, 3068893f133aSTudor Ambarus .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 3069893f133aSTudor Ambarus .div_clks = peric0_div_clks, 3070893f133aSTudor Ambarus .nr_div_clks = ARRAY_SIZE(peric0_div_clks), 3071893f133aSTudor Ambarus .gate_clks = peric0_gate_clks, 3072893f133aSTudor Ambarus .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 3073893f133aSTudor Ambarus .nr_clk_ids = CLKS_NR_PERIC0, 3074893f133aSTudor Ambarus .clk_regs = peric0_clk_regs, 3075893f133aSTudor Ambarus .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 3076893f133aSTudor Ambarus .clk_name = "bus", 3077893f133aSTudor Ambarus }; 3078893f133aSTudor Ambarus 30792999e786SAndré Draszik /* ---- CMU_PERIC1 ---------------------------------------------------------- */ 30802999e786SAndré Draszik 30812999e786SAndré Draszik /* Register Offset definitions for CMU_PERIC1 (0x10c00000) */ 30822999e786SAndré Draszik #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600 30832999e786SAndré Draszik #define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604 30842999e786SAndré Draszik #define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610 30852999e786SAndré Draszik #define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614 30862999e786SAndré Draszik #define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620 30872999e786SAndré Draszik #define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624 30882999e786SAndré Draszik #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630 30892999e786SAndré Draszik #define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634 30902999e786SAndré Draszik #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640 30912999e786SAndré Draszik #define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644 30922999e786SAndré Draszik #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650 30932999e786SAndré Draszik #define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654 30942999e786SAndré Draszik #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660 30952999e786SAndré Draszik #define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664 30962999e786SAndré Draszik #define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670 30972999e786SAndré Draszik #define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674 30982999e786SAndré Draszik #define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800 30992999e786SAndré Draszik #define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810 31002999e786SAndré Draszik #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 31012999e786SAndré Draszik #define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804 31022999e786SAndré Draszik #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 31032999e786SAndré Draszik #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c 31042999e786SAndré Draszik #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 31052999e786SAndré Draszik #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 31062999e786SAndré Draszik #define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818 31072999e786SAndré Draszik #define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000 31082999e786SAndré Draszik #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004 31092999e786SAndré Draszik #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008 31102999e786SAndré Draszik #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c 31112999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010 31122999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014 31132999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018 31142999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c 31152999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020 31162999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024 31172999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028 31182999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c 31192999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030 31202999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034 31212999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038 31222999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c 31232999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040 31242999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044 31252999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048 31262999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c 31272999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050 31282999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054 31292999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058 31302999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c 31312999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060 31322999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064 31332999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068 31342999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c 31352999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070 31362999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074 31372999e786SAndré Draszik #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078 31382999e786SAndré Draszik #define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000 31392999e786SAndré Draszik #define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004 31402999e786SAndré Draszik #define QCH_CON_D_TZPC_PERIC1_QCH 0x3008 31412999e786SAndré Draszik #define QCH_CON_GPC_PERIC1_QCH 0x300c 31422999e786SAndré Draszik #define QCH_CON_GPIO_PERIC1_QCH 0x3010 31432999e786SAndré Draszik #define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014 31442999e786SAndré Draszik #define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018 31452999e786SAndré Draszik #define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c 31462999e786SAndré Draszik #define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020 31472999e786SAndré Draszik #define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024 31482999e786SAndré Draszik #define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028 31492999e786SAndré Draszik #define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c 31502999e786SAndré Draszik #define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030 31512999e786SAndré Draszik #define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034 31522999e786SAndré Draszik #define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038 31532999e786SAndré Draszik #define QCH_CON_SYSREG_PERIC1_QCH 0x303c 31542999e786SAndré Draszik #define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00 31552999e786SAndré Draszik 31562999e786SAndré Draszik static const unsigned long peric1_clk_regs[] __initconst = { 31572999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 31582999e786SAndré Draszik PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER, 31592999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 31602999e786SAndré Draszik PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER, 31612999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 31622999e786SAndré Draszik PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER, 31632999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 31642999e786SAndré Draszik PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, 31652999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 31662999e786SAndré Draszik PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, 31672999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 31682999e786SAndré Draszik PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, 31692999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 31702999e786SAndré Draszik PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER, 31712999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 31722999e786SAndré Draszik PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER, 31732999e786SAndré Draszik PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 31742999e786SAndré Draszik CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0, 31752999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 31762999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 31772999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 31782999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 31792999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 31802999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 31812999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 31822999e786SAndré Draszik CLK_CON_BUF_CLKBUF_PERIC1_IP, 31832999e786SAndré Draszik CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 31842999e786SAndré Draszik CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 31852999e786SAndré Draszik CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 31862999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 31872999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 31882999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 31892999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 31902999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 31912999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 31922999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 31932999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 31942999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 31952999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 31962999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 31972999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 31982999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, 31992999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 32002999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 32012999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 32022999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 32032999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 32042999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 32052999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 32062999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 32072999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 32082999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 32092999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 32102999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 32112999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 32122999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 32132999e786SAndré Draszik DMYQCH_CON_PERIC1_TOP0_QCH_S, 32142999e786SAndré Draszik PCH_CON_LHM_AXI_P_PERIC1_PCH, 32152999e786SAndré Draszik QCH_CON_D_TZPC_PERIC1_QCH, 32162999e786SAndré Draszik QCH_CON_GPC_PERIC1_QCH, 32172999e786SAndré Draszik QCH_CON_GPIO_PERIC1_QCH, 32182999e786SAndré Draszik QCH_CON_LHM_AXI_P_PERIC1_QCH, 32192999e786SAndré Draszik QCH_CON_PERIC1_CMU_PERIC1_QCH, 32202999e786SAndré Draszik QCH_CON_PERIC1_TOP0_QCH_I3C0, 32212999e786SAndré Draszik QCH_CON_PERIC1_TOP0_QCH_PWM, 32222999e786SAndré Draszik QCH_CON_PERIC1_TOP0_QCH_USI0_USI, 32232999e786SAndré Draszik QCH_CON_PERIC1_TOP0_QCH_USI10_USI, 32242999e786SAndré Draszik QCH_CON_PERIC1_TOP0_QCH_USI11_USI, 32252999e786SAndré Draszik QCH_CON_PERIC1_TOP0_QCH_USI12_USI, 32262999e786SAndré Draszik QCH_CON_PERIC1_TOP0_QCH_USI13_USI, 32272999e786SAndré Draszik QCH_CON_PERIC1_TOP0_QCH_USI9_USI, 32282999e786SAndré Draszik QCH_CON_SYSREG_PERIC1_QCH, 32292999e786SAndré Draszik QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1, 32302999e786SAndré Draszik }; 32312999e786SAndré Draszik 32322999e786SAndré Draszik /* List of parent clocks for Muxes in CMU_PERIC1 */ 32332999e786SAndré Draszik PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" }; 32342999e786SAndré Draszik PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" }; 32352999e786SAndré Draszik 32362999e786SAndré Draszik static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { 32372999e786SAndré Draszik MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user", 32382999e786SAndré Draszik mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1), 32392999e786SAndré Draszik MUX(CLK_MOUT_PERIC1_I3C_USER, 32402999e786SAndré Draszik "mout_peric1_i3c_user", mout_peric1_nonbususer_p, 32412999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1), 32422999e786SAndré Draszik MUX(CLK_MOUT_PERIC1_USI0_USI_USER, 32432999e786SAndré Draszik "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p, 32442999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1), 32452999e786SAndré Draszik MUX(CLK_MOUT_PERIC1_USI10_USI_USER, 32462999e786SAndré Draszik "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p, 32472999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1), 32482999e786SAndré Draszik MUX(CLK_MOUT_PERIC1_USI11_USI_USER, 32492999e786SAndré Draszik "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p, 32502999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1), 32512999e786SAndré Draszik MUX(CLK_MOUT_PERIC1_USI12_USI_USER, 32522999e786SAndré Draszik "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p, 32532999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1), 32542999e786SAndré Draszik MUX(CLK_MOUT_PERIC1_USI13_USI_USER, 32552999e786SAndré Draszik "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p, 32562999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1), 32572999e786SAndré Draszik MUX(CLK_MOUT_PERIC1_USI9_USI_USER, 32582999e786SAndré Draszik "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p, 32592999e786SAndré Draszik PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1), 32602999e786SAndré Draszik }; 32612999e786SAndré Draszik 32622999e786SAndré Draszik static const struct samsung_div_clock peric1_div_clks[] __initconst = { 32632999e786SAndré Draszik DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user", 32642999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), 32652999e786SAndré Draszik DIV(CLK_DOUT_PERIC1_USI0_USI, 32662999e786SAndré Draszik "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user", 32672999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4), 32682999e786SAndré Draszik DIV(CLK_DOUT_PERIC1_USI10_USI, 32692999e786SAndré Draszik "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user", 32702999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4), 32712999e786SAndré Draszik DIV(CLK_DOUT_PERIC1_USI11_USI, 32722999e786SAndré Draszik "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user", 32732999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4), 32742999e786SAndré Draszik DIV(CLK_DOUT_PERIC1_USI12_USI, 32752999e786SAndré Draszik "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user", 32762999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4), 32772999e786SAndré Draszik DIV(CLK_DOUT_PERIC1_USI13_USI, 32782999e786SAndré Draszik "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user", 32792999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4), 32802999e786SAndré Draszik DIV(CLK_DOUT_PERIC1_USI9_USI, 32812999e786SAndré Draszik "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user", 32822999e786SAndré Draszik CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4), 32832999e786SAndré Draszik }; 32842999e786SAndré Draszik 32852999e786SAndré Draszik static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { 32862999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PCLK, 32872999e786SAndré Draszik "gout_peric1_peric1_pclk", "mout_peric1_bus_user", 32882999e786SAndré Draszik CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 32892999e786SAndré Draszik 21, CLK_IS_CRITICAL, 0), 32902999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK, 32912999e786SAndré Draszik "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c", 32922999e786SAndré Draszik CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 32932999e786SAndré Draszik 21, 0, 0), 32942999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK, 32952999e786SAndré Draszik "gout_peric1_clk_peric1_oscclk_clk", "oscclk", 32962999e786SAndré Draszik CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 32972999e786SAndré Draszik 21, 0, 0), 32982999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK, 32992999e786SAndré Draszik "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user", 33002999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 33012999e786SAndré Draszik 21, 0, 0), 33022999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK, 33032999e786SAndré Draszik "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user", 33042999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 33052999e786SAndré Draszik 21, 0, 0), 33062999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK, 33072999e786SAndré Draszik "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user", 33082999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 33092999e786SAndré Draszik 21, CLK_IGNORE_UNUSED, 0), 33102999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK, 33112999e786SAndré Draszik "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user", 33122999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 33132999e786SAndré Draszik 21, CLK_IS_CRITICAL, 0), 33142999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1, 33152999e786SAndré Draszik "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi", 33162999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1, 33172999e786SAndré Draszik 21, 0, 0), 33182999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2, 33192999e786SAndré Draszik "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi", 33202999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2, 33212999e786SAndré Draszik 21, 0, 0), 33222999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3, 33232999e786SAndré Draszik "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi", 33242999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3, 33252999e786SAndré Draszik 21, 0, 0), 33262999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4, 33272999e786SAndré Draszik "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi", 33282999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4, 33292999e786SAndré Draszik 21, 0, 0), 33302999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5, 33312999e786SAndré Draszik "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi", 33322999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5, 33332999e786SAndré Draszik 21, 0, 0), 33342999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6, 33352999e786SAndré Draszik "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi", 33362999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6, 33372999e786SAndré Draszik 21, 0, 0), 33382999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8, 33392999e786SAndré Draszik "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c", 33402999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8, 33412999e786SAndré Draszik 21, 0, 0), 33422999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1, 33432999e786SAndré Draszik "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user", 33442999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1, 33452999e786SAndré Draszik 21, 0, 0), 33462999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15, 33472999e786SAndré Draszik "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user", 33482999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15, 33492999e786SAndré Draszik 21, 0, 0), 33502999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2, 33512999e786SAndré Draszik "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user", 33522999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2, 33532999e786SAndré Draszik 21, 0, 0), 33542999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3, 33552999e786SAndré Draszik "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user", 33562999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3, 33572999e786SAndré Draszik 21, 0, 0), 33582999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4, 33592999e786SAndré Draszik "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user", 33602999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4, 33612999e786SAndré Draszik 21, 0, 0), 33622999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5, 33632999e786SAndré Draszik "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user", 33642999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5, 33652999e786SAndré Draszik 21, 0, 0), 33662999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6, 33672999e786SAndré Draszik "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user", 33682999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6, 33692999e786SAndré Draszik 21, 0, 0), 33702999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8, 33712999e786SAndré Draszik "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user", 33722999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8, 33732999e786SAndré Draszik 21, 0, 0), 33742999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK, 33752999e786SAndré Draszik "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user", 33762999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 33772999e786SAndré Draszik 21, 0, 0), 33782999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK, 33792999e786SAndré Draszik "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi", 33802999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 33812999e786SAndré Draszik 21, 0, 0), 33822999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK, 33832999e786SAndré Draszik "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi", 33842999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 33852999e786SAndré Draszik 21, 0, 0), 33862999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK, 33872999e786SAndré Draszik "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi", 33882999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 33892999e786SAndré Draszik 21, 0, 0), 33902999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK, 33912999e786SAndré Draszik "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi", 33922999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 33932999e786SAndré Draszik 21, 0, 0), 33942999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK, 33952999e786SAndré Draszik "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi", 33962999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 33972999e786SAndré Draszik 21, 0, 0), 33982999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK, 33992999e786SAndré Draszik "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi", 34002999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 34012999e786SAndré Draszik 21, 0, 0), 34022999e786SAndré Draszik GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK, 34032999e786SAndré Draszik "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user", 34042999e786SAndré Draszik CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 34052999e786SAndré Draszik 21, 0, 0), 34062999e786SAndré Draszik }; 34072999e786SAndré Draszik 34082999e786SAndré Draszik static const struct samsung_cmu_info peric1_cmu_info __initconst = { 34092999e786SAndré Draszik .mux_clks = peric1_mux_clks, 34102999e786SAndré Draszik .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 34112999e786SAndré Draszik .div_clks = peric1_div_clks, 34122999e786SAndré Draszik .nr_div_clks = ARRAY_SIZE(peric1_div_clks), 34132999e786SAndré Draszik .gate_clks = peric1_gate_clks, 34142999e786SAndré Draszik .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 34152999e786SAndré Draszik .nr_clk_ids = CLKS_NR_PERIC1, 34162999e786SAndré Draszik .clk_regs = peric1_clk_regs, 34172999e786SAndré Draszik .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 34182999e786SAndré Draszik .clk_name = "bus", 34192999e786SAndré Draszik }; 34202999e786SAndré Draszik 34212c597bb7SPeter Griffin /* ---- platform_driver ----------------------------------------------------- */ 34222c597bb7SPeter Griffin 34232c597bb7SPeter Griffin static int __init gs101_cmu_probe(struct platform_device *pdev) 34242c597bb7SPeter Griffin { 34252c597bb7SPeter Griffin const struct samsung_cmu_info *info; 34262c597bb7SPeter Griffin struct device *dev = &pdev->dev; 34272c597bb7SPeter Griffin 34282c597bb7SPeter Griffin info = of_device_get_match_data(dev); 34292c597bb7SPeter Griffin exynos_arm64_register_cmu(dev, dev->of_node, info); 34302c597bb7SPeter Griffin 34312c597bb7SPeter Griffin return 0; 34322c597bb7SPeter Griffin } 34332c597bb7SPeter Griffin 34342c597bb7SPeter Griffin static const struct of_device_id gs101_cmu_of_match[] = { 34352c597bb7SPeter Griffin { 34362c597bb7SPeter Griffin .compatible = "google,gs101-cmu-apm", 34372c597bb7SPeter Griffin .data = &apm_cmu_info, 34382c597bb7SPeter Griffin }, { 3439893f133aSTudor Ambarus .compatible = "google,gs101-cmu-peric0", 3440893f133aSTudor Ambarus .data = &peric0_cmu_info, 3441893f133aSTudor Ambarus }, { 34422999e786SAndré Draszik .compatible = "google,gs101-cmu-peric1", 34432999e786SAndré Draszik .data = &peric1_cmu_info, 34442999e786SAndré Draszik }, { 34452c597bb7SPeter Griffin }, 34462c597bb7SPeter Griffin }; 34472c597bb7SPeter Griffin 34482c597bb7SPeter Griffin static struct platform_driver gs101_cmu_driver __refdata = { 34492c597bb7SPeter Griffin .driver = { 34502c597bb7SPeter Griffin .name = "gs101-cmu", 34512c597bb7SPeter Griffin .of_match_table = gs101_cmu_of_match, 34522c597bb7SPeter Griffin .suppress_bind_attrs = true, 34532c597bb7SPeter Griffin }, 34542c597bb7SPeter Griffin .probe = gs101_cmu_probe, 34552c597bb7SPeter Griffin }; 34562c597bb7SPeter Griffin 34572c597bb7SPeter Griffin static int __init gs101_cmu_init(void) 34582c597bb7SPeter Griffin { 34592c597bb7SPeter Griffin return platform_driver_register(&gs101_cmu_driver); 34602c597bb7SPeter Griffin } 34612c597bb7SPeter Griffin core_initcall(gs101_cmu_init); 3462