1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 4 * https://www.samsung.com 5 * Copyright (c) 2017-2022 Tesla, Inc. 6 * https://www.tesla.com 7 * 8 * Common Clock Framework support for FSD SoC. 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 17 #include <dt-bindings/clock/fsd-clk.h> 18 19 #include "clk.h" 20 #include "clk-exynos-arm64.h" 21 22 /* Register Offset definitions for CMU_CMU (0x11c10000) */ 23 #define PLL_LOCKTIME_PLL_SHARED0 0x0 24 #define PLL_LOCKTIME_PLL_SHARED1 0x4 25 #define PLL_LOCKTIME_PLL_SHARED2 0x8 26 #define PLL_LOCKTIME_PLL_SHARED3 0xc 27 #define PLL_CON0_PLL_SHARED0 0x100 28 #define PLL_CON0_PLL_SHARED1 0x120 29 #define PLL_CON0_PLL_SHARED2 0x140 30 #define PLL_CON0_PLL_SHARED3 0x160 31 #define MUX_CMU_CIS0_CLKMUX 0x1000 32 #define MUX_CMU_CIS1_CLKMUX 0x1004 33 #define MUX_CMU_CIS2_CLKMUX 0x1008 34 #define MUX_CMU_CPUCL_SWITCHMUX 0x100c 35 #define MUX_CMU_FSYS1_ACLK_MUX 0x1014 36 #define MUX_PLL_SHARED0_MUX 0x1020 37 #define MUX_PLL_SHARED1_MUX 0x1024 38 #define DIV_CMU_CIS0_CLK 0x1800 39 #define DIV_CMU_CIS1_CLK 0x1804 40 #define DIV_CMU_CIS2_CLK 0x1808 41 #define DIV_CMU_CMU_ACLK 0x180c 42 #define DIV_CMU_CPUCL_SWITCH 0x1810 43 #define DIV_CMU_FSYS0_SHARED0DIV4 0x181c 44 #define DIV_CMU_FSYS0_SHARED1DIV3 0x1820 45 #define DIV_CMU_FSYS0_SHARED1DIV4 0x1824 46 #define DIV_CMU_FSYS1_SHARED0DIV4 0x1828 47 #define DIV_CMU_FSYS1_SHARED0DIV8 0x182c 48 #define DIV_CMU_IMEM_ACLK 0x1834 49 #define DIV_CMU_IMEM_DMACLK 0x1838 50 #define DIV_CMU_IMEM_TCUCLK 0x183c 51 #define DIV_CMU_PERIC_SHARED0DIV20 0x1844 52 #define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848 53 #define DIV_CMU_PERIC_SHARED1DIV36 0x184c 54 #define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850 55 #define DIV_PLL_SHARED0_DIV2 0x1858 56 #define DIV_PLL_SHARED0_DIV3 0x185c 57 #define DIV_PLL_SHARED0_DIV4 0x1860 58 #define DIV_PLL_SHARED0_DIV6 0x1864 59 #define DIV_PLL_SHARED1_DIV3 0x1868 60 #define DIV_PLL_SHARED1_DIV36 0x186c 61 #define DIV_PLL_SHARED1_DIV4 0x1870 62 #define DIV_PLL_SHARED1_DIV9 0x1874 63 #define GAT_CMU_CIS0_CLKGATE 0x2000 64 #define GAT_CMU_CIS1_CLKGATE 0x2004 65 #define GAT_CMU_CIS2_CLKGATE 0x2008 66 #define GAT_CMU_CPUCL_SWITCH_GATE 0x200c 67 #define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018 68 #define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c 69 #define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020 70 #define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024 71 #define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028 72 #define GAT_CMU_IMEM_ACLK_GATE 0x2030 73 #define GAT_CMU_IMEM_DMACLK_GATE 0x2034 74 #define GAT_CMU_IMEM_TCUCLK_GATE 0x2038 75 #define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040 76 #define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044 77 #define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048 78 #define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c 79 #define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054 80 #define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058 81 #define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c 82 #define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060 83 84 /* NOTE: Must be equal to the last clock ID increased by one */ 85 #define CLKS_NR_CMU (GAT_CMU_FSYS0_SHARED0DIV4 + 1) 86 #define CLKS_NR_PERIC (PERIC_DOUT_RGMII_CLK + 1) 87 #define CLKS_NR_FSYS0 (FSYS0_DOUT_FSYS0_PERIBUS_GRP + 1) 88 #define CLKS_NR_FSYS1 (PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1) 89 #define CLKS_NR_IMEM (IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1) 90 #define CLKS_NR_MFC (MFC_MFC_IPCLKPORT_ACLK + 1) 91 #define CLKS_NR_CAM_CSI (CAM_CSI2_3_IPCLKPORT_I_PCLK + 1) 92 93 static const unsigned long cmu_clk_regs[] __initconst = { 94 PLL_LOCKTIME_PLL_SHARED0, 95 PLL_LOCKTIME_PLL_SHARED1, 96 PLL_LOCKTIME_PLL_SHARED2, 97 PLL_LOCKTIME_PLL_SHARED3, 98 PLL_CON0_PLL_SHARED0, 99 PLL_CON0_PLL_SHARED1, 100 PLL_CON0_PLL_SHARED2, 101 PLL_CON0_PLL_SHARED3, 102 MUX_CMU_CIS0_CLKMUX, 103 MUX_CMU_CIS1_CLKMUX, 104 MUX_CMU_CIS2_CLKMUX, 105 MUX_CMU_CPUCL_SWITCHMUX, 106 MUX_CMU_FSYS1_ACLK_MUX, 107 MUX_PLL_SHARED0_MUX, 108 MUX_PLL_SHARED1_MUX, 109 DIV_CMU_CIS0_CLK, 110 DIV_CMU_CIS1_CLK, 111 DIV_CMU_CIS2_CLK, 112 DIV_CMU_CMU_ACLK, 113 DIV_CMU_CPUCL_SWITCH, 114 DIV_CMU_FSYS0_SHARED0DIV4, 115 DIV_CMU_FSYS0_SHARED1DIV3, 116 DIV_CMU_FSYS0_SHARED1DIV4, 117 DIV_CMU_FSYS1_SHARED0DIV4, 118 DIV_CMU_FSYS1_SHARED0DIV8, 119 DIV_CMU_IMEM_ACLK, 120 DIV_CMU_IMEM_DMACLK, 121 DIV_CMU_IMEM_TCUCLK, 122 DIV_CMU_PERIC_SHARED0DIV20, 123 DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 124 DIV_CMU_PERIC_SHARED1DIV36, 125 DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 126 DIV_PLL_SHARED0_DIV2, 127 DIV_PLL_SHARED0_DIV3, 128 DIV_PLL_SHARED0_DIV4, 129 DIV_PLL_SHARED0_DIV6, 130 DIV_PLL_SHARED1_DIV3, 131 DIV_PLL_SHARED1_DIV36, 132 DIV_PLL_SHARED1_DIV4, 133 DIV_PLL_SHARED1_DIV9, 134 GAT_CMU_CIS0_CLKGATE, 135 GAT_CMU_CIS1_CLKGATE, 136 GAT_CMU_CIS2_CLKGATE, 137 GAT_CMU_CPUCL_SWITCH_GATE, 138 GAT_CMU_FSYS0_SHARED0DIV4_GATE, 139 GAT_CMU_FSYS0_SHARED1DIV4_CLK, 140 GAT_CMU_FSYS0_SHARED1DIV4_GATE, 141 GAT_CMU_FSYS1_SHARED0DIV4_GATE, 142 GAT_CMU_FSYS1_SHARED1DIV4_GATE, 143 GAT_CMU_IMEM_ACLK_GATE, 144 GAT_CMU_IMEM_DMACLK_GATE, 145 GAT_CMU_IMEM_TCUCLK_GATE, 146 GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 147 GAT_CMU_PERIC_SHARED0DIVE4_GATE, 148 GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 149 GAT_CMU_PERIC_SHARED1DIVE4_GATE, 150 GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 151 GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 152 GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 153 GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 154 }; 155 156 static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = { 157 PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0), 158 }; 159 160 static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = { 161 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0), 162 }; 163 164 static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = { 165 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0), 166 }; 167 168 static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = { 169 PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0), 170 }; 171 172 static const struct samsung_pll_clock cmu_pll_clks[] __initconst = { 173 PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0, 174 PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), 175 PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1, 176 PLL_CON0_PLL_SHARED1, pll_shared1_rate_table), 177 PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2, 178 PLL_CON0_PLL_SHARED2, pll_shared2_rate_table), 179 PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3, 180 PLL_CON0_PLL_SHARED3, pll_shared3_rate_table), 181 }; 182 183 /* List of parent clocks for Muxes in CMU_CMU */ 184 PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" }; 185 PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" }; 186 PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" }; 187 PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" }; 188 PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 189 PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 190 PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 191 PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" }; 192 PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" }; 193 PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" }; 194 PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" }; 195 196 static const struct samsung_mux_clock cmu_mux_clks[] __initconst = { 197 MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1), 198 MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1), 199 MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1), 200 MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1), 201 MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1), 202 MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1), 203 MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1), 204 MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p, 205 MUX_CMU_CPUCL_SWITCHMUX, 0, 1), 206 MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1), 207 MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1), 208 MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1), 209 }; 210 211 static const struct samsung_div_clock cmu_div_clks[] __initconst = { 212 DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4), 213 DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4), 214 DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4), 215 DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4), 216 DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4), 217 DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate", 218 DIV_CMU_FSYS0_SHARED0DIV4, 0, 4), 219 DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk", 220 DIV_CMU_FSYS0_SHARED1DIV3, 0, 4), 221 DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate", 222 DIV_CMU_FSYS0_SHARED1DIV4, 0, 4), 223 DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate", 224 DIV_CMU_FSYS1_SHARED0DIV4, 0, 4), 225 DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate", 226 DIV_CMU_FSYS1_SHARED0DIV8, 0, 4), 227 DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate", 228 DIV_CMU_IMEM_ACLK, 0, 4), 229 DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate", 230 DIV_CMU_IMEM_DMACLK, 0, 4), 231 DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate", 232 DIV_CMU_IMEM_TCUCLK, 0, 4), 233 DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20", 234 "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4), 235 DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk", 236 "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4), 237 DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36", 238 "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4), 239 DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk", 240 "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4), 241 DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux", 242 DIV_PLL_SHARED0_DIV2, 0, 4), 243 DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux", 244 DIV_PLL_SHARED0_DIV3, 0, 4), 245 DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2", 246 DIV_PLL_SHARED0_DIV4, 0, 4), 247 DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3", 248 DIV_PLL_SHARED0_DIV6, 0, 4), 249 DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux", 250 DIV_PLL_SHARED1_DIV3, 0, 4), 251 DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9", 252 DIV_PLL_SHARED1_DIV36, 0, 4), 253 DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux", 254 DIV_PLL_SHARED1_DIV4, 0, 4), 255 DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3", 256 DIV_PLL_SHARED1_DIV9, 0, 4), 257 }; 258 259 static const struct samsung_gate_clock cmu_gate_clks[] __initconst = { 260 GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21, 261 CLK_IGNORE_UNUSED, 0), 262 GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21, 263 CLK_IGNORE_UNUSED, 0), 264 GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21, 265 CLK_IGNORE_UNUSED, 0), 266 GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux", 267 GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0), 268 GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4", 269 GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 270 GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3", 271 GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0), 272 GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4", 273 GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 274 GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux", 275 GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 276 GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4", 277 GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 278 GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21, 279 CLK_IGNORE_UNUSED, 0), 280 GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21, 281 CLK_IGNORE_UNUSED, 0), 282 GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21, 283 CLK_IGNORE_UNUSED, 0), 284 GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3", 285 GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0), 286 GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4", 287 GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), 288 GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4", 289 GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0), 290 GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36", 291 GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), 292 GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", 293 GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 294 GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk", 295 GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 296 GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk", 297 GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0), 298 GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", 299 GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 300 }; 301 302 static const struct samsung_cmu_info cmu_cmu_info __initconst = { 303 .pll_clks = cmu_pll_clks, 304 .nr_pll_clks = ARRAY_SIZE(cmu_pll_clks), 305 .mux_clks = cmu_mux_clks, 306 .nr_mux_clks = ARRAY_SIZE(cmu_mux_clks), 307 .div_clks = cmu_div_clks, 308 .nr_div_clks = ARRAY_SIZE(cmu_div_clks), 309 .gate_clks = cmu_gate_clks, 310 .nr_gate_clks = ARRAY_SIZE(cmu_gate_clks), 311 .nr_clk_ids = CLKS_NR_CMU, 312 .clk_regs = cmu_clk_regs, 313 .nr_clk_regs = ARRAY_SIZE(cmu_clk_regs), 314 }; 315 316 static void __init fsd_clk_cmu_init(struct device_node *np) 317 { 318 samsung_cmu_register_one(np, &cmu_cmu_info); 319 } 320 321 CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init); 322 323 /* Register Offset definitions for CMU_PERIC (0x14010000) */ 324 #define PLL_CON0_PERIC_DMACLK_MUX 0x100 325 #define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120 326 #define PLL_CON0_PERIC_PCLK_MUX 0x140 327 #define PLL_CON0_PERIC_TBUCLK_MUX 0x160 328 #define PLL_CON0_SPI_CLK 0x180 329 #define PLL_CON0_SPI_PCLK 0x1a0 330 #define PLL_CON0_UART_CLK 0x1c0 331 #define PLL_CON0_UART_PCLK 0x1e0 332 #define MUX_PERIC_EQOS_PHYRXCLK 0x1000 333 #define DIV_EQOS_BUSCLK 0x1800 334 #define DIV_PERIC_MCAN_CLK 0x1804 335 #define DIV_RGMII_CLK 0x1808 336 #define DIV_RII_CLK 0x180c 337 #define DIV_RMII_CLK 0x1810 338 #define DIV_SPI_CLK 0x1814 339 #define DIV_UART_CLK 0x1818 340 #define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000 341 #define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004 342 #define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008 343 #define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c 344 #define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010 345 #define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014 346 #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018 347 #define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c 348 #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020 349 #define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024 350 #define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028 351 #define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c 352 #define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030 353 #define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034 354 #define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038 355 #define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c 356 #define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040 357 #define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044 358 #define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048 359 #define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c 360 #define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050 361 #define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054 362 #define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058 363 #define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c 364 #define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060 365 #define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064 366 #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068 367 #define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c 368 #define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070 369 #define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074 370 #define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078 371 #define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c 372 #define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080 373 #define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084 374 #define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088 375 #define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c 376 #define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090 377 #define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094 378 #define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098 379 #define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c 380 #define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0 381 #define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4 382 #define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8 383 #define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac 384 #define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0 385 #define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4 386 #define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8 387 #define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc 388 #define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0 389 #define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4 390 #define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8 391 #define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc 392 #define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0 393 #define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4 394 #define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8 395 #define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc 396 #define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0 397 #define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4 398 #define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8 399 #define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec 400 #define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0 401 #define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4 402 #define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8 403 #define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc 404 #define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100 405 #define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104 406 407 static const unsigned long peric_clk_regs[] __initconst = { 408 PLL_CON0_PERIC_DMACLK_MUX, 409 PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 410 PLL_CON0_PERIC_PCLK_MUX, 411 PLL_CON0_PERIC_TBUCLK_MUX, 412 PLL_CON0_SPI_CLK, 413 PLL_CON0_SPI_PCLK, 414 PLL_CON0_UART_CLK, 415 PLL_CON0_UART_PCLK, 416 MUX_PERIC_EQOS_PHYRXCLK, 417 DIV_EQOS_BUSCLK, 418 DIV_PERIC_MCAN_CLK, 419 DIV_RGMII_CLK, 420 DIV_RII_CLK, 421 DIV_RMII_CLK, 422 DIV_SPI_CLK, 423 DIV_UART_CLK, 424 GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 425 GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, 426 GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 427 GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 428 GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 429 GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 430 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 431 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 432 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 433 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 434 GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 435 GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 436 GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 437 GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 438 GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 439 GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 440 GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 441 GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 442 GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 443 GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 444 GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 445 GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 446 GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 447 GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 448 GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 449 GAT_GPIO_PERIC_IPCLKPORT_PCLK, 450 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 451 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 452 GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 453 GAT_PERIC_DMA0_IPCLKPORT_ACLK, 454 GAT_PERIC_DMA1_IPCLKPORT_ACLK, 455 GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 456 GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 457 GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 458 GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 459 GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 460 GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 461 GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 462 GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 463 GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 464 GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 465 GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 466 GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 467 GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 468 GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 469 GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 470 GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 471 GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 472 GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 473 GAT_PERIC_SMMU_IPCLKPORT_CCLK, 474 GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 475 GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 476 GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 477 GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 478 GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 479 GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 480 GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 481 GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 482 GAT_PERIC_TDM0_IPCLKPORT_PCLK, 483 GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 484 GAT_PERIC_TDM1_IPCLKPORT_PCLK, 485 GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 486 GAT_PERIC_UART0_IPCLKPORT_PCLK, 487 GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 488 GAT_PERIC_UART1_IPCLKPORT_PCLK, 489 GAT_SYSREG_PERI_IPCLKPORT_PCLK, 490 }; 491 492 static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = { 493 FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000), 494 }; 495 496 /* List of parent clocks for Muxes in CMU_PERIC */ 497 PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" }; 498 PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; 499 PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 500 PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" }; 501 PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" }; 502 PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 503 PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" }; 504 PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; 505 PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" }; 506 507 static const struct samsung_mux_clock peric_mux_clks[] __initconst = { 508 MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1), 509 MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p, 510 PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1), 511 MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1), 512 MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1), 513 MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1), 514 MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1), 515 MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1), 516 MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1), 517 MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p, 518 MUX_PERIC_EQOS_PHYRXCLK, 0, 1), 519 }; 520 521 static const struct samsung_div_clock peric_div_clks[] __initconst = { 522 DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4), 523 DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4), 524 DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk", 525 DIV_RGMII_CLK, 0, 4), 526 DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4), 527 DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4), 528 DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6), 529 DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6), 530 }; 531 532 static const struct samsung_gate_clock peric_gate_clks[] __initconst = { 533 GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i", 534 "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), 535 GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, 536 21, CLK_IGNORE_UNUSED, 0), 537 GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll", 538 GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 539 GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk", 540 GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 541 GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21, 542 CLK_IGNORE_UNUSED, 0), 543 GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21, 544 CLK_IGNORE_UNUSED, 0), 545 GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk", 546 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 547 GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk", 548 GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 549 GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk", 550 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 551 GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk", 552 GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 553 GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk", 554 GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 555 GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk", 556 GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 557 GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk", 558 GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 559 GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk", 560 GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0), 561 GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk", 562 "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), 563 GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk", 564 GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 565 GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk", 566 "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), 567 GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk", 568 GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 569 GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk", 570 GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0), 571 GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i", 572 "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0), 573 GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i", 574 "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0), 575 GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i", 576 "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0), 577 GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i", 578 "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 579 GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk", 580 GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 581 GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk", 582 GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 583 GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk", 584 GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 585 GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk", 586 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0), 587 GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk", 588 GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0), 589 GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk", 590 GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 591 GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk", 592 GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 593 GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk", 594 GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 595 GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk", 596 GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 597 GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk", 598 GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 599 GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk", 600 GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 601 GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk", 602 GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 603 GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk", 604 GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 605 GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk", 606 GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 607 GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk", 608 GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 609 GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk", 610 GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 611 GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk", 612 GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 613 GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk", 614 GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 615 GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk", 616 GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 617 GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk", 618 GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 619 GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk", 620 GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 621 GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk", 622 GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 623 GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk", 624 GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 625 GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk", 626 GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 627 GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk", 628 GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 629 GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk", 630 GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), 631 GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk", 632 GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 633 GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk", 634 GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0), 635 GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk", 636 GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 637 GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 638 GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 639 GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk", 640 GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 641 GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 642 GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 643 GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk", 644 GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 645 GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk", 646 GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), 647 GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk", 648 GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), 649 GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk", 650 GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 651 GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk", 652 GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), 653 GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk", 654 GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 655 GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk", 656 GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), 657 GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk", 658 GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 659 GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk", 660 GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), 661 GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk", 662 GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 663 GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk", 664 GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 665 }; 666 667 static const struct samsung_cmu_info peric_cmu_info __initconst = { 668 .mux_clks = peric_mux_clks, 669 .nr_mux_clks = ARRAY_SIZE(peric_mux_clks), 670 .div_clks = peric_div_clks, 671 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 672 .gate_clks = peric_gate_clks, 673 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 674 .fixed_clks = peric_fixed_clks, 675 .nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks), 676 .nr_clk_ids = CLKS_NR_PERIC, 677 .clk_regs = peric_clk_regs, 678 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 679 .clk_name = "dout_cmu_pll_shared0_div4", 680 }; 681 682 /* Register Offset definitions for CMU_FSYS0 (0x15010000) */ 683 #define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100 684 #define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140 685 #define PLL_CON0_EQOS_RGMII_125_MUX1 0x160 686 #define DIV_CLK_UNIPRO 0x1800 687 #define DIV_EQS_RGMII_CLK_125 0x1804 688 #define DIV_PERIBUS_GRP 0x1808 689 #define DIV_EQOS_RII_CLK2O5 0x180c 690 #define DIV_EQOS_RMIICLK_25 0x1810 691 #define DIV_PCIE_PHY_OSCCLK 0x1814 692 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004 693 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008 694 #define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c 695 #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010 696 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014 697 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018 698 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c 699 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020 700 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024 701 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028 702 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c 703 #define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038 704 #define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c 705 #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040 706 #define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044 707 #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048 708 #define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c 709 #define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050 710 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054 711 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058 712 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c 713 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060 714 #define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064 715 #define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068 716 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c 717 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070 718 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074 719 #define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078 720 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c 721 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080 722 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084 723 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088 724 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c 725 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090 726 #define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094 727 #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098 728 #define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c 729 #define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0 730 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4 731 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8 732 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac 733 #define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0 734 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4 735 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8 736 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc 737 #define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0 738 #define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4 739 740 static const unsigned long fsys0_clk_regs[] __initconst = { 741 PLL_CON0_CLKCMU_FSYS0_UNIPRO, 742 PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 743 PLL_CON0_EQOS_RGMII_125_MUX1, 744 DIV_CLK_UNIPRO, 745 DIV_EQS_RGMII_CLK_125, 746 DIV_PERIBUS_GRP, 747 DIV_EQOS_RII_CLK2O5, 748 DIV_EQOS_RMIICLK_25, 749 DIV_PCIE_PHY_OSCCLK, 750 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 751 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 752 GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 753 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 754 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 755 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 756 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 757 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 758 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 759 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 760 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 761 GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 762 GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 763 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 764 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 765 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 766 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 767 GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 768 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 769 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 770 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 771 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 772 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 773 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 774 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 775 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 776 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 777 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 778 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 779 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, 780 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 781 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 782 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 783 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 784 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 785 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 786 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 787 GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 788 GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 789 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 790 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 791 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 792 GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 793 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 794 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 795 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 796 GAT_FSYS0_RII_CLK_DIVGATE, 797 }; 798 799 static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = { 800 FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000), 801 FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000), 802 FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000), 803 }; 804 805 /* List of parent clocks for Muxes in CMU_FSYS0 */ 806 PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" }; 807 PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" }; 808 PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" }; 809 810 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { 811 MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p, 812 PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1), 813 MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p, 814 PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1), 815 MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p, 816 PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1), 817 }; 818 819 static const struct samsung_div_clock fsys0_div_clks[] __initconst = { 820 DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4), 821 DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1", 822 DIV_EQS_RGMII_CLK_125, 0, 4), 823 DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp", 824 "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4), 825 DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4), 826 DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1", 827 DIV_EQOS_RMIICLK_25, 0, 5), 828 DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1", 829 DIV_PCIE_PHY_OSCCLK, 0, 4), 830 }; 831 832 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { 833 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i", 834 "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21, 835 CLK_IGNORE_UNUSED, 0), 836 GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC, 837 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll", 838 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21, 839 CLK_IGNORE_UNUSED, 0), 840 GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 841 GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 842 GATE(0, 843 "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo", 844 "xtal_clk_pcie_phy", 845 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21, 846 CLK_IGNORE_UNUSED, 0), 847 GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24", 848 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, 849 CLK_IGNORE_UNUSED, 0), 850 GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26", 851 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, 852 CLK_IGNORE_UNUSED, 0), 853 GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24", 854 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, 855 CLK_IGNORE_UNUSED, 0), 856 GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26", 857 "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, 858 CLK_IGNORE_UNUSED, 0), 859 GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp", 860 GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0), 861 GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp", 862 GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 863 GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk", 864 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 865 GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp", 866 GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), 867 GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp", 868 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 869 GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1", 870 GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), 871 GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk", 872 GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 873 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i", 874 "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21, 875 CLK_IGNORE_UNUSED, 0), 876 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i", 877 "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21, 878 CLK_IGNORE_UNUSED, 0), 879 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i", 880 "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21, 881 CLK_IGNORE_UNUSED, 0), 882 GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5", 883 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 884 GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25", 885 GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), 886 GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 887 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 888 GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll", 889 GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 890 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d", 891 "mout_fsys0_clk_fsys0_slavebusclk", 892 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21, 893 CLK_IGNORE_UNUSED, 0), 894 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1", 895 "mout_fsys0_eqos_rgmii_125_mux1", 896 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21, 897 CLK_IGNORE_UNUSED, 0), 898 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p", 899 "dout_fsys0_peribus_grp", 900 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21, 901 CLK_IGNORE_UNUSED, 0), 902 GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s", 903 "mout_fsys0_clk_fsys0_slavebusclk", 904 GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21, 905 CLK_IGNORE_UNUSED, 0), 906 GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk", 907 "dout_fsys0_peribus_grp", 908 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21, 909 CLK_IGNORE_UNUSED, 0), 910 GATE(0, 911 "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll", 912 "dout_fsys0_pcie_phy_oscclk", 913 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, 914 21, CLK_IGNORE_UNUSED, 0), 915 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp", 916 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0), 917 GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll", 918 GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0), 919 GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC, 920 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc", 921 "dout_fsys0_peribus_grp", 922 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21, 923 CLK_IGNORE_UNUSED, 0), 924 GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk", 925 "dout_fsys0_peribus_grp", 926 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21, 927 CLK_IGNORE_UNUSED, 0), 928 GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC, 929 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc", 930 "mout_fsys0_clk_fsys0_slavebusclk", 931 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21, 932 CLK_IGNORE_UNUSED, 0), 933 GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC, 934 "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc", 935 "mout_fsys0_clk_fsys0_slavebusclk", 936 GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21, 937 CLK_IGNORE_UNUSED, 0), 938 GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1", 939 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), 940 GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk", 941 GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0), 942 GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", 943 GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 944 GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", 945 GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), 946 GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp", 947 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 948 GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", 949 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), 950 GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", 951 GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), 952 GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", 953 GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), 954 GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp", 955 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 956 GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", 957 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), 958 GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", 959 GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), 960 GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE, 961 21, CLK_IGNORE_UNUSED, 0), 962 GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i", 963 "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), 964 }; 965 966 static const struct samsung_cmu_info fsys0_cmu_info __initconst = { 967 .mux_clks = fsys0_mux_clks, 968 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 969 .div_clks = fsys0_div_clks, 970 .nr_div_clks = ARRAY_SIZE(fsys0_div_clks), 971 .gate_clks = fsys0_gate_clks, 972 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 973 .fixed_clks = fsys0_fixed_clks, 974 .nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks), 975 .nr_clk_ids = CLKS_NR_FSYS0, 976 .clk_regs = fsys0_clk_regs, 977 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 978 .clk_name = "dout_cmu_fsys0_shared1div4", 979 }; 980 981 /* Register Offset definitions for CMU_FSYS1 (0x16810000) */ 982 #define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100 983 #define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180 984 #define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800 985 #define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804 986 #define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000 987 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004 988 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008 989 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c 990 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c 991 #define GAT_FSYS1_PHY0_OSCCLLK 0x2034 992 #define GAT_FSYS1_PHY1_OSCCLK 0x2038 993 #define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c 994 #define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040 995 #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048 996 #define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c 997 #define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054 998 #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c 999 #define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064 1000 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c 1001 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070 1002 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074 1003 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078 1004 #define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c 1005 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080 1006 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084 1007 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088 1008 #define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c 1009 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4 1010 #define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8 1011 #define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4 1012 #define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8 1013 1014 static const unsigned long fsys1_clk_regs[] __initconst = { 1015 PLL_CON0_ACLK_FSYS1_BUSP_MUX, 1016 PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 1017 DIV_CLK_FSYS1_PHY0_OSCCLK, 1018 DIV_CLK_FSYS1_PHY1_OSCCLK, 1019 GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 1020 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 1021 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 1022 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 1023 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 1024 GAT_FSYS1_PHY0_OSCCLLK, 1025 GAT_FSYS1_PHY1_OSCCLK, 1026 GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 1027 GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 1028 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 1029 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 1030 GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 1031 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 1032 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 1033 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 1034 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 1035 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 1036 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 1037 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 1038 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 1039 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 1040 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 1041 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 1042 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 1043 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 1044 GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 1045 GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 1046 }; 1047 1048 static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = { 1049 FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000), 1050 FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000), 1051 }; 1052 1053 /* List of parent clocks for Muxes in CMU_FSYS1 */ 1054 PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" }; 1055 PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" }; 1056 1057 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { 1058 MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p, 1059 PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1), 1060 MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p, 1061 PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1), 1062 }; 1063 1064 static const struct samsung_div_clock fsys1_div_clks[] __initconst = { 1065 DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk", 1066 DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4), 1067 DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk", 1068 DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4), 1069 }; 1070 1071 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { 1072 GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1073 GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1074 GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref", 1075 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0), 1076 GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux", 1077 GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0), 1078 GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux", 1079 GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 1080 GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1081 GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1082 GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", 1083 GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1084 GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1085 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0), 1086 GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", 1087 GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1088 GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", 1089 GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1090 GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0", 1091 "mout_fsys1_aclk_fsys1_busp_mux", 1092 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21, 1093 CLK_IGNORE_UNUSED, 0), 1094 GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0", 1095 "mout_fsys1_aclk_fsys1_busp_mux", 1096 GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21, 1097 CLK_IGNORE_UNUSED, 0), 1098 GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk", 1099 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21, 1100 CLK_IGNORE_UNUSED, 0), 1101 GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1102 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1103 GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll", 1104 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0), 1105 GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1106 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1107 GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk", 1108 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21, 1109 CLK_IGNORE_UNUSED, 0), 1110 GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk", 1111 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21, 1112 CLK_IGNORE_UNUSED, 0), 1113 GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk", 1114 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21, 1115 CLK_IGNORE_UNUSED, 0), 1116 GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1117 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1118 GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk", 1119 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21, 1120 CLK_IGNORE_UNUSED, 0), 1121 GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk", 1122 "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21, 1123 CLK_IGNORE_UNUSED, 0), 1124 GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", 1125 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), 1126 GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll", 1127 GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), 1128 GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll", 1129 GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), 1130 GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk", 1131 GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0), 1132 GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", 1133 GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1134 GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", 1135 GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1136 }; 1137 1138 static const struct samsung_cmu_info fsys1_cmu_info __initconst = { 1139 .mux_clks = fsys1_mux_clks, 1140 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 1141 .div_clks = fsys1_div_clks, 1142 .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), 1143 .gate_clks = fsys1_gate_clks, 1144 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 1145 .fixed_clks = fsys1_fixed_clks, 1146 .nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks), 1147 .nr_clk_ids = CLKS_NR_FSYS1, 1148 .clk_regs = fsys1_clk_regs, 1149 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 1150 .clk_name = "dout_cmu_fsys1_shared0div4", 1151 }; 1152 1153 /* Register Offset definitions for CMU_IMEM (0x10010000) */ 1154 #define PLL_CON0_CLK_IMEM_ACLK 0x100 1155 #define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120 1156 #define PLL_CON0_CLK_IMEM_TCUCLK 0x140 1157 #define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800 1158 #define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000 1159 #define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004 1160 #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008 1161 #define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c 1162 #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010 1163 #define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014 1164 #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018 1165 #define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c 1166 #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020 1167 #define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024 1168 #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028 1169 #define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c 1170 #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030 1171 #define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034 1172 #define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038 1173 #define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c 1174 #define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040 1175 #define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044 1176 #define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048 1177 #define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c 1178 #define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050 1179 #define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054 1180 #define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058 1181 #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c 1182 #define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060 1183 #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064 1184 #define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068 1185 #define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c 1186 #define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070 1187 #define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074 1188 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078 1189 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c 1190 #define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080 1191 #define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084 1192 #define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088 1193 #define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c 1194 #define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090 1195 #define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094 1196 #define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098 1197 #define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c 1198 #define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0 1199 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4 1200 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8 1201 #define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac 1202 #define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0 1203 #define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4 1204 #define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8 1205 #define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc 1206 #define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0 1207 #define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4 1208 #define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8 1209 #define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc 1210 #define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0 1211 #define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4 1212 #define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8 1213 #define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc 1214 1215 static const unsigned long imem_clk_regs[] __initconst = { 1216 PLL_CON0_CLK_IMEM_ACLK, 1217 PLL_CON0_CLK_IMEM_INTMEMCLK, 1218 PLL_CON0_CLK_IMEM_TCUCLK, 1219 DIV_OSCCLK_IMEM_TMUTSCLK, 1220 GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 1221 GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 1222 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 1223 GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 1224 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 1225 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 1226 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 1227 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 1228 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 1229 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 1230 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 1231 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 1232 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 1233 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 1234 GAT_IMEM_WDT0_IPCLKPORT_CLK, 1235 GAT_IMEM_WDT1_IPCLKPORT_CLK, 1236 GAT_IMEM_WDT2_IPCLKPORT_CLK, 1237 GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 1238 GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 1239 GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 1240 GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 1241 GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 1242 GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 1243 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 1244 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 1245 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 1246 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 1247 GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 1248 GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 1249 GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 1250 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 1251 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 1252 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 1253 GAT_IMEM_DMA0_IPCLKPORT_ACLK, 1254 GAT_IMEM_DMA1_IPCLKPORT_ACLK, 1255 GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 1256 GAT_IMEM_GIC_IPCLKPORT_CLK, 1257 GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 1258 GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 1259 GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 1260 GAT_IMEM_MCT_IPCLKPORT_PCLK, 1261 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 1262 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 1263 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 1264 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 1265 GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 1266 GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 1267 GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 1268 GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 1269 GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 1270 GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 1271 GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 1272 GAT_IMEM_TCU_IPCLKPORT_ACLK, 1273 GAT_IMEM_WDT0_IPCLKPORT_PCLK, 1274 GAT_IMEM_WDT1_IPCLKPORT_PCLK, 1275 GAT_IMEM_WDT2_IPCLKPORT_PCLK, 1276 }; 1277 1278 PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" }; 1279 PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" }; 1280 PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" }; 1281 1282 static const struct samsung_mux_clock imem_mux_clks[] __initconst = { 1283 MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p, 1284 PLL_CON0_CLK_IMEM_TCUCLK, 4, 1), 1285 MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1), 1286 MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p, 1287 PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1), 1288 }; 1289 1290 static const struct samsung_div_clock imem_div_clks[] __initconst = { 1291 DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4), 1292 }; 1293 1294 static const struct samsung_gate_clock imem_gate_clks[] __initconst = { 1295 GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1296 GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1297 GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll", 1298 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), 1299 GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll", 1300 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1301 GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll", 1302 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1303 GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll", 1304 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1305 GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll", 1306 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1307 GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll", 1308 GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0), 1309 GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll", 1310 GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1311 GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll", 1312 GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1313 GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll", 1314 GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1315 GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts", 1316 "dout_imem_oscclk_imem_tmutsclk", 1317 GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1318 GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts", 1319 "dout_imem_oscclk_imem_tmutsclk", 1320 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1321 GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts", 1322 "dout_imem_oscclk_imem_tmutsclk", 1323 GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1324 GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts", 1325 "dout_imem_oscclk_imem_tmutsclk", 1326 GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1327 GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts", 1328 "dout_imem_oscclk_imem_tmutsclk", 1329 GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), 1330 GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1331 GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1332 GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1333 GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1334 GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", 1335 GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), 1336 GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1337 GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1338 GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1339 GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1340 GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", 1341 GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), 1342 GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", 1343 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1344 GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk", 1345 GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1346 GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", 1347 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1348 GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk", 1349 GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1350 GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk", 1351 GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1352 GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk", 1353 GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1354 GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk", 1355 GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1356 GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk", 1357 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), 1358 GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk", 1359 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), 1360 GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk", 1361 GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), 1362 GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1363 GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), 1364 GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1365 GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), 1366 GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk", 1367 GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1368 GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk", 1369 GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1370 GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk", 1371 GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1372 GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1373 GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1374 GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1375 GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1376 GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1377 GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1378 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d", 1379 "mout_imem_clk_imem_tcuclk", 1380 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0), 1381 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu", 1382 "mout_imem_clk_imem_tcuclk", 1383 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21, 1384 CLK_IGNORE_UNUSED, 0), 1385 GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk", 1386 GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0), 1387 GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1388 GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1389 GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk", 1390 GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1391 GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll", 1392 GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1393 GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk", 1394 GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1395 GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk", 1396 GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1397 GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1398 GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1399 GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1400 GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1401 GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll", 1402 GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), 1403 GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1404 GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1405 GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1406 GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1407 GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", 1408 GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1409 GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1410 GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1411 GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1412 GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1413 GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk", 1414 GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1415 }; 1416 1417 static const struct samsung_cmu_info imem_cmu_info __initconst = { 1418 .mux_clks = imem_mux_clks, 1419 .nr_mux_clks = ARRAY_SIZE(imem_mux_clks), 1420 .div_clks = imem_div_clks, 1421 .nr_div_clks = ARRAY_SIZE(imem_div_clks), 1422 .gate_clks = imem_gate_clks, 1423 .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), 1424 .nr_clk_ids = CLKS_NR_IMEM, 1425 .clk_regs = imem_clk_regs, 1426 .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), 1427 }; 1428 1429 static void __init fsd_clk_imem_init(struct device_node *np) 1430 { 1431 samsung_cmu_register_one(np, &imem_cmu_info); 1432 } 1433 1434 CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init); 1435 1436 /* Register Offset definitions for CMU_MFC (0x12810000) */ 1437 #define PLL_LOCKTIME_PLL_MFC 0x0 1438 #define PLL_CON0_PLL_MFC 0x100 1439 #define MUX_MFC_BUSD 0x1000 1440 #define MUX_MFC_BUSP 0x1008 1441 #define DIV_MFC_BUSD_DIV4 0x1800 1442 #define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000 1443 #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004 1444 #define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008 1445 #define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c 1446 #define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010 1447 #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018 1448 #define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c 1449 #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028 1450 #define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c 1451 #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030 1452 #define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034 1453 #define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038 1454 #define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c 1455 #define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040 1456 #define GAT_MFC_BUSD_DIV4_GATE 0x2044 1457 #define GAT_MFC_BUSD_GATE 0x2048 1458 1459 static const unsigned long mfc_clk_regs[] __initconst = { 1460 PLL_LOCKTIME_PLL_MFC, 1461 PLL_CON0_PLL_MFC, 1462 MUX_MFC_BUSD, 1463 MUX_MFC_BUSP, 1464 DIV_MFC_BUSD_DIV4, 1465 GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 1466 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 1467 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 1468 GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 1469 GAT_MFC_MFC_IPCLKPORT_ACLK, 1470 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 1471 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 1472 GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 1473 GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 1474 GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 1475 GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 1476 GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 1477 GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 1478 GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 1479 GAT_MFC_BUSD_DIV4_GATE, 1480 GAT_MFC_BUSD_GATE, 1481 }; 1482 1483 static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = { 1484 PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0), 1485 }; 1486 1487 static const struct samsung_pll_clock mfc_pll_clks[] __initconst = { 1488 PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll", 1489 PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table), 1490 }; 1491 1492 PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" }; 1493 PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" }; 1494 PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" }; 1495 1496 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 1497 MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1), 1498 MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1), 1499 MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1), 1500 }; 1501 1502 static const struct samsung_div_clock mfc_div_clks[] __initconst = { 1503 DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4), 1504 }; 1505 1506 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 1507 GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp", 1508 GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1509 GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd", 1510 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), 1511 GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp", 1512 GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), 1513 GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp", 1514 GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1515 GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd", 1516 GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1517 GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd", 1518 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0), 1519 GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp", 1520 GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0), 1521 GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd", 1522 GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1523 GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp", 1524 GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1525 GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd", 1526 GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1527 GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp", 1528 GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1529 GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp", 1530 GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1531 GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd", 1532 GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1533 GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd", 1534 GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), 1535 GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll", 1536 GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), 1537 GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0), 1538 }; 1539 1540 static const struct samsung_cmu_info mfc_cmu_info __initconst = { 1541 .pll_clks = mfc_pll_clks, 1542 .nr_pll_clks = ARRAY_SIZE(mfc_pll_clks), 1543 .mux_clks = mfc_mux_clks, 1544 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 1545 .div_clks = mfc_div_clks, 1546 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 1547 .gate_clks = mfc_gate_clks, 1548 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 1549 .nr_clk_ids = CLKS_NR_MFC, 1550 .clk_regs = mfc_clk_regs, 1551 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 1552 }; 1553 1554 /* Register Offset definitions for CMU_CAM_CSI (0x12610000) */ 1555 #define PLL_LOCKTIME_PLL_CAM_CSI 0x0 1556 #define PLL_CON0_PLL_CAM_CSI 0x100 1557 #define DIV_CAM_CSI0_ACLK 0x1800 1558 #define DIV_CAM_CSI1_ACLK 0x1804 1559 #define DIV_CAM_CSI2_ACLK 0x1808 1560 #define DIV_CAM_CSI_BUSD 0x180c 1561 #define DIV_CAM_CSI_BUSP 0x1810 1562 #define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000 1563 #define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004 1564 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008 1565 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c 1566 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010 1567 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014 1568 #define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018 1569 #define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c 1570 #define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020 1571 #define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024 1572 #define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028 1573 #define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c 1574 #define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030 1575 #define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034 1576 #define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038 1577 #define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c 1578 #define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040 1579 #define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044 1580 #define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048 1581 #define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c 1582 #define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050 1583 #define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054 1584 #define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058 1585 #define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c 1586 #define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060 1587 #define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064 1588 #define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068 1589 #define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c 1590 #define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070 1591 #define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074 1592 #define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078 1593 #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c 1594 #define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080 1595 #define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084 1596 #define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088 1597 1598 static const unsigned long cam_csi_clk_regs[] __initconst = { 1599 PLL_LOCKTIME_PLL_CAM_CSI, 1600 PLL_CON0_PLL_CAM_CSI, 1601 DIV_CAM_CSI0_ACLK, 1602 DIV_CAM_CSI1_ACLK, 1603 DIV_CAM_CSI2_ACLK, 1604 DIV_CAM_CSI_BUSD, 1605 DIV_CAM_CSI_BUSP, 1606 GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 1607 GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 1608 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 1609 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 1610 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 1611 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 1612 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 1613 GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 1614 GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 1615 GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 1616 GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 1617 GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 1618 GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 1619 GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 1620 GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 1621 GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 1622 GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 1623 GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 1624 GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 1625 GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 1626 GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 1627 GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 1628 GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 1629 GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 1630 GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 1631 GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 1632 GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 1633 GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 1634 GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 1635 GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 1636 GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 1637 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 1638 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 1639 GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 1640 GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 1641 }; 1642 1643 static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = { 1644 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0), 1645 }; 1646 1647 static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = { 1648 PLL(pll_142xx, CAM_CSI_PLL, "fout_pll_cam_csi", "fin_pll", 1649 PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table), 1650 }; 1651 1652 PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" }; 1653 1654 static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = { 1655 MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1), 1656 }; 1657 1658 static const struct samsung_div_clock cam_csi_div_clks[] __initconst = { 1659 DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4), 1660 DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4), 1661 DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4), 1662 DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4), 1663 DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4), 1664 }; 1665 1666 static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = { 1667 GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", 1668 GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1669 GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp", 1670 GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1671 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk", 1672 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0), 1673 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk", 1674 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0), 1675 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk", 1676 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0), 1677 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd", 1678 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21, 1679 CLK_IGNORE_UNUSED, 0), 1680 GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd", 1681 GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0), 1682 GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1683 GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1684 GATE(CAM_CSI0_0_IPCLKPORT_I_PCLK, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1685 GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1686 GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1687 GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1688 GATE(CAM_CSI0_1_IPCLKPORT_I_PCLK, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1689 GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1690 GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1691 GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1692 GATE(CAM_CSI0_2_IPCLKPORT_I_PCLK, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1693 GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1694 GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk", 1695 GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1696 GATE(CAM_CSI0_3_IPCLKPORT_I_PCLK, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1697 GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1698 GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1699 GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1700 GATE(CAM_CSI1_0_IPCLKPORT_I_PCLK, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1701 GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1702 GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1703 GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1704 GATE(CAM_CSI1_1_IPCLKPORT_I_PCLK, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1705 GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1706 GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1707 GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1708 GATE(CAM_CSI1_2_IPCLKPORT_I_PCLK, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1709 GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1710 GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk", 1711 GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1712 GATE(CAM_CSI1_3_IPCLKPORT_I_PCLK, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1713 GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1714 GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1715 GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1716 GATE(CAM_CSI2_0_IPCLKPORT_I_PCLK, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp", 1717 GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1718 GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1719 GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1720 GATE(CAM_CSI2_1_IPCLKPORT_I_PCLK, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp", 1721 GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1722 GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1723 GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1724 GATE(CAM_CSI2_2_IPCLKPORT_I_PCLK, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp", 1725 GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1726 GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk", 1727 GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1728 GATE(CAM_CSI2_3_IPCLKPORT_I_PCLK, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp", 1729 GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1730 GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d", 1731 "dout_cam_csi_busd", 1732 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21, 1733 CLK_IGNORE_UNUSED, 0), 1734 GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p", 1735 "dout_cam_csi_busp", 1736 GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21, 1737 CLK_IGNORE_UNUSED, 0), 1738 GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", 1739 GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), 1740 GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd", 1741 GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), 1742 }; 1743 1744 static const struct samsung_cmu_info cam_csi_cmu_info __initconst = { 1745 .pll_clks = cam_csi_pll_clks, 1746 .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks), 1747 .mux_clks = cam_csi_mux_clks, 1748 .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks), 1749 .div_clks = cam_csi_div_clks, 1750 .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks), 1751 .gate_clks = cam_csi_gate_clks, 1752 .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks), 1753 .nr_clk_ids = CLKS_NR_CAM_CSI, 1754 .clk_regs = cam_csi_clk_regs, 1755 .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs), 1756 }; 1757 1758 /** 1759 * fsd_cmu_probe - Probe function for FSD platform clocks 1760 * @pdev: Pointer to platform device 1761 * 1762 * Configure clock hierarchy for clock domains of FSD platform 1763 */ 1764 static int __init fsd_cmu_probe(struct platform_device *pdev) 1765 { 1766 const struct samsung_cmu_info *info; 1767 struct device *dev = &pdev->dev; 1768 1769 info = of_device_get_match_data(dev); 1770 exynos_arm64_register_cmu(dev, dev->of_node, info); 1771 1772 return 0; 1773 } 1774 1775 /* CMUs which belong to Power Domains and need runtime PM to be implemented */ 1776 static const struct of_device_id fsd_cmu_of_match[] = { 1777 { 1778 .compatible = "tesla,fsd-clock-peric", 1779 .data = &peric_cmu_info, 1780 }, { 1781 .compatible = "tesla,fsd-clock-fsys0", 1782 .data = &fsys0_cmu_info, 1783 }, { 1784 .compatible = "tesla,fsd-clock-fsys1", 1785 .data = &fsys1_cmu_info, 1786 }, { 1787 .compatible = "tesla,fsd-clock-mfc", 1788 .data = &mfc_cmu_info, 1789 }, { 1790 .compatible = "tesla,fsd-clock-cam_csi", 1791 .data = &cam_csi_cmu_info, 1792 }, { 1793 }, 1794 }; 1795 1796 static struct platform_driver fsd_cmu_driver __refdata = { 1797 .driver = { 1798 .name = "fsd-cmu", 1799 .of_match_table = fsd_cmu_of_match, 1800 .suppress_bind_attrs = true, 1801 }, 1802 .probe = fsd_cmu_probe, 1803 }; 1804 1805 static int __init fsd_cmu_init(void) 1806 { 1807 return platform_driver_register(&fsd_cmu_driver); 1808 } 1809 core_initcall(fsd_cmu_init); 1810