1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 Samsung Electronics Co., Ltd. 4 * Author: Sunyeal Hong <sunyeal.hong@samsung.com> 5 * 6 * Common Clock Framework support for ExynosAuto v920 SoC. 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 14 #include <dt-bindings/clock/samsung,exynosautov920.h> 15 16 #include "clk.h" 17 #include "clk-exynos-arm64.h" 18 19 /* NOTE: Must be equal to the last clock ID increased by one */ 20 #define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1) 21 #define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1) 22 #define CLKS_NR_CPUCL1 (CLK_DOUT_CPUCL1_NOCP + 1) 23 #define CLKS_NR_CPUCL2 (CLK_DOUT_CPUCL2_NOCP + 1) 24 #define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1) 25 #define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1) 26 #define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1) 27 #define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1) 28 #define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1) 29 #define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1) 30 31 /* ---- CMU_TOP ------------------------------------------------------------ */ 32 33 /* Register Offset definitions for CMU_TOP (0x11000000) */ 34 #define PLL_LOCKTIME_PLL_MMC 0x0004 35 #define PLL_LOCKTIME_PLL_SHARED0 0x0008 36 #define PLL_LOCKTIME_PLL_SHARED1 0x000c 37 #define PLL_LOCKTIME_PLL_SHARED2 0x0010 38 #define PLL_LOCKTIME_PLL_SHARED3 0x0014 39 #define PLL_LOCKTIME_PLL_SHARED4 0x0018 40 #define PLL_LOCKTIME_PLL_SHARED5 0x0018 41 #define PLL_CON0_PLL_MMC 0x0140 42 #define PLL_CON3_PLL_MMC 0x014c 43 #define PLL_CON0_PLL_SHARED0 0x0180 44 #define PLL_CON3_PLL_SHARED0 0x018c 45 #define PLL_CON0_PLL_SHARED1 0x01c0 46 #define PLL_CON3_PLL_SHARED1 0x01cc 47 #define PLL_CON0_PLL_SHARED2 0x0200 48 #define PLL_CON3_PLL_SHARED2 0x020c 49 #define PLL_CON0_PLL_SHARED3 0x0240 50 #define PLL_CON3_PLL_SHARED3 0x024c 51 #define PLL_CON0_PLL_SHARED4 0x0280 52 #define PLL_CON3_PLL_SHARED4 0x028c 53 #define PLL_CON0_PLL_SHARED5 0x02c0 54 #define PLL_CON3_PLL_SHARED5 0x02cc 55 56 /* MUX */ 57 #define CLK_CON_MUX_MUX_CLKCMU_ACC_NOC 0x1000 58 #define CLK_CON_MUX_MUX_CLKCMU_APM_NOC 0x1004 59 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008 60 #define CLK_CON_MUX_MUX_CLKCMU_AUD_NOC 0x100c 61 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0 0x1010 62 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1 0x1014 63 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2 0x1018 64 #define CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3 0x101c 65 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1020 66 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024 67 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1028 68 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c 69 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030 70 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034 71 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER 0x1038 72 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x103c 73 #define CLK_CON_MUX_MUX_CLKCMU_DNC_NOC 0x1040 74 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044 75 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC 0x1048 76 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC 0x104c 77 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM 0x1050 78 #define CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC 0x1054 79 #define CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC 0x1058 80 #define CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC 0x105c 81 #define CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC 0x1060 82 #define CLK_CON_MUX_MUX_CLKCMU_DSP_NOC 0x1064 83 #define CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP 0x1068 84 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x106c 85 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC 0x1070 86 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC 0x1074 87 #define CLK_CON_MUX_MUX_CLKCMU_ACC_ORB 0x1078 88 #define CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA 0x107c 89 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x1080 90 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC 0x1084 91 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD 0x1088 92 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET 0x108c 93 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC 0x1090 94 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS 0x1094 95 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x1098 96 #define CLK_CON_MUX_MUX_CLKCMU_ISP_NOC 0x109c 97 #define CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG 0x10a0 98 #define CLK_CON_MUX_MUX_CLKCMU_M2M_NOC 0x10a4 99 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10a8 100 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x10ac 101 #define CLK_CON_MUX_MUX_CLKCMU_MFD_NOC 0x10b0 102 #define CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP 0x10b4 103 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10b8 104 #define CLK_CON_MUX_MUX_CLKCMU_MISC_NOC 0x10bc 105 #define CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC 0x10c0 106 #define CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC 0x10c4 107 #define CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC 0x10c8 108 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10cc 109 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC 0x10d0 110 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d4 111 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC 0x10d8 112 #define CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC 0x10dc 113 #define CLK_CON_MUX_MUX_CLKCMU_SNW_NOC 0x10e0 114 #define CLK_CON_MUX_MUX_CLKCMU_SSP_NOC 0x10e4 115 #define CLK_CON_MUX_MUX_CLKCMU_TAA_NOC 0x10e8 116 #define CLK_CON_MUX_MUX_CLK_CMU_NOCP 0x10ec 117 #define CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT 0x10f0 118 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4 119 120 /* DIV */ 121 #define CLK_CON_DIV_CLKCMU_ACC_NOC 0x1800 122 #define CLK_CON_DIV_CLKCMU_APM_NOC 0x1804 123 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1808 124 #define CLK_CON_DIV_CLKCMU_AUD_NOC 0x180c 125 #define CLK_CON_DIV_CLKCMU_CIS_MCLK0 0x1810 126 #define CLK_CON_DIV_CLKCMU_CIS_MCLK1 0x1814 127 #define CLK_CON_DIV_CLKCMU_CIS_MCLK2 0x1818 128 #define CLK_CON_DIV_CLKCMU_CIS_MCLK3 0x181c 129 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820 130 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1824 131 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828 132 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c 133 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830 134 #define CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER 0x1834 135 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1838 136 #define CLK_CON_DIV_CLKCMU_DNC_NOC 0x183c 137 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840 138 #define CLK_CON_DIV_CLKCMU_DPTX_DPOSC 0x1844 139 #define CLK_CON_DIV_CLKCMU_DPTX_NOC 0x1848 140 #define CLK_CON_DIV_CLKCMU_DPUB_DSIM 0x184c 141 #define CLK_CON_DIV_CLKCMU_DPUB_NOC 0x1850 142 #define CLK_CON_DIV_CLKCMU_DPUF0_NOC 0x1854 143 #define CLK_CON_DIV_CLKCMU_DPUF1_NOC 0x1858 144 #define CLK_CON_DIV_CLKCMU_DPUF2_NOC 0x185c 145 #define CLK_CON_DIV_CLKCMU_DSP_NOC 0x1860 146 #define CLK_CON_DIV_CLKCMU_G3D_NOCP 0x1864 147 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868 148 #define CLK_CON_DIV_CLKCMU_GNPU_NOC 0x186c 149 #define CLK_CON_DIV_CLKCMU_HSI0_NOC 0x1870 150 #define CLK_CON_DIV_CLKCMU_ACC_ORB 0x1874 151 #define CLK_CON_DIV_CLKCMU_GNPU_XMAA 0x1878 152 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x187c 153 #define CLK_CON_DIV_CLKCMU_HSI1_NOC 0x1880 154 #define CLK_CON_DIV_CLKCMU_HSI1_USBDRD 0x1884 155 #define CLK_CON_DIV_CLKCMU_HSI2_ETHERNET 0x1888 156 #define CLK_CON_DIV_CLKCMU_HSI2_NOC 0x188c 157 #define CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS 0x1890 158 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x1894 159 #define CLK_CON_DIV_CLKCMU_ISP_NOC 0x1898 160 #define CLK_CON_DIV_CLKCMU_M2M_JPEG 0x189c 161 #define CLK_CON_DIV_CLKCMU_M2M_NOC 0x18a0 162 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18a4 163 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x18a8 164 #define CLK_CON_DIV_CLKCMU_MFD_NOC 0x18ac 165 #define CLK_CON_DIV_CLKCMU_MIF_NOCP 0x18b0 166 #define CLK_CON_DIV_CLKCMU_MISC_NOC 0x18b4 167 #define CLK_CON_DIV_CLKCMU_NOCL0_NOC 0x18b8 168 #define CLK_CON_DIV_CLKCMU_NOCL1_NOC 0x18bc 169 #define CLK_CON_DIV_CLKCMU_NOCL2_NOC 0x18c0 170 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c4 171 #define CLK_CON_DIV_CLKCMU_PERIC0_NOC 0x18c8 172 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18cc 173 #define CLK_CON_DIV_CLKCMU_PERIC1_NOC 0x18d0 174 #define CLK_CON_DIV_CLKCMU_SDMA_NOC 0x18d4 175 #define CLK_CON_DIV_CLKCMU_SNW_NOC 0x18d8 176 #define CLK_CON_DIV_CLKCMU_SSP_NOC 0x18dc 177 #define CLK_CON_DIV_CLKCMU_TAA_NOC 0x18e0 178 #define CLK_CON_DIV_CLK_ADD_CH_CLK 0x18e4 179 #define CLK_CON_DIV_CLK_CMU_PLLCLKOUT 0x18e8 180 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18ec 181 #define CLK_CON_DIV_DIV_CLK_CMU_NOCP 0x18f0 182 183 static const unsigned long top_clk_regs[] __initconst = { 184 PLL_LOCKTIME_PLL_MMC, 185 PLL_LOCKTIME_PLL_SHARED0, 186 PLL_LOCKTIME_PLL_SHARED1, 187 PLL_LOCKTIME_PLL_SHARED2, 188 PLL_LOCKTIME_PLL_SHARED3, 189 PLL_LOCKTIME_PLL_SHARED4, 190 PLL_LOCKTIME_PLL_SHARED5, 191 PLL_CON0_PLL_MMC, 192 PLL_CON3_PLL_MMC, 193 PLL_CON0_PLL_SHARED0, 194 PLL_CON3_PLL_SHARED0, 195 PLL_CON0_PLL_SHARED1, 196 PLL_CON3_PLL_SHARED1, 197 PLL_CON0_PLL_SHARED2, 198 PLL_CON3_PLL_SHARED2, 199 PLL_CON0_PLL_SHARED3, 200 PLL_CON3_PLL_SHARED3, 201 PLL_CON0_PLL_SHARED4, 202 PLL_CON3_PLL_SHARED4, 203 PLL_CON0_PLL_SHARED5, 204 PLL_CON3_PLL_SHARED5, 205 CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 206 CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 207 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 208 CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 209 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK0, 210 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK1, 211 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK2, 212 CLK_CON_MUX_MUX_CLKCMU_CIS_MCLK3, 213 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 214 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 215 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 216 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 217 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 218 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 219 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER, 220 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 221 CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 222 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 223 CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 224 CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 225 CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 226 CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 227 CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 228 CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 229 CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 230 CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 231 CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 232 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 233 CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 234 CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 235 CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 236 CLK_CON_MUX_MUX_CLKCMU_GNPU_XMAA, 237 CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD, 238 CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, 239 CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD, 240 CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET, 241 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC, 242 CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS, 243 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 244 CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 245 CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 246 CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 247 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 248 CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 249 CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 250 CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 251 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 252 CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 253 CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 254 CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 255 CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 256 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 257 CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 258 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 259 CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 260 CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 261 CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 262 CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 263 CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 264 CLK_CON_MUX_MUX_CLK_CMU_NOCP, 265 CLK_CON_MUX_MUX_CLK_CMU_PLLCLKOUT, 266 CLK_CON_MUX_MUX_CMU_CMUREF, 267 CLK_CON_DIV_CLKCMU_ACC_NOC, 268 CLK_CON_DIV_CLKCMU_APM_NOC, 269 CLK_CON_DIV_CLKCMU_AUD_CPU, 270 CLK_CON_DIV_CLKCMU_AUD_NOC, 271 CLK_CON_DIV_CLKCMU_CIS_MCLK0, 272 CLK_CON_DIV_CLKCMU_CIS_MCLK1, 273 CLK_CON_DIV_CLKCMU_CIS_MCLK2, 274 CLK_CON_DIV_CLKCMU_CIS_MCLK3, 275 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 276 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 277 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 278 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 279 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 280 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 281 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 282 CLK_CON_DIV_CLKCMU_DNC_NOC, 283 CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 284 CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 285 CLK_CON_DIV_CLKCMU_DPTX_NOC, 286 CLK_CON_DIV_CLKCMU_DPUB_DSIM, 287 CLK_CON_DIV_CLKCMU_DPUB_NOC, 288 CLK_CON_DIV_CLKCMU_DPUF0_NOC, 289 CLK_CON_DIV_CLKCMU_DPUF1_NOC, 290 CLK_CON_DIV_CLKCMU_DPUF2_NOC, 291 CLK_CON_DIV_CLKCMU_DSP_NOC, 292 CLK_CON_DIV_CLKCMU_G3D_NOCP, 293 CLK_CON_DIV_CLKCMU_G3D_SWITCH, 294 CLK_CON_DIV_CLKCMU_GNPU_NOC, 295 CLK_CON_DIV_CLKCMU_HSI0_NOC, 296 CLK_CON_DIV_CLKCMU_ACC_ORB, 297 CLK_CON_DIV_CLKCMU_GNPU_XMAA, 298 CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 299 CLK_CON_DIV_CLKCMU_HSI1_NOC, 300 CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 301 CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 302 CLK_CON_DIV_CLKCMU_HSI2_NOC, 303 CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 304 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 305 CLK_CON_DIV_CLKCMU_ISP_NOC, 306 CLK_CON_DIV_CLKCMU_M2M_JPEG, 307 CLK_CON_DIV_CLKCMU_M2M_NOC, 308 CLK_CON_DIV_CLKCMU_MFC_MFC, 309 CLK_CON_DIV_CLKCMU_MFC_WFD, 310 CLK_CON_DIV_CLKCMU_MFD_NOC, 311 CLK_CON_DIV_CLKCMU_MIF_NOCP, 312 CLK_CON_DIV_CLKCMU_MISC_NOC, 313 CLK_CON_DIV_CLKCMU_NOCL0_NOC, 314 CLK_CON_DIV_CLKCMU_NOCL1_NOC, 315 CLK_CON_DIV_CLKCMU_NOCL2_NOC, 316 CLK_CON_DIV_CLKCMU_PERIC0_IP, 317 CLK_CON_DIV_CLKCMU_PERIC0_NOC, 318 CLK_CON_DIV_CLKCMU_PERIC1_IP, 319 CLK_CON_DIV_CLKCMU_PERIC1_NOC, 320 CLK_CON_DIV_CLKCMU_SDMA_NOC, 321 CLK_CON_DIV_CLKCMU_SNW_NOC, 322 CLK_CON_DIV_CLKCMU_SSP_NOC, 323 CLK_CON_DIV_CLKCMU_TAA_NOC, 324 CLK_CON_DIV_CLK_ADD_CH_CLK, 325 CLK_CON_DIV_CLK_CMU_PLLCLKOUT, 326 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 327 CLK_CON_DIV_DIV_CLK_CMU_NOCP, 328 }; 329 330 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 331 /* CMU_TOP_PURECLKCOMP */ 332 PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", 333 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), 334 PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", 335 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL), 336 PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk", 337 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL), 338 PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk", 339 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL), 340 PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk", 341 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL), 342 PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk", 343 PLL_LOCKTIME_PLL_SHARED5, PLL_CON3_PLL_SHARED5, NULL), 344 PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", 345 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), 346 }; 347 348 /* List of parent clocks for Muxes in CMU_TOP */ 349 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" }; 350 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" }; 351 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" }; 352 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" }; 353 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" }; 354 PNAME(mout_shared5_pll_p) = { "oscclk", "fout_shared5_pll" }; 355 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" }; 356 357 PNAME(mout_clkcmu_cmu_boost_p) = { "dout_shared2_div3", "dout_shared1_div4", 358 "dout_shared2_div4", "dout_shared4_div4" }; 359 360 PNAME(mout_clkcmu_cmu_cmuref_p) = { "oscclk", "dout_cmu_boost" }; 361 362 PNAME(mout_clkcmu_acc_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", 363 "dout_shared4_div2", "dout_shared1_div3", 364 "dout_shared2_div3", "dout_shared5_div1", 365 "dout_shared3_div1", "oscclk" }; 366 367 PNAME(mout_clkcmu_acc_orb_p) = { "dout_shared2_div2", "dout_shared0_div3", 368 "dout_shared1_div2", "dout_shared1_div3", 369 "dout_shared2_div3", "fout_shared5_pll", 370 "fout_shared3_pll", "oscclk" }; 371 372 PNAME(mout_clkcmu_apm_noc_p) = { "dout_shared2_div2", "dout_shared1_div4", 373 "dout_shared2_div4", "dout_shared4_div4" }; 374 375 PNAME(mout_clkcmu_aud_cpu_p) = { "dout_shared0_div2", "dout_shared1_div2", 376 "dout_shared2_div2", "dout_shared0_div3", 377 "dout_shared4_div2", "dout_shared1_div3", 378 "dout_shared2_div3", "dout_shared4_div3" }; 379 380 PNAME(mout_clkcmu_aud_noc_p) = { "dout_shared2_div2", "dout_shared4_div2", 381 "dout_shared1_div2", "dout_shared2_div3" }; 382 383 PNAME(mout_clkcmu_cpucl0_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", 384 "dout_shared2_div2", "dout_shared4_div2" }; 385 386 PNAME(mout_clkcmu_cpucl0_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll", 387 "dout_shared0_div2", "dout_shared1_div2", 388 "dout_shared2_div2", "dout_shared4_div2", 389 "dout_shared2_div3", "fout_shared3_pll" }; 390 391 PNAME(mout_clkcmu_cpucl0_dbg_p) = { "dout_shared2_div2", "dout_shared0_div3", 392 "dout_shared4_div2", "dout_shared0_div4" }; 393 394 PNAME(mout_clkcmu_cpucl1_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", 395 "dout_shared2_div2", "dout_shared4_div2" }; 396 397 PNAME(mout_clkcmu_cpucl1_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll", 398 "dout_shared0_div2", "dout_shared1_div2", 399 "dout_shared2_div2", "dout_shared4_div2", 400 "dout_shared2_div3", "fout_shared3_pll" }; 401 402 PNAME(mout_clkcmu_cpucl2_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", 403 "dout_shared2_div2", "dout_shared4_div2" }; 404 405 PNAME(mout_clkcmu_cpucl2_cluster_p) = { "fout_shared2_pll", "fout_shared4_pll", 406 "dout_shared0_div2", "dout_shared1_div2", 407 "dout_shared2_div2", "dout_shared4_div2", 408 "dout_shared2_div3", "fout_shared3_pll" }; 409 410 PNAME(mout_clkcmu_dnc_noc_p) = { "dout_shared1_div2", "dout_shared2_div2", 411 "dout_shared0_div3", "dout_shared4_div2", 412 "dout_shared1_div3", "dout_shared2_div3", 413 "dout_shared1_div4", "fout_shared3_pll" }; 414 415 PNAME(mout_clkcmu_dptx_noc_p) = { "dout_shared4_div2", "dout_shared2_div3", 416 "dout_shared1_div4", "dout_shared2_div4" }; 417 418 PNAME(mout_clkcmu_dptx_dpgtc_p) = { "oscclk", "dout_shared2_div3", 419 "dout_shared2_div4", "dout_shared4_div4" }; 420 421 PNAME(mout_clkcmu_dptx_dposc_p) = { "oscclk", "dout_shared2_div4" }; 422 423 PNAME(mout_clkcmu_dpub_noc_p) = { "dout_shared4_div2", "dout_shared1_div3", 424 "dout_shared2_div3", "dout_shared1_div4", 425 "dout_shared2_div4", "dout_shared4_div4", 426 "fout_shared3_pll" }; 427 428 PNAME(mout_clkcmu_dpub_dsim_p) = { "dout_shared2_div3", "dout_shared2_div4" }; 429 430 PNAME(mout_clkcmu_dpuf_noc_p) = { "dout_shared4_div2", "dout_shared1_div3", 431 "dout_shared2_div3", "dout_shared1_div4", 432 "dout_shared2_div4", "dout_shared4_div4", 433 "fout_shared3_pll" }; 434 435 PNAME(mout_clkcmu_dsp_noc_p) = { "dout_shared0_div2", "dout_shared1_div2", 436 "dout_shared2_div2", "dout_shared0_div3", 437 "dout_shared4_div2", "dout_shared1_div3", 438 "fout_shared5_pll", "fout_shared3_pll" }; 439 440 PNAME(mout_clkcmu_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", 441 "dout_shared2_div2", "dout_shared4_div2" }; 442 443 PNAME(mout_clkcmu_g3d_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4", 444 "dout_shared2_div4", "dout_shared4_div4" }; 445 446 PNAME(mout_clkcmu_gnpu_noc_p) = { "dout_shared0_div2", "dout_shared1_div2", 447 "dout_shared2_div2", "dout_shared0_div3", 448 "dout_shared4_div2", "dout_shared2_div3", 449 "fout_shared5_pll", "fout_shared3_pll" }; 450 451 PNAME(mout_clkcmu_hsi0_noc_p) = { "dout_shared4_div2", "dout_shared2_div3", 452 "dout_shared1_div4", "dout_shared2_div4" }; 453 454 PNAME(mout_clkcmu_hsi1_noc_p) = { "dout_shared2_div3", "dout_shared1_div4", 455 "dout_shared2_div4", "dout_shared4_div4" }; 456 457 PNAME(mout_clkcmu_hsi1_usbdrd_p) = { "oscclk", "dout_shared2_div3", 458 "dout_shared2_div4", "dout_shared4_div4" }; 459 460 PNAME(mout_clkcmu_hsi1_mmc_card_p) = { "oscclk", "dout_shared2_div2", 461 "dout_shared4_div2", "fout_mmc_pll" }; 462 463 PNAME(mout_clkcmu_hsi2_noc_p) = { "dout_shared4_div2", "dout_shared2_div3", 464 "dout_shared1_div4", "dout_shared2_div4" }; 465 466 PNAME(mout_clkcmu_hsi2_noc_ufs_p) = { "dout_shared4_div2", "dout_shared2_div3", 467 "dout_shared1_div4", "dout_shared2_div2" }; 468 469 PNAME(mout_clkcmu_hsi2_ufs_embd_p) = { "oscclk", "dout_shared2_div3", 470 "dout_shared2_div4", "dout_shared4_div4" }; 471 472 PNAME(mout_clkcmu_hsi2_ethernet_p) = { "oscclk", "dout_shared2_div2", 473 "dout_shared0_div3", "dout_shared1_div3" }; 474 475 PNAME(mout_clkcmu_isp_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", 476 "dout_shared4_div2", "dout_shared1_div3", 477 "dout_shared2_div3", "fout_shared5_pll", 478 "fout_shared3_pll", "oscclk" }; 479 480 PNAME(mout_clkcmu_m2m_noc_p) = { "dout_shared0_div3", "dout_shared4_div2", 481 "dout_shared2_div3", "dout_shared1_div4" }; 482 483 PNAME(mout_clkcmu_m2m_jpeg_p) = { "dout_shared0_div3", "dout_shared4_div2", 484 "dout_shared2_div3", "dout_shared1_div4" }; 485 486 PNAME(mout_clkcmu_mfc_mfc_p) = { "dout_shared0_div3", "dout_shared4_div2", 487 "dout_shared2_div3", "dout_shared1_div4" }; 488 489 PNAME(mout_clkcmu_mfc_wfd_p) = { "dout_shared0_div3", "dout_shared4_div2", 490 "dout_shared2_div3", "dout_shared1_div4" }; 491 492 PNAME(mout_clkcmu_mfd_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", 493 "dout_shared4_div2", "dout_shared1_div3", 494 "dout_shared2_div3", "fout_shared5_pll", 495 "fout_shared3_pll", "oscclk" }; 496 497 PNAME(mout_clkcmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll", 498 "fout_shared2_pll", "fout_shared4_pll", 499 "dout_shared0_div2", "dout_shared1_div2", 500 "dout_shared2_div2", "fout_shared5_pll" }; 501 502 PNAME(mout_clkcmu_mif_nocp_p) = { "dout_shared2_div3", "dout_shared1_div4", 503 "dout_shared2_div4", "dout_shared4_div4" }; 504 505 PNAME(mout_clkcmu_misc_noc_p) = { "dout_shared4_div2", "dout_shared2_div3", 506 "dout_shared1_div4", "dout_shared2_div4" }; 507 508 PNAME(mout_clkcmu_nocl0_noc_p) = { "dout_shared0_div2", "dout_shared1_div2", 509 "dout_shared2_div2", "dout_shared0_div3", 510 "dout_shared4_div2", "dout_shared1_div3", 511 "dout_shared2_div3", "fout_shared3_pll" }; 512 513 PNAME(mout_clkcmu_nocl1_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", 514 "dout_shared4_div2", "dout_shared1_div3", 515 "dout_shared2_div3", "fout_shared5_pll", 516 "fout_shared3_pll", "oscclk" }; 517 518 PNAME(mout_clkcmu_nocl2_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", 519 "dout_shared4_div2", "dout_shared1_div3", 520 "dout_shared2_div3", "fout_shared5_pll", 521 "fout_shared3_pll", "oscclk" }; 522 523 PNAME(mout_clkcmu_peric0_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" }; 524 525 PNAME(mout_clkcmu_peric0_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" }; 526 527 PNAME(mout_clkcmu_peric1_noc_p) = { "dout_shared2_div3", "dout_shared2_div4" }; 528 529 PNAME(mout_clkcmu_peric1_ip_p) = { "dout_shared2_div3", "dout_shared2_div4" }; 530 531 PNAME(mout_clkcmu_sdma_noc_p) = { "dout_shared1_div2", "dout_shared2_div2", 532 "dout_shared0_div3", "dout_shared4_div2", 533 "dout_shared1_div3", "dout_shared2_div3", 534 "dout_shared1_div4", "fout_shared3_pll" }; 535 536 PNAME(mout_clkcmu_snw_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", 537 "dout_shared4_div2", "dout_shared1_div3", 538 "dout_shared2_div3", "fout_shared5_pll", 539 "fout_shared3_pll", "oscclk" }; 540 541 PNAME(mout_clkcmu_ssp_noc_p) = { "dout_shared2_div3", "dout_shared1_div4", 542 "dout_shared2_div2", "dout_shared4_div4" }; 543 544 PNAME(mout_clkcmu_taa_noc_p) = { "dout_shared2_div2", "dout_shared0_div3", 545 "dout_shared4_div2", "dout_shared1_div3", 546 "dout_shared2_div3", "fout_shared5_pll", 547 "fout_shared3_pll", "oscclk" }; 548 549 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 550 /* CMU_TOP_PURECLKCOMP */ 551 MUX(MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, 552 PLL_CON0_PLL_SHARED0, 4, 1), 553 MUX(MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, 554 PLL_CON0_PLL_SHARED1, 4, 1), 555 MUX(MOUT_SHARED2_PLL, "mout_shared2_pll", mout_shared2_pll_p, 556 PLL_CON0_PLL_SHARED2, 4, 1), 557 MUX(MOUT_SHARED3_PLL, "mout_shared3_pll", mout_shared3_pll_p, 558 PLL_CON0_PLL_SHARED3, 4, 1), 559 MUX(MOUT_SHARED4_PLL, "mout_shared4_pll", mout_shared4_pll_p, 560 PLL_CON0_PLL_SHARED4, 4, 1), 561 MUX(MOUT_SHARED5_PLL, "mout_shared5_pll", mout_shared5_pll_p, 562 PLL_CON0_PLL_SHARED5, 4, 1), 563 MUX(MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, 564 PLL_CON0_PLL_MMC, 4, 1), 565 566 /* BOOST */ 567 MUX(MOUT_CLKCMU_CMU_BOOST, "mout_clkcmu_cmu_boost", 568 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2), 569 MUX(MOUT_CLKCMU_CMU_CMUREF, "mout_clkcmu_cmu_cmuref", 570 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), 571 572 /* ACC */ 573 MUX(MOUT_CLKCMU_ACC_NOC, "mout_clkcmu_acc_noc", 574 mout_clkcmu_acc_noc_p, CLK_CON_MUX_MUX_CLKCMU_ACC_NOC, 0, 3), 575 MUX(MOUT_CLKCMU_ACC_ORB, "mout_clkcmu_acc_orb", 576 mout_clkcmu_acc_orb_p, CLK_CON_MUX_MUX_CLKCMU_ACC_ORB, 0, 3), 577 578 /* APM */ 579 MUX(MOUT_CLKCMU_APM_NOC, "mout_clkcmu_apm_noc", 580 mout_clkcmu_apm_noc_p, CLK_CON_MUX_MUX_CLKCMU_APM_NOC, 0, 2), 581 582 /* AUD */ 583 MUX(MOUT_CLKCMU_AUD_CPU, "mout_clkcmu_aud_cpu", 584 mout_clkcmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3), 585 MUX(MOUT_CLKCMU_AUD_NOC, "mout_clkcmu_aud_noc", 586 mout_clkcmu_aud_noc_p, CLK_CON_MUX_MUX_CLKCMU_AUD_NOC, 0, 2), 587 588 /* CPUCL0 */ 589 MUX(MOUT_CLKCMU_CPUCL0_SWITCH, "mout_clkcmu_cpucl0_switch", 590 mout_clkcmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 591 0, 2), 592 MUX(MOUT_CLKCMU_CPUCL0_CLUSTER, "mout_clkcmu_cpucl0_cluster", 593 mout_clkcmu_cpucl0_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 594 0, 3), 595 MUX(MOUT_CLKCMU_CPUCL0_DBG, "mout_clkcmu_cpucl0_dbg", 596 mout_clkcmu_cpucl0_dbg_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 597 0, 2), 598 599 /* CPUCL1 */ 600 MUX(MOUT_CLKCMU_CPUCL1_SWITCH, "mout_clkcmu_cpucl1_switch", 601 mout_clkcmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 602 0, 2), 603 MUX(MOUT_CLKCMU_CPUCL1_CLUSTER, "mout_clkcmu_cpucl1_cluster", 604 mout_clkcmu_cpucl1_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 605 0, 3), 606 607 /* CPUCL2 */ 608 MUX(MOUT_CLKCMU_CPUCL2_SWITCH, "mout_clkcmu_cpucl2_switch", 609 mout_clkcmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 610 0, 2), 611 MUX(MOUT_CLKCMU_CPUCL2_CLUSTER, "mout_clkcmu_cpucl2_cluster", 612 mout_clkcmu_cpucl2_cluster_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_CLUSTER, 613 0, 3), 614 615 /* DNC */ 616 MUX(MOUT_CLKCMU_DNC_NOC, "mout_clkcmu_dnc_noc", 617 mout_clkcmu_dnc_noc_p, CLK_CON_MUX_MUX_CLKCMU_DNC_NOC, 0, 3), 618 619 /* DPTX */ 620 MUX(MOUT_CLKCMU_DPTX_NOC, "mout_clkcmu_dptx_noc", 621 mout_clkcmu_dptx_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_NOC, 0, 2), 622 MUX(MOUT_CLKCMU_DPTX_DPGTC, "mout_clkcmu_dptx_dpgtc", 623 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2), 624 MUX(MOUT_CLKCMU_DPTX_DPOSC, "mout_clkcmu_dptx_dposc", 625 mout_clkcmu_dptx_dposc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPOSC, 0, 1), 626 627 /* DPUB */ 628 MUX(MOUT_CLKCMU_DPUB_NOC, "mout_clkcmu_dpub_noc", 629 mout_clkcmu_dpub_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_NOC, 0, 3), 630 MUX(MOUT_CLKCMU_DPUB_DSIM, "mout_clkcmu_dpub_dsim", 631 mout_clkcmu_dpub_dsim_p, CLK_CON_MUX_MUX_CLKCMU_DPUB_DSIM, 0, 1), 632 633 /* DPUF */ 634 MUX(MOUT_CLKCMU_DPUF0_NOC, "mout_clkcmu_dpuf0_noc", 635 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF0_NOC, 0, 3), 636 MUX(MOUT_CLKCMU_DPUF1_NOC, "mout_clkcmu_dpuf1_noc", 637 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF1_NOC, 0, 3), 638 MUX(MOUT_CLKCMU_DPUF2_NOC, "mout_clkcmu_dpuf2_noc", 639 mout_clkcmu_dpuf_noc_p, CLK_CON_MUX_MUX_CLKCMU_DPUF2_NOC, 0, 3), 640 641 /* DSP */ 642 MUX(MOUT_CLKCMU_DSP_NOC, "mout_clkcmu_dsp_noc", 643 mout_clkcmu_dsp_noc_p, CLK_CON_MUX_MUX_CLKCMU_DSP_NOC, 0, 3), 644 645 /* G3D */ 646 MUX(MOUT_CLKCMU_G3D_SWITCH, "mout_clkcmu_g3d_switch", 647 mout_clkcmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), 648 MUX(MOUT_CLKCMU_G3D_NOCP, "mout_clkcmu_g3d_nocp", 649 mout_clkcmu_g3d_nocp_p, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCP, 0, 2), 650 651 /* GNPU */ 652 MUX(MOUT_CLKCMU_GNPU_NOC, "mout_clkcmu_gnpu_noc", 653 mout_clkcmu_gnpu_noc_p, CLK_CON_MUX_MUX_CLKCMU_GNPU_NOC, 0, 3), 654 655 /* HSI0 */ 656 MUX(MOUT_CLKCMU_HSI0_NOC, "mout_clkcmu_hsi0_noc", 657 mout_clkcmu_hsi0_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0, 2), 658 659 /* HSI1 */ 660 MUX(MOUT_CLKCMU_HSI1_NOC, "mout_clkcmu_hsi1_noc", 661 mout_clkcmu_hsi1_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, 662 0, 2), 663 MUX(MOUT_CLKCMU_HSI1_USBDRD, "mout_clkcmu_hsi1_usbdrd", 664 mout_clkcmu_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_USBDRD, 665 0, 2), 666 MUX(MOUT_CLKCMU_HSI1_MMC_CARD, "mout_clkcmu_hsi1_mmc_card", 667 mout_clkcmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD, 668 0, 2), 669 670 /* HSI2 */ 671 MUX(MOUT_CLKCMU_HSI2_NOC, "mout_clkcmu_hsi2_noc", 672 mout_clkcmu_hsi2_noc_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC, 673 0, 2), 674 MUX(MOUT_CLKCMU_HSI2_NOC_UFS, "mout_clkcmu_hsi2_noc_ufs", 675 mout_clkcmu_hsi2_noc_ufs_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_UFS, 676 0, 2), 677 MUX(MOUT_CLKCMU_HSI2_UFS_EMBD, "mout_clkcmu_hsi2_ufs_embd", 678 mout_clkcmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 679 0, 2), 680 MUX(MOUT_CLKCMU_HSI2_ETHERNET, "mout_clkcmu_hsi2_ethernet", 681 mout_clkcmu_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_ETHERNET, 682 0, 2), 683 684 /* ISP */ 685 MUX(MOUT_CLKCMU_ISP_NOC, "mout_clkcmu_isp_noc", 686 mout_clkcmu_isp_noc_p, CLK_CON_MUX_MUX_CLKCMU_ISP_NOC, 0, 3), 687 688 /* M2M */ 689 MUX(MOUT_CLKCMU_M2M_NOC, "mout_clkcmu_m2m_noc", 690 mout_clkcmu_m2m_noc_p, CLK_CON_MUX_MUX_CLKCMU_M2M_NOC, 0, 2), 691 MUX(MOUT_CLKCMU_M2M_JPEG, "mout_clkcmu_m2m_jpeg", 692 mout_clkcmu_m2m_jpeg_p, CLK_CON_MUX_MUX_CLKCMU_M2M_JPEG, 0, 2), 693 694 /* MFC */ 695 MUX(MOUT_CLKCMU_MFC_MFC, "mout_clkcmu_mfc_mfc", 696 mout_clkcmu_mfc_mfc_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2), 697 MUX(MOUT_CLKCMU_MFC_WFD, "mout_clkcmu_mfc_wfd", 698 mout_clkcmu_mfc_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2), 699 700 /* MFD */ 701 MUX(MOUT_CLKCMU_MFD_NOC, "mout_clkcmu_mfd_noc", 702 mout_clkcmu_mfd_noc_p, CLK_CON_MUX_MUX_CLKCMU_MFD_NOC, 0, 3), 703 704 /* MIF */ 705 MUX(MOUT_CLKCMU_MIF_SWITCH, "mout_clkcmu_mif_switch", 706 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), 707 MUX(MOUT_CLKCMU_MIF_NOCP, "mout_clkcmu_mif_nocp", 708 mout_clkcmu_mif_nocp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0, 2), 709 710 /* MISC */ 711 MUX(MOUT_CLKCMU_MISC_NOC, "mout_clkcmu_misc_noc", 712 mout_clkcmu_misc_noc_p, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0, 2), 713 714 /* NOCL0 */ 715 MUX(MOUT_CLKCMU_NOCL0_NOC, "mout_clkcmu_nocl0_noc", 716 mout_clkcmu_nocl0_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0, 3), 717 718 /* NOCL1 */ 719 MUX(MOUT_CLKCMU_NOCL1_NOC, "mout_clkcmu_nocl1_noc", 720 mout_clkcmu_nocl1_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL1_NOC, 0, 3), 721 722 /* NOCL2 */ 723 MUX(MOUT_CLKCMU_NOCL2_NOC, "mout_clkcmu_nocl2_noc", 724 mout_clkcmu_nocl2_noc_p, CLK_CON_MUX_MUX_CLKCMU_NOCL2_NOC, 0, 3), 725 726 /* PERIC0 */ 727 MUX(MOUT_CLKCMU_PERIC0_NOC, "mout_clkcmu_peric0_noc", 728 mout_clkcmu_peric0_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0, 1), 729 MUX(MOUT_CLKCMU_PERIC0_IP, "mout_clkcmu_peric0_ip", 730 mout_clkcmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1), 731 732 /* PERIC1 */ 733 MUX(MOUT_CLKCMU_PERIC1_NOC, "mout_clkcmu_peric1_noc", 734 mout_clkcmu_peric1_noc_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0, 1), 735 MUX(MOUT_CLKCMU_PERIC1_IP, "mout_clkcmu_peric1_ip", 736 mout_clkcmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1), 737 738 /* SDMA */ 739 MUX(MOUT_CLKCMU_SDMA_NOC, "mout_clkcmu_sdma_noc", 740 mout_clkcmu_sdma_noc_p, CLK_CON_MUX_MUX_CLKCMU_SDMA_NOC, 0, 3), 741 742 /* SNW */ 743 MUX(MOUT_CLKCMU_SNW_NOC, "mout_clkcmu_snw_noc", 744 mout_clkcmu_snw_noc_p, CLK_CON_MUX_MUX_CLKCMU_SNW_NOC, 0, 3), 745 746 /* SSP */ 747 MUX(MOUT_CLKCMU_SSP_NOC, "mout_clkcmu_ssp_noc", 748 mout_clkcmu_ssp_noc_p, CLK_CON_MUX_MUX_CLKCMU_SSP_NOC, 0, 2), 749 750 /* TAA */ 751 MUX(MOUT_CLKCMU_TAA_NOC, "mout_clkcmu_taa_noc", 752 mout_clkcmu_taa_noc_p, CLK_CON_MUX_MUX_CLKCMU_TAA_NOC, 0, 3), 753 }; 754 755 static const struct samsung_div_clock top_div_clks[] __initconst = { 756 /* CMU_TOP_PURECLKCOMP */ 757 758 /* BOOST */ 759 DIV(DOUT_CLKCMU_CMU_BOOST, "dout_clkcmu_cmu_boost", 760 "mout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2), 761 762 /* ACC */ 763 DIV(DOUT_CLKCMU_ACC_NOC, "dout_clkcmu_acc_noc", 764 "mout_clkcmu_acc_noc", CLK_CON_DIV_CLKCMU_ACC_NOC, 0, 4), 765 DIV(DOUT_CLKCMU_ACC_ORB, "dout_clkcmu_acc_orb", 766 "mout_clkcmu_acc_orb", CLK_CON_DIV_CLKCMU_ACC_ORB, 0, 4), 767 768 /* APM */ 769 DIV(DOUT_CLKCMU_APM_NOC, "dout_clkcmu_apm_noc", 770 "mout_clkcmu_apm_noc", CLK_CON_DIV_CLKCMU_APM_NOC, 0, 3), 771 772 /* AUD */ 773 DIV(DOUT_CLKCMU_AUD_CPU, "dout_clkcmu_aud_cpu", 774 "mout_clkcmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3), 775 DIV(DOUT_CLKCMU_AUD_NOC, "dout_clkcmu_aud_noc", 776 "mout_clkcmu_aud_noc", CLK_CON_DIV_CLKCMU_AUD_NOC, 0, 4), 777 778 /* CPUCL0 */ 779 DIV(DOUT_CLKCMU_CPUCL0_SWITCH, "dout_clkcmu_cpucl0_switch", 780 "mout_clkcmu_cpucl0_switch", 781 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), 782 DIV(DOUT_CLKCMU_CPUCL0_CLUSTER, "dout_clkcmu_cpucl0_cluster", 783 "mout_clkcmu_cpucl0_cluster", 784 CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER, 0, 3), 785 DIV(DOUT_CLKCMU_CPUCL0_DBG, "dout_clkcmu_cpucl0_dbg", 786 "mout_clkcmu_cpucl0_dbg", 787 CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4), 788 789 /* CPUCL1 */ 790 DIV(DOUT_CLKCMU_CPUCL1_SWITCH, "dout_clkcmu_cpucl1_switch", 791 "mout_clkcmu_cpucl1_switch", 792 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), 793 DIV(DOUT_CLKCMU_CPUCL1_CLUSTER, "dout_clkcmu_cpucl1_cluster", 794 "mout_clkcmu_cpucl1_cluster", 795 CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER, 0, 3), 796 797 /* CPUCL2 */ 798 DIV(DOUT_CLKCMU_CPUCL2_SWITCH, "dout_clkcmu_cpucl2_switch", 799 "mout_clkcmu_cpucl2_switch", 800 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3), 801 DIV(DOUT_CLKCMU_CPUCL2_CLUSTER, "dout_clkcmu_cpucl2_cluster", 802 "mout_clkcmu_cpucl2_cluster", 803 CLK_CON_DIV_CLKCMU_CPUCL2_CLUSTER, 0, 3), 804 805 /* DNC */ 806 DIV(DOUT_CLKCMU_DNC_NOC, "dout_clkcmu_dnc_noc", 807 "mout_clkcmu_dnc_noc", CLK_CON_DIV_CLKCMU_DNC_NOC, 0, 4), 808 809 /* DPTX */ 810 DIV(DOUT_CLKCMU_DPTX_NOC, "dout_clkcmu_dptx_noc", 811 "mout_clkcmu_dptx_noc", CLK_CON_DIV_CLKCMU_DPTX_NOC, 0, 4), 812 DIV(DOUT_CLKCMU_DPTX_DPGTC, "dout_clkcmu_dptx_dpgtc", 813 "mout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3), 814 DIV(DOUT_CLKCMU_DPTX_DPOSC, "dout_clkcmu_dptx_dposc", 815 "mout_clkcmu_dptx_dposc", CLK_CON_DIV_CLKCMU_DPTX_DPOSC, 0, 5), 816 817 /* DPUB */ 818 DIV(DOUT_CLKCMU_DPUB_NOC, "dout_clkcmu_dpub_noc", 819 "mout_clkcmu_dpub_noc", CLK_CON_DIV_CLKCMU_DPUB_NOC, 0, 4), 820 DIV(DOUT_CLKCMU_DPUB_DSIM, "dout_clkcmu_dpub_dsim", 821 "mout_clkcmu_dpub_dsim", CLK_CON_DIV_CLKCMU_DPUB_DSIM, 0, 4), 822 823 /* DPUF */ 824 DIV(DOUT_CLKCMU_DPUF0_NOC, "dout_clkcmu_dpuf0_noc", 825 "mout_clkcmu_dpuf0_noc", CLK_CON_DIV_CLKCMU_DPUF0_NOC, 0, 4), 826 DIV(DOUT_CLKCMU_DPUF1_NOC, "dout_clkcmu_dpuf1_noc", 827 "mout_clkcmu_dpuf1_noc", CLK_CON_DIV_CLKCMU_DPUF1_NOC, 0, 4), 828 DIV(DOUT_CLKCMU_DPUF2_NOC, "dout_clkcmu_dpuf2_noc", 829 "mout_clkcmu_dpuf2_noc", CLK_CON_DIV_CLKCMU_DPUF2_NOC, 0, 4), 830 831 /* DSP */ 832 DIV(DOUT_CLKCMU_DSP_NOC, "dout_clkcmu_dsp_noc", 833 "mout_clkcmu_dsp_noc", CLK_CON_DIV_CLKCMU_DSP_NOC, 0, 4), 834 835 /* G3D */ 836 DIV(DOUT_CLKCMU_G3D_SWITCH, "dout_clkcmu_g3d_switch", 837 "mout_clkcmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), 838 DIV(DOUT_CLKCMU_G3D_NOCP, "dout_clkcmu_g3d_nocp", 839 "mout_clkcmu_g3d_nocp", CLK_CON_DIV_CLKCMU_G3D_NOCP, 0, 3), 840 841 /* GNPU */ 842 DIV(DOUT_CLKCMU_GNPU_NOC, "dout_clkcmu_gnpu_noc", 843 "mout_clkcmu_gnpu_noc", CLK_CON_DIV_CLKCMU_GNPU_NOC, 0, 4), 844 845 /* HSI0 */ 846 DIV(DOUT_CLKCMU_HSI0_NOC, "dout_clkcmu_hsi0_noc", 847 "mout_clkcmu_hsi0_noc", CLK_CON_DIV_CLKCMU_HSI0_NOC, 0, 4), 848 849 /* HSI1 */ 850 DIV(DOUT_CLKCMU_HSI1_NOC, "dout_clkcmu_hsi1_noc", 851 "mout_clkcmu_hsi1_noc", CLK_CON_DIV_CLKCMU_HSI1_NOC, 0, 4), 852 DIV(DOUT_CLKCMU_HSI1_USBDRD, "dout_clkcmu_hsi1_usbdrd", 853 "mout_clkcmu_hsi1_usbdrd", CLK_CON_DIV_CLKCMU_HSI1_USBDRD, 0, 4), 854 DIV(DOUT_CLKCMU_HSI1_MMC_CARD, "dout_clkcmu_hsi1_mmc_card", 855 "mout_clkcmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9), 856 857 /* HSI2 */ 858 DIV(DOUT_CLKCMU_HSI2_NOC, "dout_clkcmu_hsi2_noc", 859 "mout_clkcmu_hsi2_noc", CLK_CON_DIV_CLKCMU_HSI2_NOC, 0, 4), 860 DIV(DOUT_CLKCMU_HSI2_NOC_UFS, "dout_clkcmu_hsi2_noc_ufs", 861 "mout_clkcmu_hsi2_noc_ufs", CLK_CON_DIV_CLKCMU_HSI2_NOC_UFS, 0, 4), 862 DIV(DOUT_CLKCMU_HSI2_UFS_EMBD, "dout_clkcmu_hsi2_ufs_embd", 863 "mout_clkcmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 3), 864 DIV(DOUT_CLKCMU_HSI2_ETHERNET, "dout_clkcmu_hsi2_ethernet", 865 "mout_clkcmu_hsi2_ethernet", CLK_CON_DIV_CLKCMU_HSI2_ETHERNET, 0, 3), 866 867 /* ISP */ 868 DIV(DOUT_CLKCMU_ISP_NOC, "dout_clkcmu_isp_noc", 869 "mout_clkcmu_isp_noc", CLK_CON_DIV_CLKCMU_ISP_NOC, 0, 4), 870 871 /* M2M */ 872 DIV(DOUT_CLKCMU_M2M_NOC, "dout_clkcmu_m2m_noc", 873 "mout_clkcmu_m2m_noc", CLK_CON_DIV_CLKCMU_M2M_NOC, 0, 4), 874 DIV(DOUT_CLKCMU_M2M_JPEG, "dout_clkcmu_m2m_jpeg", 875 "mout_clkcmu_m2m_jpeg", CLK_CON_DIV_CLKCMU_M2M_JPEG, 0, 4), 876 877 /* MFC */ 878 DIV(DOUT_CLKCMU_MFC_MFC, "dout_clkcmu_mfc_mfc", 879 "mout_clkcmu_mfc_mfc", CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), 880 DIV(DOUT_CLKCMU_MFC_WFD, "dout_clkcmu_mfc_wfd", 881 "mout_clkcmu_mfc_wfd", CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4), 882 883 /* MFD */ 884 DIV(DOUT_CLKCMU_MFD_NOC, "dout_clkcmu_mfd_noc", 885 "mout_clkcmu_mfd_noc", CLK_CON_DIV_CLKCMU_MFD_NOC, 0, 4), 886 887 /* MIF */ 888 DIV(DOUT_CLKCMU_MIF_NOCP, "dout_clkcmu_mif_nocp", 889 "mout_clkcmu_mif_nocp", CLK_CON_DIV_CLKCMU_MIF_NOCP, 0, 4), 890 891 /* MISC */ 892 DIV(DOUT_CLKCMU_MISC_NOC, "dout_clkcmu_misc_noc", 893 "mout_clkcmu_misc_noc", CLK_CON_DIV_CLKCMU_MISC_NOC, 0, 4), 894 895 /* NOCL0 */ 896 DIV(DOUT_CLKCMU_NOCL0_NOC, "dout_clkcmu_nocl0_noc", 897 "mout_clkcmu_nocl0_noc", CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0, 4), 898 899 /* NOCL1 */ 900 DIV(DOUT_CLKCMU_NOCL1_NOC, "dout_clkcmu_nocl1_noc", 901 "mout_clkcmu_nocl1_noc", CLK_CON_DIV_CLKCMU_NOCL1_NOC, 0, 4), 902 903 /* NOCL2 */ 904 DIV(DOUT_CLKCMU_NOCL2_NOC, "dout_clkcmu_nocl2_noc", 905 "mout_clkcmu_nocl2_noc", CLK_CON_DIV_CLKCMU_NOCL2_NOC, 0, 4), 906 907 /* PERIC0 */ 908 DIV(DOUT_CLKCMU_PERIC0_NOC, "dout_clkcmu_peric0_noc", 909 "mout_clkcmu_peric0_noc", CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0, 4), 910 DIV(DOUT_CLKCMU_PERIC0_IP, "dout_clkcmu_peric0_ip", 911 "mout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4), 912 913 /* PERIC1 */ 914 DIV(DOUT_CLKCMU_PERIC1_NOC, "dout_clkcmu_peric1_noc", 915 "mout_clkcmu_peric1_noc", CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0, 4), 916 DIV(DOUT_CLKCMU_PERIC1_IP, "dout_clkcmu_peric1_ip", 917 "mout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4), 918 919 /* SDMA */ 920 DIV(DOUT_CLKCMU_SDMA_NOC, "dout_clkcmu_sdma_noc", 921 "mout_clkcmu_sdma_noc", CLK_CON_DIV_CLKCMU_SDMA_NOC, 0, 4), 922 923 /* SNW */ 924 DIV(DOUT_CLKCMU_SNW_NOC, "dout_clkcmu_snw_noc", 925 "mout_clkcmu_snw_noc", CLK_CON_DIV_CLKCMU_SNW_NOC, 0, 4), 926 927 /* SSP */ 928 DIV(DOUT_CLKCMU_SSP_NOC, "dout_clkcmu_ssp_noc", 929 "mout_clkcmu_ssp_noc", CLK_CON_DIV_CLKCMU_SSP_NOC, 0, 4), 930 931 /* TAA */ 932 DIV(DOUT_CLKCMU_TAA_NOC, "dout_clkcmu_taa_noc", 933 "mout_clkcmu_taa_noc", CLK_CON_DIV_CLKCMU_TAA_NOC, 0, 4), 934 }; 935 936 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { 937 FFACTOR(DOUT_SHARED0_DIV1, "dout_shared0_div1", 938 "mout_shared0_pll", 1, 1, 0), 939 FFACTOR(DOUT_SHARED0_DIV2, "dout_shared0_div2", 940 "mout_shared0_pll", 1, 2, 0), 941 FFACTOR(DOUT_SHARED0_DIV3, "dout_shared0_div3", 942 "mout_shared0_pll", 1, 3, 0), 943 FFACTOR(DOUT_SHARED0_DIV4, "dout_shared0_div4", 944 "mout_shared0_pll", 1, 4, 0), 945 FFACTOR(DOUT_SHARED1_DIV1, "dout_shared1_div1", 946 "mout_shared1_pll", 1, 1, 0), 947 FFACTOR(DOUT_SHARED1_DIV2, "dout_shared1_div2", 948 "mout_shared1_pll", 1, 2, 0), 949 FFACTOR(DOUT_SHARED1_DIV3, "dout_shared1_div3", 950 "mout_shared1_pll", 1, 3, 0), 951 FFACTOR(DOUT_SHARED1_DIV4, "dout_shared1_div4", 952 "mout_shared1_pll", 1, 4, 0), 953 FFACTOR(DOUT_SHARED2_DIV1, "dout_shared2_div1", 954 "mout_shared2_pll", 1, 1, 0), 955 FFACTOR(DOUT_SHARED2_DIV2, "dout_shared2_div2", 956 "mout_shared2_pll", 1, 2, 0), 957 FFACTOR(DOUT_SHARED2_DIV3, "dout_shared2_div3", 958 "mout_shared2_pll", 1, 3, 0), 959 FFACTOR(DOUT_SHARED2_DIV4, "dout_shared2_div4", 960 "mout_shared2_pll", 1, 4, 0), 961 FFACTOR(DOUT_SHARED3_DIV1, "dout_shared3_div1", 962 "mout_shared3_pll", 1, 1, 0), 963 FFACTOR(DOUT_SHARED3_DIV2, "dout_shared3_div2", 964 "mout_shared3_pll", 1, 2, 0), 965 FFACTOR(DOUT_SHARED3_DIV3, "dout_shared3_div3", 966 "mout_shared3_pll", 1, 3, 0), 967 FFACTOR(DOUT_SHARED3_DIV4, "dout_shared3_div4", 968 "mout_shared3_pll", 1, 4, 0), 969 FFACTOR(DOUT_SHARED4_DIV1, "dout_shared4_div1", 970 "mout_shared4_pll", 1, 1, 0), 971 FFACTOR(DOUT_SHARED4_DIV2, "dout_shared4_div2", 972 "mout_shared4_pll", 1, 2, 0), 973 FFACTOR(DOUT_SHARED4_DIV3, "dout_shared4_div3", 974 "mout_shared4_pll", 1, 3, 0), 975 FFACTOR(DOUT_SHARED4_DIV4, "dout_shared4_div4", 976 "mout_shared4_pll", 1, 4, 0), 977 FFACTOR(DOUT_SHARED5_DIV1, "dout_shared5_div1", 978 "mout_shared5_pll", 1, 1, 0), 979 FFACTOR(DOUT_SHARED5_DIV2, "dout_shared5_div2", 980 "mout_shared5_pll", 1, 2, 0), 981 FFACTOR(DOUT_SHARED5_DIV3, "dout_shared5_div3", 982 "mout_shared5_pll", 1, 3, 0), 983 FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4", 984 "mout_shared5_pll", 1, 4, 0), 985 FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2", 986 "oscclk", 1, 2, 0), 987 }; 988 989 static const struct samsung_cmu_info top_cmu_info __initconst = { 990 .pll_clks = top_pll_clks, 991 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 992 .mux_clks = top_mux_clks, 993 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 994 .div_clks = top_div_clks, 995 .nr_div_clks = ARRAY_SIZE(top_div_clks), 996 .fixed_factor_clks = top_fixed_factor_clks, 997 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 998 .nr_clk_ids = CLKS_NR_TOP, 999 .clk_regs = top_clk_regs, 1000 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 1001 }; 1002 1003 static void __init exynosautov920_cmu_top_init(struct device_node *np) 1004 { 1005 exynos_arm64_register_cmu(NULL, np, &top_cmu_info); 1006 } 1007 1008 /* Register CMU_TOP early, as it's a dependency for other early domains */ 1009 CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top", 1010 exynosautov920_cmu_top_init); 1011 1012 /* ---- CMU_CPUCL0 --------------------------------------------------------- */ 1013 1014 /* Register Offset definitions for CMU_CPUCL0 (0x1EC00000) */ 1015 #define PLL_LOCKTIME_PLL_CPUCL0 0x0000 1016 #define PLL_CON0_PLL_CPUCL0 0x0100 1017 #define PLL_CON1_PLL_CPUCL0 0x0104 1018 #define PLL_CON3_PLL_CPUCL0 0x010c 1019 #define PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER 0x0600 1020 #define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0610 1021 #define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0620 1022 1023 #define CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER 0x1000 1024 #define CLK_CON_MUX_MUX_CLK_CPUCL0_CORE 0x1004 1025 1026 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800 1027 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1804 1028 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK 0x1808 1029 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK 0x180c 1030 #define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810 1031 #define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC 0x181c 1032 #define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG 0x1820 1033 #define CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP 0x1824 1034 1035 static const unsigned long cpucl0_clk_regs[] __initconst = { 1036 PLL_LOCKTIME_PLL_CPUCL0, 1037 PLL_CON0_PLL_CPUCL0, 1038 PLL_CON1_PLL_CPUCL0, 1039 PLL_CON3_PLL_CPUCL0, 1040 PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER, 1041 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 1042 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 1043 CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER, 1044 CLK_CON_MUX_MUX_CLK_CPUCL0_CORE, 1045 CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 1046 CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 1047 CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK, 1048 CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, 1049 CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 1050 CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 1051 CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 1052 CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP, 1053 }; 1054 1055 /* List of parent clocks for Muxes in CMU_CPUCL0 */ 1056 PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" }; 1057 PNAME(mout_cpucl0_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl0_cluster" }; 1058 PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_clkcmu_cpucl0_dbg" }; 1059 PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl0_switch" }; 1060 PNAME(mout_cpucl0_cluster_p) = { "oscclk", "mout_cpucl0_cluster_user", 1061 "mout_cpucl0_switch_user"}; 1062 PNAME(mout_cpucl0_core_p) = { "oscclk", "mout_pll_cpucl0", 1063 "mout_cpucl0_switch_user"}; 1064 1065 static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = { 1066 PLL_35XX_RATE(38400000U, 2400000000U, 250, 4, 0), 1067 PLL_35XX_RATE(38400000U, 2304000000U, 240, 4, 0), 1068 PLL_35XX_RATE(38400000U, 2208000000U, 230, 4, 0), 1069 PLL_35XX_RATE(38400000U, 2112000000U, 220, 4, 0), 1070 PLL_35XX_RATE(38400000U, 2016000000U, 210, 4, 0), 1071 PLL_35XX_RATE(38400000U, 1824000000U, 190, 4, 0), 1072 PLL_35XX_RATE(38400000U, 1680000000U, 175, 4, 0), 1073 PLL_35XX_RATE(38400000U, 1344000000U, 140, 4, 0), 1074 PLL_35XX_RATE(38400000U, 1152000000U, 120, 4, 0), 1075 PLL_35XX_RATE(38400000U, 576000000U, 120, 4, 1), 1076 PLL_35XX_RATE(38400000U, 288000000U, 120, 4, 2), 1077 }; 1078 1079 static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = { 1080 /* CMU_CPUCL0_PURECLKCOMP */ 1081 PLL(pll_531x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk", 1082 PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates), 1083 }; 1084 1085 static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = { 1086 MUX(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p, 1087 PLL_CON0_PLL_CPUCL0, 4, 1), 1088 MUX(CLK_MOUT_CPUCL0_CLUSTER_USER, "mout_cpucl0_cluster_user", mout_cpucl0_cluster_user_p, 1089 PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER, 4, 1), 1090 MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user", mout_cpucl0_dbg_user_p, 1091 PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1), 1092 MUX(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user", mout_cpucl0_switch_user_p, 1093 PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1), 1094 MUX(CLK_MOUT_CPUCL0_CLUSTER, "mout_cpucl0_cluster", mout_cpucl0_cluster_p, 1095 CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER, 0, 2), 1096 MUX(CLK_MOUT_CPUCL0_CORE, "mout_cpucl0_core", mout_cpucl0_core_p, 1097 CLK_CON_MUX_MUX_CLK_CPUCL0_CORE, 0, 2), 1098 }; 1099 1100 static const struct samsung_div_clock cpucl0_div_clks[] __initconst = { 1101 DIV(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk", 1102 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4), 1103 DIV(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk", 1104 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4), 1105 DIV(CLK_DOUT_CLUSTER0_MPCLK, "dout_cluster0_mpclk", 1106 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK, 0, 4), 1107 DIV(CLK_DOUT_CLUSTER0_PCLK, "dout_cluster0_pclk", 1108 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, 0, 4), 1109 DIV(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk", 1110 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4), 1111 DIV(CLK_DOUT_CPUCL0_DBG_NOC, "dout_cpucl0_dbg_noc", 1112 "mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 0, 3), 1113 DIV(CLK_DOUT_CPUCL0_DBG_PCLKDBG, "dout_cpucl0_dbg_pclkdbg", 1114 "mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0, 3), 1115 DIV(CLK_DOUT_CPUCL0_NOCP, "dout_cpucl0_nocp", 1116 "mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP, 0, 4), 1117 }; 1118 1119 static const struct samsung_cmu_info cpucl0_cmu_info __initconst = { 1120 .pll_clks = cpucl0_pll_clks, 1121 .nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks), 1122 .mux_clks = cpucl0_mux_clks, 1123 .nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks), 1124 .div_clks = cpucl0_div_clks, 1125 .nr_div_clks = ARRAY_SIZE(cpucl0_div_clks), 1126 .nr_clk_ids = CLKS_NR_CPUCL0, 1127 .clk_regs = cpucl0_clk_regs, 1128 .nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs), 1129 .clk_name = "cpucl0", 1130 }; 1131 1132 static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np) 1133 { 1134 exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info); 1135 } 1136 1137 /* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */ 1138 CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0", 1139 exynosautov920_cmu_cpucl0_init); 1140 1141 /* ---- CMU_CPUCL1 --------------------------------------------------------- */ 1142 1143 /* Register Offset definitions for CMU_CPUCL1 (0x1ED00000) */ 1144 #define PLL_LOCKTIME_PLL_CPUCL1 0x0000 1145 #define PLL_CON0_PLL_CPUCL1 0x0100 1146 #define PLL_CON1_PLL_CPUCL1 0x0104 1147 #define PLL_CON3_PLL_CPUCL1 0x010c 1148 #define PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER 0x0600 1149 #define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610 1150 1151 #define CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER 0x1000 1152 #define CLK_CON_MUX_MUX_CLK_CPUCL1_CORE 0x1004 1153 1154 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800 1155 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1804 1156 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK 0x1808 1157 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK 0x180c 1158 #define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810 1159 #define CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP 0x181c 1160 1161 static const unsigned long cpucl1_clk_regs[] __initconst = { 1162 PLL_LOCKTIME_PLL_CPUCL1, 1163 PLL_CON0_PLL_CPUCL1, 1164 PLL_CON1_PLL_CPUCL1, 1165 PLL_CON3_PLL_CPUCL1, 1166 PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 1167 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 1168 CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 1169 CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 1170 CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 1171 CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 1172 CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 1173 CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 1174 CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 1175 CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 1176 }; 1177 1178 /* List of parent clocks for Muxes in CMU_CPUCL1 */ 1179 PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" }; 1180 PNAME(mout_cpucl1_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl1_cluster" }; 1181 PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl1_switch" }; 1182 PNAME(mout_cpucl1_cluster_p) = { "oscclk", "mout_cpucl1_cluster_user", 1183 "mout_cpucl1_switch_user"}; 1184 PNAME(mout_cpucl1_core_p) = { "oscclk", "mout_pll_cpucl1", 1185 "mout_cpucl1_switch_user"}; 1186 1187 static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = { 1188 /* CMU_CPUCL1_PURECLKCOMP */ 1189 PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk", 1190 PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates), 1191 }; 1192 1193 static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = { 1194 MUX(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p, 1195 PLL_CON0_PLL_CPUCL1, 4, 1), 1196 MUX(CLK_MOUT_CPUCL1_CLUSTER_USER, "mout_cpucl1_cluster_user", mout_cpucl1_cluster_user_p, 1197 PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 4, 1), 1198 MUX(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user", mout_cpucl1_switch_user_p, 1199 PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1), 1200 MUX(CLK_MOUT_CPUCL1_CLUSTER, "mout_cpucl1_cluster", mout_cpucl1_cluster_p, 1201 CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 0, 2), 1202 MUX(CLK_MOUT_CPUCL1_CORE, "mout_cpucl1_core", mout_cpucl1_core_p, 1203 CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0, 2), 1204 }; 1205 1206 static const struct samsung_div_clock cpucl1_div_clks[] __initconst = { 1207 DIV(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", 1208 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4), 1209 DIV(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk", 1210 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4), 1211 DIV(CLK_DOUT_CLUSTER1_MPCLK, "dout_cluster1_mpclk", 1212 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 0, 4), 1213 DIV(CLK_DOUT_CLUSTER1_PCLK, "dout_cluster1_pclk", 1214 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 0, 4), 1215 DIV(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk", 1216 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4), 1217 DIV(CLK_DOUT_CPUCL1_NOCP, "dout_cpucl1_nocp", 1218 "mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 0, 4), 1219 }; 1220 1221 static const struct samsung_cmu_info cpucl1_cmu_info __initconst = { 1222 .pll_clks = cpucl1_pll_clks, 1223 .nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks), 1224 .mux_clks = cpucl1_mux_clks, 1225 .nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks), 1226 .div_clks = cpucl1_div_clks, 1227 .nr_div_clks = ARRAY_SIZE(cpucl1_div_clks), 1228 .nr_clk_ids = CLKS_NR_CPUCL1, 1229 .clk_regs = cpucl1_clk_regs, 1230 .nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs), 1231 .clk_name = "cpucl1", 1232 }; 1233 1234 static void __init exynosautov920_cmu_cpucl1_init(struct device_node *np) 1235 { 1236 exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info); 1237 } 1238 1239 /* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */ 1240 CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1", 1241 exynosautov920_cmu_cpucl1_init); 1242 1243 /* ---- CMU_CPUCL2 --------------------------------------------------------- */ 1244 1245 /* Register Offset definitions for CMU_CPUCL2 (0x1EE00000) */ 1246 #define PLL_LOCKTIME_PLL_CPUCL2 0x0000 1247 #define PLL_CON0_PLL_CPUCL2 0x0100 1248 #define PLL_CON1_PLL_CPUCL2 0x0104 1249 #define PLL_CON3_PLL_CPUCL2 0x010c 1250 #define PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER 0x0600 1251 #define PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER 0x0610 1252 1253 #define CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER 0x1000 1254 #define CLK_CON_MUX_MUX_CLK_CPUCL2_CORE 0x1004 1255 1256 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK 0x1800 1257 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK 0x1804 1258 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK 0x1808 1259 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK 0x180c 1260 #define CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK 0x1810 1261 #define CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP 0x181c 1262 1263 static const unsigned long cpucl2_clk_regs[] __initconst = { 1264 PLL_LOCKTIME_PLL_CPUCL2, 1265 PLL_CON0_PLL_CPUCL2, 1266 PLL_CON1_PLL_CPUCL2, 1267 PLL_CON3_PLL_CPUCL2, 1268 PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 1269 PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 1270 CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 1271 CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 1272 CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 1273 CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 1274 CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 1275 CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 1276 CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 1277 CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 1278 }; 1279 1280 /* List of parent clocks for Muxes in CMU_CPUCL2 */ 1281 PNAME(mout_pll_cpucl2_p) = { "oscclk", "fout_cpucl2_pll" }; 1282 PNAME(mout_cpucl2_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl2_cluster" }; 1283 PNAME(mout_cpucl2_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl2_switch" }; 1284 PNAME(mout_cpucl2_cluster_p) = { "oscclk", "mout_cpucl2_cluster_user", 1285 "mout_cpucl2_switch_user"}; 1286 PNAME(mout_cpucl2_core_p) = { "oscclk", "mout_pll_cpucl2", 1287 "mout_cpucl2_switch_user"}; 1288 1289 static const struct samsung_pll_clock cpucl2_pll_clks[] __initconst = { 1290 /* CMU_CPUCL2_PURECLKCOMP */ 1291 PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk", 1292 PLL_LOCKTIME_PLL_CPUCL2, PLL_CON3_PLL_CPUCL2, cpu_pll_rates), 1293 }; 1294 1295 static const struct samsung_mux_clock cpucl2_mux_clks[] __initconst = { 1296 MUX(CLK_MOUT_PLL_CPUCL2, "mout_pll_cpucl2", mout_pll_cpucl2_p, 1297 PLL_CON0_PLL_CPUCL2, 4, 1), 1298 MUX(CLK_MOUT_CPUCL2_CLUSTER_USER, "mout_cpucl2_cluster_user", mout_cpucl2_cluster_user_p, 1299 PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 4, 1), 1300 MUX(CLK_MOUT_CPUCL2_SWITCH_USER, "mout_cpucl2_switch_user", mout_cpucl2_switch_user_p, 1301 PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 4, 1), 1302 MUX(CLK_MOUT_CPUCL2_CLUSTER, "mout_cpucl2_cluster", mout_cpucl2_cluster_p, 1303 CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 0, 2), 1304 MUX(CLK_MOUT_CPUCL2_CORE, "mout_cpucl2_core", mout_cpucl2_core_p, 1305 CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0, 2), 1306 }; 1307 1308 static const struct samsung_div_clock cpucl2_div_clks[] __initconst = { 1309 DIV(CLK_DOUT_CLUSTER2_ACLK, "dout_cluster2_aclk", 1310 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 0, 4), 1311 DIV(CLK_DOUT_CLUSTER2_ATCLK, "dout_cluster2_atclk", 1312 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 0, 4), 1313 DIV(CLK_DOUT_CLUSTER2_MPCLK, "dout_cluster2_mpclk", 1314 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 0, 4), 1315 DIV(CLK_DOUT_CLUSTER2_PCLK, "dout_cluster2_pclk", 1316 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 0, 4), 1317 DIV(CLK_DOUT_CLUSTER2_PERIPHCLK, "dout_cluster2_periphclk", 1318 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 0, 4), 1319 DIV(CLK_DOUT_CPUCL2_NOCP, "dout_cpucl2_nocp", 1320 "mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 0, 4), 1321 }; 1322 1323 static const struct samsung_cmu_info cpucl2_cmu_info __initconst = { 1324 .pll_clks = cpucl2_pll_clks, 1325 .nr_pll_clks = ARRAY_SIZE(cpucl2_pll_clks), 1326 .mux_clks = cpucl2_mux_clks, 1327 .nr_mux_clks = ARRAY_SIZE(cpucl2_mux_clks), 1328 .div_clks = cpucl2_div_clks, 1329 .nr_div_clks = ARRAY_SIZE(cpucl2_div_clks), 1330 .nr_clk_ids = CLKS_NR_CPUCL2, 1331 .clk_regs = cpucl2_clk_regs, 1332 .nr_clk_regs = ARRAY_SIZE(cpucl2_clk_regs), 1333 .clk_name = "cpucl2", 1334 }; 1335 1336 static void __init exynosautov920_cmu_cpucl2_init(struct device_node *np) 1337 { 1338 exynos_arm64_register_cmu(NULL, np, &cpucl2_cmu_info); 1339 } 1340 1341 /* Register CMU_CPUCL2 early, as CPU clocks should be available ASAP */ 1342 CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2", 1343 exynosautov920_cmu_cpucl2_init); 1344 1345 /* ---- CMU_PERIC0 --------------------------------------------------------- */ 1346 1347 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */ 1348 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0600 1349 #define PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER 0x0610 1350 #define CLK_CON_MUX_MUX_CLK_PERIC0_I3C 0x1000 1351 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1004 1352 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1008 1353 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x100c 1354 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x1010 1355 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1014 1356 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1018 1357 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI 0x101c 1358 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI 0x1020 1359 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI 0x1024 1360 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1028 1361 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800 1362 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1804 1363 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1808 1364 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x180c 1365 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x1810 1366 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1814 1367 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1818 1368 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI 0x181c 1369 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI 0x1820 1370 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI 0x1824 1371 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1828 1372 1373 static const unsigned long peric0_clk_regs[] __initconst = { 1374 PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 1375 PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 1376 CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 1377 CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 1378 CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 1379 CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 1380 CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 1381 CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 1382 CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 1383 CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 1384 CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 1385 CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 1386 CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 1387 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 1388 CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 1389 CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 1390 CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 1391 CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 1392 CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 1393 CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 1394 CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI, 1395 CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI, 1396 CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI, 1397 CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 1398 }; 1399 1400 /* List of parent clocks for Muxes in CMU_PERIC0 */ 1401 PNAME(mout_peric0_ip_user_p) = { "oscclk", "dout_clkcmu_peric0_ip" }; 1402 PNAME(mout_peric0_noc_user_p) = { "oscclk", "dout_clkcmu_peric0_noc" }; 1403 PNAME(mout_peric0_usi_p) = { "oscclk", "mout_peric0_ip_user" }; 1404 1405 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { 1406 MUX(CLK_MOUT_PERIC0_IP_USER, "mout_peric0_ip_user", 1407 mout_peric0_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER, 4, 1), 1408 MUX(CLK_MOUT_PERIC0_NOC_USER, "mout_peric0_noc_user", 1409 mout_peric0_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 4, 1), 1410 /* USI00 ~ USI08 */ 1411 MUX(CLK_MOUT_PERIC0_USI00_USI, "mout_peric0_usi00_usi", 1412 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1), 1413 MUX(CLK_MOUT_PERIC0_USI01_USI, "mout_peric0_usi01_usi", 1414 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1), 1415 MUX(CLK_MOUT_PERIC0_USI02_USI, "mout_peric0_usi02_usi", 1416 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1), 1417 MUX(CLK_MOUT_PERIC0_USI03_USI, "mout_peric0_usi03_usi", 1418 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1), 1419 MUX(CLK_MOUT_PERIC0_USI04_USI, "mout_peric0_usi04_usi", 1420 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1), 1421 MUX(CLK_MOUT_PERIC0_USI05_USI, "mout_peric0_usi05_usi", 1422 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1), 1423 MUX(CLK_MOUT_PERIC0_USI06_USI, "mout_peric0_usi06_usi", 1424 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI06_USI, 0, 1), 1425 MUX(CLK_MOUT_PERIC0_USI07_USI, "mout_peric0_usi07_usi", 1426 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI07_USI, 0, 1), 1427 MUX(CLK_MOUT_PERIC0_USI08_USI, "mout_peric0_usi08_usi", 1428 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI08_USI, 0, 1), 1429 /* USI_I2C */ 1430 MUX(CLK_MOUT_PERIC0_USI_I2C, "mout_peric0_usi_i2c", 1431 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1), 1432 /* USI_I3C */ 1433 MUX(CLK_MOUT_PERIC0_I3C, "mout_peric0_i3c", 1434 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_I3C, 0, 1), 1435 }; 1436 1437 static const struct samsung_div_clock peric0_div_clks[] __initconst = { 1438 /* USI00 ~ USI08 */ 1439 DIV(CLK_DOUT_PERIC0_USI00_USI, "dout_peric0_usi00_usi", 1440 "mout_peric0_usi00_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI, 1441 0, 4), 1442 DIV(CLK_DOUT_PERIC0_USI01_USI, "dout_peric0_usi01_usi", 1443 "mout_peric0_usi01_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI, 1444 0, 4), 1445 DIV(CLK_DOUT_PERIC0_USI02_USI, "dout_peric0_usi02_usi", 1446 "mout_peric0_usi02_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI, 1447 0, 4), 1448 DIV(CLK_DOUT_PERIC0_USI03_USI, "dout_peric0_usi03_usi", 1449 "mout_peric0_usi03_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI, 1450 0, 4), 1451 DIV(CLK_DOUT_PERIC0_USI04_USI, "dout_peric0_usi04_usi", 1452 "mout_peric0_usi04_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI, 1453 0, 4), 1454 DIV(CLK_DOUT_PERIC0_USI05_USI, "dout_peric0_usi05_usi", 1455 "mout_peric0_usi05_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI, 1456 0, 4), 1457 DIV(CLK_DOUT_PERIC0_USI06_USI, "dout_peric0_usi06_usi", 1458 "mout_peric0_usi06_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI06_USI, 1459 0, 4), 1460 DIV(CLK_DOUT_PERIC0_USI07_USI, "dout_peric0_usi07_usi", 1461 "mout_peric0_usi07_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI07_USI, 1462 0, 4), 1463 DIV(CLK_DOUT_PERIC0_USI08_USI, "dout_peric0_usi08_usi", 1464 "mout_peric0_usi08_usi", CLK_CON_DIV_DIV_CLK_PERIC0_USI08_USI, 1465 0, 4), 1466 /* USI_I2C */ 1467 DIV(CLK_DOUT_PERIC0_USI_I2C, "dout_peric0_usi_i2c", 1468 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4), 1469 /* USI_I3C */ 1470 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", 1471 "mout_peric0_i3c", CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4), 1472 }; 1473 1474 static const struct samsung_cmu_info peric0_cmu_info __initconst = { 1475 .mux_clks = peric0_mux_clks, 1476 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 1477 .div_clks = peric0_div_clks, 1478 .nr_div_clks = ARRAY_SIZE(peric0_div_clks), 1479 .nr_clk_ids = CLKS_NR_PERIC0, 1480 .clk_regs = peric0_clk_regs, 1481 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 1482 .clk_name = "noc", 1483 }; 1484 1485 /* ---- CMU_PERIC1 --------------------------------------------------------- */ 1486 1487 /* Register Offset definitions for CMU_PERIC1 (0x10C00000) */ 1488 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x600 1489 #define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER 0x610 1490 #define CLK_CON_MUX_MUX_CLK_PERIC1_I3C 0x1000 1491 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x1004 1492 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1008 1493 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x100c 1494 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI 0x1010 1495 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI 0x1014 1496 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI 0x1018 1497 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI 0x101c 1498 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI 0x1020 1499 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI 0x1024 1500 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1028 1501 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800 1502 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x1804 1503 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808 1504 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c 1505 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810 1506 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814 1507 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI 0x1818 1508 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI 0x181c 1509 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI 0x1820 1510 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI 0x1824 1511 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1828 1512 1513 static const unsigned long peric1_clk_regs[] __initconst = { 1514 PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 1515 PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 1516 CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 1517 CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 1518 CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 1519 CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 1520 CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 1521 CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 1522 CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 1523 CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 1524 CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 1525 CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 1526 CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 1527 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 1528 CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 1529 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 1530 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 1531 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 1532 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 1533 CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI, 1534 CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI, 1535 CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, 1536 CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, 1537 CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 1538 }; 1539 1540 /* List of parent clocks for Muxes in CMU_PERIC1 */ 1541 PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" }; 1542 PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" }; 1543 PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" }; 1544 1545 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { 1546 MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user", 1547 mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1), 1548 MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user", 1549 mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1), 1550 /* USI09 ~ USI17 */ 1551 MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi", 1552 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1), 1553 MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi", 1554 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1), 1555 MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi", 1556 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1), 1557 MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi", 1558 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1), 1559 MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi", 1560 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1), 1561 MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi", 1562 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1), 1563 MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi", 1564 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1), 1565 MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi", 1566 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1), 1567 MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi", 1568 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1), 1569 /* USI_I2C */ 1570 MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c", 1571 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1), 1572 /* USI_I3C */ 1573 MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c", 1574 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1), 1575 }; 1576 1577 static const struct samsung_div_clock peric1_div_clks[] __initconst = { 1578 /* USI09 ~ USI17 */ 1579 DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi", 1580 "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI, 1581 0, 4), 1582 DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi", 1583 "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 1584 0, 4), 1585 DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi", 1586 "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 1587 0, 4), 1588 DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi", 1589 "mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 1590 0, 4), 1591 DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi", 1592 "mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 1593 0, 4), 1594 DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi", 1595 "mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI, 1596 0, 4), 1597 DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi", 1598 "mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI, 1599 0, 4), 1600 DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi", 1601 "mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, 1602 0, 4), 1603 DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi", 1604 "mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI, 1605 0, 4), 1606 /* USI_I2C */ 1607 DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c", 1608 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4), 1609 /* USI_I3C */ 1610 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", 1611 "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4), 1612 }; 1613 1614 static const struct samsung_cmu_info peric1_cmu_info __initconst = { 1615 .mux_clks = peric1_mux_clks, 1616 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 1617 .div_clks = peric1_div_clks, 1618 .nr_div_clks = ARRAY_SIZE(peric1_div_clks), 1619 .nr_clk_ids = CLKS_NR_PERIC1, 1620 .clk_regs = peric1_clk_regs, 1621 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 1622 .clk_name = "noc", 1623 }; 1624 1625 /* ---- CMU_MISC --------------------------------------------------------- */ 1626 1627 /* Register Offset definitions for CMU_MISC (0x10020000) */ 1628 #define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER 0x600 1629 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000 1630 #define CLK_CON_DIV_CLKCMU_OTP 0x1800 1631 #define CLK_CON_DIV_DIV_CLK_MISC_NOCP 0x1804 1632 #define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2 0x1808 1633 1634 static const unsigned long misc_clk_regs[] __initconst = { 1635 PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 1636 CLK_CON_MUX_MUX_CLK_MISC_GIC, 1637 CLK_CON_DIV_CLKCMU_OTP, 1638 CLK_CON_DIV_DIV_CLK_MISC_NOCP, 1639 CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2, 1640 }; 1641 1642 /* List of parent clocks for Muxes in CMU_MISC */ 1643 PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" }; 1644 PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" }; 1645 1646 static const struct samsung_mux_clock misc_mux_clks[] __initconst = { 1647 MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user", 1648 mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1), 1649 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", 1650 mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1), 1651 }; 1652 1653 static const struct samsung_div_clock misc_div_clks[] __initconst = { 1654 DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp", 1655 "mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP, 1656 0, 3), 1657 }; 1658 1659 static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = { 1660 FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp", 1661 "oscclk", 1, 10, 0), 1662 FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2", 1663 "oscclk", 1, 2, 0), 1664 }; 1665 1666 static const struct samsung_cmu_info misc_cmu_info __initconst = { 1667 .mux_clks = misc_mux_clks, 1668 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks), 1669 .div_clks = misc_div_clks, 1670 .nr_div_clks = ARRAY_SIZE(misc_div_clks), 1671 .fixed_factor_clks = misc_fixed_factor_clks, 1672 .nr_fixed_factor_clks = ARRAY_SIZE(misc_fixed_factor_clks), 1673 .nr_clk_ids = CLKS_NR_MISC, 1674 .clk_regs = misc_clk_regs, 1675 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs), 1676 .clk_name = "noc", 1677 }; 1678 1679 /* ---- CMU_HSI0 --------------------------------------------------------- */ 1680 1681 /* Register Offset definitions for CMU_HSI0 (0x16000000) */ 1682 #define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER 0x600 1683 #define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB 0x1800 1684 1685 static const unsigned long hsi0_clk_regs[] __initconst = { 1686 PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 1687 CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB, 1688 }; 1689 1690 /* List of parent clocks for Muxes in CMU_HSI0 */ 1691 PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" }; 1692 1693 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = { 1694 MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user", 1695 mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1), 1696 }; 1697 1698 static const struct samsung_div_clock hsi0_div_clks[] __initconst = { 1699 DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb", 1700 "mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB, 1701 0, 4), 1702 }; 1703 1704 static const struct samsung_cmu_info hsi0_cmu_info __initconst = { 1705 .mux_clks = hsi0_mux_clks, 1706 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks), 1707 .div_clks = hsi0_div_clks, 1708 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks), 1709 .nr_clk_ids = CLKS_NR_HSI0, 1710 .clk_regs = hsi0_clk_regs, 1711 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs), 1712 .clk_name = "noc", 1713 }; 1714 1715 /* ---- CMU_HSI1 --------------------------------------------------------- */ 1716 1717 /* Register Offset definitions for CMU_HSI1 (0x16400000) */ 1718 #define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER 0x600 1719 #define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER 0x610 1720 #define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER 0x620 1721 #define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD 0x1000 1722 1723 static const unsigned long hsi1_clk_regs[] __initconst = { 1724 PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 1725 PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 1726 PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 1727 CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 1728 }; 1729 1730 /* List of parent clocks for Muxes in CMU_HSI1 */ 1731 PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"}; 1732 PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" }; 1733 PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_hsi1_usbdrd" }; 1734 PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" }; 1735 1736 static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = { 1737 MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user", 1738 mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1), 1739 MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user", 1740 mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1), 1741 MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user", 1742 mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1), 1743 MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd", 1744 mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1), 1745 }; 1746 1747 static const struct samsung_cmu_info hsi1_cmu_info __initconst = { 1748 .mux_clks = hsi1_mux_clks, 1749 .nr_mux_clks = ARRAY_SIZE(hsi1_mux_clks), 1750 .nr_clk_ids = CLKS_NR_HSI1, 1751 .clk_regs = hsi1_clk_regs, 1752 .nr_clk_regs = ARRAY_SIZE(hsi1_clk_regs), 1753 .clk_name = "noc", 1754 }; 1755 1756 /* ---- CMU_HSI2 --------------------------------------------------------- */ 1757 1758 /* Register Offset definitions for CMU_HSI2 (0x16b00000) */ 1759 #define PLL_LOCKTIME_PLL_ETH 0x0 1760 #define PLL_CON3_PLL_ETH 0x10c 1761 #define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER 0x600 1762 #define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER 0x610 1763 #define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x630 1764 #define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET 0x1000 1765 #define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET 0x1800 1766 #define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP 0x1804 1767 1768 static const unsigned long hsi2_clk_regs[] __initconst = { 1769 PLL_LOCKTIME_PLL_ETH, 1770 PLL_CON3_PLL_ETH, 1771 PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 1772 PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 1773 PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 1774 CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 1775 CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET, 1776 CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP, 1777 }; 1778 1779 static const struct samsung_pll_clock hsi2_pll_clks[] __initconst = { 1780 /* CMU_HSI2_PLL */ 1781 PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk", 1782 PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL), 1783 }; 1784 1785 /* List of parent clocks for Muxes in CMU_HSI2 */ 1786 PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) = { "oscclk", "dout_clkcmu_hsi2_noc_ufs" }; 1787 PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) = { "oscclk", "dout_clkcmu_hsi2_ufs_embd" }; 1788 PNAME(mout_hsi2_ethernet_p) = { "fout_pll_eth", "mout_clkcmu_hsi2_ethernet_user" }; 1789 PNAME(mout_clkcmu_hsi2_ethernet_user_p) = { "oscclk", "dout_clkcmu_hsi2_ethernet" }; 1790 1791 static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = { 1792 MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user", 1793 mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, 4, 1), 1794 MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user", 1795 mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 4, 1), 1796 MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet", 1797 mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1), 1798 MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user", 1799 mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, 4, 1), 1800 }; 1801 1802 static const struct samsung_div_clock hsi2_div_clks[] __initconst = { 1803 DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet", 1804 "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET, 1805 0, 4), 1806 DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp", 1807 "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP, 1808 0, 4), 1809 }; 1810 1811 static const struct samsung_cmu_info hsi2_cmu_info __initconst = { 1812 .pll_clks = hsi2_pll_clks, 1813 .nr_pll_clks = ARRAY_SIZE(hsi2_pll_clks), 1814 .mux_clks = hsi2_mux_clks, 1815 .nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks), 1816 .div_clks = hsi2_div_clks, 1817 .nr_div_clks = ARRAY_SIZE(hsi2_div_clks), 1818 .nr_clk_ids = CLKS_NR_HSI2, 1819 .clk_regs = hsi2_clk_regs, 1820 .nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs), 1821 .clk_name = "noc", 1822 }; 1823 1824 static int __init exynosautov920_cmu_probe(struct platform_device *pdev) 1825 { 1826 const struct samsung_cmu_info *info; 1827 struct device *dev = &pdev->dev; 1828 1829 info = of_device_get_match_data(dev); 1830 exynos_arm64_register_cmu(dev, dev->of_node, info); 1831 1832 return 0; 1833 } 1834 1835 static const struct of_device_id exynosautov920_cmu_of_match[] = { 1836 { 1837 .compatible = "samsung,exynosautov920-cmu-peric0", 1838 .data = &peric0_cmu_info, 1839 }, { 1840 .compatible = "samsung,exynosautov920-cmu-peric1", 1841 .data = &peric1_cmu_info, 1842 }, { 1843 .compatible = "samsung,exynosautov920-cmu-misc", 1844 .data = &misc_cmu_info, 1845 }, { 1846 .compatible = "samsung,exynosautov920-cmu-hsi0", 1847 .data = &hsi0_cmu_info, 1848 }, { 1849 .compatible = "samsung,exynosautov920-cmu-hsi1", 1850 .data = &hsi1_cmu_info, 1851 }, { 1852 .compatible = "samsung,exynosautov920-cmu-hsi2", 1853 .data = &hsi2_cmu_info, 1854 }, 1855 { } 1856 }; 1857 1858 static struct platform_driver exynosautov920_cmu_driver __refdata = { 1859 .driver = { 1860 .name = "exynosautov920-cmu", 1861 .of_match_table = exynosautov920_cmu_of_match, 1862 .suppress_bind_attrs = true, 1863 }, 1864 .probe = exynosautov920_cmu_probe, 1865 }; 1866 1867 static int __init exynosautov920_cmu_init(void) 1868 { 1869 return platform_driver_register(&exynosautov920_cmu_driver); 1870 } 1871 core_initcall(exynosautov920_cmu_init); 1872