1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/of.h> 13 14 #include "clk.h" 15 #include <dt-bindings/clock/exynos7-clk.h> 16 17 /* Register Offset definitions for CMU_TOPC (0x10570000) */ 18 #define CC_PLL_LOCK 0x0000 19 #define BUS0_PLL_LOCK 0x0004 20 #define BUS1_DPLL_LOCK 0x0008 21 #define MFC_PLL_LOCK 0x000C 22 #define AUD_PLL_LOCK 0x0010 23 #define CC_PLL_CON0 0x0100 24 #define BUS0_PLL_CON0 0x0110 25 #define BUS1_DPLL_CON0 0x0120 26 #define MFC_PLL_CON0 0x0130 27 #define AUD_PLL_CON0 0x0140 28 #define MUX_SEL_TOPC0 0x0200 29 #define MUX_SEL_TOPC1 0x0204 30 #define MUX_SEL_TOPC2 0x0208 31 #define MUX_SEL_TOPC3 0x020C 32 #define DIV_TOPC0 0x0600 33 #define DIV_TOPC1 0x0604 34 #define DIV_TOPC3 0x060C 35 #define ENABLE_ACLK_TOPC0 0x0800 36 #define ENABLE_ACLK_TOPC1 0x0804 37 #define ENABLE_SCLK_TOPC1 0x0A04 38 39 static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = { 40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), 41 FFACTOR(0, "ffac_topc_bus0_pll_div4", 42 "ffac_topc_bus0_pll_div2", 1, 2, 0), 43 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0), 44 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0), 45 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0), 46 }; 47 48 /* List of parent clocks for Muxes in CMU_TOPC */ 49 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; 50 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 51 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 52 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 53 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 54 55 PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half", 56 "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half", 57 "mout_topc_mfc_pll_half" }; 58 59 PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll", 60 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 61 PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll", 62 "ffac_topc_bus1_pll_div2"}; 63 PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll", 64 "ffac_topc_cc_pll_div2"}; 65 PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", 66 "ffac_topc_mfc_pll_div2"}; 67 68 69 PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", 70 "ffac_topc_bus0_pll_div2"}; 71 72 static const unsigned long topc_clk_regs[] __initconst = { 73 CC_PLL_LOCK, 74 BUS0_PLL_LOCK, 75 BUS1_DPLL_LOCK, 76 MFC_PLL_LOCK, 77 AUD_PLL_LOCK, 78 CC_PLL_CON0, 79 BUS0_PLL_CON0, 80 BUS1_DPLL_CON0, 81 MFC_PLL_CON0, 82 AUD_PLL_CON0, 83 MUX_SEL_TOPC0, 84 MUX_SEL_TOPC1, 85 MUX_SEL_TOPC2, 86 MUX_SEL_TOPC3, 87 DIV_TOPC0, 88 DIV_TOPC1, 89 DIV_TOPC3, 90 }; 91 92 static const struct samsung_mux_clock topc_mux_clks[] __initconst = { 93 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, 94 MUX_SEL_TOPC0, 0, 1), 95 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, 96 MUX_SEL_TOPC0, 4, 1), 97 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, 98 MUX_SEL_TOPC0, 8, 1), 99 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, 100 MUX_SEL_TOPC0, 12, 1), 101 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, 102 MUX_SEL_TOPC0, 16, 2), 103 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, 104 MUX_SEL_TOPC0, 20, 1), 105 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, 106 MUX_SEL_TOPC0, 24, 1), 107 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, 108 MUX_SEL_TOPC0, 28, 1), 109 110 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p, 111 MUX_SEL_TOPC1, 0, 1), 112 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p, 113 MUX_SEL_TOPC1, 16, 1), 114 115 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 116 117 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), 118 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 119 }; 120 121 static const struct samsung_div_clock topc_div_clks[] __initconst = { 122 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 123 DIV_TOPC0, 4, 4), 124 125 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", 126 DIV_TOPC1, 20, 4), 127 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 128 DIV_TOPC1, 24, 4), 129 130 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", 131 DIV_TOPC3, 0, 4), 132 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", 133 DIV_TOPC3, 8, 4), 134 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", 135 DIV_TOPC3, 12, 4), 136 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", 137 DIV_TOPC3, 16, 4), 138 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", 139 DIV_TOPC3, 28, 4), 140 }; 141 142 static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { 143 PLL_36XX_RATE(491520000, 20, 1, 0, 31457), 144 {}, 145 }; 146 147 static const struct samsung_gate_clock topc_gate_clks[] __initconst = { 148 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", 149 ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0), 150 151 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 152 ENABLE_ACLK_TOPC1, 20, 0, 0), 153 154 GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66", 155 ENABLE_ACLK_TOPC1, 24, 0, 0), 156 157 GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", 158 ENABLE_SCLK_TOPC1, 20, 0, 0), 159 GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", 160 ENABLE_SCLK_TOPC1, 17, 0, 0), 161 GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll", 162 ENABLE_SCLK_TOPC1, 16, 0, 0), 163 GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", 164 ENABLE_SCLK_TOPC1, 13, 0, 0), 165 GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", 166 ENABLE_SCLK_TOPC1, 12, 0, 0), 167 GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll", 168 ENABLE_SCLK_TOPC1, 5, 0, 0), 169 GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll", 170 ENABLE_SCLK_TOPC1, 4, 0, 0), 171 GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll", 172 ENABLE_SCLK_TOPC1, 1, 0, 0), 173 GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll", 174 ENABLE_SCLK_TOPC1, 0, 0, 0), 175 }; 176 177 static const struct samsung_pll_clock topc_pll_clks[] __initconst = { 178 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 179 BUS0_PLL_CON0, NULL), 180 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 181 CC_PLL_CON0, NULL), 182 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 183 BUS1_DPLL_CON0, NULL), 184 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 185 MFC_PLL_CON0, NULL), 186 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 187 AUD_PLL_CON0, pll1460x_24mhz_tbl), 188 }; 189 190 static const struct samsung_cmu_info topc_cmu_info __initconst = { 191 .pll_clks = topc_pll_clks, 192 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 193 .mux_clks = topc_mux_clks, 194 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 195 .div_clks = topc_div_clks, 196 .nr_div_clks = ARRAY_SIZE(topc_div_clks), 197 .gate_clks = topc_gate_clks, 198 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), 199 .fixed_factor_clks = topc_fixed_factor_clks, 200 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 201 .nr_clk_ids = TOPC_NR_CLK, 202 .clk_regs = topc_clk_regs, 203 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 204 }; 205 206 static void __init exynos7_clk_topc_init(struct device_node *np) 207 { 208 samsung_cmu_register_one(np, &topc_cmu_info); 209 } 210 211 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 212 exynos7_clk_topc_init); 213 214 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 215 #define MUX_SEL_TOP00 0x0200 216 #define MUX_SEL_TOP01 0x0204 217 #define MUX_SEL_TOP03 0x020C 218 #define MUX_SEL_TOP0_PERIC0 0x0230 219 #define MUX_SEL_TOP0_PERIC1 0x0234 220 #define MUX_SEL_TOP0_PERIC2 0x0238 221 #define MUX_SEL_TOP0_PERIC3 0x023C 222 #define DIV_TOP03 0x060C 223 #define DIV_TOP0_PERIC0 0x0630 224 #define DIV_TOP0_PERIC1 0x0634 225 #define DIV_TOP0_PERIC2 0x0638 226 #define DIV_TOP0_PERIC3 0x063C 227 #define ENABLE_ACLK_TOP03 0x080C 228 #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 229 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 230 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 231 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 232 233 /* List of parent clocks for Muxes in CMU_TOP0 */ 234 PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" }; 235 PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" }; 236 PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" }; 237 PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" }; 238 PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" }; 239 240 PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user", 241 "ffac_top0_bus0_pll_div2"}; 242 PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user", 243 "ffac_top0_bus1_pll_div2"}; 244 PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user", 245 "ffac_top0_cc_pll_div2"}; 246 PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user", 247 "ffac_top0_mfc_pll_div2"}; 248 249 PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half", 250 "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half", 251 "mout_top0_mfc_pll_half"}; 252 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", 253 "ioclk_audiocdclk1", "ioclk_spdif_extclk", 254 "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half", 255 "mout_top0_bus1_pll_half"}; 256 PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user", 257 "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"}; 258 259 static const unsigned long top0_clk_regs[] __initconst = { 260 MUX_SEL_TOP00, 261 MUX_SEL_TOP01, 262 MUX_SEL_TOP03, 263 MUX_SEL_TOP0_PERIC0, 264 MUX_SEL_TOP0_PERIC1, 265 MUX_SEL_TOP0_PERIC2, 266 MUX_SEL_TOP0_PERIC3, 267 DIV_TOP03, 268 DIV_TOP0_PERIC0, 269 DIV_TOP0_PERIC1, 270 DIV_TOP0_PERIC2, 271 DIV_TOP0_PERIC3, 272 ENABLE_SCLK_TOP0_PERIC0, 273 ENABLE_SCLK_TOP0_PERIC1, 274 ENABLE_SCLK_TOP0_PERIC2, 275 ENABLE_SCLK_TOP0_PERIC3, 276 }; 277 278 static const struct samsung_mux_clock top0_mux_clks[] __initconst = { 279 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p, 280 MUX_SEL_TOP00, 0, 1), 281 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p, 282 MUX_SEL_TOP00, 4, 1), 283 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p, 284 MUX_SEL_TOP00, 8, 1), 285 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p, 286 MUX_SEL_TOP00, 12, 1), 287 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p, 288 MUX_SEL_TOP00, 16, 1), 289 290 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p, 291 MUX_SEL_TOP01, 4, 1), 292 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p, 293 MUX_SEL_TOP01, 8, 1), 294 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p, 295 MUX_SEL_TOP01, 12, 1), 296 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p, 297 MUX_SEL_TOP01, 16, 1), 298 299 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 300 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 301 302 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), 303 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), 304 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), 305 306 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), 307 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), 308 309 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), 310 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), 311 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 312 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 313 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 314 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 315 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), 316 }; 317 318 static const struct samsung_div_clock top0_div_clks[] __initconst = { 319 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 320 DIV_TOP03, 12, 6), 321 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 322 DIV_TOP03, 20, 6), 323 324 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), 325 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), 326 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), 327 328 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), 329 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), 330 331 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), 332 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), 333 334 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 335 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 336 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 337 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 338 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), 339 }; 340 341 static const struct samsung_gate_clock top0_gate_clks[] __initconst = { 342 GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66", 343 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0), 344 GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66", 345 ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0), 346 347 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", 348 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 349 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", 350 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 351 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", 352 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), 353 354 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", 355 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), 356 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", 357 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 358 359 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", 360 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), 361 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", 362 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), 363 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 364 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 365 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 366 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 367 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 368 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 369 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 370 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 371 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", 372 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), 373 }; 374 375 static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = { 376 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user", 377 1, 2, 0), 378 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user", 379 1, 2, 0), 380 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0), 381 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), 382 }; 383 384 static const struct samsung_cmu_info top0_cmu_info __initconst = { 385 .mux_clks = top0_mux_clks, 386 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 387 .div_clks = top0_div_clks, 388 .nr_div_clks = ARRAY_SIZE(top0_div_clks), 389 .gate_clks = top0_gate_clks, 390 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 391 .fixed_factor_clks = top0_fixed_factor_clks, 392 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 393 .nr_clk_ids = TOP0_NR_CLK, 394 .clk_regs = top0_clk_regs, 395 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 396 }; 397 398 static void __init exynos7_clk_top0_init(struct device_node *np) 399 { 400 samsung_cmu_register_one(np, &top0_cmu_info); 401 } 402 403 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 404 exynos7_clk_top0_init); 405 406 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 407 #define MUX_SEL_TOP10 0x0200 408 #define MUX_SEL_TOP11 0x0204 409 #define MUX_SEL_TOP13 0x020C 410 #define MUX_SEL_TOP1_FSYS0 0x0224 411 #define MUX_SEL_TOP1_FSYS1 0x0228 412 #define MUX_SEL_TOP1_FSYS11 0x022C 413 #define DIV_TOP13 0x060C 414 #define DIV_TOP1_FSYS0 0x0624 415 #define DIV_TOP1_FSYS1 0x0628 416 #define DIV_TOP1_FSYS11 0x062C 417 #define ENABLE_ACLK_TOP13 0x080C 418 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 419 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 420 #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C 421 422 /* List of parent clocks for Muxes in CMU_TOP1 */ 423 PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" }; 424 PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" }; 425 PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" }; 426 PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" }; 427 428 PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user", 429 "ffac_top1_bus0_pll_div2"}; 430 PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user", 431 "ffac_top1_bus1_pll_div2"}; 432 PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user", 433 "ffac_top1_cc_pll_div2"}; 434 PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user", 435 "ffac_top1_mfc_pll_div2"}; 436 437 PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half", 438 "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half", 439 "mout_top1_mfc_pll_half"}; 440 441 static const unsigned long top1_clk_regs[] __initconst = { 442 MUX_SEL_TOP10, 443 MUX_SEL_TOP11, 444 MUX_SEL_TOP13, 445 MUX_SEL_TOP1_FSYS0, 446 MUX_SEL_TOP1_FSYS1, 447 MUX_SEL_TOP1_FSYS11, 448 DIV_TOP13, 449 DIV_TOP1_FSYS0, 450 DIV_TOP1_FSYS1, 451 DIV_TOP1_FSYS11, 452 ENABLE_ACLK_TOP13, 453 ENABLE_SCLK_TOP1_FSYS0, 454 ENABLE_SCLK_TOP1_FSYS1, 455 ENABLE_SCLK_TOP1_FSYS11, 456 }; 457 458 static const struct samsung_mux_clock top1_mux_clks[] __initconst = { 459 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p, 460 MUX_SEL_TOP10, 4, 1), 461 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p, 462 MUX_SEL_TOP10, 8, 1), 463 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p, 464 MUX_SEL_TOP10, 12, 1), 465 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p, 466 MUX_SEL_TOP10, 16, 1), 467 468 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p, 469 MUX_SEL_TOP11, 4, 1), 470 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p, 471 MUX_SEL_TOP11, 8, 1), 472 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p, 473 MUX_SEL_TOP11, 12, 1), 474 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p, 475 MUX_SEL_TOP11, 16, 1), 476 477 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 478 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 479 480 MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1, 481 MUX_SEL_TOP1_FSYS0, 0, 2), 482 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), 483 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, 484 MUX_SEL_TOP1_FSYS0, 28, 2), 485 486 MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1, 487 MUX_SEL_TOP1_FSYS1, 0, 2), 488 MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1, 489 MUX_SEL_TOP1_FSYS1, 16, 2), 490 491 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), 492 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), 493 MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1, 494 MUX_SEL_TOP1_FSYS11, 24, 2), 495 }; 496 497 static const struct samsung_div_clock top1_div_clks[] __initconst = { 498 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 499 DIV_TOP13, 24, 4), 500 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 501 DIV_TOP13, 28, 4), 502 503 DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1", 504 "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6), 505 506 DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20", 507 "mout_sclk_ufsunipro20", 508 DIV_TOP1_FSYS1, 16, 6), 509 510 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 511 DIV_TOP1_FSYS0, 16, 10), 512 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", 513 DIV_TOP1_FSYS0, 28, 4), 514 515 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 516 DIV_TOP1_FSYS11, 0, 10), 517 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 518 DIV_TOP1_FSYS11, 12, 10), 519 520 DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m", 521 "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6), 522 }; 523 524 static const struct samsung_gate_clock top1_gate_clks[] __initconst = { 525 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 526 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), 527 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", 528 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), 529 530 GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1", 531 ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0), 532 533 GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20", 534 ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0), 535 536 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 537 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), 538 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 539 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), 540 541 GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", 542 ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT | 543 CLK_IS_CRITICAL, 0), 544 GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", 545 ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), 546 547 GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m", 548 "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11, 549 24, CLK_SET_RATE_PARENT, 0), 550 }; 551 552 static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = { 553 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user", 554 1, 2, 0), 555 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user", 556 1, 2, 0), 557 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0), 558 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), 559 }; 560 561 static const struct samsung_cmu_info top1_cmu_info __initconst = { 562 .mux_clks = top1_mux_clks, 563 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 564 .div_clks = top1_div_clks, 565 .nr_div_clks = ARRAY_SIZE(top1_div_clks), 566 .gate_clks = top1_gate_clks, 567 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 568 .fixed_factor_clks = top1_fixed_factor_clks, 569 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 570 .nr_clk_ids = TOP1_NR_CLK, 571 .clk_regs = top1_clk_regs, 572 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 573 }; 574 575 static void __init exynos7_clk_top1_init(struct device_node *np) 576 { 577 samsung_cmu_register_one(np, &top1_cmu_info); 578 } 579 580 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 581 exynos7_clk_top1_init); 582 583 /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 584 #define MUX_SEL_CCORE 0x0200 585 #define DIV_CCORE 0x0600 586 #define ENABLE_ACLK_CCORE0 0x0800 587 #define ENABLE_ACLK_CCORE1 0x0804 588 #define ENABLE_PCLK_CCORE 0x0900 589 590 /* 591 * List of parent clocks for Muxes in CMU_CCORE 592 */ 593 PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" }; 594 595 static const unsigned long ccore_clk_regs[] __initconst = { 596 MUX_SEL_CCORE, 597 ENABLE_PCLK_CCORE, 598 }; 599 600 static const struct samsung_mux_clock ccore_mux_clks[] __initconst = { 601 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p, 602 MUX_SEL_CCORE, 1, 1), 603 }; 604 605 static const struct samsung_gate_clock ccore_gate_clks[] __initconst = { 606 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 607 ENABLE_PCLK_CCORE, 8, 0, 0), 608 }; 609 610 static const struct samsung_cmu_info ccore_cmu_info __initconst = { 611 .mux_clks = ccore_mux_clks, 612 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 613 .gate_clks = ccore_gate_clks, 614 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 615 .nr_clk_ids = CCORE_NR_CLK, 616 .clk_regs = ccore_clk_regs, 617 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 618 }; 619 620 static void __init exynos7_clk_ccore_init(struct device_node *np) 621 { 622 samsung_cmu_register_one(np, &ccore_cmu_info); 623 } 624 625 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 626 exynos7_clk_ccore_init); 627 628 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 629 #define MUX_SEL_PERIC0 0x0200 630 #define ENABLE_PCLK_PERIC0 0x0900 631 #define ENABLE_SCLK_PERIC0 0x0A00 632 633 /* List of parent clocks for Muxes in CMU_PERIC0 */ 634 PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" }; 635 PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" }; 636 637 static const unsigned long peric0_clk_regs[] __initconst = { 638 MUX_SEL_PERIC0, 639 ENABLE_PCLK_PERIC0, 640 ENABLE_SCLK_PERIC0, 641 }; 642 643 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { 644 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p, 645 MUX_SEL_PERIC0, 0, 1), 646 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p, 647 MUX_SEL_PERIC0, 16, 1), 648 }; 649 650 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { 651 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 652 ENABLE_PCLK_PERIC0, 8, 0, 0), 653 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 654 ENABLE_PCLK_PERIC0, 9, 0, 0), 655 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 656 ENABLE_PCLK_PERIC0, 10, 0, 0), 657 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 658 ENABLE_PCLK_PERIC0, 11, 0, 0), 659 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 660 ENABLE_PCLK_PERIC0, 12, 0, 0), 661 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 662 ENABLE_PCLK_PERIC0, 13, 0, 0), 663 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 664 ENABLE_PCLK_PERIC0, 14, 0, 0), 665 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 666 ENABLE_PCLK_PERIC0, 16, 0, 0), 667 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 668 ENABLE_PCLK_PERIC0, 20, 0, 0), 669 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 670 ENABLE_PCLK_PERIC0, 21, 0, 0), 671 672 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 673 ENABLE_SCLK_PERIC0, 16, 0, 0), 674 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 675 }; 676 677 static const struct samsung_cmu_info peric0_cmu_info __initconst = { 678 .mux_clks = peric0_mux_clks, 679 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 680 .gate_clks = peric0_gate_clks, 681 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 682 .nr_clk_ids = PERIC0_NR_CLK, 683 .clk_regs = peric0_clk_regs, 684 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 685 }; 686 687 static void __init exynos7_clk_peric0_init(struct device_node *np) 688 { 689 samsung_cmu_register_one(np, &peric0_cmu_info); 690 } 691 692 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 693 #define MUX_SEL_PERIC10 0x0200 694 #define MUX_SEL_PERIC11 0x0204 695 #define MUX_SEL_PERIC12 0x0208 696 #define ENABLE_PCLK_PERIC1 0x0900 697 #define ENABLE_SCLK_PERIC10 0x0A00 698 699 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 700 exynos7_clk_peric0_init); 701 702 /* List of parent clocks for Muxes in CMU_PERIC1 */ 703 PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" }; 704 PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" }; 705 PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" }; 706 PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" }; 707 PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" }; 708 PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" }; 709 PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" }; 710 PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" }; 711 PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" }; 712 713 static const unsigned long peric1_clk_regs[] __initconst = { 714 MUX_SEL_PERIC10, 715 MUX_SEL_PERIC11, 716 MUX_SEL_PERIC12, 717 ENABLE_PCLK_PERIC1, 718 ENABLE_SCLK_PERIC10, 719 }; 720 721 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { 722 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p, 723 MUX_SEL_PERIC10, 0, 1), 724 725 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p, 726 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), 727 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p, 728 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), 729 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p, 730 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), 731 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p, 732 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), 733 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p, 734 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), 735 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p, 736 MUX_SEL_PERIC11, 20, 1), 737 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p, 738 MUX_SEL_PERIC11, 24, 1), 739 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p, 740 MUX_SEL_PERIC11, 28, 1), 741 }; 742 743 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { 744 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 745 ENABLE_PCLK_PERIC1, 4, 0, 0), 746 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 747 ENABLE_PCLK_PERIC1, 5, 0, 0), 748 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 749 ENABLE_PCLK_PERIC1, 6, 0, 0), 750 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 751 ENABLE_PCLK_PERIC1, 7, 0, 0), 752 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 753 ENABLE_PCLK_PERIC1, 8, 0, 0), 754 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 755 ENABLE_PCLK_PERIC1, 9, 0, 0), 756 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 757 ENABLE_PCLK_PERIC1, 10, 0, 0), 758 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 759 ENABLE_PCLK_PERIC1, 11, 0, 0), 760 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", 761 ENABLE_PCLK_PERIC1, 12, 0, 0), 762 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", 763 ENABLE_PCLK_PERIC1, 13, 0, 0), 764 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", 765 ENABLE_PCLK_PERIC1, 14, 0, 0), 766 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", 767 ENABLE_PCLK_PERIC1, 15, 0, 0), 768 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", 769 ENABLE_PCLK_PERIC1, 16, 0, 0), 770 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", 771 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), 772 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", 773 ENABLE_PCLK_PERIC1, 18, 0, 0), 774 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", 775 ENABLE_PCLK_PERIC1, 19, 0, 0), 776 777 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 778 ENABLE_SCLK_PERIC10, 9, 0, 0), 779 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 780 ENABLE_SCLK_PERIC10, 10, 0, 0), 781 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 782 ENABLE_SCLK_PERIC10, 11, 0, 0), 783 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", 784 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), 785 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", 786 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), 787 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", 788 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), 789 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", 790 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), 791 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", 792 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), 793 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", 794 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), 795 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", 796 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), 797 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", 798 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 799 }; 800 801 static const struct samsung_cmu_info peric1_cmu_info __initconst = { 802 .mux_clks = peric1_mux_clks, 803 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 804 .gate_clks = peric1_gate_clks, 805 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 806 .nr_clk_ids = PERIC1_NR_CLK, 807 .clk_regs = peric1_clk_regs, 808 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 809 }; 810 811 static void __init exynos7_clk_peric1_init(struct device_node *np) 812 { 813 samsung_cmu_register_one(np, &peric1_cmu_info); 814 } 815 816 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 817 exynos7_clk_peric1_init); 818 819 /* Register Offset definitions for CMU_PERIS (0x10040000) */ 820 #define MUX_SEL_PERIS 0x0200 821 #define ENABLE_PCLK_PERIS 0x0900 822 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 823 #define ENABLE_SCLK_PERIS 0x0A00 824 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 825 826 /* List of parent clocks for Muxes in CMU_PERIS */ 827 PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" }; 828 829 static const unsigned long peris_clk_regs[] __initconst = { 830 MUX_SEL_PERIS, 831 ENABLE_PCLK_PERIS, 832 ENABLE_PCLK_PERIS_SECURE_CHIPID, 833 ENABLE_SCLK_PERIS, 834 ENABLE_SCLK_PERIS_SECURE_CHIPID, 835 }; 836 837 static const struct samsung_mux_clock peris_mux_clks[] __initconst = { 838 MUX(0, "mout_aclk_peris_66_user", 839 mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1), 840 }; 841 842 static const struct samsung_gate_clock peris_gate_clks[] __initconst = { 843 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 844 ENABLE_PCLK_PERIS, 6, 0, 0), 845 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 846 ENABLE_PCLK_PERIS, 10, 0, 0), 847 848 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 849 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 850 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 851 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 852 853 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 854 }; 855 856 static const struct samsung_cmu_info peris_cmu_info __initconst = { 857 .mux_clks = peris_mux_clks, 858 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 859 .gate_clks = peris_gate_clks, 860 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 861 .nr_clk_ids = PERIS_NR_CLK, 862 .clk_regs = peris_clk_regs, 863 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 864 }; 865 866 static void __init exynos7_clk_peris_init(struct device_node *np) 867 { 868 samsung_cmu_register_one(np, &peris_cmu_info); 869 } 870 871 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 872 exynos7_clk_peris_init); 873 874 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 875 #define MUX_SEL_FSYS00 0x0200 876 #define MUX_SEL_FSYS01 0x0204 877 #define MUX_SEL_FSYS02 0x0208 878 #define ENABLE_ACLK_FSYS00 0x0800 879 #define ENABLE_ACLK_FSYS01 0x0804 880 #define ENABLE_SCLK_FSYS01 0x0A04 881 #define ENABLE_SCLK_FSYS02 0x0A08 882 #define ENABLE_SCLK_FSYS04 0x0A10 883 884 /* 885 * List of parent clocks for Muxes in CMU_FSYS0 886 */ 887 PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" }; 888 PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" }; 889 890 PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" }; 891 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll", 892 "phyclk_usbdrd300_udrd30_phyclock" }; 893 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", 894 "phyclk_usbdrd300_udrd30_pipe_pclk" }; 895 896 /* fixed rate clocks used in the FSYS0 block */ 897 static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = { 898 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000), 899 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000), 900 }; 901 902 static const unsigned long fsys0_clk_regs[] __initconst = { 903 MUX_SEL_FSYS00, 904 MUX_SEL_FSYS01, 905 MUX_SEL_FSYS02, 906 ENABLE_ACLK_FSYS00, 907 ENABLE_ACLK_FSYS01, 908 ENABLE_SCLK_FSYS01, 909 ENABLE_SCLK_FSYS02, 910 ENABLE_SCLK_FSYS04, 911 }; 912 913 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { 914 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p, 915 MUX_SEL_FSYS00, 24, 1), 916 917 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p, 918 MUX_SEL_FSYS01, 24, 1), 919 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p, 920 MUX_SEL_FSYS01, 28, 1), 921 922 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 923 mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p, 924 MUX_SEL_FSYS02, 24, 1), 925 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", 926 mout_phyclk_usbdrd300_udrd30_phyclk_user_p, 927 MUX_SEL_FSYS02, 28, 1), 928 }; 929 930 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { 931 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", 932 ENABLE_ACLK_FSYS00, 3, 0, 0), 933 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", 934 ENABLE_ACLK_FSYS00, 4, 0, 0), 935 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", 936 "mout_aclk_fsys0_200_user", 937 ENABLE_ACLK_FSYS00, 19, 0, 0), 938 939 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", 940 ENABLE_ACLK_FSYS01, 29, 0, 0), 941 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 942 ENABLE_ACLK_FSYS01, 31, 0, 0), 943 944 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk", 945 "mout_sclk_usbdrd300_user", 946 ENABLE_SCLK_FSYS01, 4, 0, 0), 947 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll", 948 ENABLE_SCLK_FSYS01, 8, 0, 0), 949 950 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER, 951 "phyclk_usbdrd300_udrd30_pipe_pclk_user", 952 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 953 ENABLE_SCLK_FSYS02, 24, 0, 0), 954 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER, 955 "phyclk_usbdrd300_udrd30_phyclk_user", 956 "mout_phyclk_usbdrd300_udrd30_phyclk_user", 957 ENABLE_SCLK_FSYS02, 28, 0, 0), 958 959 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy", 960 "fin_pll", 961 ENABLE_SCLK_FSYS04, 28, 0, 0), 962 }; 963 964 static const struct samsung_cmu_info fsys0_cmu_info __initconst = { 965 .fixed_clks = fixed_rate_clks_fsys0, 966 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0), 967 .mux_clks = fsys0_mux_clks, 968 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 969 .gate_clks = fsys0_gate_clks, 970 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 971 .nr_clk_ids = FSYS0_NR_CLK, 972 .clk_regs = fsys0_clk_regs, 973 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 974 }; 975 976 static void __init exynos7_clk_fsys0_init(struct device_node *np) 977 { 978 samsung_cmu_register_one(np, &fsys0_cmu_info); 979 } 980 981 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 982 exynos7_clk_fsys0_init); 983 984 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 985 #define MUX_SEL_FSYS10 0x0200 986 #define MUX_SEL_FSYS11 0x0204 987 #define MUX_SEL_FSYS12 0x0208 988 #define DIV_FSYS1 0x0600 989 #define ENABLE_ACLK_FSYS1 0x0800 990 #define ENABLE_PCLK_FSYS1 0x0900 991 #define ENABLE_SCLK_FSYS11 0x0A04 992 #define ENABLE_SCLK_FSYS12 0x0A08 993 #define ENABLE_SCLK_FSYS13 0x0A0C 994 995 /* 996 * List of parent clocks for Muxes in CMU_FSYS1 997 */ 998 PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" }; 999 PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m", 1000 "sclk_phy_fsys1_26m" }; 1001 PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" }; 1002 PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" }; 1003 PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" }; 1004 PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" }; 1005 PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" }; 1006 PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" }; 1007 1008 /* fixed rate clocks used in the FSYS1 block */ 1009 static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = { 1010 FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL, 1011 0, 300000000), 1012 FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL, 1013 0, 300000000), 1014 FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL, 1015 0, 300000000), 1016 }; 1017 1018 static const unsigned long fsys1_clk_regs[] __initconst = { 1019 MUX_SEL_FSYS10, 1020 MUX_SEL_FSYS11, 1021 MUX_SEL_FSYS12, 1022 DIV_FSYS1, 1023 ENABLE_ACLK_FSYS1, 1024 ENABLE_PCLK_FSYS1, 1025 ENABLE_SCLK_FSYS11, 1026 ENABLE_SCLK_FSYS12, 1027 ENABLE_SCLK_FSYS13, 1028 }; 1029 1030 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { 1031 MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1", 1032 mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2), 1033 MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p, 1034 MUX_SEL_FSYS10, 20, 2), 1035 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p, 1036 MUX_SEL_FSYS10, 28, 1), 1037 1038 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p, 1039 MUX_SEL_FSYS11, 24, 1), 1040 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p, 1041 MUX_SEL_FSYS11, 28, 1), 1042 MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p, 1043 MUX_SEL_FSYS11, 20, 1), 1044 1045 MUX(0, "mout_phyclk_ufs20_rx1_symbol_user", 1046 mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1), 1047 MUX(0, "mout_phyclk_ufs20_rx0_symbol_user", 1048 mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1), 1049 MUX(0, "mout_phyclk_ufs20_tx0_symbol_user", 1050 mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1), 1051 }; 1052 1053 static const struct samsung_div_clock fsys1_div_clks[] __initconst = { 1054 DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user", 1055 DIV_FSYS1, 0, 2), 1056 }; 1057 1058 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { 1059 GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user", 1060 "mout_sclk_ufsunipro20_user", 1061 ENABLE_SCLK_FSYS11, 20, 0, 0), 1062 1063 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 1064 ENABLE_ACLK_FSYS1, 29, 0, 0), 1065 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 1066 ENABLE_ACLK_FSYS1, 30, 0, 0), 1067 1068 GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1", 1069 ENABLE_ACLK_FSYS1, 31, 0, 0), 1070 GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user", 1071 ENABLE_PCLK_FSYS1, 30, 0, 0), 1072 1073 GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user", 1074 "mout_phyclk_ufs20_rx1_symbol_user", 1075 ENABLE_SCLK_FSYS12, 16, 0, 0), 1076 GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user", 1077 "mout_phyclk_ufs20_rx0_symbol_user", 1078 ENABLE_SCLK_FSYS12, 24, 0, 0), 1079 GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user", 1080 "mout_phyclk_ufs20_tx0_symbol_user", 1081 ENABLE_SCLK_FSYS12, 28, 0, 0), 1082 1083 GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY, 1084 "oscclk_phy_clkout_embedded_combo_phy", 1085 "fin_pll", 1086 ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0), 1087 1088 GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m", 1089 "mout_fsys1_phyclk_sel1", 1090 ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0), 1091 }; 1092 1093 static const struct samsung_cmu_info fsys1_cmu_info __initconst = { 1094 .fixed_clks = fixed_rate_clks_fsys1, 1095 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1), 1096 .mux_clks = fsys1_mux_clks, 1097 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 1098 .div_clks = fsys1_div_clks, 1099 .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), 1100 .gate_clks = fsys1_gate_clks, 1101 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 1102 .nr_clk_ids = FSYS1_NR_CLK, 1103 .clk_regs = fsys1_clk_regs, 1104 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 1105 }; 1106 1107 static void __init exynos7_clk_fsys1_init(struct device_node *np) 1108 { 1109 samsung_cmu_register_one(np, &fsys1_cmu_info); 1110 } 1111 1112 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 1113 exynos7_clk_fsys1_init); 1114 1115 #define MUX_SEL_MSCL 0x0200 1116 #define DIV_MSCL 0x0600 1117 #define ENABLE_ACLK_MSCL 0x0800 1118 #define ENABLE_PCLK_MSCL 0x0900 1119 1120 /* List of parent clocks for Muxes in CMU_MSCL */ 1121 PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 1122 1123 static const unsigned long mscl_clk_regs[] __initconst = { 1124 MUX_SEL_MSCL, 1125 DIV_MSCL, 1126 ENABLE_ACLK_MSCL, 1127 ENABLE_PCLK_MSCL, 1128 }; 1129 1130 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { 1131 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 1132 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 1133 }; 1134 static const struct samsung_div_clock mscl_div_clks[] __initconst = { 1135 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 1136 DIV_MSCL, 0, 3), 1137 }; 1138 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { 1139 1140 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 1141 ENABLE_ACLK_MSCL, 31, 0, 0), 1142 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", 1143 ENABLE_ACLK_MSCL, 30, 0, 0), 1144 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", 1145 ENABLE_ACLK_MSCL, 29, 0, 0), 1146 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", 1147 ENABLE_ACLK_MSCL, 28, 0, 0), 1148 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", 1149 "usermux_aclk_mscl_532", 1150 ENABLE_ACLK_MSCL, 27, 0, 0), 1151 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", 1152 "usermux_aclk_mscl_532", 1153 ENABLE_ACLK_MSCL, 26, 0, 0), 1154 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", 1155 ENABLE_ACLK_MSCL, 25, 0, 0), 1156 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", 1157 ENABLE_ACLK_MSCL, 24, 0, 0), 1158 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", 1159 "usermux_aclk_mscl_532", 1160 ENABLE_ACLK_MSCL, 23, 0, 0), 1161 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", 1162 ENABLE_ACLK_MSCL, 22, 0, 0), 1163 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", 1164 ENABLE_ACLK_MSCL, 21, 0, 0), 1165 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", 1166 ENABLE_ACLK_MSCL, 20, 0, 0), 1167 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", 1168 ENABLE_ACLK_MSCL, 19, 0, 0), 1169 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", 1170 ENABLE_ACLK_MSCL, 18, 0, 0), 1171 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", 1172 ENABLE_ACLK_MSCL, 17, 0, 0), 1173 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", 1174 ENABLE_ACLK_MSCL, 16, 0, 0), 1175 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", 1176 "usermux_aclk_mscl_532", 1177 ENABLE_ACLK_MSCL, 15, 0, 0), 1178 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", 1179 "usermux_aclk_mscl_532", 1180 ENABLE_ACLK_MSCL, 14, 0, 0), 1181 1182 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", 1183 ENABLE_PCLK_MSCL, 31, 0, 0), 1184 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", 1185 ENABLE_PCLK_MSCL, 30, 0, 0), 1186 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", 1187 ENABLE_PCLK_MSCL, 29, 0, 0), 1188 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", 1189 ENABLE_PCLK_MSCL, 28, 0, 0), 1190 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", 1191 ENABLE_PCLK_MSCL, 27, 0, 0), 1192 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", 1193 ENABLE_PCLK_MSCL, 26, 0, 0), 1194 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", 1195 ENABLE_PCLK_MSCL, 25, 0, 0), 1196 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", 1197 ENABLE_PCLK_MSCL, 24, 0, 0), 1198 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", 1199 ENABLE_PCLK_MSCL, 23, 0, 0), 1200 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", 1201 ENABLE_PCLK_MSCL, 22, 0, 0), 1202 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", 1203 ENABLE_PCLK_MSCL, 21, 0, 0), 1204 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", 1205 ENABLE_PCLK_MSCL, 20, 0, 0), 1206 }; 1207 1208 static const struct samsung_cmu_info mscl_cmu_info __initconst = { 1209 .mux_clks = mscl_mux_clks, 1210 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 1211 .div_clks = mscl_div_clks, 1212 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 1213 .gate_clks = mscl_gate_clks, 1214 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 1215 .nr_clk_ids = MSCL_NR_CLK, 1216 .clk_regs = mscl_clk_regs, 1217 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 1218 }; 1219 1220 static void __init exynos7_clk_mscl_init(struct device_node *np) 1221 { 1222 samsung_cmu_register_one(np, &mscl_cmu_info); 1223 } 1224 1225 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 1226 exynos7_clk_mscl_init); 1227 1228 /* Register Offset definitions for CMU_AUD (0x114C0000) */ 1229 #define MUX_SEL_AUD 0x0200 1230 #define DIV_AUD0 0x0600 1231 #define DIV_AUD1 0x0604 1232 #define ENABLE_ACLK_AUD 0x0800 1233 #define ENABLE_PCLK_AUD 0x0900 1234 #define ENABLE_SCLK_AUD 0x0A00 1235 1236 /* 1237 * List of parent clocks for Muxes in CMU_AUD 1238 */ 1239 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 1240 PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 1241 1242 static const unsigned long aud_clk_regs[] __initconst = { 1243 MUX_SEL_AUD, 1244 DIV_AUD0, 1245 DIV_AUD1, 1246 ENABLE_ACLK_AUD, 1247 ENABLE_PCLK_AUD, 1248 ENABLE_SCLK_AUD, 1249 }; 1250 1251 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 1252 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 1253 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 1254 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 1255 }; 1256 1257 static const struct samsung_div_clock aud_div_clks[] __initconst = { 1258 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 1259 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 1260 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 1261 1262 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), 1263 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), 1264 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), 1265 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), 1266 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 1267 }; 1268 1269 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 1270 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 1271 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1272 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 1273 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), 1274 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), 1275 GATE(0, "sclk_slimbus", "dout_sclk_slimbus", 1276 ENABLE_SCLK_AUD, 30, 0, 0), 1277 1278 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 1279 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 1280 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 1281 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 1282 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 1283 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 1284 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", 1285 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 1286 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", 1287 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1288 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), 1289 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), 1290 1291 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), 1292 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", 1293 ENABLE_ACLK_AUD, 28, 0, 0), 1294 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 1295 }; 1296 1297 static const struct samsung_cmu_info aud_cmu_info __initconst = { 1298 .mux_clks = aud_mux_clks, 1299 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 1300 .div_clks = aud_div_clks, 1301 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 1302 .gate_clks = aud_gate_clks, 1303 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 1304 .nr_clk_ids = AUD_NR_CLK, 1305 .clk_regs = aud_clk_regs, 1306 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 1307 }; 1308 1309 static void __init exynos7_clk_aud_init(struct device_node *np) 1310 { 1311 samsung_cmu_register_one(np, &aud_cmu_info); 1312 } 1313 1314 CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", 1315 exynos7_clk_aud_init); 1316