1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/of.h> 9 10 #include "clk.h" 11 #include <dt-bindings/clock/exynos7-clk.h> 12 13 /* Register Offset definitions for CMU_TOPC (0x10570000) */ 14 #define CC_PLL_LOCK 0x0000 15 #define BUS0_PLL_LOCK 0x0004 16 #define BUS1_DPLL_LOCK 0x0008 17 #define MFC_PLL_LOCK 0x000C 18 #define AUD_PLL_LOCK 0x0010 19 #define CC_PLL_CON0 0x0100 20 #define BUS0_PLL_CON0 0x0110 21 #define BUS1_DPLL_CON0 0x0120 22 #define MFC_PLL_CON0 0x0130 23 #define AUD_PLL_CON0 0x0140 24 #define MUX_SEL_TOPC0 0x0200 25 #define MUX_SEL_TOPC1 0x0204 26 #define MUX_SEL_TOPC2 0x0208 27 #define MUX_SEL_TOPC3 0x020C 28 #define DIV_TOPC0 0x0600 29 #define DIV_TOPC1 0x0604 30 #define DIV_TOPC3 0x060C 31 #define ENABLE_ACLK_TOPC0 0x0800 32 #define ENABLE_ACLK_TOPC1 0x0804 33 #define ENABLE_SCLK_TOPC1 0x0A04 34 35 static const struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initconst = { 36 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0), 37 FFACTOR(0, "ffac_topc_bus0_pll_div4", 38 "ffac_topc_bus0_pll_div2", 1, 2, 0), 39 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0), 40 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0), 41 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0), 42 }; 43 44 /* List of parent clocks for Muxes in CMU_TOPC */ 45 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" }; 46 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" }; 47 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" }; 48 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" }; 49 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" }; 50 51 PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half", 52 "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half", 53 "mout_topc_mfc_pll_half" }; 54 55 PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll", 56 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"}; 57 PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll", 58 "ffac_topc_bus1_pll_div2"}; 59 PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll", 60 "ffac_topc_cc_pll_div2"}; 61 PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll", 62 "ffac_topc_mfc_pll_div2"}; 63 64 65 PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll", 66 "ffac_topc_bus0_pll_div2"}; 67 68 static const unsigned long topc_clk_regs[] __initconst = { 69 CC_PLL_LOCK, 70 BUS0_PLL_LOCK, 71 BUS1_DPLL_LOCK, 72 MFC_PLL_LOCK, 73 AUD_PLL_LOCK, 74 CC_PLL_CON0, 75 BUS0_PLL_CON0, 76 BUS1_DPLL_CON0, 77 MFC_PLL_CON0, 78 AUD_PLL_CON0, 79 MUX_SEL_TOPC0, 80 MUX_SEL_TOPC1, 81 MUX_SEL_TOPC2, 82 MUX_SEL_TOPC3, 83 DIV_TOPC0, 84 DIV_TOPC1, 85 DIV_TOPC3, 86 }; 87 88 static const struct samsung_mux_clock topc_mux_clks[] __initconst = { 89 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p, 90 MUX_SEL_TOPC0, 0, 1), 91 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p, 92 MUX_SEL_TOPC0, 4, 1), 93 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p, 94 MUX_SEL_TOPC0, 8, 1), 95 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p, 96 MUX_SEL_TOPC0, 12, 1), 97 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p, 98 MUX_SEL_TOPC0, 16, 2), 99 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p, 100 MUX_SEL_TOPC0, 20, 1), 101 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p, 102 MUX_SEL_TOPC0, 24, 1), 103 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p, 104 MUX_SEL_TOPC0, 28, 1), 105 106 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p, 107 MUX_SEL_TOPC1, 0, 1), 108 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p, 109 MUX_SEL_TOPC1, 16, 1), 110 111 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2), 112 113 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2), 114 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2), 115 }; 116 117 static const struct samsung_div_clock topc_div_clks[] __initconst = { 118 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133", 119 DIV_TOPC0, 4, 4), 120 121 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532", 122 DIV_TOPC1, 20, 4), 123 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66", 124 DIV_TOPC1, 24, 4), 125 126 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out", 127 DIV_TOPC3, 0, 4), 128 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll", 129 DIV_TOPC3, 8, 4), 130 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll", 131 DIV_TOPC3, 12, 4), 132 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll", 133 DIV_TOPC3, 16, 4), 134 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll", 135 DIV_TOPC3, 28, 4), 136 }; 137 138 static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { 139 PLL_36XX_RATE(24 * MHZ, 491519897, 20, 1, 0, 31457), 140 {}, 141 }; 142 143 static const struct samsung_gate_clock topc_gate_clks[] __initconst = { 144 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133", 145 ENABLE_ACLK_TOPC0, 4, CLK_IS_CRITICAL, 0), 146 147 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532", 148 ENABLE_ACLK_TOPC1, 20, 0, 0), 149 150 GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66", 151 ENABLE_ACLK_TOPC1, 24, 0, 0), 152 153 GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll", 154 ENABLE_SCLK_TOPC1, 20, 0, 0), 155 GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll", 156 ENABLE_SCLK_TOPC1, 17, 0, 0), 157 GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll", 158 ENABLE_SCLK_TOPC1, 16, 0, 0), 159 GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll", 160 ENABLE_SCLK_TOPC1, 13, 0, 0), 161 GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll", 162 ENABLE_SCLK_TOPC1, 12, 0, 0), 163 GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll", 164 ENABLE_SCLK_TOPC1, 5, 0, 0), 165 GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll", 166 ENABLE_SCLK_TOPC1, 4, 0, 0), 167 GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll", 168 ENABLE_SCLK_TOPC1, 1, 0, 0), 169 GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll", 170 ENABLE_SCLK_TOPC1, 0, 0, 0), 171 }; 172 173 static const struct samsung_pll_clock topc_pll_clks[] __initconst = { 174 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK, 175 BUS0_PLL_CON0, NULL), 176 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK, 177 CC_PLL_CON0, NULL), 178 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK, 179 BUS1_DPLL_CON0, NULL), 180 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK, 181 MFC_PLL_CON0, NULL), 182 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK, 183 AUD_PLL_CON0, pll1460x_24mhz_tbl), 184 }; 185 186 static const struct samsung_cmu_info topc_cmu_info __initconst = { 187 .pll_clks = topc_pll_clks, 188 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks), 189 .mux_clks = topc_mux_clks, 190 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks), 191 .div_clks = topc_div_clks, 192 .nr_div_clks = ARRAY_SIZE(topc_div_clks), 193 .gate_clks = topc_gate_clks, 194 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks), 195 .fixed_factor_clks = topc_fixed_factor_clks, 196 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks), 197 .nr_clk_ids = TOPC_NR_CLK, 198 .clk_regs = topc_clk_regs, 199 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs), 200 }; 201 202 static void __init exynos7_clk_topc_init(struct device_node *np) 203 { 204 samsung_cmu_register_one(np, &topc_cmu_info); 205 } 206 207 CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc", 208 exynos7_clk_topc_init); 209 210 /* Register Offset definitions for CMU_TOP0 (0x105D0000) */ 211 #define MUX_SEL_TOP00 0x0200 212 #define MUX_SEL_TOP01 0x0204 213 #define MUX_SEL_TOP03 0x020C 214 #define MUX_SEL_TOP0_PERIC0 0x0230 215 #define MUX_SEL_TOP0_PERIC1 0x0234 216 #define MUX_SEL_TOP0_PERIC2 0x0238 217 #define MUX_SEL_TOP0_PERIC3 0x023C 218 #define DIV_TOP03 0x060C 219 #define DIV_TOP0_PERIC0 0x0630 220 #define DIV_TOP0_PERIC1 0x0634 221 #define DIV_TOP0_PERIC2 0x0638 222 #define DIV_TOP0_PERIC3 0x063C 223 #define ENABLE_ACLK_TOP03 0x080C 224 #define ENABLE_SCLK_TOP0_PERIC0 0x0A30 225 #define ENABLE_SCLK_TOP0_PERIC1 0x0A34 226 #define ENABLE_SCLK_TOP0_PERIC2 0x0A38 227 #define ENABLE_SCLK_TOP0_PERIC3 0x0A3C 228 229 /* List of parent clocks for Muxes in CMU_TOP0 */ 230 PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" }; 231 PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" }; 232 PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" }; 233 PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" }; 234 PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" }; 235 236 PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user", 237 "ffac_top0_bus0_pll_div2"}; 238 PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user", 239 "ffac_top0_bus1_pll_div2"}; 240 PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user", 241 "ffac_top0_cc_pll_div2"}; 242 PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user", 243 "ffac_top0_mfc_pll_div2"}; 244 245 PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half", 246 "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half", 247 "mout_top0_mfc_pll_half"}; 248 PNAME(mout_top0_group3) = {"ioclk_audiocdclk0", 249 "ioclk_audiocdclk1", "ioclk_spdif_extclk", 250 "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half", 251 "mout_top0_bus1_pll_half"}; 252 PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user", 253 "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"}; 254 255 static const unsigned long top0_clk_regs[] __initconst = { 256 MUX_SEL_TOP00, 257 MUX_SEL_TOP01, 258 MUX_SEL_TOP03, 259 MUX_SEL_TOP0_PERIC0, 260 MUX_SEL_TOP0_PERIC1, 261 MUX_SEL_TOP0_PERIC2, 262 MUX_SEL_TOP0_PERIC3, 263 DIV_TOP03, 264 DIV_TOP0_PERIC0, 265 DIV_TOP0_PERIC1, 266 DIV_TOP0_PERIC2, 267 DIV_TOP0_PERIC3, 268 ENABLE_SCLK_TOP0_PERIC0, 269 ENABLE_SCLK_TOP0_PERIC1, 270 ENABLE_SCLK_TOP0_PERIC2, 271 ENABLE_SCLK_TOP0_PERIC3, 272 }; 273 274 static const struct samsung_mux_clock top0_mux_clks[] __initconst = { 275 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p, 276 MUX_SEL_TOP00, 0, 1), 277 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p, 278 MUX_SEL_TOP00, 4, 1), 279 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p, 280 MUX_SEL_TOP00, 8, 1), 281 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p, 282 MUX_SEL_TOP00, 12, 1), 283 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p, 284 MUX_SEL_TOP00, 16, 1), 285 286 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p, 287 MUX_SEL_TOP01, 4, 1), 288 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p, 289 MUX_SEL_TOP01, 8, 1), 290 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p, 291 MUX_SEL_TOP01, 12, 1), 292 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p, 293 MUX_SEL_TOP01, 16, 1), 294 295 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2), 296 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2), 297 298 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3), 299 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2), 300 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2), 301 302 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2), 303 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2), 304 305 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2), 306 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2), 307 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2), 308 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2), 309 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2), 310 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2), 311 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2), 312 }; 313 314 static const struct samsung_div_clock top0_div_clks[] __initconst = { 315 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66", 316 DIV_TOP03, 12, 6), 317 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66", 318 DIV_TOP03, 20, 6), 319 320 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4), 321 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12), 322 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10), 323 324 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12), 325 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12), 326 327 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12), 328 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12), 329 330 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4), 331 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4), 332 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4), 333 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4), 334 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12), 335 }; 336 337 static const struct samsung_gate_clock top0_gate_clks[] __initconst = { 338 GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66", 339 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0), 340 GATE(CLK_ACLK_PERIC1_66, "aclk_peric1_66", "dout_aclk_peric1_66", 341 ENABLE_ACLK_TOP03, 12, CLK_SET_RATE_PARENT, 0), 342 343 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif", 344 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 345 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1", 346 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 347 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1", 348 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0), 349 350 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1", 351 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0), 352 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0", 353 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 354 355 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3", 356 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0), 357 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2", 358 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0), 359 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3", 360 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0), 361 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2", 362 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0), 363 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1", 364 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0), 365 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0", 366 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0), 367 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4", 368 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0), 369 }; 370 371 static const struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initconst = { 372 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user", 373 1, 2, 0), 374 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user", 375 1, 2, 0), 376 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0), 377 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0), 378 }; 379 380 static const struct samsung_cmu_info top0_cmu_info __initconst = { 381 .mux_clks = top0_mux_clks, 382 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks), 383 .div_clks = top0_div_clks, 384 .nr_div_clks = ARRAY_SIZE(top0_div_clks), 385 .gate_clks = top0_gate_clks, 386 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks), 387 .fixed_factor_clks = top0_fixed_factor_clks, 388 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks), 389 .nr_clk_ids = TOP0_NR_CLK, 390 .clk_regs = top0_clk_regs, 391 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs), 392 }; 393 394 static void __init exynos7_clk_top0_init(struct device_node *np) 395 { 396 samsung_cmu_register_one(np, &top0_cmu_info); 397 } 398 399 CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 400 exynos7_clk_top0_init); 401 402 /* Register Offset definitions for CMU_TOP1 (0x105E0000) */ 403 #define MUX_SEL_TOP10 0x0200 404 #define MUX_SEL_TOP11 0x0204 405 #define MUX_SEL_TOP13 0x020C 406 #define MUX_SEL_TOP1_FSYS0 0x0224 407 #define MUX_SEL_TOP1_FSYS1 0x0228 408 #define MUX_SEL_TOP1_FSYS11 0x022C 409 #define DIV_TOP13 0x060C 410 #define DIV_TOP1_FSYS0 0x0624 411 #define DIV_TOP1_FSYS1 0x0628 412 #define DIV_TOP1_FSYS11 0x062C 413 #define ENABLE_ACLK_TOP13 0x080C 414 #define ENABLE_SCLK_TOP1_FSYS0 0x0A24 415 #define ENABLE_SCLK_TOP1_FSYS1 0x0A28 416 #define ENABLE_SCLK_TOP1_FSYS11 0x0A2C 417 418 /* List of parent clocks for Muxes in CMU_TOP1 */ 419 PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" }; 420 PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" }; 421 PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" }; 422 PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" }; 423 424 PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user", 425 "ffac_top1_bus0_pll_div2"}; 426 PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user", 427 "ffac_top1_bus1_pll_div2"}; 428 PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user", 429 "ffac_top1_cc_pll_div2"}; 430 PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user", 431 "ffac_top1_mfc_pll_div2"}; 432 433 PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half", 434 "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half", 435 "mout_top1_mfc_pll_half"}; 436 437 static const unsigned long top1_clk_regs[] __initconst = { 438 MUX_SEL_TOP10, 439 MUX_SEL_TOP11, 440 MUX_SEL_TOP13, 441 MUX_SEL_TOP1_FSYS0, 442 MUX_SEL_TOP1_FSYS1, 443 MUX_SEL_TOP1_FSYS11, 444 DIV_TOP13, 445 DIV_TOP1_FSYS0, 446 DIV_TOP1_FSYS1, 447 DIV_TOP1_FSYS11, 448 ENABLE_ACLK_TOP13, 449 ENABLE_SCLK_TOP1_FSYS0, 450 ENABLE_SCLK_TOP1_FSYS1, 451 ENABLE_SCLK_TOP1_FSYS11, 452 }; 453 454 static const struct samsung_mux_clock top1_mux_clks[] __initconst = { 455 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p, 456 MUX_SEL_TOP10, 4, 1), 457 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p, 458 MUX_SEL_TOP10, 8, 1), 459 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p, 460 MUX_SEL_TOP10, 12, 1), 461 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p, 462 MUX_SEL_TOP10, 16, 1), 463 464 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p, 465 MUX_SEL_TOP11, 4, 1), 466 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p, 467 MUX_SEL_TOP11, 8, 1), 468 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p, 469 MUX_SEL_TOP11, 12, 1), 470 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p, 471 MUX_SEL_TOP11, 16, 1), 472 473 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2), 474 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2), 475 476 MUX(0, "mout_sclk_phy_fsys0_26m", mout_top1_group1, 477 MUX_SEL_TOP1_FSYS0, 0, 2), 478 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2), 479 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1, 480 MUX_SEL_TOP1_FSYS0, 28, 2), 481 482 MUX(0, "mout_sclk_phy_fsys1", mout_top1_group1, 483 MUX_SEL_TOP1_FSYS1, 0, 2), 484 MUX(0, "mout_sclk_ufsunipro20", mout_top1_group1, 485 MUX_SEL_TOP1_FSYS1, 16, 2), 486 487 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2), 488 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2), 489 MUX(0, "mout_sclk_phy_fsys1_26m", mout_top1_group1, 490 MUX_SEL_TOP1_FSYS11, 24, 2), 491 }; 492 493 static const struct samsung_div_clock top1_div_clks[] __initconst = { 494 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200", 495 DIV_TOP13, 24, 4), 496 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200", 497 DIV_TOP13, 28, 4), 498 499 DIV(DOUT_SCLK_PHY_FSYS1, "dout_sclk_phy_fsys1", 500 "mout_sclk_phy_fsys1", DIV_TOP1_FSYS1, 0, 6), 501 502 DIV(DOUT_SCLK_UFSUNIPRO20, "dout_sclk_ufsunipro20", 503 "mout_sclk_ufsunipro20", 504 DIV_TOP1_FSYS1, 16, 6), 505 506 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2", 507 DIV_TOP1_FSYS0, 16, 10), 508 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300", 509 DIV_TOP1_FSYS0, 28, 4), 510 511 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1", 512 DIV_TOP1_FSYS11, 0, 10), 513 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0", 514 DIV_TOP1_FSYS11, 12, 10), 515 516 DIV(DOUT_SCLK_PHY_FSYS1_26M, "dout_sclk_phy_fsys1_26m", 517 "mout_sclk_phy_fsys1_26m", DIV_TOP1_FSYS11, 24, 6), 518 }; 519 520 static const struct samsung_gate_clock top1_gate_clks[] __initconst = { 521 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2", 522 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0), 523 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300", 524 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0), 525 526 GATE(CLK_SCLK_PHY_FSYS1, "sclk_phy_fsys1", "dout_sclk_phy_fsys1", 527 ENABLE_SCLK_TOP1_FSYS1, 0, CLK_SET_RATE_PARENT, 0), 528 529 GATE(CLK_SCLK_UFSUNIPRO20, "sclk_ufsunipro20", "dout_sclk_ufsunipro20", 530 ENABLE_SCLK_TOP1_FSYS1, 16, CLK_SET_RATE_PARENT, 0), 531 532 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1", 533 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0), 534 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0", 535 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0), 536 537 GATE(CLK_ACLK_FSYS0_200, "aclk_fsys0_200", "dout_aclk_fsys0_200", 538 ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT | 539 CLK_IS_CRITICAL, 0), 540 GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200", 541 ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0), 542 543 GATE(CLK_SCLK_PHY_FSYS1_26M, "sclk_phy_fsys1_26m", 544 "dout_sclk_phy_fsys1_26m", ENABLE_SCLK_TOP1_FSYS11, 545 24, CLK_SET_RATE_PARENT, 0), 546 }; 547 548 static const struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initconst = { 549 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user", 550 1, 2, 0), 551 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user", 552 1, 2, 0), 553 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0), 554 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0), 555 }; 556 557 static const struct samsung_cmu_info top1_cmu_info __initconst = { 558 .mux_clks = top1_mux_clks, 559 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks), 560 .div_clks = top1_div_clks, 561 .nr_div_clks = ARRAY_SIZE(top1_div_clks), 562 .gate_clks = top1_gate_clks, 563 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks), 564 .fixed_factor_clks = top1_fixed_factor_clks, 565 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks), 566 .nr_clk_ids = TOP1_NR_CLK, 567 .clk_regs = top1_clk_regs, 568 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs), 569 }; 570 571 static void __init exynos7_clk_top1_init(struct device_node *np) 572 { 573 samsung_cmu_register_one(np, &top1_cmu_info); 574 } 575 576 CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1", 577 exynos7_clk_top1_init); 578 579 /* Register Offset definitions for CMU_CCORE (0x105B0000) */ 580 #define MUX_SEL_CCORE 0x0200 581 #define DIV_CCORE 0x0600 582 #define ENABLE_ACLK_CCORE0 0x0800 583 #define ENABLE_ACLK_CCORE1 0x0804 584 #define ENABLE_PCLK_CCORE 0x0900 585 586 /* 587 * List of parent clocks for Muxes in CMU_CCORE 588 */ 589 PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" }; 590 591 static const unsigned long ccore_clk_regs[] __initconst = { 592 MUX_SEL_CCORE, 593 ENABLE_PCLK_CCORE, 594 }; 595 596 static const struct samsung_mux_clock ccore_mux_clks[] __initconst = { 597 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p, 598 MUX_SEL_CCORE, 1, 1), 599 }; 600 601 static const struct samsung_gate_clock ccore_gate_clks[] __initconst = { 602 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user", 603 ENABLE_PCLK_CCORE, 8, 0, 0), 604 }; 605 606 static const struct samsung_cmu_info ccore_cmu_info __initconst = { 607 .mux_clks = ccore_mux_clks, 608 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks), 609 .gate_clks = ccore_gate_clks, 610 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks), 611 .nr_clk_ids = CCORE_NR_CLK, 612 .clk_regs = ccore_clk_regs, 613 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs), 614 }; 615 616 static void __init exynos7_clk_ccore_init(struct device_node *np) 617 { 618 samsung_cmu_register_one(np, &ccore_cmu_info); 619 } 620 621 CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore", 622 exynos7_clk_ccore_init); 623 624 /* Register Offset definitions for CMU_PERIC0 (0x13610000) */ 625 #define MUX_SEL_PERIC0 0x0200 626 #define ENABLE_PCLK_PERIC0 0x0900 627 #define ENABLE_SCLK_PERIC0 0x0A00 628 629 /* List of parent clocks for Muxes in CMU_PERIC0 */ 630 PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" }; 631 PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" }; 632 633 static const unsigned long peric0_clk_regs[] __initconst = { 634 MUX_SEL_PERIC0, 635 ENABLE_PCLK_PERIC0, 636 ENABLE_SCLK_PERIC0, 637 }; 638 639 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = { 640 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p, 641 MUX_SEL_PERIC0, 0, 1), 642 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p, 643 MUX_SEL_PERIC0, 16, 1), 644 }; 645 646 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = { 647 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user", 648 ENABLE_PCLK_PERIC0, 8, 0, 0), 649 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user", 650 ENABLE_PCLK_PERIC0, 9, 0, 0), 651 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user", 652 ENABLE_PCLK_PERIC0, 10, 0, 0), 653 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user", 654 ENABLE_PCLK_PERIC0, 11, 0, 0), 655 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user", 656 ENABLE_PCLK_PERIC0, 12, 0, 0), 657 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user", 658 ENABLE_PCLK_PERIC0, 13, 0, 0), 659 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user", 660 ENABLE_PCLK_PERIC0, 14, 0, 0), 661 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user", 662 ENABLE_PCLK_PERIC0, 16, 0, 0), 663 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user", 664 ENABLE_PCLK_PERIC0, 20, 0, 0), 665 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user", 666 ENABLE_PCLK_PERIC0, 21, 0, 0), 667 668 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user", 669 ENABLE_SCLK_PERIC0, 16, 0, 0), 670 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0), 671 }; 672 673 static const struct samsung_cmu_info peric0_cmu_info __initconst = { 674 .mux_clks = peric0_mux_clks, 675 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks), 676 .gate_clks = peric0_gate_clks, 677 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks), 678 .nr_clk_ids = PERIC0_NR_CLK, 679 .clk_regs = peric0_clk_regs, 680 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs), 681 }; 682 683 static void __init exynos7_clk_peric0_init(struct device_node *np) 684 { 685 samsung_cmu_register_one(np, &peric0_cmu_info); 686 } 687 688 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */ 689 #define MUX_SEL_PERIC10 0x0200 690 #define MUX_SEL_PERIC11 0x0204 691 #define MUX_SEL_PERIC12 0x0208 692 #define ENABLE_PCLK_PERIC1 0x0900 693 #define ENABLE_SCLK_PERIC10 0x0A00 694 695 CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0", 696 exynos7_clk_peric0_init); 697 698 /* List of parent clocks for Muxes in CMU_PERIC1 */ 699 PNAME(mout_aclk_peric1_66_user_p) = { "fin_pll", "aclk_peric1_66" }; 700 PNAME(mout_sclk_uart1_user_p) = { "fin_pll", "sclk_uart1" }; 701 PNAME(mout_sclk_uart2_user_p) = { "fin_pll", "sclk_uart2" }; 702 PNAME(mout_sclk_uart3_user_p) = { "fin_pll", "sclk_uart3" }; 703 PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" }; 704 PNAME(mout_sclk_spi1_user_p) = { "fin_pll", "sclk_spi1" }; 705 PNAME(mout_sclk_spi2_user_p) = { "fin_pll", "sclk_spi2" }; 706 PNAME(mout_sclk_spi3_user_p) = { "fin_pll", "sclk_spi3" }; 707 PNAME(mout_sclk_spi4_user_p) = { "fin_pll", "sclk_spi4" }; 708 709 static const unsigned long peric1_clk_regs[] __initconst = { 710 MUX_SEL_PERIC10, 711 MUX_SEL_PERIC11, 712 MUX_SEL_PERIC12, 713 ENABLE_PCLK_PERIC1, 714 ENABLE_SCLK_PERIC10, 715 }; 716 717 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = { 718 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_user_p, 719 MUX_SEL_PERIC10, 0, 1), 720 721 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_user_p, 722 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0), 723 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_user_p, 724 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0), 725 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_user_p, 726 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0), 727 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_user_p, 728 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0), 729 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_user_p, 730 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0), 731 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_user_p, 732 MUX_SEL_PERIC11, 20, 1), 733 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_user_p, 734 MUX_SEL_PERIC11, 24, 1), 735 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_user_p, 736 MUX_SEL_PERIC11, 28, 1), 737 }; 738 739 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = { 740 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user", 741 ENABLE_PCLK_PERIC1, 4, 0, 0), 742 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user", 743 ENABLE_PCLK_PERIC1, 5, 0, 0), 744 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user", 745 ENABLE_PCLK_PERIC1, 6, 0, 0), 746 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user", 747 ENABLE_PCLK_PERIC1, 7, 0, 0), 748 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user", 749 ENABLE_PCLK_PERIC1, 8, 0, 0), 750 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user", 751 ENABLE_PCLK_PERIC1, 9, 0, 0), 752 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user", 753 ENABLE_PCLK_PERIC1, 10, 0, 0), 754 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user", 755 ENABLE_PCLK_PERIC1, 11, 0, 0), 756 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user", 757 ENABLE_PCLK_PERIC1, 12, 0, 0), 758 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user", 759 ENABLE_PCLK_PERIC1, 13, 0, 0), 760 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user", 761 ENABLE_PCLK_PERIC1, 14, 0, 0), 762 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user", 763 ENABLE_PCLK_PERIC1, 15, 0, 0), 764 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user", 765 ENABLE_PCLK_PERIC1, 16, 0, 0), 766 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user", 767 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0), 768 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user", 769 ENABLE_PCLK_PERIC1, 18, 0, 0), 770 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user", 771 ENABLE_PCLK_PERIC1, 19, 0, 0), 772 773 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user", 774 ENABLE_SCLK_PERIC10, 9, 0, 0), 775 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user", 776 ENABLE_SCLK_PERIC10, 10, 0, 0), 777 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user", 778 ENABLE_SCLK_PERIC10, 11, 0, 0), 779 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user", 780 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0), 781 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user", 782 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0), 783 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user", 784 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0), 785 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user", 786 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0), 787 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user", 788 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0), 789 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1", 790 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0), 791 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1", 792 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0), 793 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif", 794 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0), 795 }; 796 797 static const struct samsung_cmu_info peric1_cmu_info __initconst = { 798 .mux_clks = peric1_mux_clks, 799 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks), 800 .gate_clks = peric1_gate_clks, 801 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks), 802 .nr_clk_ids = PERIC1_NR_CLK, 803 .clk_regs = peric1_clk_regs, 804 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs), 805 }; 806 807 static void __init exynos7_clk_peric1_init(struct device_node *np) 808 { 809 samsung_cmu_register_one(np, &peric1_cmu_info); 810 } 811 812 CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1", 813 exynos7_clk_peric1_init); 814 815 /* Register Offset definitions for CMU_PERIS (0x10040000) */ 816 #define MUX_SEL_PERIS 0x0200 817 #define ENABLE_PCLK_PERIS 0x0900 818 #define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910 819 #define ENABLE_SCLK_PERIS 0x0A00 820 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10 821 822 /* List of parent clocks for Muxes in CMU_PERIS */ 823 PNAME(mout_aclk_peris_66_user_p) = { "fin_pll", "aclk_peris_66" }; 824 825 static const unsigned long peris_clk_regs[] __initconst = { 826 MUX_SEL_PERIS, 827 ENABLE_PCLK_PERIS, 828 ENABLE_PCLK_PERIS_SECURE_CHIPID, 829 ENABLE_SCLK_PERIS, 830 ENABLE_SCLK_PERIS_SECURE_CHIPID, 831 }; 832 833 static const struct samsung_mux_clock peris_mux_clks[] __initconst = { 834 MUX(0, "mout_aclk_peris_66_user", 835 mout_aclk_peris_66_user_p, MUX_SEL_PERIS, 0, 1), 836 }; 837 838 static const struct samsung_gate_clock peris_gate_clks[] __initconst = { 839 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user", 840 ENABLE_PCLK_PERIS, 6, 0, 0), 841 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user", 842 ENABLE_PCLK_PERIS, 10, 0, 0), 843 844 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user", 845 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 846 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll", 847 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0), 848 849 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0), 850 }; 851 852 static const struct samsung_cmu_info peris_cmu_info __initconst = { 853 .mux_clks = peris_mux_clks, 854 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks), 855 .gate_clks = peris_gate_clks, 856 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 857 .nr_clk_ids = PERIS_NR_CLK, 858 .clk_regs = peris_clk_regs, 859 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 860 }; 861 862 static void __init exynos7_clk_peris_init(struct device_node *np) 863 { 864 samsung_cmu_register_one(np, &peris_cmu_info); 865 } 866 867 CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris", 868 exynos7_clk_peris_init); 869 870 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */ 871 #define MUX_SEL_FSYS00 0x0200 872 #define MUX_SEL_FSYS01 0x0204 873 #define MUX_SEL_FSYS02 0x0208 874 #define ENABLE_ACLK_FSYS00 0x0800 875 #define ENABLE_ACLK_FSYS01 0x0804 876 #define ENABLE_SCLK_FSYS01 0x0A04 877 #define ENABLE_SCLK_FSYS02 0x0A08 878 #define ENABLE_SCLK_FSYS04 0x0A10 879 880 /* 881 * List of parent clocks for Muxes in CMU_FSYS0 882 */ 883 PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" }; 884 PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" }; 885 886 PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" }; 887 PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll", 888 "phyclk_usbdrd300_udrd30_phyclock" }; 889 PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", 890 "phyclk_usbdrd300_udrd30_pipe_pclk" }; 891 892 /* fixed rate clocks used in the FSYS0 block */ 893 static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initconst = { 894 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000), 895 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000), 896 }; 897 898 static const unsigned long fsys0_clk_regs[] __initconst = { 899 MUX_SEL_FSYS00, 900 MUX_SEL_FSYS01, 901 MUX_SEL_FSYS02, 902 ENABLE_ACLK_FSYS00, 903 ENABLE_ACLK_FSYS01, 904 ENABLE_SCLK_FSYS01, 905 ENABLE_SCLK_FSYS02, 906 ENABLE_SCLK_FSYS04, 907 }; 908 909 static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { 910 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_user_p, 911 MUX_SEL_FSYS00, 24, 1), 912 913 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_user_p, 914 MUX_SEL_FSYS01, 24, 1), 915 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_user_p, 916 MUX_SEL_FSYS01, 28, 1), 917 918 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 919 mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p, 920 MUX_SEL_FSYS02, 24, 1), 921 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user", 922 mout_phyclk_usbdrd300_udrd30_phyclk_user_p, 923 MUX_SEL_FSYS02, 28, 1), 924 }; 925 926 static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { 927 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", 928 ENABLE_ACLK_FSYS00, 3, 0, 0), 929 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", 930 ENABLE_ACLK_FSYS00, 4, 0, 0), 931 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", 932 "mout_aclk_fsys0_200_user", 933 ENABLE_ACLK_FSYS00, 19, 0, 0), 934 935 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", 936 ENABLE_ACLK_FSYS01, 29, 0, 0), 937 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user", 938 ENABLE_ACLK_FSYS01, 31, 0, 0), 939 940 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk", 941 "mout_sclk_usbdrd300_user", 942 ENABLE_SCLK_FSYS01, 4, 0, 0), 943 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll", 944 ENABLE_SCLK_FSYS01, 8, 0, 0), 945 946 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER, 947 "phyclk_usbdrd300_udrd30_pipe_pclk_user", 948 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user", 949 ENABLE_SCLK_FSYS02, 24, 0, 0), 950 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER, 951 "phyclk_usbdrd300_udrd30_phyclk_user", 952 "mout_phyclk_usbdrd300_udrd30_phyclk_user", 953 ENABLE_SCLK_FSYS02, 28, 0, 0), 954 955 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy", 956 "fin_pll", 957 ENABLE_SCLK_FSYS04, 28, 0, 0), 958 }; 959 960 static const struct samsung_cmu_info fsys0_cmu_info __initconst = { 961 .fixed_clks = fixed_rate_clks_fsys0, 962 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys0), 963 .mux_clks = fsys0_mux_clks, 964 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), 965 .gate_clks = fsys0_gate_clks, 966 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), 967 .nr_clk_ids = FSYS0_NR_CLK, 968 .clk_regs = fsys0_clk_regs, 969 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), 970 }; 971 972 static void __init exynos7_clk_fsys0_init(struct device_node *np) 973 { 974 samsung_cmu_register_one(np, &fsys0_cmu_info); 975 } 976 977 CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0", 978 exynos7_clk_fsys0_init); 979 980 /* Register Offset definitions for CMU_FSYS1 (0x156E0000) */ 981 #define MUX_SEL_FSYS10 0x0200 982 #define MUX_SEL_FSYS11 0x0204 983 #define MUX_SEL_FSYS12 0x0208 984 #define DIV_FSYS1 0x0600 985 #define ENABLE_ACLK_FSYS1 0x0800 986 #define ENABLE_PCLK_FSYS1 0x0900 987 #define ENABLE_SCLK_FSYS11 0x0A04 988 #define ENABLE_SCLK_FSYS12 0x0A08 989 #define ENABLE_SCLK_FSYS13 0x0A0C 990 991 /* 992 * List of parent clocks for Muxes in CMU_FSYS1 993 */ 994 PNAME(mout_aclk_fsys1_200_user_p) = { "fin_pll", "aclk_fsys1_200" }; 995 PNAME(mout_fsys1_group_p) = { "fin_pll", "fin_pll_26m", 996 "sclk_phy_fsys1_26m" }; 997 PNAME(mout_sclk_mmc0_user_p) = { "fin_pll", "sclk_mmc0" }; 998 PNAME(mout_sclk_mmc1_user_p) = { "fin_pll", "sclk_mmc1" }; 999 PNAME(mout_sclk_ufsunipro20_user_p) = { "fin_pll", "sclk_ufsunipro20" }; 1000 PNAME(mout_phyclk_ufs20_tx0_user_p) = { "fin_pll", "phyclk_ufs20_tx0_symbol" }; 1001 PNAME(mout_phyclk_ufs20_rx0_user_p) = { "fin_pll", "phyclk_ufs20_rx0_symbol" }; 1002 PNAME(mout_phyclk_ufs20_rx1_user_p) = { "fin_pll", "phyclk_ufs20_rx1_symbol" }; 1003 1004 /* fixed rate clocks used in the FSYS1 block */ 1005 static const struct samsung_fixed_rate_clock fixed_rate_clks_fsys1[] __initconst = { 1006 FRATE(PHYCLK_UFS20_TX0_SYMBOL, "phyclk_ufs20_tx0_symbol", NULL, 1007 0, 300000000), 1008 FRATE(PHYCLK_UFS20_RX0_SYMBOL, "phyclk_ufs20_rx0_symbol", NULL, 1009 0, 300000000), 1010 FRATE(PHYCLK_UFS20_RX1_SYMBOL, "phyclk_ufs20_rx1_symbol", NULL, 1011 0, 300000000), 1012 }; 1013 1014 static const unsigned long fsys1_clk_regs[] __initconst = { 1015 MUX_SEL_FSYS10, 1016 MUX_SEL_FSYS11, 1017 MUX_SEL_FSYS12, 1018 DIV_FSYS1, 1019 ENABLE_ACLK_FSYS1, 1020 ENABLE_PCLK_FSYS1, 1021 ENABLE_SCLK_FSYS11, 1022 ENABLE_SCLK_FSYS12, 1023 ENABLE_SCLK_FSYS13, 1024 }; 1025 1026 static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { 1027 MUX(MOUT_FSYS1_PHYCLK_SEL1, "mout_fsys1_phyclk_sel1", 1028 mout_fsys1_group_p, MUX_SEL_FSYS10, 16, 2), 1029 MUX(0, "mout_fsys1_phyclk_sel0", mout_fsys1_group_p, 1030 MUX_SEL_FSYS10, 20, 2), 1031 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_user_p, 1032 MUX_SEL_FSYS10, 28, 1), 1033 1034 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_user_p, 1035 MUX_SEL_FSYS11, 24, 1), 1036 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_user_p, 1037 MUX_SEL_FSYS11, 28, 1), 1038 MUX(0, "mout_sclk_ufsunipro20_user", mout_sclk_ufsunipro20_user_p, 1039 MUX_SEL_FSYS11, 20, 1), 1040 1041 MUX(0, "mout_phyclk_ufs20_rx1_symbol_user", 1042 mout_phyclk_ufs20_rx1_user_p, MUX_SEL_FSYS12, 16, 1), 1043 MUX(0, "mout_phyclk_ufs20_rx0_symbol_user", 1044 mout_phyclk_ufs20_rx0_user_p, MUX_SEL_FSYS12, 24, 1), 1045 MUX(0, "mout_phyclk_ufs20_tx0_symbol_user", 1046 mout_phyclk_ufs20_tx0_user_p, MUX_SEL_FSYS12, 28, 1), 1047 }; 1048 1049 static const struct samsung_div_clock fsys1_div_clks[] __initconst = { 1050 DIV(DOUT_PCLK_FSYS1, "dout_pclk_fsys1", "mout_aclk_fsys1_200_user", 1051 DIV_FSYS1, 0, 2), 1052 }; 1053 1054 static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { 1055 GATE(SCLK_UFSUNIPRO20_USER, "sclk_ufsunipro20_user", 1056 "mout_sclk_ufsunipro20_user", 1057 ENABLE_SCLK_FSYS11, 20, 0, 0), 1058 1059 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user", 1060 ENABLE_ACLK_FSYS1, 29, 0, 0), 1061 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user", 1062 ENABLE_ACLK_FSYS1, 30, 0, 0), 1063 1064 GATE(ACLK_UFS20_LINK, "aclk_ufs20_link", "dout_pclk_fsys1", 1065 ENABLE_ACLK_FSYS1, 31, 0, 0), 1066 GATE(PCLK_GPIO_FSYS1, "pclk_gpio_fsys1", "mout_aclk_fsys1_200_user", 1067 ENABLE_PCLK_FSYS1, 30, 0, 0), 1068 1069 GATE(PHYCLK_UFS20_RX1_SYMBOL_USER, "phyclk_ufs20_rx1_symbol_user", 1070 "mout_phyclk_ufs20_rx1_symbol_user", 1071 ENABLE_SCLK_FSYS12, 16, 0, 0), 1072 GATE(PHYCLK_UFS20_RX0_SYMBOL_USER, "phyclk_ufs20_rx0_symbol_user", 1073 "mout_phyclk_ufs20_rx0_symbol_user", 1074 ENABLE_SCLK_FSYS12, 24, 0, 0), 1075 GATE(PHYCLK_UFS20_TX0_SYMBOL_USER, "phyclk_ufs20_tx0_symbol_user", 1076 "mout_phyclk_ufs20_tx0_symbol_user", 1077 ENABLE_SCLK_FSYS12, 28, 0, 0), 1078 1079 GATE(OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY, 1080 "oscclk_phy_clkout_embedded_combo_phy", 1081 "fin_pll", 1082 ENABLE_SCLK_FSYS12, 4, CLK_IGNORE_UNUSED, 0), 1083 1084 GATE(SCLK_COMBO_PHY_EMBEDDED_26M, "sclk_combo_phy_embedded_26m", 1085 "mout_fsys1_phyclk_sel1", 1086 ENABLE_SCLK_FSYS13, 24, CLK_IGNORE_UNUSED, 0), 1087 }; 1088 1089 static const struct samsung_cmu_info fsys1_cmu_info __initconst = { 1090 .fixed_clks = fixed_rate_clks_fsys1, 1091 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks_fsys1), 1092 .mux_clks = fsys1_mux_clks, 1093 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), 1094 .div_clks = fsys1_div_clks, 1095 .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), 1096 .gate_clks = fsys1_gate_clks, 1097 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), 1098 .nr_clk_ids = FSYS1_NR_CLK, 1099 .clk_regs = fsys1_clk_regs, 1100 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), 1101 }; 1102 1103 static void __init exynos7_clk_fsys1_init(struct device_node *np) 1104 { 1105 samsung_cmu_register_one(np, &fsys1_cmu_info); 1106 } 1107 1108 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1", 1109 exynos7_clk_fsys1_init); 1110 1111 #define MUX_SEL_MSCL 0x0200 1112 #define DIV_MSCL 0x0600 1113 #define ENABLE_ACLK_MSCL 0x0800 1114 #define ENABLE_PCLK_MSCL 0x0900 1115 1116 /* List of parent clocks for Muxes in CMU_MSCL */ 1117 PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" }; 1118 1119 static const unsigned long mscl_clk_regs[] __initconst = { 1120 MUX_SEL_MSCL, 1121 DIV_MSCL, 1122 ENABLE_ACLK_MSCL, 1123 ENABLE_PCLK_MSCL, 1124 }; 1125 1126 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { 1127 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532", 1128 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1), 1129 }; 1130 static const struct samsung_div_clock mscl_div_clks[] __initconst = { 1131 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532", 1132 DIV_MSCL, 0, 3), 1133 }; 1134 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { 1135 1136 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532", 1137 ENABLE_ACLK_MSCL, 31, 0, 0), 1138 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532", 1139 ENABLE_ACLK_MSCL, 30, 0, 0), 1140 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532", 1141 ENABLE_ACLK_MSCL, 29, 0, 0), 1142 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532", 1143 ENABLE_ACLK_MSCL, 28, 0, 0), 1144 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0", 1145 "usermux_aclk_mscl_532", 1146 ENABLE_ACLK_MSCL, 27, 0, 0), 1147 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1", 1148 "usermux_aclk_mscl_532", 1149 ENABLE_ACLK_MSCL, 26, 0, 0), 1150 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532", 1151 ENABLE_ACLK_MSCL, 25, 0, 0), 1152 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532", 1153 ENABLE_ACLK_MSCL, 24, 0, 0), 1154 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge", 1155 "usermux_aclk_mscl_532", 1156 ENABLE_ACLK_MSCL, 23, 0, 0), 1157 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532", 1158 ENABLE_ACLK_MSCL, 22, 0, 0), 1159 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532", 1160 ENABLE_ACLK_MSCL, 21, 0, 0), 1161 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532", 1162 ENABLE_ACLK_MSCL, 20, 0, 0), 1163 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532", 1164 ENABLE_ACLK_MSCL, 19, 0, 0), 1165 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532", 1166 ENABLE_ACLK_MSCL, 18, 0, 0), 1167 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532", 1168 ENABLE_ACLK_MSCL, 17, 0, 0), 1169 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532", 1170 ENABLE_ACLK_MSCL, 16, 0, 0), 1171 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p", 1172 "usermux_aclk_mscl_532", 1173 ENABLE_ACLK_MSCL, 15, 0, 0), 1174 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p", 1175 "usermux_aclk_mscl_532", 1176 ENABLE_ACLK_MSCL, 14, 0, 0), 1177 1178 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl", 1179 ENABLE_PCLK_MSCL, 31, 0, 0), 1180 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl", 1181 ENABLE_PCLK_MSCL, 30, 0, 0), 1182 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl", 1183 ENABLE_PCLK_MSCL, 29, 0, 0), 1184 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl", 1185 ENABLE_PCLK_MSCL, 28, 0, 0), 1186 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl", 1187 ENABLE_PCLK_MSCL, 27, 0, 0), 1188 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl", 1189 ENABLE_PCLK_MSCL, 26, 0, 0), 1190 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl", 1191 ENABLE_PCLK_MSCL, 25, 0, 0), 1192 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl", 1193 ENABLE_PCLK_MSCL, 24, 0, 0), 1194 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl", 1195 ENABLE_PCLK_MSCL, 23, 0, 0), 1196 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl", 1197 ENABLE_PCLK_MSCL, 22, 0, 0), 1198 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl", 1199 ENABLE_PCLK_MSCL, 21, 0, 0), 1200 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl", 1201 ENABLE_PCLK_MSCL, 20, 0, 0), 1202 }; 1203 1204 static const struct samsung_cmu_info mscl_cmu_info __initconst = { 1205 .mux_clks = mscl_mux_clks, 1206 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 1207 .div_clks = mscl_div_clks, 1208 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 1209 .gate_clks = mscl_gate_clks, 1210 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 1211 .nr_clk_ids = MSCL_NR_CLK, 1212 .clk_regs = mscl_clk_regs, 1213 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 1214 }; 1215 1216 static void __init exynos7_clk_mscl_init(struct device_node *np) 1217 { 1218 samsung_cmu_register_one(np, &mscl_cmu_info); 1219 } 1220 1221 CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl", 1222 exynos7_clk_mscl_init); 1223 1224 /* Register Offset definitions for CMU_AUD (0x114C0000) */ 1225 #define MUX_SEL_AUD 0x0200 1226 #define DIV_AUD0 0x0600 1227 #define DIV_AUD1 0x0604 1228 #define ENABLE_ACLK_AUD 0x0800 1229 #define ENABLE_PCLK_AUD 0x0900 1230 #define ENABLE_SCLK_AUD 0x0A00 1231 1232 /* 1233 * List of parent clocks for Muxes in CMU_AUD 1234 */ 1235 PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" }; 1236 PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" }; 1237 1238 static const unsigned long aud_clk_regs[] __initconst = { 1239 MUX_SEL_AUD, 1240 DIV_AUD0, 1241 DIV_AUD1, 1242 ENABLE_ACLK_AUD, 1243 ENABLE_PCLK_AUD, 1244 ENABLE_SCLK_AUD, 1245 }; 1246 1247 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 1248 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1), 1249 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1), 1250 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1), 1251 }; 1252 1253 static const struct samsung_div_clock aud_div_clks[] __initconst = { 1254 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4), 1255 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4), 1256 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4), 1257 1258 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4), 1259 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8), 1260 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4), 1261 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5), 1262 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4), 1263 }; 1264 1265 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 1266 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm", 1267 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1268 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s", 1269 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0), 1270 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0), 1271 GATE(0, "sclk_slimbus", "dout_sclk_slimbus", 1272 ENABLE_SCLK_AUD, 30, 0, 0), 1273 1274 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0), 1275 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0), 1276 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0), 1277 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0), 1278 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0), 1279 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0), 1280 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud", 1281 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0), 1282 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud", 1283 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0), 1284 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0), 1285 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0), 1286 1287 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0), 1288 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud", 1289 ENABLE_ACLK_AUD, 28, 0, 0), 1290 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0), 1291 }; 1292 1293 static const struct samsung_cmu_info aud_cmu_info __initconst = { 1294 .mux_clks = aud_mux_clks, 1295 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 1296 .div_clks = aud_div_clks, 1297 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 1298 .gate_clks = aud_gate_clks, 1299 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 1300 .nr_clk_ids = AUD_NR_CLK, 1301 .clk_regs = aud_clk_regs, 1302 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 1303 }; 1304 1305 static void __init exynos7_clk_aud_init(struct device_node *np) 1306 { 1307 samsung_cmu_register_one(np, &aud_cmu_info); 1308 } 1309 1310 CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud", 1311 exynos7_clk_aud_init); 1312