1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Common Clock Framework support for Exynos5443 SoC. 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 16 #include <dt-bindings/clock/exynos5433.h> 17 18 #include "clk.h" 19 #include "clk-cpu.h" 20 #include "clk-pll.h" 21 22 /* 23 * Register offset definitions for CMU_TOP 24 */ 25 #define ISP_PLL_LOCK 0x0000 26 #define AUD_PLL_LOCK 0x0004 27 #define ISP_PLL_CON0 0x0100 28 #define ISP_PLL_CON1 0x0104 29 #define ISP_PLL_FREQ_DET 0x0108 30 #define AUD_PLL_CON0 0x0110 31 #define AUD_PLL_CON1 0x0114 32 #define AUD_PLL_CON2 0x0118 33 #define AUD_PLL_FREQ_DET 0x011c 34 #define MUX_SEL_TOP0 0x0200 35 #define MUX_SEL_TOP1 0x0204 36 #define MUX_SEL_TOP2 0x0208 37 #define MUX_SEL_TOP3 0x020c 38 #define MUX_SEL_TOP4 0x0210 39 #define MUX_SEL_TOP_MSCL 0x0220 40 #define MUX_SEL_TOP_CAM1 0x0224 41 #define MUX_SEL_TOP_DISP 0x0228 42 #define MUX_SEL_TOP_FSYS0 0x0230 43 #define MUX_SEL_TOP_FSYS1 0x0234 44 #define MUX_SEL_TOP_PERIC0 0x0238 45 #define MUX_SEL_TOP_PERIC1 0x023c 46 #define MUX_ENABLE_TOP0 0x0300 47 #define MUX_ENABLE_TOP1 0x0304 48 #define MUX_ENABLE_TOP2 0x0308 49 #define MUX_ENABLE_TOP3 0x030c 50 #define MUX_ENABLE_TOP4 0x0310 51 #define MUX_ENABLE_TOP_MSCL 0x0320 52 #define MUX_ENABLE_TOP_CAM1 0x0324 53 #define MUX_ENABLE_TOP_DISP 0x0328 54 #define MUX_ENABLE_TOP_FSYS0 0x0330 55 #define MUX_ENABLE_TOP_FSYS1 0x0334 56 #define MUX_ENABLE_TOP_PERIC0 0x0338 57 #define MUX_ENABLE_TOP_PERIC1 0x033c 58 #define MUX_STAT_TOP0 0x0400 59 #define MUX_STAT_TOP1 0x0404 60 #define MUX_STAT_TOP2 0x0408 61 #define MUX_STAT_TOP3 0x040c 62 #define MUX_STAT_TOP4 0x0410 63 #define MUX_STAT_TOP_MSCL 0x0420 64 #define MUX_STAT_TOP_CAM1 0x0424 65 #define MUX_STAT_TOP_FSYS0 0x0430 66 #define MUX_STAT_TOP_FSYS1 0x0434 67 #define MUX_STAT_TOP_PERIC0 0x0438 68 #define MUX_STAT_TOP_PERIC1 0x043c 69 #define DIV_TOP0 0x0600 70 #define DIV_TOP1 0x0604 71 #define DIV_TOP2 0x0608 72 #define DIV_TOP3 0x060c 73 #define DIV_TOP4 0x0610 74 #define DIV_TOP_MSCL 0x0618 75 #define DIV_TOP_CAM10 0x061c 76 #define DIV_TOP_CAM11 0x0620 77 #define DIV_TOP_FSYS0 0x062c 78 #define DIV_TOP_FSYS1 0x0630 79 #define DIV_TOP_FSYS2 0x0634 80 #define DIV_TOP_PERIC0 0x0638 81 #define DIV_TOP_PERIC1 0x063c 82 #define DIV_TOP_PERIC2 0x0640 83 #define DIV_TOP_PERIC3 0x0644 84 #define DIV_TOP_PERIC4 0x0648 85 #define DIV_TOP_PLL_FREQ_DET 0x064c 86 #define DIV_STAT_TOP0 0x0700 87 #define DIV_STAT_TOP1 0x0704 88 #define DIV_STAT_TOP2 0x0708 89 #define DIV_STAT_TOP3 0x070c 90 #define DIV_STAT_TOP4 0x0710 91 #define DIV_STAT_TOP_MSCL 0x0718 92 #define DIV_STAT_TOP_CAM10 0x071c 93 #define DIV_STAT_TOP_CAM11 0x0720 94 #define DIV_STAT_TOP_FSYS0 0x072c 95 #define DIV_STAT_TOP_FSYS1 0x0730 96 #define DIV_STAT_TOP_FSYS2 0x0734 97 #define DIV_STAT_TOP_PERIC0 0x0738 98 #define DIV_STAT_TOP_PERIC1 0x073c 99 #define DIV_STAT_TOP_PERIC2 0x0740 100 #define DIV_STAT_TOP_PERIC3 0x0744 101 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c 102 #define ENABLE_ACLK_TOP 0x0800 103 #define ENABLE_SCLK_TOP 0x0a00 104 #define ENABLE_SCLK_TOP_MSCL 0x0a04 105 #define ENABLE_SCLK_TOP_CAM1 0x0a08 106 #define ENABLE_SCLK_TOP_DISP 0x0a0c 107 #define ENABLE_SCLK_TOP_FSYS 0x0a10 108 #define ENABLE_SCLK_TOP_PERIC 0x0a14 109 #define ENABLE_IP_TOP 0x0b00 110 #define ENABLE_CMU_TOP 0x0c00 111 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04 112 113 static const unsigned long top_clk_regs[] __initconst = { 114 ISP_PLL_LOCK, 115 AUD_PLL_LOCK, 116 ISP_PLL_CON0, 117 ISP_PLL_CON1, 118 ISP_PLL_FREQ_DET, 119 AUD_PLL_CON0, 120 AUD_PLL_CON1, 121 AUD_PLL_CON2, 122 AUD_PLL_FREQ_DET, 123 MUX_SEL_TOP0, 124 MUX_SEL_TOP1, 125 MUX_SEL_TOP2, 126 MUX_SEL_TOP3, 127 MUX_SEL_TOP4, 128 MUX_SEL_TOP_MSCL, 129 MUX_SEL_TOP_CAM1, 130 MUX_SEL_TOP_DISP, 131 MUX_SEL_TOP_FSYS0, 132 MUX_SEL_TOP_FSYS1, 133 MUX_SEL_TOP_PERIC0, 134 MUX_SEL_TOP_PERIC1, 135 MUX_ENABLE_TOP0, 136 MUX_ENABLE_TOP1, 137 MUX_ENABLE_TOP2, 138 MUX_ENABLE_TOP3, 139 MUX_ENABLE_TOP4, 140 MUX_ENABLE_TOP_MSCL, 141 MUX_ENABLE_TOP_CAM1, 142 MUX_ENABLE_TOP_DISP, 143 MUX_ENABLE_TOP_FSYS0, 144 MUX_ENABLE_TOP_FSYS1, 145 MUX_ENABLE_TOP_PERIC0, 146 MUX_ENABLE_TOP_PERIC1, 147 DIV_TOP0, 148 DIV_TOP1, 149 DIV_TOP2, 150 DIV_TOP3, 151 DIV_TOP4, 152 DIV_TOP_MSCL, 153 DIV_TOP_CAM10, 154 DIV_TOP_CAM11, 155 DIV_TOP_FSYS0, 156 DIV_TOP_FSYS1, 157 DIV_TOP_FSYS2, 158 DIV_TOP_PERIC0, 159 DIV_TOP_PERIC1, 160 DIV_TOP_PERIC2, 161 DIV_TOP_PERIC3, 162 DIV_TOP_PERIC4, 163 DIV_TOP_PLL_FREQ_DET, 164 ENABLE_ACLK_TOP, 165 ENABLE_SCLK_TOP, 166 ENABLE_SCLK_TOP_MSCL, 167 ENABLE_SCLK_TOP_CAM1, 168 ENABLE_SCLK_TOP_DISP, 169 ENABLE_SCLK_TOP_FSYS, 170 ENABLE_SCLK_TOP_PERIC, 171 ENABLE_IP_TOP, 172 ENABLE_CMU_TOP, 173 ENABLE_CMU_TOP_DIV_STAT, 174 }; 175 176 /* list of all parent clock list */ 177 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", }; 178 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", }; 179 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", }; 180 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", }; 181 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", }; 182 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", }; 183 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", }; 184 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", }; 185 186 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",}; 187 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",}; 188 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a", 189 "mout_mfc_pll_user", }; 190 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", }; 191 192 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b", 193 "mout_mphy_pll_user", }; 194 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a", 195 "mout_bus_pll_user", }; 196 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", }; 197 198 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user", 199 "mout_mphy_pll_user", }; 200 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a", 201 "mout_mphy_pll_user", }; 202 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a", 203 "mout_mphy_pll_user", }; 204 205 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",}; 206 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", }; 207 208 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",}; 209 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",}; 210 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", }; 211 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",}; 212 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", }; 213 214 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1", 215 "oscclk", "ioclk_spdif_extclk", }; 216 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk", 217 "mout_aud_pll_user_t",}; 218 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk", 219 "mout_aud_pll_user_t",}; 220 221 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", }; 222 223 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = { 224 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0), 225 }; 226 227 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = { 228 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */ 229 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000), 230 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000), 231 /* Xi2s1SDI input clock for SPDIF */ 232 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000), 233 /* XspiCLK[4:0] input clock for SPI */ 234 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000), 235 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000), 236 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000), 237 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000), 238 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000), 239 /* Xi2s1SCLK input clock for I2S1_BCLK */ 240 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000), 241 }; 242 243 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 244 /* MUX_SEL_TOP0 */ 245 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0, 246 4, 1), 247 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0, 248 0, 1), 249 250 /* MUX_SEL_TOP1 */ 251 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t", 252 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1), 253 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p, 254 MUX_SEL_TOP1, 8, 1), 255 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p, 256 MUX_SEL_TOP1, 4, 1), 257 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p, 258 MUX_SEL_TOP1, 0, 1), 259 260 /* MUX_SEL_TOP2 */ 261 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400", 262 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1), 263 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333", 264 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1), 265 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b", 266 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1), 267 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a", 268 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1), 269 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400", 270 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1), 271 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400", 272 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1), 273 274 /* MUX_SEL_TOP3 */ 275 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400", 276 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1), 277 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b", 278 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1), 279 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a", 280 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1), 281 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 282 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1), 283 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b", 284 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1), 285 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a", 286 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1), 287 288 /* MUX_SEL_TOP4 */ 289 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c", 290 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1), 291 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b", 292 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1), 293 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a", 294 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1), 295 296 /* MUX_SEL_TOP_MSCL */ 297 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p, 298 MUX_SEL_TOP_MSCL, 8, 1), 299 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p, 300 MUX_SEL_TOP_MSCL, 4, 1), 301 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p, 302 MUX_SEL_TOP_MSCL, 0, 1), 303 304 /* MUX_SEL_TOP_CAM1 */ 305 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2", 306 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1), 307 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1", 308 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1), 309 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0", 310 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1), 311 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart", 312 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1), 313 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1", 314 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1), 315 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0", 316 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1), 317 318 /* MUX_SEL_TOP_FSYS0 */ 319 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p, 320 MUX_SEL_TOP_FSYS0, 28, 1), 321 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p, 322 MUX_SEL_TOP_FSYS0, 24, 1), 323 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p, 324 MUX_SEL_TOP_FSYS0, 20, 1), 325 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p, 326 MUX_SEL_TOP_FSYS0, 16, 1), 327 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p, 328 MUX_SEL_TOP_FSYS0, 12, 1), 329 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p, 330 MUX_SEL_TOP_FSYS0, 8, 1), 331 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p, 332 MUX_SEL_TOP_FSYS0, 4, 1), 333 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p, 334 MUX_SEL_TOP_FSYS0, 0, 1), 335 336 /* MUX_SEL_TOP_FSYS1 */ 337 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p, 338 MUX_SEL_TOP_FSYS1, 12, 1), 339 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro", 340 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1), 341 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30", 342 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1), 343 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30", 344 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1), 345 346 /* MUX_SEL_TOP_PERIC0 */ 347 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p, 348 MUX_SEL_TOP_PERIC0, 28, 1), 349 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p, 350 MUX_SEL_TOP_PERIC0, 24, 1), 351 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p, 352 MUX_SEL_TOP_PERIC0, 20, 1), 353 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p, 354 MUX_SEL_TOP_PERIC0, 16, 1), 355 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p, 356 MUX_SEL_TOP_PERIC0, 12, 1), 357 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p, 358 MUX_SEL_TOP_PERIC0, 8, 1), 359 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p, 360 MUX_SEL_TOP_PERIC0, 4, 1), 361 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p, 362 MUX_SEL_TOP_PERIC0, 0, 1), 363 364 /* MUX_SEL_TOP_PERIC1 */ 365 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p, 366 MUX_SEL_TOP_PERIC1, 16, 1), 367 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 368 MUX_SEL_TOP_PERIC1, 12, 2), 369 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p, 370 MUX_SEL_TOP_PERIC1, 4, 2), 371 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p, 372 MUX_SEL_TOP_PERIC1, 0, 2), 373 374 /* MUX_SEL_TOP_DISP */ 375 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 376 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1), 377 }; 378 379 static const struct samsung_div_clock top_div_clks[] __initconst = { 380 /* DIV_TOP0 */ 381 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333", 382 DIV_TOP0, 28, 3), 383 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user", 384 DIV_TOP0, 24, 3), 385 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b", 386 DIV_TOP0, 20, 3), 387 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user", 388 DIV_TOP0, 16, 3), 389 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user", 390 DIV_TOP0, 12, 3), 391 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll", 392 DIV_TOP0, 8, 3), 393 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400", 394 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4), 395 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400", 396 "mout_aclk_isp_400", DIV_TOP0, 0, 4), 397 398 /* DIV_TOP1 */ 399 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333", 400 DIV_TOP1, 28, 3), 401 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333", 402 DIV_TOP1, 24, 3), 403 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400", 404 DIV_TOP1, 20, 3), 405 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c", 406 DIV_TOP1, 12, 3), 407 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user", 408 DIV_TOP1, 8, 3), 409 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b", 410 DIV_TOP1, 0, 3), 411 412 /* DIV_TOP2 */ 413 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b", 414 DIV_TOP2, 4, 3), 415 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user", 416 DIV_TOP2, 0, 3), 417 418 /* DIV_TOP3 */ 419 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266", 420 "mout_bus_pll_user", DIV_TOP3, 24, 3), 421 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200", 422 "mout_bus_pll_user", DIV_TOP3, 20, 3), 423 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266", 424 "mout_bus_pll_user", DIV_TOP3, 16, 3), 425 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b", 426 "div_aclk_peric_66_a", DIV_TOP3, 12, 3), 427 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a", 428 "mout_bus_pll_user", DIV_TOP3, 8, 3), 429 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b", 430 "div_aclk_peris_66_a", DIV_TOP3, 4, 3), 431 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a", 432 "mout_bus_pll_user", DIV_TOP3, 0, 3), 433 434 /* DIV_TOP4 */ 435 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user", 436 DIV_TOP4, 8, 3), 437 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400", 438 DIV_TOP4, 4, 3), 439 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user", 440 DIV_TOP4, 0, 3), 441 442 /* DIV_TOP_MSCL */ 443 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c", 444 DIV_TOP_MSCL, 0, 4), 445 446 /* DIV_TOP_CAM10 */ 447 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart", 448 DIV_TOP_CAM10, 24, 5), 449 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b", 450 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8), 451 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a", 452 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4), 453 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b", 454 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8), 455 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a", 456 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4), 457 458 /* DIV_TOP_CAM11 */ 459 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b", 460 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4), 461 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a", 462 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4), 463 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b", 464 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4), 465 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a", 466 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4), 467 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b", 468 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4), 469 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a", 470 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4), 471 472 /* DIV_TOP_FSYS0 */ 473 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a", 474 DIV_TOP_FSYS0, 16, 8), 475 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b", 476 DIV_TOP_FSYS0, 12, 4), 477 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a", 478 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0), 479 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d", 480 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0), 481 482 /* DIV_TOP_FSYS1 */ 483 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a", 484 DIV_TOP_FSYS1, 4, 8), 485 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b", 486 DIV_TOP_FSYS1, 0, 4), 487 488 /* DIV_TOP_FSYS2 */ 489 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100", 490 DIV_TOP_FSYS2, 12, 3), 491 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30", 492 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4), 493 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro", 494 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4), 495 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30", 496 DIV_TOP_FSYS2, 0, 4), 497 498 /* DIV_TOP_PERIC0 */ 499 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a", 500 DIV_TOP_PERIC0, 16, 8), 501 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1", 502 DIV_TOP_PERIC0, 12, 4), 503 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a", 504 DIV_TOP_PERIC0, 4, 8), 505 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0", 506 DIV_TOP_PERIC0, 0, 4), 507 508 /* DIV_TOP_PERIC1 */ 509 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a", 510 DIV_TOP_PERIC1, 4, 8), 511 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2", 512 DIV_TOP_PERIC1, 0, 4), 513 514 /* DIV_TOP_PERIC2 */ 515 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2", 516 DIV_TOP_PERIC2, 8, 4), 517 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0", 518 DIV_TOP_PERIC2, 4, 4), 519 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1", 520 DIV_TOP_PERIC2, 0, 4), 521 522 /* DIV_TOP_PERIC3 */ 523 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1", 524 DIV_TOP_PERIC3, 16, 6), 525 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1", 526 DIV_TOP_PERIC3, 8, 8), 527 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1", 528 DIV_TOP_PERIC3, 4, 4), 529 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0", 530 DIV_TOP_PERIC3, 0, 4), 531 532 /* DIV_TOP_PERIC4 */ 533 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a", 534 DIV_TOP_PERIC4, 16, 8), 535 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4", 536 DIV_TOP_PERIC4, 12, 4), 537 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a", 538 DIV_TOP_PERIC4, 4, 8), 539 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3", 540 DIV_TOP_PERIC4, 0, 4), 541 }; 542 543 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 544 /* ENABLE_ACLK_TOP */ 545 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400", 546 ENABLE_ACLK_TOP, 30, 0, 0), 547 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266", 548 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP, 549 29, CLK_IGNORE_UNUSED, 0), 550 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400", 551 ENABLE_ACLK_TOP, 26, 552 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 553 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400", 554 ENABLE_ACLK_TOP, 25, 555 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 556 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266", 557 ENABLE_ACLK_TOP, 24, 558 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 559 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200", 560 ENABLE_ACLK_TOP, 23, 561 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 562 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b", 563 ENABLE_ACLK_TOP, 22, 564 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 565 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b", 566 ENABLE_ACLK_TOP, 21, 567 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 568 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400", 569 ENABLE_ACLK_TOP, 19, 570 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 571 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200", 572 ENABLE_ACLK_TOP, 18, 573 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 574 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111", 575 ENABLE_ACLK_TOP, 15, 576 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 577 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333", 578 ENABLE_ACLK_TOP, 14, 579 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 580 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333", 581 ENABLE_ACLK_TOP, 13, 582 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 583 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400", 584 ENABLE_ACLK_TOP, 12, 585 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 586 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552", 587 ENABLE_ACLK_TOP, 11, 588 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 589 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333", 590 ENABLE_ACLK_TOP, 10, 591 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 592 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400", 593 ENABLE_ACLK_TOP, 9, 594 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 595 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552", 596 ENABLE_ACLK_TOP, 8, 597 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 598 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400", 599 ENABLE_ACLK_TOP, 7, 600 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 601 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400", 602 ENABLE_ACLK_TOP, 6, 603 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 604 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400", 605 ENABLE_ACLK_TOP, 5, 606 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 607 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400", 608 ENABLE_ACLK_TOP, 3, 609 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 610 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266", 611 ENABLE_ACLK_TOP, 2, 612 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 613 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400", 614 ENABLE_ACLK_TOP, 0, 615 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 616 617 /* ENABLE_SCLK_TOP_MSCL */ 618 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg", 619 ENABLE_SCLK_TOP_MSCL, 0, 0, 0), 620 621 /* ENABLE_SCLK_TOP_CAM1 */ 622 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b", 623 ENABLE_SCLK_TOP_CAM1, 7, 0, 0), 624 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b", 625 ENABLE_SCLK_TOP_CAM1, 6, 0, 0), 626 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b", 627 ENABLE_SCLK_TOP_CAM1, 5, 0, 0), 628 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk", 629 ENABLE_SCLK_TOP_CAM1, 4, 0, 0), 630 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart", 631 ENABLE_SCLK_TOP_CAM1, 2, 0, 0), 632 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b", 633 ENABLE_SCLK_TOP_CAM1, 1, 0, 0), 634 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b", 635 ENABLE_SCLK_TOP_CAM1, 0, 0, 0), 636 637 /* ENABLE_SCLK_TOP_DISP */ 638 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp", 639 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0, 640 CLK_IGNORE_UNUSED, 0), 641 642 /* ENABLE_SCLK_TOP_FSYS */ 643 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100", 644 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0), 645 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b", 646 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0), 647 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b", 648 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0), 649 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b", 650 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0), 651 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys", 652 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS, 653 3, CLK_SET_RATE_PARENT, 0), 654 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys", 655 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS, 656 1, CLK_SET_RATE_PARENT, 0), 657 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys", 658 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS, 659 0, CLK_SET_RATE_PARENT, 0), 660 661 /* ENABLE_SCLK_TOP_PERIC */ 662 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b", 663 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0), 664 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b", 665 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0), 666 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif", 667 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0), 668 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1", 669 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0), 670 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1", 671 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0), 672 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2", 673 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT | 674 CLK_IGNORE_UNUSED, 0), 675 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1", 676 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT | 677 CLK_IGNORE_UNUSED, 0), 678 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0", 679 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT | 680 CLK_IGNORE_UNUSED, 0), 681 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b", 682 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0), 683 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b", 684 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0), 685 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b", 686 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0), 687 688 /* MUX_ENABLE_TOP_PERIC1 */ 689 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus", 690 MUX_ENABLE_TOP_PERIC1, 16, 0, 0), 691 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1", 692 MUX_ENABLE_TOP_PERIC1, 4, 0, 0), 693 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0", 694 MUX_ENABLE_TOP_PERIC1, 0, 0, 0), 695 }; 696 697 /* 698 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL 699 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL 700 */ 701 static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = { 702 PLL_35XX_RATE(2500000000U, 625, 6, 0), 703 PLL_35XX_RATE(2400000000U, 500, 5, 0), 704 PLL_35XX_RATE(2300000000U, 575, 6, 0), 705 PLL_35XX_RATE(2200000000U, 550, 6, 0), 706 PLL_35XX_RATE(2100000000U, 350, 4, 0), 707 PLL_35XX_RATE(2000000000U, 500, 6, 0), 708 PLL_35XX_RATE(1900000000U, 475, 6, 0), 709 PLL_35XX_RATE(1800000000U, 375, 5, 0), 710 PLL_35XX_RATE(1700000000U, 425, 6, 0), 711 PLL_35XX_RATE(1600000000U, 400, 6, 0), 712 PLL_35XX_RATE(1500000000U, 250, 4, 0), 713 PLL_35XX_RATE(1400000000U, 350, 6, 0), 714 PLL_35XX_RATE(1332000000U, 222, 4, 0), 715 PLL_35XX_RATE(1300000000U, 325, 6, 0), 716 PLL_35XX_RATE(1200000000U, 500, 5, 1), 717 PLL_35XX_RATE(1100000000U, 550, 6, 1), 718 PLL_35XX_RATE(1086000000U, 362, 4, 1), 719 PLL_35XX_RATE(1066000000U, 533, 6, 1), 720 PLL_35XX_RATE(1000000000U, 500, 6, 1), 721 PLL_35XX_RATE(933000000U, 311, 4, 1), 722 PLL_35XX_RATE(921000000U, 307, 4, 1), 723 PLL_35XX_RATE(900000000U, 375, 5, 1), 724 PLL_35XX_RATE(825000000U, 275, 4, 1), 725 PLL_35XX_RATE(800000000U, 400, 6, 1), 726 PLL_35XX_RATE(733000000U, 733, 12, 1), 727 PLL_35XX_RATE(700000000U, 175, 3, 1), 728 PLL_35XX_RATE(667000000U, 222, 4, 1), 729 PLL_35XX_RATE(633000000U, 211, 4, 1), 730 PLL_35XX_RATE(600000000U, 500, 5, 2), 731 PLL_35XX_RATE(552000000U, 460, 5, 2), 732 PLL_35XX_RATE(550000000U, 550, 6, 2), 733 PLL_35XX_RATE(543000000U, 362, 4, 2), 734 PLL_35XX_RATE(533000000U, 533, 6, 2), 735 PLL_35XX_RATE(500000000U, 500, 6, 2), 736 PLL_35XX_RATE(444000000U, 370, 5, 2), 737 PLL_35XX_RATE(420000000U, 350, 5, 2), 738 PLL_35XX_RATE(400000000U, 400, 6, 2), 739 PLL_35XX_RATE(350000000U, 350, 6, 2), 740 PLL_35XX_RATE(333000000U, 222, 4, 2), 741 PLL_35XX_RATE(300000000U, 500, 5, 3), 742 PLL_35XX_RATE(266000000U, 532, 6, 3), 743 PLL_35XX_RATE(200000000U, 400, 6, 3), 744 PLL_35XX_RATE(166000000U, 332, 6, 3), 745 PLL_35XX_RATE(160000000U, 320, 6, 3), 746 PLL_35XX_RATE(133000000U, 532, 6, 4), 747 PLL_35XX_RATE(100000000U, 400, 6, 4), 748 { /* sentinel */ } 749 }; 750 751 /* AUD_PLL */ 752 static const struct samsung_pll_rate_table exynos5443_aud_pll_rates[] __initconst = { 753 PLL_36XX_RATE(400000000U, 200, 3, 2, 0), 754 PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), 755 PLL_36XX_RATE(384000000U, 128, 2, 2, 0), 756 PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), 757 PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), 758 PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), 759 PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), 760 PLL_36XX_RATE(288000000U, 96, 1, 3, 0), 761 PLL_36XX_RATE(252000000U, 84, 1, 3, 0), 762 { /* sentinel */ } 763 }; 764 765 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 766 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk", 767 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5443_pll_rates), 768 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", 769 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5443_aud_pll_rates), 770 }; 771 772 static const struct samsung_cmu_info top_cmu_info __initconst = { 773 .pll_clks = top_pll_clks, 774 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 775 .mux_clks = top_mux_clks, 776 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 777 .div_clks = top_div_clks, 778 .nr_div_clks = ARRAY_SIZE(top_div_clks), 779 .gate_clks = top_gate_clks, 780 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 781 .fixed_clks = top_fixed_clks, 782 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks), 783 .fixed_factor_clks = top_fixed_factor_clks, 784 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks), 785 .nr_clk_ids = TOP_NR_CLK, 786 .clk_regs = top_clk_regs, 787 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 788 }; 789 790 static void __init exynos5433_cmu_top_init(struct device_node *np) 791 { 792 samsung_cmu_register_one(np, &top_cmu_info); 793 } 794 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top", 795 exynos5433_cmu_top_init); 796 797 /* 798 * Register offset definitions for CMU_CPIF 799 */ 800 #define MPHY_PLL_LOCK 0x0000 801 #define MPHY_PLL_CON0 0x0100 802 #define MPHY_PLL_CON1 0x0104 803 #define MPHY_PLL_FREQ_DET 0x010c 804 #define MUX_SEL_CPIF0 0x0200 805 #define DIV_CPIF 0x0600 806 #define ENABLE_SCLK_CPIF 0x0a00 807 808 static const unsigned long cpif_clk_regs[] __initconst = { 809 MPHY_PLL_LOCK, 810 MPHY_PLL_CON0, 811 MPHY_PLL_CON1, 812 MPHY_PLL_FREQ_DET, 813 MUX_SEL_CPIF0, 814 DIV_CPIF, 815 ENABLE_SCLK_CPIF, 816 }; 817 818 /* list of all parent clock list */ 819 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", }; 820 821 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = { 822 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk", 823 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5443_pll_rates), 824 }; 825 826 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = { 827 /* MUX_SEL_CPIF0 */ 828 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0, 829 0, 1), 830 }; 831 832 static const struct samsung_div_clock cpif_div_clks[] __initconst = { 833 /* DIV_CPIF */ 834 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF, 835 0, 6), 836 }; 837 838 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = { 839 /* ENABLE_SCLK_CPIF */ 840 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll", 841 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0), 842 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy", 843 ENABLE_SCLK_CPIF, 4, 0, 0), 844 }; 845 846 static const struct samsung_cmu_info cpif_cmu_info __initconst = { 847 .pll_clks = cpif_pll_clks, 848 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks), 849 .mux_clks = cpif_mux_clks, 850 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks), 851 .div_clks = cpif_div_clks, 852 .nr_div_clks = ARRAY_SIZE(cpif_div_clks), 853 .gate_clks = cpif_gate_clks, 854 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks), 855 .nr_clk_ids = CPIF_NR_CLK, 856 .clk_regs = cpif_clk_regs, 857 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs), 858 }; 859 860 static void __init exynos5433_cmu_cpif_init(struct device_node *np) 861 { 862 samsung_cmu_register_one(np, &cpif_cmu_info); 863 } 864 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif", 865 exynos5433_cmu_cpif_init); 866 867 /* 868 * Register offset definitions for CMU_MIF 869 */ 870 #define MEM0_PLL_LOCK 0x0000 871 #define MEM1_PLL_LOCK 0x0004 872 #define BUS_PLL_LOCK 0x0008 873 #define MFC_PLL_LOCK 0x000c 874 #define MEM0_PLL_CON0 0x0100 875 #define MEM0_PLL_CON1 0x0104 876 #define MEM0_PLL_FREQ_DET 0x010c 877 #define MEM1_PLL_CON0 0x0110 878 #define MEM1_PLL_CON1 0x0114 879 #define MEM1_PLL_FREQ_DET 0x011c 880 #define BUS_PLL_CON0 0x0120 881 #define BUS_PLL_CON1 0x0124 882 #define BUS_PLL_FREQ_DET 0x012c 883 #define MFC_PLL_CON0 0x0130 884 #define MFC_PLL_CON1 0x0134 885 #define MFC_PLL_FREQ_DET 0x013c 886 #define MUX_SEL_MIF0 0x0200 887 #define MUX_SEL_MIF1 0x0204 888 #define MUX_SEL_MIF2 0x0208 889 #define MUX_SEL_MIF3 0x020c 890 #define MUX_SEL_MIF4 0x0210 891 #define MUX_SEL_MIF5 0x0214 892 #define MUX_SEL_MIF6 0x0218 893 #define MUX_SEL_MIF7 0x021c 894 #define MUX_ENABLE_MIF0 0x0300 895 #define MUX_ENABLE_MIF1 0x0304 896 #define MUX_ENABLE_MIF2 0x0308 897 #define MUX_ENABLE_MIF3 0x030c 898 #define MUX_ENABLE_MIF4 0x0310 899 #define MUX_ENABLE_MIF5 0x0314 900 #define MUX_ENABLE_MIF6 0x0318 901 #define MUX_ENABLE_MIF7 0x031c 902 #define MUX_STAT_MIF0 0x0400 903 #define MUX_STAT_MIF1 0x0404 904 #define MUX_STAT_MIF2 0x0408 905 #define MUX_STAT_MIF3 0x040c 906 #define MUX_STAT_MIF4 0x0410 907 #define MUX_STAT_MIF5 0x0414 908 #define MUX_STAT_MIF6 0x0418 909 #define MUX_STAT_MIF7 0x041c 910 #define DIV_MIF1 0x0604 911 #define DIV_MIF2 0x0608 912 #define DIV_MIF3 0x060c 913 #define DIV_MIF4 0x0610 914 #define DIV_MIF5 0x0614 915 #define DIV_MIF_PLL_FREQ_DET 0x0618 916 #define DIV_STAT_MIF1 0x0704 917 #define DIV_STAT_MIF2 0x0708 918 #define DIV_STAT_MIF3 0x070c 919 #define DIV_STAT_MIF4 0x0710 920 #define DIV_STAT_MIF5 0x0714 921 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718 922 #define ENABLE_ACLK_MIF0 0x0800 923 #define ENABLE_ACLK_MIF1 0x0804 924 #define ENABLE_ACLK_MIF2 0x0808 925 #define ENABLE_ACLK_MIF3 0x080c 926 #define ENABLE_PCLK_MIF 0x0900 927 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904 928 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908 929 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c 930 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910 931 #define ENABLE_SCLK_MIF 0x0a00 932 #define ENABLE_IP_MIF0 0x0b00 933 #define ENABLE_IP_MIF1 0x0b04 934 #define ENABLE_IP_MIF2 0x0b08 935 #define ENABLE_IP_MIF3 0x0b0c 936 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10 937 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14 938 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18 939 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c 940 #define CLKOUT_CMU_MIF 0x0c00 941 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04 942 #define DREX_FREQ_CTRL0 0x1000 943 #define DREX_FREQ_CTRL1 0x1004 944 #define PAUSE 0x1008 945 #define DDRPHY_LOCK_CTRL 0x100c 946 947 static const unsigned long mif_clk_regs[] __initconst = { 948 MEM0_PLL_LOCK, 949 MEM1_PLL_LOCK, 950 BUS_PLL_LOCK, 951 MFC_PLL_LOCK, 952 MEM0_PLL_CON0, 953 MEM0_PLL_CON1, 954 MEM0_PLL_FREQ_DET, 955 MEM1_PLL_CON0, 956 MEM1_PLL_CON1, 957 MEM1_PLL_FREQ_DET, 958 BUS_PLL_CON0, 959 BUS_PLL_CON1, 960 BUS_PLL_FREQ_DET, 961 MFC_PLL_CON0, 962 MFC_PLL_CON1, 963 MFC_PLL_FREQ_DET, 964 MUX_SEL_MIF0, 965 MUX_SEL_MIF1, 966 MUX_SEL_MIF2, 967 MUX_SEL_MIF3, 968 MUX_SEL_MIF4, 969 MUX_SEL_MIF5, 970 MUX_SEL_MIF6, 971 MUX_SEL_MIF7, 972 MUX_ENABLE_MIF0, 973 MUX_ENABLE_MIF1, 974 MUX_ENABLE_MIF2, 975 MUX_ENABLE_MIF3, 976 MUX_ENABLE_MIF4, 977 MUX_ENABLE_MIF5, 978 MUX_ENABLE_MIF6, 979 MUX_ENABLE_MIF7, 980 DIV_MIF1, 981 DIV_MIF2, 982 DIV_MIF3, 983 DIV_MIF4, 984 DIV_MIF5, 985 DIV_MIF_PLL_FREQ_DET, 986 ENABLE_ACLK_MIF0, 987 ENABLE_ACLK_MIF1, 988 ENABLE_ACLK_MIF2, 989 ENABLE_ACLK_MIF3, 990 ENABLE_PCLK_MIF, 991 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 992 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 993 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 994 ENABLE_PCLK_MIF_SECURE_RTC, 995 ENABLE_SCLK_MIF, 996 ENABLE_IP_MIF0, 997 ENABLE_IP_MIF1, 998 ENABLE_IP_MIF2, 999 ENABLE_IP_MIF3, 1000 ENABLE_IP_MIF_SECURE_DREX0_TZ, 1001 ENABLE_IP_MIF_SECURE_DREX1_TZ, 1002 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT, 1003 ENABLE_IP_MIF_SECURE_RTC, 1004 CLKOUT_CMU_MIF, 1005 CLKOUT_CMU_MIF_DIV_STAT, 1006 DREX_FREQ_CTRL0, 1007 DREX_FREQ_CTRL1, 1008 PAUSE, 1009 DDRPHY_LOCK_CTRL, 1010 }; 1011 1012 static const struct samsung_pll_clock mif_pll_clks[] __initconst = { 1013 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk", 1014 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5443_pll_rates), 1015 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk", 1016 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5443_pll_rates), 1017 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk", 1018 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5443_pll_rates), 1019 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk", 1020 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5443_pll_rates), 1021 }; 1022 1023 /* list of all parent clock list */ 1024 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", }; 1025 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", }; 1026 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", }; 1027 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", }; 1028 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", }; 1029 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", }; 1030 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", }; 1031 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", }; 1032 1033 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", }; 1034 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", }; 1035 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", }; 1036 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", }; 1037 1038 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", }; 1039 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",}; 1040 1041 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a", 1042 "mout_bus_pll_div2", }; 1043 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", }; 1044 1045 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b", 1046 "sclk_mphy_pll", }; 1047 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a", 1048 "mout_mfc_pll_div2", }; 1049 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", }; 1050 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b", 1051 "sclk_mphy_pll", }; 1052 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a", 1053 "mout_mfc_pll_div2", }; 1054 1055 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b", 1056 "sclk_mphy_pll", }; 1057 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a", 1058 "mout_mfc_pll_div2", }; 1059 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", }; 1060 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", }; 1061 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", }; 1062 1063 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", }; 1064 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" }; 1065 1066 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b", 1067 "sclk_mphy_pll", }; 1068 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a", 1069 "mout_mfc_pll_div2", }; 1070 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", }; 1071 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",}; 1072 1073 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = { 1074 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */ 1075 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0), 1076 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0), 1077 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0), 1078 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0), 1079 }; 1080 1081 static const struct samsung_mux_clock mif_mux_clks[] __initconst = { 1082 /* MUX_SEL_MIF0 */ 1083 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p, 1084 MUX_SEL_MIF0, 28, 1), 1085 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p, 1086 MUX_SEL_MIF0, 24, 1), 1087 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p, 1088 MUX_SEL_MIF0, 20, 1), 1089 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p, 1090 MUX_SEL_MIF0, 16, 1), 1091 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0, 1092 12, 1), 1093 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0, 1094 8, 1), 1095 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0, 1096 4, 1), 1097 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0, 1098 0, 1), 1099 1100 /* MUX_SEL_MIF1 */ 1101 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p, 1102 MUX_SEL_MIF1, 24, 1), 1103 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p, 1104 MUX_SEL_MIF1, 20, 1), 1105 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p, 1106 MUX_SEL_MIF1, 16, 1), 1107 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p, 1108 MUX_SEL_MIF1, 12, 1), 1109 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p, 1110 MUX_SEL_MIF1, 8, 1), 1111 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p, 1112 MUX_SEL_MIF1, 4, 1), 1113 1114 /* MUX_SEL_MIF2 */ 1115 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200", 1116 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1), 1117 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400", 1118 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1), 1119 1120 /* MUX_SEL_MIF3 */ 1121 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b", 1122 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1), 1123 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a", 1124 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1), 1125 1126 /* MUX_SEL_MIF4 */ 1127 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c", 1128 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1), 1129 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b", 1130 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1), 1131 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a", 1132 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1), 1133 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c", 1134 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1), 1135 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b", 1136 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1), 1137 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a", 1138 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1), 1139 1140 /* MUX_SEL_MIF5 */ 1141 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c", 1142 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1), 1143 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b", 1144 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1), 1145 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a", 1146 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1), 1147 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p, 1148 MUX_SEL_MIF5, 8, 1), 1149 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p, 1150 MUX_SEL_MIF5, 4, 1), 1151 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p, 1152 MUX_SEL_MIF5, 0, 1), 1153 1154 /* MUX_SEL_MIF6 */ 1155 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p, 1156 MUX_SEL_MIF6, 8, 1), 1157 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p, 1158 MUX_SEL_MIF6, 4, 1), 1159 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p, 1160 MUX_SEL_MIF6, 0, 1), 1161 1162 /* MUX_SEL_MIF7 */ 1163 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c", 1164 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1), 1165 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b", 1166 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1), 1167 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a", 1168 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1), 1169 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p, 1170 MUX_SEL_MIF7, 8, 1), 1171 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p, 1172 MUX_SEL_MIF7, 4, 1), 1173 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p, 1174 MUX_SEL_MIF7, 0, 1), 1175 }; 1176 1177 static const struct samsung_div_clock mif_div_clks[] __initconst = { 1178 /* DIV_MIF1 */ 1179 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy", 1180 DIV_MIF1, 16, 2), 1181 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1, 1182 12, 2), 1183 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1, 1184 8, 2), 1185 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1, 1186 4, 4), 1187 1188 /* DIV_MIF2 */ 1189 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2", 1190 DIV_MIF2, 20, 3), 1191 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre", 1192 DIV_MIF2, 16, 4), 1193 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre", 1194 DIV_MIF2, 12, 4), 1195 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200", 1196 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3), 1197 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400", 1198 DIV_MIF2, 4, 2), 1199 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400", 1200 DIV_MIF2, 0, 3), 1201 1202 /* DIV_MIF3 */ 1203 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre", 1204 DIV_MIF3, 16, 4), 1205 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b", 1206 DIV_MIF3, 4, 3), 1207 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200", 1208 DIV_MIF3, 0, 3), 1209 1210 /* DIV_MIF4 */ 1211 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c", 1212 DIV_MIF4, 24, 4), 1213 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk", 1214 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4), 1215 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c", 1216 DIV_MIF4, 16, 4), 1217 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c", 1218 DIV_MIF4, 12, 4), 1219 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk", 1220 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4), 1221 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk", 1222 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4), 1223 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk", 1224 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4), 1225 1226 /* DIV_MIF5 */ 1227 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5, 1228 0, 3), 1229 }; 1230 1231 static const struct samsung_gate_clock mif_gate_clks[] __initconst = { 1232 /* ENABLE_ACLK_MIF0 */ 1233 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1234 19, CLK_IGNORE_UNUSED, 0), 1235 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0, 1236 18, CLK_IGNORE_UNUSED, 0), 1237 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1238 17, CLK_IGNORE_UNUSED, 0), 1239 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0, 1240 16, CLK_IGNORE_UNUSED, 0), 1241 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0, 1242 15, CLK_IGNORE_UNUSED, 0), 1243 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0, 1244 14, CLK_IGNORE_UNUSED, 0), 1245 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1", 1246 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0), 1247 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0", 1248 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0), 1249 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1", 1250 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0), 1251 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0", 1252 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0), 1253 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1", 1254 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0), 1255 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0", 1256 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0), 1257 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1", 1258 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0), 1259 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0", 1260 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0), 1261 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1", 1262 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0), 1263 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0", 1264 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0), 1265 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1", 1266 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0), 1267 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0", 1268 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1269 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1", 1270 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0), 1271 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0", 1272 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0), 1273 1274 /* ENABLE_ACLK_MIF1 */ 1275 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem", 1276 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28, 1277 CLK_IGNORE_UNUSED, 0), 1278 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci", 1279 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 1280 27, CLK_IGNORE_UNUSED, 0), 1281 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci", 1282 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1283 26, CLK_IGNORE_UNUSED, 0), 1284 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1", 1285 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1286 25, CLK_IGNORE_UNUSED, 0), 1287 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1", 1288 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1289 24, CLK_IGNORE_UNUSED, 0), 1290 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0", 1291 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1, 1292 23, CLK_IGNORE_UNUSED, 0), 1293 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0", 1294 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1295 22, CLK_IGNORE_UNUSED, 0), 1296 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3", 1297 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1298 21, CLK_IGNORE_UNUSED, 0), 1299 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3", 1300 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1301 20, CLK_IGNORE_UNUSED, 0), 1302 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1", 1303 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1304 19, CLK_IGNORE_UNUSED, 0), 1305 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1", 1306 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1307 18, CLK_IGNORE_UNUSED, 0), 1308 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0", 1309 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1310 17, CLK_IGNORE_UNUSED, 0), 1311 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0", 1312 "div_aclk_drex1", ENABLE_ACLK_MIF1, 1313 16, CLK_IGNORE_UNUSED, 0), 1314 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3", 1315 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1316 15, CLK_IGNORE_UNUSED, 0), 1317 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3", 1318 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1319 14, CLK_IGNORE_UNUSED, 0), 1320 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1", 1321 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1322 13, CLK_IGNORE_UNUSED, 0), 1323 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1", 1324 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1325 12, CLK_IGNORE_UNUSED, 0), 1326 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0", 1327 "div_aclk_mif_133", ENABLE_ACLK_MIF1, 1328 11, CLK_IGNORE_UNUSED, 0), 1329 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0", 1330 "div_aclk_drex0", ENABLE_ACLK_MIF1, 1331 10, CLK_IGNORE_UNUSED, 0), 1332 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133", 1333 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0), 1334 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133", 1335 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0), 1336 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133", 1337 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0), 1338 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400", 1339 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0), 1340 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200", 1341 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0), 1342 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133", 1343 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0), 1344 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200", 1345 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0), 1346 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133", 1347 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0), 1348 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400", 1349 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0), 1350 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1, 1351 0, CLK_IGNORE_UNUSED, 0), 1352 1353 /* ENABLE_ACLK_MIF2 */ 1354 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266", 1355 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0), 1356 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1", 1357 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0), 1358 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1", 1359 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0), 1360 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1", 1361 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0), 1362 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0", 1363 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0), 1364 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0", 1365 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0), 1366 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0", 1367 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0), 1368 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx", 1369 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7, 1370 CLK_IGNORE_UNUSED, 0), 1371 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci", 1372 "div_aclk_mif_400", ENABLE_ACLK_MIF2, 1373 5, CLK_IGNORE_UNUSED, 0), 1374 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400", 1375 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0), 1376 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d", 1377 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 1378 3, CLK_IGNORE_UNUSED, 0), 1379 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys", 1380 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0), 1381 1382 /* ENABLE_ACLK_MIF3 */ 1383 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400", 1384 ENABLE_ACLK_MIF3, 4, 1385 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1386 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333", 1387 ENABLE_ACLK_MIF3, 1, 1388 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1389 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200", 1390 ENABLE_ACLK_MIF3, 0, 1391 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1392 1393 /* ENABLE_PCLK_MIF */ 1394 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1", 1395 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0), 1396 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1", 1397 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0), 1398 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1", 1399 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0), 1400 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0", 1401 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0), 1402 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0", 1403 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0), 1404 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0", 1405 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0), 1406 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci", 1407 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21, 1408 CLK_IGNORE_UNUSED, 0), 1409 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133", 1410 ENABLE_PCLK_MIF, 19, 0, 0), 1411 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133", 1412 ENABLE_PCLK_MIF, 18, 0, 0), 1413 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3", 1414 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0), 1415 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1", 1416 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0), 1417 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0", 1418 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0), 1419 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3", 1420 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0), 1421 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1", 1422 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0), 1423 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0", 1424 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0), 1425 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133", 1426 ENABLE_PCLK_MIF, 11, 0, 0), 1427 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133", 1428 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0), 1429 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133", 1430 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1431 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133", 1432 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1433 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133", 1434 ENABLE_PCLK_MIF, 7, 0, 0), 1435 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133", 1436 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0), 1437 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133", 1438 ENABLE_PCLK_MIF, 5, 0, 0), 1439 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133", 1440 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1441 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133", 1442 ENABLE_PCLK_MIF, 2, 0, 0), 1443 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133", 1444 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1445 1446 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */ 1447 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133", 1448 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0, 1449 CLK_IGNORE_UNUSED, 0), 1450 1451 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */ 1452 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133", 1453 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0, 1454 CLK_IGNORE_UNUSED, 0), 1455 1456 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */ 1457 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133", 1458 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0), 1459 1460 /* ENABLE_PCLK_MIF_SECURE_RTC */ 1461 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133", 1462 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0), 1463 1464 /* ENABLE_SCLK_MIF */ 1465 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1", 1466 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0), 1467 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp", 1468 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF, 1469 14, CLK_IGNORE_UNUSED, 0), 1470 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0", 1471 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0), 1472 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd", 1473 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0), 1474 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp", 1475 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF, 1476 7, CLK_IGNORE_UNUSED, 0), 1477 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp", 1478 "div_sclk_decon_vclk", ENABLE_SCLK_MIF, 1479 6, CLK_IGNORE_UNUSED, 0), 1480 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp", 1481 "div_sclk_decon_eclk", ENABLE_SCLK_MIF, 1482 5, CLK_IGNORE_UNUSED, 0), 1483 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif", 1484 ENABLE_SCLK_MIF, 4, 1485 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1486 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2", 1487 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0), 1488 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2", 1489 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0), 1490 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll", 1491 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0), 1492 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll", 1493 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0), 1494 }; 1495 1496 static const struct samsung_cmu_info mif_cmu_info __initconst = { 1497 .pll_clks = mif_pll_clks, 1498 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1499 .mux_clks = mif_mux_clks, 1500 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), 1501 .div_clks = mif_div_clks, 1502 .nr_div_clks = ARRAY_SIZE(mif_div_clks), 1503 .gate_clks = mif_gate_clks, 1504 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1505 .fixed_factor_clks = mif_fixed_factor_clks, 1506 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks), 1507 .nr_clk_ids = MIF_NR_CLK, 1508 .clk_regs = mif_clk_regs, 1509 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1510 }; 1511 1512 static void __init exynos5433_cmu_mif_init(struct device_node *np) 1513 { 1514 samsung_cmu_register_one(np, &mif_cmu_info); 1515 } 1516 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif", 1517 exynos5433_cmu_mif_init); 1518 1519 /* 1520 * Register offset definitions for CMU_PERIC 1521 */ 1522 #define DIV_PERIC 0x0600 1523 #define DIV_STAT_PERIC 0x0700 1524 #define ENABLE_ACLK_PERIC 0x0800 1525 #define ENABLE_PCLK_PERIC0 0x0900 1526 #define ENABLE_PCLK_PERIC1 0x0904 1527 #define ENABLE_SCLK_PERIC 0x0A00 1528 #define ENABLE_IP_PERIC0 0x0B00 1529 #define ENABLE_IP_PERIC1 0x0B04 1530 #define ENABLE_IP_PERIC2 0x0B08 1531 1532 static const unsigned long peric_clk_regs[] __initconst = { 1533 DIV_PERIC, 1534 ENABLE_ACLK_PERIC, 1535 ENABLE_PCLK_PERIC0, 1536 ENABLE_PCLK_PERIC1, 1537 ENABLE_SCLK_PERIC, 1538 ENABLE_IP_PERIC0, 1539 ENABLE_IP_PERIC1, 1540 ENABLE_IP_PERIC2, 1541 }; 1542 1543 static const struct samsung_div_clock peric_div_clks[] __initconst = { 1544 /* DIV_PERIC */ 1545 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4), 1546 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4), 1547 }; 1548 1549 static const struct samsung_gate_clock peric_gate_clks[] __initconst = { 1550 /* ENABLE_ACLK_PERIC */ 1551 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66", 1552 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0), 1553 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66", 1554 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0), 1555 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66", 1556 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0), 1557 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66", 1558 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0), 1559 1560 /* ENABLE_PCLK_PERIC0 */ 1561 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1562 31, CLK_SET_RATE_PARENT, 0), 1563 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66", 1564 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0), 1565 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66", 1566 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0), 1567 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1568 28, CLK_SET_RATE_PARENT, 0), 1569 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1570 26, CLK_SET_RATE_PARENT, 0), 1571 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1572 25, CLK_SET_RATE_PARENT, 0), 1573 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1574 24, CLK_SET_RATE_PARENT, 0), 1575 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1576 23, CLK_SET_RATE_PARENT, 0), 1577 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1578 22, CLK_SET_RATE_PARENT, 0), 1579 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1580 21, CLK_SET_RATE_PARENT, 0), 1581 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1582 20, CLK_SET_RATE_PARENT, 0), 1583 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66", 1584 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0), 1585 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66", 1586 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0), 1587 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66", 1588 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0), 1589 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66", 1590 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0), 1591 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66", 1592 ENABLE_PCLK_PERIC0, 15, 1593 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1594 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1595 14, CLK_SET_RATE_PARENT, 0), 1596 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1597 13, CLK_SET_RATE_PARENT, 0), 1598 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1599 12, CLK_SET_RATE_PARENT, 0), 1600 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66", 1601 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0), 1602 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66", 1603 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0), 1604 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66", 1605 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0), 1606 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66", 1607 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 1608 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1609 7, CLK_SET_RATE_PARENT, 0), 1610 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1611 6, CLK_SET_RATE_PARENT, 0), 1612 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1613 5, CLK_SET_RATE_PARENT, 0), 1614 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1615 4, CLK_SET_RATE_PARENT, 0), 1616 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1617 3, CLK_SET_RATE_PARENT, 0), 1618 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1619 2, CLK_SET_RATE_PARENT, 0), 1620 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1621 1, CLK_SET_RATE_PARENT, 0), 1622 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0, 1623 0, CLK_SET_RATE_PARENT, 0), 1624 1625 /* ENABLE_PCLK_PERIC1 */ 1626 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1627 9, CLK_SET_RATE_PARENT, 0), 1628 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1, 1629 8, CLK_SET_RATE_PARENT, 0), 1630 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66", 1631 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0), 1632 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66", 1633 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0), 1634 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66", 1635 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0), 1636 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66", 1637 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 1638 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66", 1639 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0), 1640 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66", 1641 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0), 1642 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66", 1643 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0), 1644 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66", 1645 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 1646 1647 /* ENABLE_SCLK_PERIC */ 1648 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in", 1649 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0), 1650 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in", 1651 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0), 1652 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC, 1653 19, CLK_SET_RATE_PARENT, 0), 1654 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC, 1655 18, CLK_SET_RATE_PARENT, 0), 1656 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC, 1657 17, 0, 0), 1658 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC, 1659 16, 0, 0), 1660 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0), 1661 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in", 1662 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0), 1663 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in", 1664 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0), 1665 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in", 1666 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1667 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk", 1668 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10, 1669 CLK_SET_RATE_PARENT, 0), 1670 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric", 1671 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 1672 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric", 1673 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 1674 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric", 1675 ENABLE_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 1676 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC, 1677 5, CLK_SET_RATE_PARENT, 0), 1678 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC, 1679 4, CLK_SET_RATE_PARENT, 0), 1680 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC, 1681 3, CLK_SET_RATE_PARENT, 0), 1682 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric", 1683 ENABLE_SCLK_PERIC, 2, 1684 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1685 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric", 1686 ENABLE_SCLK_PERIC, 1, 1687 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1688 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric", 1689 ENABLE_SCLK_PERIC, 0, 1690 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0), 1691 }; 1692 1693 static const struct samsung_cmu_info peric_cmu_info __initconst = { 1694 .div_clks = peric_div_clks, 1695 .nr_div_clks = ARRAY_SIZE(peric_div_clks), 1696 .gate_clks = peric_gate_clks, 1697 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), 1698 .nr_clk_ids = PERIC_NR_CLK, 1699 .clk_regs = peric_clk_regs, 1700 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), 1701 }; 1702 1703 static void __init exynos5433_cmu_peric_init(struct device_node *np) 1704 { 1705 samsung_cmu_register_one(np, &peric_cmu_info); 1706 } 1707 1708 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric", 1709 exynos5433_cmu_peric_init); 1710 1711 /* 1712 * Register offset definitions for CMU_PERIS 1713 */ 1714 #define ENABLE_ACLK_PERIS 0x0800 1715 #define ENABLE_PCLK_PERIS 0x0900 1716 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904 1717 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908 1718 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c 1719 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910 1720 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914 1721 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918 1722 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c 1723 #define ENABLE_SCLK_PERIS 0x0a00 1724 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04 1725 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08 1726 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c 1727 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10 1728 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14 1729 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18 1730 #define ENABLE_IP_PERIS0 0x0b00 1731 #define ENABLE_IP_PERIS1 0x0b04 1732 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08 1733 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c 1734 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10 1735 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14 1736 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18 1737 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c 1738 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20 1739 1740 static const unsigned long peris_clk_regs[] __initconst = { 1741 ENABLE_ACLK_PERIS, 1742 ENABLE_PCLK_PERIS, 1743 ENABLE_PCLK_PERIS_SECURE_TZPC, 1744 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 1745 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 1746 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 1747 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 1748 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 1749 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 1750 ENABLE_SCLK_PERIS, 1751 ENABLE_SCLK_PERIS_SECURE_SECKEY, 1752 ENABLE_SCLK_PERIS_SECURE_CHIPID, 1753 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 1754 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 1755 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 1756 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 1757 ENABLE_IP_PERIS0, 1758 ENABLE_IP_PERIS1, 1759 ENABLE_IP_PERIS_SECURE_TZPC, 1760 ENABLE_IP_PERIS_SECURE_SECKEY, 1761 ENABLE_IP_PERIS_SECURE_CHIPID, 1762 ENABLE_IP_PERIS_SECURE_TOPRTC, 1763 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE, 1764 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT, 1765 ENABLE_IP_PERIS_SECURE_OTP_CON, 1766 }; 1767 1768 static const struct samsung_gate_clock peris_gate_clks[] __initconst = { 1769 /* ENABLE_ACLK_PERIS */ 1770 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66", 1771 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0), 1772 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66", 1773 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1774 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66", 1775 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1776 1777 /* ENABLE_PCLK_PERIS */ 1778 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66", 1779 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0), 1780 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66", 1781 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0), 1782 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66", 1783 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0), 1784 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66", 1785 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0), 1786 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66", 1787 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0), 1788 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66", 1789 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0), 1790 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66", 1791 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0), 1792 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66", 1793 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0), 1794 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66", 1795 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0), 1796 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66", 1797 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0), 1798 1799 /* ENABLE_PCLK_PERIS_SECURE_TZPC */ 1800 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66", 1801 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0), 1802 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66", 1803 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0), 1804 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66", 1805 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0), 1806 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66", 1807 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0), 1808 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66", 1809 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0), 1810 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66", 1811 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0), 1812 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66", 1813 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0), 1814 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66", 1815 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0), 1816 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66", 1817 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0), 1818 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66", 1819 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0), 1820 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66", 1821 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0), 1822 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66", 1823 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0), 1824 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66", 1825 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0), 1826 1827 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */ 1828 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66", 1829 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1830 1831 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */ 1832 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66", 1833 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0), 1834 1835 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */ 1836 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66", 1837 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1838 1839 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */ 1840 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif", 1841 "aclk_peris_66", 1842 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0), 1843 1844 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */ 1845 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif", 1846 "aclk_peris_66", 1847 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0), 1848 1849 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */ 1850 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif", 1851 "aclk_peris_66", 1852 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0), 1853 1854 /* ENABLE_SCLK_PERIS */ 1855 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common", 1856 ENABLE_SCLK_PERIS, 10, 0, 0), 1857 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common", 1858 ENABLE_SCLK_PERIS, 4, 0, 0), 1859 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common", 1860 ENABLE_SCLK_PERIS, 3, 0, 0), 1861 1862 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */ 1863 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common", 1864 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0), 1865 1866 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */ 1867 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common", 1868 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0), 1869 1870 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */ 1871 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common", 1872 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0), 1873 1874 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */ 1875 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common", 1876 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0), 1877 1878 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */ 1879 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common", 1880 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0), 1881 1882 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */ 1883 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common", 1884 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0), 1885 }; 1886 1887 static const struct samsung_cmu_info peris_cmu_info __initconst = { 1888 .gate_clks = peris_gate_clks, 1889 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks), 1890 .nr_clk_ids = PERIS_NR_CLK, 1891 .clk_regs = peris_clk_regs, 1892 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs), 1893 }; 1894 1895 static void __init exynos5433_cmu_peris_init(struct device_node *np) 1896 { 1897 samsung_cmu_register_one(np, &peris_cmu_info); 1898 } 1899 1900 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris", 1901 exynos5433_cmu_peris_init); 1902 1903 /* 1904 * Register offset definitions for CMU_FSYS 1905 */ 1906 #define MUX_SEL_FSYS0 0x0200 1907 #define MUX_SEL_FSYS1 0x0204 1908 #define MUX_SEL_FSYS2 0x0208 1909 #define MUX_SEL_FSYS3 0x020c 1910 #define MUX_SEL_FSYS4 0x0210 1911 #define MUX_ENABLE_FSYS0 0x0300 1912 #define MUX_ENABLE_FSYS1 0x0304 1913 #define MUX_ENABLE_FSYS2 0x0308 1914 #define MUX_ENABLE_FSYS3 0x030c 1915 #define MUX_ENABLE_FSYS4 0x0310 1916 #define MUX_STAT_FSYS0 0x0400 1917 #define MUX_STAT_FSYS1 0x0404 1918 #define MUX_STAT_FSYS2 0x0408 1919 #define MUX_STAT_FSYS3 0x040c 1920 #define MUX_STAT_FSYS4 0x0410 1921 #define MUX_IGNORE_FSYS2 0x0508 1922 #define MUX_IGNORE_FSYS3 0x050c 1923 #define ENABLE_ACLK_FSYS0 0x0800 1924 #define ENABLE_ACLK_FSYS1 0x0804 1925 #define ENABLE_PCLK_FSYS 0x0900 1926 #define ENABLE_SCLK_FSYS 0x0a00 1927 #define ENABLE_IP_FSYS0 0x0b00 1928 #define ENABLE_IP_FSYS1 0x0b04 1929 1930 /* list of all parent clock list */ 1931 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", }; 1932 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "div_aclk_fsys_200", }; 1933 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",}; 1934 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",}; 1935 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", }; 1936 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", }; 1937 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", }; 1938 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",}; 1939 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", }; 1940 1941 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p) 1942 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", }; 1943 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p) 1944 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", }; 1945 PNAME(mout_phyclk_usbhost20_phy_hsic1_p) 1946 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", }; 1947 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p) 1948 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", }; 1949 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p) 1950 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", }; 1951 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p) 1952 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", }; 1953 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p) 1954 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", }; 1955 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p) 1956 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", }; 1957 PNAME(mout_phyclk_ufs_rx1_symbol_user_p) 1958 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", }; 1959 PNAME(mout_phyclk_ufs_rx0_symbol_user_p) 1960 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", }; 1961 PNAME(mout_phyclk_ufs_tx1_symbol_user_p) 1962 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", }; 1963 PNAME(mout_phyclk_ufs_tx0_symbol_user_p) 1964 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", }; 1965 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p) 1966 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", }; 1967 PNAME(mout_sclk_mphy_p) 1968 = { "mout_sclk_ufs_mphy_user", 1969 "mout_phyclk_lli_mphy_to_ufs_user", }; 1970 1971 static const unsigned long fsys_clk_regs[] __initconst = { 1972 MUX_SEL_FSYS0, 1973 MUX_SEL_FSYS1, 1974 MUX_SEL_FSYS2, 1975 MUX_SEL_FSYS3, 1976 MUX_SEL_FSYS4, 1977 MUX_ENABLE_FSYS0, 1978 MUX_ENABLE_FSYS1, 1979 MUX_ENABLE_FSYS2, 1980 MUX_ENABLE_FSYS3, 1981 MUX_ENABLE_FSYS4, 1982 MUX_IGNORE_FSYS2, 1983 MUX_IGNORE_FSYS3, 1984 ENABLE_ACLK_FSYS0, 1985 ENABLE_ACLK_FSYS1, 1986 ENABLE_PCLK_FSYS, 1987 ENABLE_SCLK_FSYS, 1988 ENABLE_IP_FSYS0, 1989 ENABLE_IP_FSYS1, 1990 }; 1991 1992 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { 1993 /* PHY clocks from USBDRD30_PHY */ 1994 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 1995 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL, 1996 0, 60000000), 1997 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY, 1998 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL, 1999 0, 125000000), 2000 /* PHY clocks from USBHOST30_PHY */ 2001 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY, 2002 "phyclk_usbhost30_uhost30_phyclock_phy", NULL, 2003 0, 60000000), 2004 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY, 2005 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL, 2006 0, 125000000), 2007 /* PHY clocks from USBHOST20_PHY */ 2008 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY, 2009 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000), 2010 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY, 2011 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000), 2012 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY, 2013 "phyclk_usbhost20_phy_clk48mohci_phy", NULL, 2014 0, 48000000), 2015 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY, 2016 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0, 2017 60000000), 2018 /* PHY clocks from UFS_PHY */ 2019 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy", 2020 NULL, 0, 300000000), 2021 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy", 2022 NULL, 0, 300000000), 2023 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy", 2024 NULL, 0, 300000000), 2025 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy", 2026 NULL, 0, 300000000), 2027 /* PHY clocks from LLI_PHY */ 2028 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy", 2029 NULL, 0, 26000000), 2030 }; 2031 2032 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 2033 /* MUX_SEL_FSYS0 */ 2034 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user", 2035 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1), 2036 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user", 2037 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1), 2038 2039 /* MUX_SEL_FSYS1 */ 2040 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user", 2041 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1), 2042 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user", 2043 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1), 2044 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user", 2045 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1), 2046 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user", 2047 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1), 2048 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user", 2049 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1), 2050 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user", 2051 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1), 2052 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user", 2053 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1), 2054 2055 /* MUX_SEL_FSYS2 */ 2056 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER, 2057 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2058 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p, 2059 MUX_SEL_FSYS2, 28, 1), 2060 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER, 2061 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2062 mout_phyclk_usbhost30_uhost30_phyclock_user_p, 2063 MUX_SEL_FSYS2, 24, 1), 2064 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER, 2065 "mout_phyclk_usbhost20_phy_hsic1", 2066 mout_phyclk_usbhost20_phy_hsic1_p, 2067 MUX_SEL_FSYS2, 20, 1), 2068 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER, 2069 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2070 mout_phyclk_usbhost20_phy_clk48mohci_user_p, 2071 MUX_SEL_FSYS2, 16, 1), 2072 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER, 2073 "mout_phyclk_usbhost20_phy_phyclock_user", 2074 mout_phyclk_usbhost20_phy_phyclock_user_p, 2075 MUX_SEL_FSYS2, 12, 1), 2076 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER, 2077 "mout_phyclk_usbhost20_phy_freeclk_user", 2078 mout_phyclk_usbhost20_phy_freeclk_user_p, 2079 MUX_SEL_FSYS2, 8, 1), 2080 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER, 2081 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2082 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p, 2083 MUX_SEL_FSYS2, 4, 1), 2084 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER, 2085 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2086 mout_phyclk_usbdrd30_udrd30_phyclock_user_p, 2087 MUX_SEL_FSYS2, 0, 1), 2088 2089 /* MUX_SEL_FSYS3 */ 2090 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER, 2091 "mout_phyclk_ufs_rx1_symbol_user", 2092 mout_phyclk_ufs_rx1_symbol_user_p, 2093 MUX_SEL_FSYS3, 16, 1), 2094 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER, 2095 "mout_phyclk_ufs_rx0_symbol_user", 2096 mout_phyclk_ufs_rx0_symbol_user_p, 2097 MUX_SEL_FSYS3, 12, 1), 2098 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER, 2099 "mout_phyclk_ufs_tx1_symbol_user", 2100 mout_phyclk_ufs_tx1_symbol_user_p, 2101 MUX_SEL_FSYS3, 8, 1), 2102 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER, 2103 "mout_phyclk_ufs_tx0_symbol_user", 2104 mout_phyclk_ufs_tx0_symbol_user_p, 2105 MUX_SEL_FSYS3, 4, 1), 2106 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER, 2107 "mout_phyclk_lli_mphy_to_ufs_user", 2108 mout_phyclk_lli_mphy_to_ufs_user_p, 2109 MUX_SEL_FSYS3, 0, 1), 2110 2111 /* MUX_SEL_FSYS4 */ 2112 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p, 2113 MUX_SEL_FSYS4, 0, 1), 2114 }; 2115 2116 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 2117 /* ENABLE_ACLK_FSYS0 */ 2118 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user", 2119 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0), 2120 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user", 2121 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0), 2122 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user", 2123 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 2124 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user", 2125 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0), 2126 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user", 2127 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0), 2128 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user", 2129 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0), 2130 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user", 2131 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0), 2132 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user", 2133 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0), 2134 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user", 2135 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0), 2136 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user", 2137 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0), 2138 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user", 2139 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0), 2140 2141 /* ENABLE_ACLK_FSYS1 */ 2142 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user", 2143 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0), 2144 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1", 2145 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2146 26, CLK_IGNORE_UNUSED, 0), 2147 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2148 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0), 2149 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user", 2150 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0), 2151 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1", 2152 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2153 22, CLK_IGNORE_UNUSED, 0), 2154 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2155 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0), 2156 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user", 2157 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0), 2158 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30", 2159 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2160 13, 0, 0), 2161 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30", 2162 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2163 12, 0, 0), 2164 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0", 2165 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2166 11, CLK_IGNORE_UNUSED, 0), 2167 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs", 2168 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2169 10, CLK_IGNORE_UNUSED, 0), 2170 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx", 2171 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2172 9, CLK_IGNORE_UNUSED, 0), 2173 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp", 2174 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2175 8, CLK_IGNORE_UNUSED, 0), 2176 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs", 2177 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2178 7, CLK_IGNORE_UNUSED, 0), 2179 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0", 2180 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1, 2181 6, CLK_IGNORE_UNUSED, 0), 2182 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user", 2183 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0), 2184 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user", 2185 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0), 2186 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user", 2187 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0), 2188 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user", 2189 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0), 2190 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user", 2191 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0), 2192 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user", 2193 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0), 2194 2195 /* ENABLE_PCLK_FSYS */ 2196 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user", 2197 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0), 2198 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user", 2199 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0), 2200 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user", 2201 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0), 2202 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user", 2203 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0), 2204 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user", 2205 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0), 2206 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user", 2207 ENABLE_PCLK_FSYS, 5, 0, 0), 2208 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30", 2209 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0), 2210 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30", 2211 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0), 2212 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user", 2213 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0), 2214 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user", 2215 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0), 2216 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys", 2217 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 2218 0, CLK_IGNORE_UNUSED, 0), 2219 2220 /* ENABLE_SCLK_FSYS */ 2221 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user", 2222 ENABLE_SCLK_FSYS, 21, 0, 0), 2223 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK, 2224 "phyclk_usbhost30_uhost30_pipe_pclk", 2225 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user", 2226 ENABLE_SCLK_FSYS, 18, 0, 0), 2227 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK, 2228 "phyclk_usbhost30_uhost30_phyclock", 2229 "mout_phyclk_usbhost30_uhost30_phyclock_user", 2230 ENABLE_SCLK_FSYS, 17, 0, 0), 2231 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol", 2232 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS, 2233 16, 0, 0), 2234 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol", 2235 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS, 2236 15, 0, 0), 2237 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol", 2238 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS, 2239 14, 0, 0), 2240 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol", 2241 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS, 2242 13, 0, 0), 2243 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1", 2244 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS, 2245 12, 0, 0), 2246 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI, 2247 "phyclk_usbhost20_phy_clk48mohci", 2248 "mout_phyclk_usbhost20_phy_clk48mohci_user", 2249 ENABLE_SCLK_FSYS, 11, 0, 0), 2250 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK, 2251 "phyclk_usbhost20_phy_phyclock", 2252 "mout_phyclk_usbhost20_phy_phyclock_user", 2253 ENABLE_SCLK_FSYS, 10, 0, 0), 2254 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK, 2255 "phyclk_usbhost20_phy_freeclk", 2256 "mout_phyclk_usbhost20_phy_freeclk_user", 2257 ENABLE_SCLK_FSYS, 9, 0, 0), 2258 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 2259 "phyclk_usbdrd30_udrd30_pipe_pclk", 2260 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user", 2261 ENABLE_SCLK_FSYS, 8, 0, 0), 2262 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 2263 "phyclk_usbdrd30_udrd30_phyclock", 2264 "mout_phyclk_usbdrd30_udrd30_phyclock_user", 2265 ENABLE_SCLK_FSYS, 7, 0, 0), 2266 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy", 2267 ENABLE_SCLK_FSYS, 6, 0, 0), 2268 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user", 2269 ENABLE_SCLK_FSYS, 5, 0, 0), 2270 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user", 2271 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 2272 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user", 2273 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0), 2274 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user", 2275 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 2276 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user", 2277 ENABLE_SCLK_FSYS, 1, 0, 0), 2278 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user", 2279 ENABLE_SCLK_FSYS, 0, 0, 0), 2280 2281 /* ENABLE_IP_FSYS0 */ 2282 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0), 2283 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0), 2284 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0), 2285 }; 2286 2287 static const struct samsung_cmu_info fsys_cmu_info __initconst = { 2288 .mux_clks = fsys_mux_clks, 2289 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 2290 .gate_clks = fsys_gate_clks, 2291 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 2292 .fixed_clks = fsys_fixed_clks, 2293 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks), 2294 .nr_clk_ids = FSYS_NR_CLK, 2295 .clk_regs = fsys_clk_regs, 2296 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 2297 }; 2298 2299 static void __init exynos5433_cmu_fsys_init(struct device_node *np) 2300 { 2301 samsung_cmu_register_one(np, &fsys_cmu_info); 2302 } 2303 2304 CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys", 2305 exynos5433_cmu_fsys_init); 2306 2307 /* 2308 * Register offset definitions for CMU_G2D 2309 */ 2310 #define MUX_SEL_G2D0 0x0200 2311 #define MUX_SEL_ENABLE_G2D0 0x0300 2312 #define MUX_SEL_STAT_G2D0 0x0400 2313 #define DIV_G2D 0x0600 2314 #define DIV_STAT_G2D 0x0700 2315 #define DIV_ENABLE_ACLK_G2D 0x0800 2316 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804 2317 #define DIV_ENABLE_PCLK_G2D 0x0900 2318 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904 2319 #define DIV_ENABLE_IP_G2D0 0x0b00 2320 #define DIV_ENABLE_IP_G2D1 0x0b04 2321 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08 2322 2323 static const unsigned long g2d_clk_regs[] __initconst = { 2324 MUX_SEL_G2D0, 2325 MUX_SEL_ENABLE_G2D0, 2326 DIV_G2D, 2327 DIV_ENABLE_ACLK_G2D, 2328 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 2329 DIV_ENABLE_PCLK_G2D, 2330 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 2331 DIV_ENABLE_IP_G2D0, 2332 DIV_ENABLE_IP_G2D1, 2333 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, 2334 }; 2335 2336 /* list of all parent clock list */ 2337 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 2338 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 2339 2340 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { 2341 /* MUX_SEL_G2D0 */ 2342 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user", 2343 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1), 2344 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user", 2345 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1), 2346 }; 2347 2348 static const struct samsung_div_clock g2d_div_clks[] __initconst = { 2349 /* DIV_G2D */ 2350 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user", 2351 DIV_G2D, 0, 2), 2352 }; 2353 2354 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { 2355 /* DIV_ENABLE_ACLK_G2D */ 2356 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user", 2357 DIV_ENABLE_ACLK_G2D, 12, 0, 0), 2358 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user", 2359 DIV_ENABLE_ACLK_G2D, 11, 0, 0), 2360 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user", 2361 DIV_ENABLE_ACLK_G2D, 10, 0, 0), 2362 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user", 2363 DIV_ENABLE_ACLK_G2D, 9, 0, 0), 2364 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user", 2365 DIV_ENABLE_ACLK_G2D, 8, 0, 0), 2366 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx", 2367 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D, 2368 7, 0, 0), 2369 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d", 2370 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0), 2371 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d", 2372 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0), 2373 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user", 2374 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0), 2375 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d", 2376 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0), 2377 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user", 2378 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2379 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user", 2380 DIV_ENABLE_ACLK_G2D, 1, 0, 0), 2381 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user", 2382 DIV_ENABLE_ACLK_G2D, 0, 0, 0), 2383 2384 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */ 2385 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user", 2386 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2387 2388 /* DIV_ENABLE_PCLK_G2D */ 2389 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d", 2390 DIV_ENABLE_PCLK_G2D, 7, 0, 0), 2391 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d", 2392 DIV_ENABLE_PCLK_G2D, 6, 0, 0), 2393 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d", 2394 DIV_ENABLE_PCLK_G2D, 5, 0, 0), 2395 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d", 2396 DIV_ENABLE_PCLK_G2D, 4, 0, 0), 2397 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d", 2398 DIV_ENABLE_PCLK_G2D, 3, 0, 0), 2399 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d", 2400 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0), 2401 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d", 2402 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0), 2403 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D, 2404 0, 0, 0), 2405 2406 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */ 2407 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d", 2408 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0), 2409 }; 2410 2411 static const struct samsung_cmu_info g2d_cmu_info __initconst = { 2412 .mux_clks = g2d_mux_clks, 2413 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 2414 .div_clks = g2d_div_clks, 2415 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 2416 .gate_clks = g2d_gate_clks, 2417 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 2418 .nr_clk_ids = G2D_NR_CLK, 2419 .clk_regs = g2d_clk_regs, 2420 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 2421 }; 2422 2423 static void __init exynos5433_cmu_g2d_init(struct device_node *np) 2424 { 2425 samsung_cmu_register_one(np, &g2d_cmu_info); 2426 } 2427 2428 CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d", 2429 exynos5433_cmu_g2d_init); 2430 2431 /* 2432 * Register offset definitions for CMU_DISP 2433 */ 2434 #define DISP_PLL_LOCK 0x0000 2435 #define DISP_PLL_CON0 0x0100 2436 #define DISP_PLL_CON1 0x0104 2437 #define DISP_PLL_FREQ_DET 0x0108 2438 #define MUX_SEL_DISP0 0x0200 2439 #define MUX_SEL_DISP1 0x0204 2440 #define MUX_SEL_DISP2 0x0208 2441 #define MUX_SEL_DISP3 0x020c 2442 #define MUX_SEL_DISP4 0x0210 2443 #define MUX_ENABLE_DISP0 0x0300 2444 #define MUX_ENABLE_DISP1 0x0304 2445 #define MUX_ENABLE_DISP2 0x0308 2446 #define MUX_ENABLE_DISP3 0x030c 2447 #define MUX_ENABLE_DISP4 0x0310 2448 #define MUX_STAT_DISP0 0x0400 2449 #define MUX_STAT_DISP1 0x0404 2450 #define MUX_STAT_DISP2 0x0408 2451 #define MUX_STAT_DISP3 0x040c 2452 #define MUX_STAT_DISP4 0x0410 2453 #define MUX_IGNORE_DISP2 0x0508 2454 #define DIV_DISP 0x0600 2455 #define DIV_DISP_PLL_FREQ_DET 0x0604 2456 #define DIV_STAT_DISP 0x0700 2457 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704 2458 #define ENABLE_ACLK_DISP0 0x0800 2459 #define ENABLE_ACLK_DISP1 0x0804 2460 #define ENABLE_PCLK_DISP 0x0900 2461 #define ENABLE_SCLK_DISP 0x0a00 2462 #define ENABLE_IP_DISP0 0x0b00 2463 #define ENABLE_IP_DISP1 0x0b04 2464 #define CLKOUT_CMU_DISP 0x0c00 2465 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04 2466 2467 static const unsigned long disp_clk_regs[] __initconst = { 2468 DISP_PLL_LOCK, 2469 DISP_PLL_CON0, 2470 DISP_PLL_CON1, 2471 DISP_PLL_FREQ_DET, 2472 MUX_SEL_DISP0, 2473 MUX_SEL_DISP1, 2474 MUX_SEL_DISP2, 2475 MUX_SEL_DISP3, 2476 MUX_SEL_DISP4, 2477 MUX_ENABLE_DISP0, 2478 MUX_ENABLE_DISP1, 2479 MUX_ENABLE_DISP2, 2480 MUX_ENABLE_DISP3, 2481 MUX_ENABLE_DISP4, 2482 MUX_IGNORE_DISP2, 2483 DIV_DISP, 2484 DIV_DISP_PLL_FREQ_DET, 2485 ENABLE_ACLK_DISP0, 2486 ENABLE_ACLK_DISP1, 2487 ENABLE_PCLK_DISP, 2488 ENABLE_SCLK_DISP, 2489 ENABLE_IP_DISP0, 2490 ENABLE_IP_DISP1, 2491 CLKOUT_CMU_DISP, 2492 CLKOUT_CMU_DISP_DIV_STAT, 2493 }; 2494 2495 /* list of all parent clock list */ 2496 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; 2497 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; 2498 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", }; 2499 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", }; 2500 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk", 2501 "sclk_decon_tv_eclk_disp", }; 2502 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk", 2503 "sclk_decon_vclk_disp", }; 2504 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk", 2505 "sclk_decon_eclk_disp", }; 2506 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk", 2507 "sclk_decon_tv_vclk_disp", }; 2508 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", }; 2509 2510 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk", 2511 "phyclk_mipidphy1_bitclkdiv8_phy", }; 2512 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk", 2513 "phyclk_mipidphy1_rxclkesc0_phy", }; 2514 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk", 2515 "phyclk_mipidphy0_bitclkdiv8_phy", }; 2516 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk", 2517 "phyclk_mipidphy0_rxclkesc0_phy", }; 2518 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk", 2519 "phyclk_hdmiphy_tmds_clko_phy", }; 2520 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk", 2521 "phyclk_hdmiphy_pixel_clko_phy", }; 2522 2523 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll", 2524 "mout_sclk_dsim0_user", }; 2525 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll", 2526 "mout_sclk_decon_tv_eclk_user", }; 2527 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll", 2528 "mout_sclk_decon_vclk_user", }; 2529 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll", 2530 "mout_sclk_decon_eclk_user", }; 2531 2532 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp", 2533 "mout_sclk_dsim1_user", }; 2534 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = { 2535 "mout_phyclk_hdmiphy_pixel_clko_user", 2536 "mout_sclk_decon_tv_vclk_b_disp", }; 2537 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp", 2538 "mout_sclk_decon_tv_vclk_user", }; 2539 2540 static const struct samsung_pll_clock disp_pll_clks[] __initconst = { 2541 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk", 2542 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5443_pll_rates), 2543 }; 2544 2545 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = { 2546 /* 2547 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}. 2548 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk} 2549 * and sclk_decon_{vclk|tv_vclk}. 2550 */ 2551 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk", 2552 1, 2, 0), 2553 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk", 2554 1, 2, 0), 2555 }; 2556 2557 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = { 2558 /* PHY clocks from MIPI_DPHY1 */ 2559 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), 2560 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), 2561 /* PHY clocks from MIPI_DPHY0 */ 2562 FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), 2563 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), 2564 /* PHY clocks from HDMI_PHY */ 2565 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", 2566 NULL, 0, 300000000), 2567 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", 2568 NULL, 0, 166000000), 2569 }; 2570 2571 static const struct samsung_mux_clock disp_mux_clks[] __initconst = { 2572 /* MUX_SEL_DISP0 */ 2573 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0, 2574 0, 1), 2575 2576 /* MUX_SEL_DISP1 */ 2577 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user", 2578 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1), 2579 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user", 2580 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1), 2581 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p, 2582 MUX_SEL_DISP1, 20, 1), 2583 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user", 2584 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1), 2585 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user", 2586 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1), 2587 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user", 2588 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1), 2589 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user", 2590 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1), 2591 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 2592 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1), 2593 2594 /* MUX_SEL_DISP2 */ 2595 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER, 2596 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2597 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2, 2598 20, 1), 2599 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER, 2600 "mout_phyclk_mipidphy1_rxclkesc0_user", 2601 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2, 2602 16, 1), 2603 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER, 2604 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2605 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2, 2606 12, 1), 2607 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER, 2608 "mout_phyclk_mipidphy0_rxclkesc0_user", 2609 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2, 2610 8, 1), 2611 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER, 2612 "mout_phyclk_hdmiphy_tmds_clko_user", 2613 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2, 2614 4, 1), 2615 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER, 2616 "mout_phyclk_hdmiphy_pixel_clko_user", 2617 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2, 2618 0, 1), 2619 2620 /* MUX_SEL_DISP3 */ 2621 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p, 2622 MUX_SEL_DISP3, 12, 1), 2623 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk", 2624 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1), 2625 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk", 2626 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1), 2627 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk", 2628 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1), 2629 2630 /* MUX_SEL_DISP4 */ 2631 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp", 2632 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1), 2633 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp", 2634 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1), 2635 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP, 2636 "mout_sclk_decon_tv_vclk_c_disp", 2637 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1), 2638 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP, 2639 "mout_sclk_decon_tv_vclk_b_disp", 2640 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1), 2641 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP, 2642 "mout_sclk_decon_tv_vclk_a_disp", 2643 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1), 2644 }; 2645 2646 static const struct samsung_div_clock disp_div_clks[] __initconst = { 2647 /* DIV_DISP */ 2648 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp", 2649 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3), 2650 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp", 2651 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3), 2652 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0", 2653 DIV_DISP, 16, 3), 2654 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp", 2655 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3), 2656 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp", 2657 "mout_sclk_decon_vclk", DIV_DISP, 8, 3), 2658 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp", 2659 "mout_sclk_decon_eclk", DIV_DISP, 4, 3), 2660 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user", 2661 DIV_DISP, 0, 2), 2662 }; 2663 2664 static const struct samsung_gate_clock disp_gate_clks[] __initconst = { 2665 /* ENABLE_ACLK_DISP0 */ 2666 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user", 2667 ENABLE_ACLK_DISP0, 2, 0, 0), 2668 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user", 2669 ENABLE_ACLK_DISP0, 0, 0, 0), 2670 2671 /* ENABLE_ACLK_DISP1 */ 2672 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user", 2673 ENABLE_ACLK_DISP1, 25, 0, 0), 2674 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user", 2675 ENABLE_ACLK_DISP1, 24, 0, 0), 2676 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x", 2677 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0), 2678 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x", 2679 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0), 2680 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3", 2681 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0), 2682 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2", 2683 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0), 2684 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1", 2685 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0), 2686 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0", 2687 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0), 2688 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4", 2689 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0), 2690 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3", 2691 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0), 2692 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2", 2693 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0), 2694 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1", 2695 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0), 2696 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0", 2697 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0), 2698 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p", 2699 "div_pclk_disp", ENABLE_ACLK_DISP1, 2700 12, CLK_IGNORE_UNUSED, 0), 2701 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p", 2702 "div_pclk_disp", ENABLE_ACLK_DISP1, 2703 11, CLK_IGNORE_UNUSED, 0), 2704 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p", 2705 "div_pclk_disp", ENABLE_ACLK_DISP1, 2706 10, CLK_IGNORE_UNUSED, 0), 2707 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp", 2708 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0), 2709 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user", 2710 ENABLE_ACLK_DISP1, 7, 0, 0), 2711 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user", 2712 ENABLE_ACLK_DISP1, 6, 0, 0), 2713 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x", 2714 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0), 2715 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x", 2716 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0), 2717 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user", 2718 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0), 2719 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp", 2720 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0), 2721 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333", 2722 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1, 2723 CLK_IGNORE_UNUSED, 0), 2724 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333", 2725 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 2726 0, CLK_IGNORE_UNUSED, 0), 2727 2728 /* ENABLE_PCLK_DISP */ 2729 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp", 2730 ENABLE_PCLK_DISP, 23, 0, 0), 2731 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp", 2732 ENABLE_PCLK_DISP, 22, 0, 0), 2733 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp", 2734 ENABLE_PCLK_DISP, 21, 0, 0), 2735 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp", 2736 ENABLE_PCLK_DISP, 20, 0, 0), 2737 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp", 2738 ENABLE_PCLK_DISP, 19, 0, 0), 2739 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp", 2740 ENABLE_PCLK_DISP, 18, 0, 0), 2741 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp", 2742 ENABLE_PCLK_DISP, 17, 0, 0), 2743 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp", 2744 ENABLE_PCLK_DISP, 16, 0, 0), 2745 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp", 2746 ENABLE_PCLK_DISP, 15, 0, 0), 2747 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp", 2748 ENABLE_PCLK_DISP, 14, 0, 0), 2749 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp", 2750 ENABLE_PCLK_DISP, 13, 0, 0), 2751 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp", 2752 ENABLE_PCLK_DISP, 12, 0, 0), 2753 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp", 2754 ENABLE_PCLK_DISP, 11, 0, 0), 2755 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp", 2756 ENABLE_PCLK_DISP, 10, 0, 0), 2757 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp", 2758 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0), 2759 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp", 2760 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0), 2761 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp", 2762 ENABLE_PCLK_DISP, 7, 0, 0), 2763 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp", 2764 ENABLE_PCLK_DISP, 6, 0, 0), 2765 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp", 2766 ENABLE_PCLK_DISP, 5, 0, 0), 2767 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp", 2768 ENABLE_PCLK_DISP, 3, 0, 0), 2769 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp", 2770 ENABLE_PCLK_DISP, 2, 0, 0), 2771 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp", 2772 ENABLE_PCLK_DISP, 1, 0, 0), 2773 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp", 2774 ENABLE_PCLK_DISP, 0, 0, 0), 2775 2776 /* ENABLE_SCLK_DISP */ 2777 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8", 2778 "mout_phyclk_mipidphy1_bitclkdiv8_user", 2779 ENABLE_SCLK_DISP, 26, 0, 0), 2780 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0", 2781 "mout_phyclk_mipidphy1_rxclkesc0_user", 2782 ENABLE_SCLK_DISP, 25, 0, 0), 2783 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1", 2784 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0), 2785 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1", 2786 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0), 2787 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp", 2788 ENABLE_SCLK_DISP, 22, 0, 0), 2789 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk", 2790 "div_sclk_decon_tv_vclk_disp", 2791 ENABLE_SCLK_DISP, 21, 0, 0), 2792 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8", 2793 "mout_phyclk_mipidphy0_bitclkdiv8_user", 2794 ENABLE_SCLK_DISP, 15, 0, 0), 2795 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0", 2796 "mout_phyclk_mipidphy0_rxclkesc0_user", 2797 ENABLE_SCLK_DISP, 14, 0, 0), 2798 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko", 2799 "mout_phyclk_hdmiphy_tmds_clko_user", 2800 ENABLE_SCLK_DISP, 13, 0, 0), 2801 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel", 2802 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0), 2803 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies", 2804 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0), 2805 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0", 2806 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0), 2807 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0", 2808 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0), 2809 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user", 2810 ENABLE_SCLK_DISP, 7, 0, 0), 2811 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp", 2812 ENABLE_SCLK_DISP, 6, 0, 0), 2813 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp", 2814 ENABLE_SCLK_DISP, 5, 0, 0), 2815 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk", 2816 "div_sclk_decon_tv_eclk_disp", 2817 ENABLE_SCLK_DISP, 4, 0, 0), 2818 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk", 2819 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0), 2820 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk", 2821 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0), 2822 }; 2823 2824 static const struct samsung_cmu_info disp_cmu_info __initconst = { 2825 .pll_clks = disp_pll_clks, 2826 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks), 2827 .mux_clks = disp_mux_clks, 2828 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), 2829 .div_clks = disp_div_clks, 2830 .nr_div_clks = ARRAY_SIZE(disp_div_clks), 2831 .gate_clks = disp_gate_clks, 2832 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), 2833 .fixed_clks = disp_fixed_clks, 2834 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks), 2835 .fixed_factor_clks = disp_fixed_factor_clks, 2836 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks), 2837 .nr_clk_ids = DISP_NR_CLK, 2838 .clk_regs = disp_clk_regs, 2839 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 2840 }; 2841 2842 static void __init exynos5433_cmu_disp_init(struct device_node *np) 2843 { 2844 samsung_cmu_register_one(np, &disp_cmu_info); 2845 } 2846 2847 CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp", 2848 exynos5433_cmu_disp_init); 2849 2850 /* 2851 * Register offset definitions for CMU_AUD 2852 */ 2853 #define MUX_SEL_AUD0 0x0200 2854 #define MUX_SEL_AUD1 0x0204 2855 #define MUX_ENABLE_AUD0 0x0300 2856 #define MUX_ENABLE_AUD1 0x0304 2857 #define MUX_STAT_AUD0 0x0400 2858 #define DIV_AUD0 0x0600 2859 #define DIV_AUD1 0x0604 2860 #define DIV_STAT_AUD0 0x0700 2861 #define DIV_STAT_AUD1 0x0704 2862 #define ENABLE_ACLK_AUD 0x0800 2863 #define ENABLE_PCLK_AUD 0x0900 2864 #define ENABLE_SCLK_AUD0 0x0a00 2865 #define ENABLE_SCLK_AUD1 0x0a04 2866 #define ENABLE_IP_AUD0 0x0b00 2867 #define ENABLE_IP_AUD1 0x0b04 2868 2869 static const unsigned long aud_clk_regs[] __initconst = { 2870 MUX_SEL_AUD0, 2871 MUX_SEL_AUD1, 2872 MUX_ENABLE_AUD0, 2873 MUX_ENABLE_AUD1, 2874 DIV_AUD0, 2875 DIV_AUD1, 2876 ENABLE_ACLK_AUD, 2877 ENABLE_PCLK_AUD, 2878 ENABLE_SCLK_AUD0, 2879 ENABLE_SCLK_AUD1, 2880 ENABLE_IP_AUD0, 2881 ENABLE_IP_AUD1, 2882 }; 2883 2884 /* list of all parent clock list */ 2885 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; 2886 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2887 2888 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = { 2889 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000), 2890 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000), 2891 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000), 2892 }; 2893 2894 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 2895 /* MUX_SEL_AUD0 */ 2896 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user", 2897 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1), 2898 2899 /* MUX_SEL_AUD1 */ 2900 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, 2901 MUX_SEL_AUD1, 8, 1), 2902 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p, 2903 MUX_SEL_AUD1, 0, 1), 2904 }; 2905 2906 static const struct samsung_div_clock aud_div_clks[] __initconst = { 2907 /* DIV_AUD0 */ 2908 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0, 2909 12, 4), 2910 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0, 2911 8, 4), 2912 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0, 2913 4, 4), 2914 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 2915 0, 4), 2916 2917 /* DIV_AUD1 */ 2918 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus", 2919 "mout_aud_pll_user", DIV_AUD1, 16, 5), 2920 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user", 2921 DIV_AUD1, 12, 4), 2922 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm", 2923 DIV_AUD1, 4, 8), 2924 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s", 2925 DIV_AUD1, 0, 4), 2926 }; 2927 2928 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 2929 /* ENABLE_ACLK_AUD */ 2930 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud", 2931 ENABLE_ACLK_AUD, 12, 0, 0), 2932 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud", 2933 ENABLE_ACLK_AUD, 7, 0, 0), 2934 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud", 2935 ENABLE_ACLK_AUD, 0, 4, 0), 2936 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud", 2937 ENABLE_ACLK_AUD, 0, 3, 0), 2938 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud", 2939 ENABLE_ACLK_AUD, 0, 2, 0), 2940 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD, 2941 0, 1, 0), 2942 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD, 2943 0, CLK_IGNORE_UNUSED, 0), 2944 2945 /* ENABLE_PCLK_AUD */ 2946 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD, 2947 13, 0, 0), 2948 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD, 2949 12, 0, 0), 2950 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD, 2951 11, 0, 0), 2952 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud", 2953 ENABLE_PCLK_AUD, 10, 0, 0), 2954 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud", 2955 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0), 2956 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud", 2957 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0), 2958 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud", 2959 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0), 2960 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud", 2961 ENABLE_PCLK_AUD, 6, 0, 0), 2962 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud", 2963 ENABLE_PCLK_AUD, 5, 0, 0), 2964 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud", 2965 ENABLE_PCLK_AUD, 4, 0, 0), 2966 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud", 2967 ENABLE_PCLK_AUD, 3, 0, 0), 2968 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD, 2969 2, 0, 0), 2970 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud", 2971 ENABLE_PCLK_AUD, 0, 0, 0), 2972 2973 /* ENABLE_SCLK_AUD0 */ 2974 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0, 2975 2, CLK_IGNORE_UNUSED, 0), 2976 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud", 2977 ENABLE_SCLK_AUD0, 1, 0, 0), 2978 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0, 2979 0, 0, 0), 2980 2981 /* ENABLE_SCLK_AUD1 */ 2982 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk", 2983 ENABLE_SCLK_AUD1, 6, 0, 0), 2984 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk", 2985 ENABLE_SCLK_AUD1, 5, 0, 0), 2986 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus", 2987 ENABLE_SCLK_AUD1, 4, 0, 0), 2988 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart", 2989 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0), 2990 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm", 2991 ENABLE_SCLK_AUD1, 2, 0, 0), 2992 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk", 2993 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0), 2994 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s", 2995 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0), 2996 }; 2997 2998 static const struct samsung_cmu_info aud_cmu_info __initconst = { 2999 .mux_clks = aud_mux_clks, 3000 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 3001 .div_clks = aud_div_clks, 3002 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 3003 .gate_clks = aud_gate_clks, 3004 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 3005 .fixed_clks = aud_fixed_clks, 3006 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks), 3007 .nr_clk_ids = AUD_NR_CLK, 3008 .clk_regs = aud_clk_regs, 3009 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 3010 }; 3011 3012 static void __init exynos5433_cmu_aud_init(struct device_node *np) 3013 { 3014 samsung_cmu_register_one(np, &aud_cmu_info); 3015 } 3016 CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud", 3017 exynos5433_cmu_aud_init); 3018 3019 3020 /* 3021 * Register offset definitions for CMU_BUS{0|1|2} 3022 */ 3023 #define DIV_BUS 0x0600 3024 #define DIV_STAT_BUS 0x0700 3025 #define ENABLE_ACLK_BUS 0x0800 3026 #define ENABLE_PCLK_BUS 0x0900 3027 #define ENABLE_IP_BUS0 0x0b00 3028 #define ENABLE_IP_BUS1 0x0b04 3029 3030 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */ 3031 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */ 3032 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */ 3033 3034 /* list of all parent clock list */ 3035 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", }; 3036 3037 #define CMU_BUS_COMMON_CLK_REGS \ 3038 DIV_BUS, \ 3039 ENABLE_ACLK_BUS, \ 3040 ENABLE_PCLK_BUS, \ 3041 ENABLE_IP_BUS0, \ 3042 ENABLE_IP_BUS1 3043 3044 static const unsigned long bus01_clk_regs[] __initconst = { 3045 CMU_BUS_COMMON_CLK_REGS, 3046 }; 3047 3048 static const unsigned long bus2_clk_regs[] __initconst = { 3049 MUX_SEL_BUS2, 3050 MUX_ENABLE_BUS2, 3051 CMU_BUS_COMMON_CLK_REGS, 3052 }; 3053 3054 static const struct samsung_div_clock bus0_div_clks[] __initconst = { 3055 /* DIV_BUS0 */ 3056 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400", 3057 DIV_BUS, 0, 3), 3058 }; 3059 3060 /* CMU_BUS0 clocks */ 3061 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = { 3062 /* ENABLE_ACLK_BUS0 */ 3063 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133", 3064 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3065 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133", 3066 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3067 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400", 3068 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3069 3070 /* ENABLE_PCLK_BUS0 */ 3071 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133", 3072 ENABLE_PCLK_BUS, 2, 0, 0), 3073 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133", 3074 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3075 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133", 3076 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3077 }; 3078 3079 /* CMU_BUS1 clocks */ 3080 static const struct samsung_div_clock bus1_div_clks[] __initconst = { 3081 /* DIV_BUS1 */ 3082 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400", 3083 DIV_BUS, 0, 3), 3084 }; 3085 3086 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = { 3087 /* ENABLE_ACLK_BUS1 */ 3088 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133", 3089 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0), 3090 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133", 3091 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3092 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400", 3093 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3094 3095 /* ENABLE_PCLK_BUS1 */ 3096 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133", 3097 ENABLE_PCLK_BUS, 2, 0, 0), 3098 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133", 3099 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3100 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133", 3101 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3102 }; 3103 3104 /* CMU_BUS2 clocks */ 3105 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = { 3106 /* MUX_SEL_BUS2 */ 3107 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user", 3108 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1), 3109 }; 3110 3111 static const struct samsung_div_clock bus2_div_clks[] __initconst = { 3112 /* DIV_BUS2 */ 3113 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133", 3114 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3), 3115 }; 3116 3117 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = { 3118 /* ENABLE_ACLK_BUS2 */ 3119 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133", 3120 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0), 3121 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133", 3122 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0), 3123 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400", 3124 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3125 1, CLK_IGNORE_UNUSED, 0), 3126 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400", 3127 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS, 3128 0, CLK_IGNORE_UNUSED, 0), 3129 3130 /* ENABLE_PCLK_BUS2 */ 3131 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133", 3132 ENABLE_PCLK_BUS, 2, 0, 0), 3133 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133", 3134 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0), 3135 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133", 3136 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0), 3137 }; 3138 3139 #define CMU_BUS_INFO_CLKS(id) \ 3140 .div_clks = bus##id##_div_clks, \ 3141 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \ 3142 .gate_clks = bus##id##_gate_clks, \ 3143 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \ 3144 .nr_clk_ids = BUSx_NR_CLK 3145 3146 static const struct samsung_cmu_info bus0_cmu_info __initconst = { 3147 CMU_BUS_INFO_CLKS(0), 3148 .clk_regs = bus01_clk_regs, 3149 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3150 }; 3151 3152 static const struct samsung_cmu_info bus1_cmu_info __initconst = { 3153 CMU_BUS_INFO_CLKS(1), 3154 .clk_regs = bus01_clk_regs, 3155 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs), 3156 }; 3157 3158 static const struct samsung_cmu_info bus2_cmu_info __initconst = { 3159 CMU_BUS_INFO_CLKS(2), 3160 .mux_clks = bus2_mux_clks, 3161 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks), 3162 .clk_regs = bus2_clk_regs, 3163 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs), 3164 }; 3165 3166 #define exynos5433_cmu_bus_init(id) \ 3167 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\ 3168 { \ 3169 samsung_cmu_register_one(np, &bus##id##_cmu_info); \ 3170 } \ 3171 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \ 3172 "samsung,exynos5433-cmu-bus"#id, \ 3173 exynos5433_cmu_bus##id##_init) 3174 3175 exynos5433_cmu_bus_init(0); 3176 exynos5433_cmu_bus_init(1); 3177 exynos5433_cmu_bus_init(2); 3178 3179 /* 3180 * Register offset definitions for CMU_G3D 3181 */ 3182 #define G3D_PLL_LOCK 0x0000 3183 #define G3D_PLL_CON0 0x0100 3184 #define G3D_PLL_CON1 0x0104 3185 #define G3D_PLL_FREQ_DET 0x010c 3186 #define MUX_SEL_G3D 0x0200 3187 #define MUX_ENABLE_G3D 0x0300 3188 #define MUX_STAT_G3D 0x0400 3189 #define DIV_G3D 0x0600 3190 #define DIV_G3D_PLL_FREQ_DET 0x0604 3191 #define DIV_STAT_G3D 0x0700 3192 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704 3193 #define ENABLE_ACLK_G3D 0x0800 3194 #define ENABLE_PCLK_G3D 0x0900 3195 #define ENABLE_SCLK_G3D 0x0a00 3196 #define ENABLE_IP_G3D0 0x0b00 3197 #define ENABLE_IP_G3D1 0x0b04 3198 #define CLKOUT_CMU_G3D 0x0c00 3199 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04 3200 #define CLK_STOPCTRL 0x1000 3201 3202 static const unsigned long g3d_clk_regs[] __initconst = { 3203 G3D_PLL_LOCK, 3204 G3D_PLL_CON0, 3205 G3D_PLL_CON1, 3206 G3D_PLL_FREQ_DET, 3207 MUX_SEL_G3D, 3208 MUX_ENABLE_G3D, 3209 DIV_G3D, 3210 DIV_G3D_PLL_FREQ_DET, 3211 ENABLE_ACLK_G3D, 3212 ENABLE_PCLK_G3D, 3213 ENABLE_SCLK_G3D, 3214 ENABLE_IP_G3D0, 3215 ENABLE_IP_G3D1, 3216 CLKOUT_CMU_G3D, 3217 CLKOUT_CMU_G3D_DIV_STAT, 3218 CLK_STOPCTRL, 3219 }; 3220 3221 /* list of all parent clock list */ 3222 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; 3223 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; 3224 3225 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 3226 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", 3227 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5443_pll_rates), 3228 }; 3229 3230 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 3231 /* MUX_SEL_G3D */ 3232 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p, 3233 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), 3234 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 3235 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), 3236 }; 3237 3238 static const struct samsung_div_clock g3d_div_clks[] __initconst = { 3239 /* DIV_G3D */ 3240 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D, 3241 8, 2), 3242 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D, 3243 4, 3), 3244 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D, 3245 0, 3, CLK_SET_RATE_PARENT, 0), 3246 }; 3247 3248 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 3249 /* ENABLE_ACLK_G3D */ 3250 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d", 3251 ENABLE_ACLK_G3D, 7, 0, 0), 3252 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d", 3253 ENABLE_ACLK_G3D, 6, 0, 0), 3254 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d", 3255 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0), 3256 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d", 3257 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0), 3258 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d", 3259 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0), 3260 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d", 3261 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0), 3262 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d", 3263 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3264 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d", 3265 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0), 3266 3267 /* ENABLE_PCLK_G3D */ 3268 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d", 3269 ENABLE_PCLK_G3D, 3, 0, 0), 3270 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d", 3271 ENABLE_PCLK_G3D, 2, 0, 0), 3272 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d", 3273 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0), 3274 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d", 3275 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0), 3276 3277 /* ENABLE_SCLK_G3D */ 3278 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d", 3279 ENABLE_SCLK_G3D, 0, 0, 0), 3280 }; 3281 3282 static const struct samsung_cmu_info g3d_cmu_info __initconst = { 3283 .pll_clks = g3d_pll_clks, 3284 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 3285 .mux_clks = g3d_mux_clks, 3286 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 3287 .div_clks = g3d_div_clks, 3288 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 3289 .gate_clks = g3d_gate_clks, 3290 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 3291 .nr_clk_ids = G3D_NR_CLK, 3292 .clk_regs = g3d_clk_regs, 3293 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 3294 }; 3295 3296 static void __init exynos5433_cmu_g3d_init(struct device_node *np) 3297 { 3298 samsung_cmu_register_one(np, &g3d_cmu_info); 3299 } 3300 CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d", 3301 exynos5433_cmu_g3d_init); 3302 3303 /* 3304 * Register offset definitions for CMU_GSCL 3305 */ 3306 #define MUX_SEL_GSCL 0x0200 3307 #define MUX_ENABLE_GSCL 0x0300 3308 #define MUX_STAT_GSCL 0x0400 3309 #define ENABLE_ACLK_GSCL 0x0800 3310 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804 3311 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808 3312 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c 3313 #define ENABLE_PCLK_GSCL 0x0900 3314 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904 3315 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908 3316 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c 3317 #define ENABLE_IP_GSCL0 0x0b00 3318 #define ENABLE_IP_GSCL1 0x0b04 3319 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08 3320 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c 3321 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10 3322 3323 static const unsigned long gscl_clk_regs[] __initconst = { 3324 MUX_SEL_GSCL, 3325 MUX_ENABLE_GSCL, 3326 ENABLE_ACLK_GSCL, 3327 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 3328 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 3329 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 3330 ENABLE_PCLK_GSCL, 3331 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 3332 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 3333 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 3334 ENABLE_IP_GSCL0, 3335 ENABLE_IP_GSCL1, 3336 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0, 3337 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1, 3338 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2, 3339 }; 3340 3341 /* list of all parent clock list */ 3342 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; 3343 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; 3344 3345 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { 3346 /* MUX_SEL_GSCL */ 3347 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user", 3348 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1), 3349 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 3350 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1), 3351 }; 3352 3353 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { 3354 /* ENABLE_ACLK_GSCL */ 3355 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user", 3356 ENABLE_ACLK_GSCL, 11, 0, 0), 3357 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user", 3358 ENABLE_ACLK_GSCL, 10, 0, 0), 3359 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user", 3360 ENABLE_ACLK_GSCL, 9, 0, 0), 3361 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp", 3362 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL, 3363 8, CLK_IGNORE_UNUSED, 0), 3364 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user", 3365 ENABLE_ACLK_GSCL, 7, 0, 0), 3366 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user", 3367 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0), 3368 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333", 3369 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5, 3370 CLK_IGNORE_UNUSED, 0), 3371 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333", 3372 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4, 3373 CLK_IGNORE_UNUSED, 0), 3374 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user", 3375 ENABLE_ACLK_GSCL, 3, 0, 0), 3376 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user", 3377 ENABLE_ACLK_GSCL, 2, 0, 0), 3378 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user", 3379 ENABLE_ACLK_GSCL, 1, 0, 0), 3380 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user", 3381 ENABLE_ACLK_GSCL, 0, 0, 0), 3382 3383 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */ 3384 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user", 3385 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3386 3387 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */ 3388 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user", 3389 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3390 3391 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */ 3392 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user", 3393 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3394 3395 /* ENABLE_PCLK_GSCL */ 3396 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user", 3397 ENABLE_PCLK_GSCL, 7, 0, 0), 3398 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user", 3399 ENABLE_PCLK_GSCL, 6, 0, 0), 3400 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user", 3401 ENABLE_PCLK_GSCL, 5, 0, 0), 3402 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user", 3403 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0), 3404 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl", 3405 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL, 3406 3, CLK_IGNORE_UNUSED, 0), 3407 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user", 3408 ENABLE_PCLK_GSCL, 2, 0, 0), 3409 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user", 3410 ENABLE_PCLK_GSCL, 1, 0, 0), 3411 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user", 3412 ENABLE_PCLK_GSCL, 0, 0, 0), 3413 3414 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */ 3415 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user", 3416 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0), 3417 3418 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */ 3419 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user", 3420 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0), 3421 3422 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */ 3423 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user", 3424 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0), 3425 }; 3426 3427 static const struct samsung_cmu_info gscl_cmu_info __initconst = { 3428 .mux_clks = gscl_mux_clks, 3429 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 3430 .gate_clks = gscl_gate_clks, 3431 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), 3432 .nr_clk_ids = GSCL_NR_CLK, 3433 .clk_regs = gscl_clk_regs, 3434 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 3435 }; 3436 3437 static void __init exynos5433_cmu_gscl_init(struct device_node *np) 3438 { 3439 samsung_cmu_register_one(np, &gscl_cmu_info); 3440 } 3441 CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl", 3442 exynos5433_cmu_gscl_init); 3443 3444 /* 3445 * Register offset definitions for CMU_APOLLO 3446 */ 3447 #define APOLLO_PLL_LOCK 0x0000 3448 #define APOLLO_PLL_CON0 0x0100 3449 #define APOLLO_PLL_CON1 0x0104 3450 #define APOLLO_PLL_FREQ_DET 0x010c 3451 #define MUX_SEL_APOLLO0 0x0200 3452 #define MUX_SEL_APOLLO1 0x0204 3453 #define MUX_SEL_APOLLO2 0x0208 3454 #define MUX_ENABLE_APOLLO0 0x0300 3455 #define MUX_ENABLE_APOLLO1 0x0304 3456 #define MUX_ENABLE_APOLLO2 0x0308 3457 #define MUX_STAT_APOLLO0 0x0400 3458 #define MUX_STAT_APOLLO1 0x0404 3459 #define MUX_STAT_APOLLO2 0x0408 3460 #define DIV_APOLLO0 0x0600 3461 #define DIV_APOLLO1 0x0604 3462 #define DIV_APOLLO_PLL_FREQ_DET 0x0608 3463 #define DIV_STAT_APOLLO0 0x0700 3464 #define DIV_STAT_APOLLO1 0x0704 3465 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708 3466 #define ENABLE_ACLK_APOLLO 0x0800 3467 #define ENABLE_PCLK_APOLLO 0x0900 3468 #define ENABLE_SCLK_APOLLO 0x0a00 3469 #define ENABLE_IP_APOLLO0 0x0b00 3470 #define ENABLE_IP_APOLLO1 0x0b04 3471 #define CLKOUT_CMU_APOLLO 0x0c00 3472 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04 3473 #define ARMCLK_STOPCTRL 0x1000 3474 #define APOLLO_PWR_CTRL 0x1020 3475 #define APOLLO_PWR_CTRL2 0x1024 3476 #define APOLLO_INTR_SPREAD_ENABLE 0x1080 3477 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084 3478 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088 3479 3480 static const unsigned long apollo_clk_regs[] __initconst = { 3481 APOLLO_PLL_LOCK, 3482 APOLLO_PLL_CON0, 3483 APOLLO_PLL_CON1, 3484 APOLLO_PLL_FREQ_DET, 3485 MUX_SEL_APOLLO0, 3486 MUX_SEL_APOLLO1, 3487 MUX_SEL_APOLLO2, 3488 MUX_ENABLE_APOLLO0, 3489 MUX_ENABLE_APOLLO1, 3490 MUX_ENABLE_APOLLO2, 3491 DIV_APOLLO0, 3492 DIV_APOLLO1, 3493 DIV_APOLLO_PLL_FREQ_DET, 3494 ENABLE_ACLK_APOLLO, 3495 ENABLE_PCLK_APOLLO, 3496 ENABLE_SCLK_APOLLO, 3497 ENABLE_IP_APOLLO0, 3498 ENABLE_IP_APOLLO1, 3499 CLKOUT_CMU_APOLLO, 3500 CLKOUT_CMU_APOLLO_DIV_STAT, 3501 ARMCLK_STOPCTRL, 3502 APOLLO_PWR_CTRL, 3503 APOLLO_PWR_CTRL2, 3504 APOLLO_INTR_SPREAD_ENABLE, 3505 APOLLO_INTR_SPREAD_USE_STANDBYWFI, 3506 APOLLO_INTR_SPREAD_BLOCKING_DURATION, 3507 }; 3508 3509 /* list of all parent clock list */ 3510 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", }; 3511 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", }; 3512 PNAME(mout_apollo_p) = { "mout_apollo_pll", 3513 "mout_bus_pll_apollo_user", }; 3514 3515 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = { 3516 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk", 3517 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5443_pll_rates), 3518 }; 3519 3520 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = { 3521 /* MUX_SEL_APOLLO0 */ 3522 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p, 3523 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT | 3524 CLK_RECALC_NEW_RATES, 0), 3525 3526 /* MUX_SEL_APOLLO1 */ 3527 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user", 3528 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1), 3529 3530 /* MUX_SEL_APOLLO2 */ 3531 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2, 3532 0, 1, CLK_SET_RATE_PARENT, 0), 3533 }; 3534 3535 static const struct samsung_div_clock apollo_div_clks[] __initconst = { 3536 /* DIV_APOLLO0 */ 3537 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2", 3538 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE, 3539 CLK_DIVIDER_READ_ONLY), 3540 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2", 3541 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE, 3542 CLK_DIVIDER_READ_ONLY), 3543 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2", 3544 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE, 3545 CLK_DIVIDER_READ_ONLY), 3546 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2", 3547 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE, 3548 CLK_DIVIDER_READ_ONLY), 3549 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2", 3550 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE, 3551 CLK_DIVIDER_READ_ONLY), 3552 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1", 3553 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0), 3554 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo", 3555 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0), 3556 3557 /* DIV_APOLLO1 */ 3558 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo", 3559 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE, 3560 CLK_DIVIDER_READ_ONLY), 3561 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo", 3562 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE, 3563 CLK_DIVIDER_READ_ONLY), 3564 }; 3565 3566 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = { 3567 /* ENABLE_ACLK_APOLLO */ 3568 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys", 3569 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3570 6, CLK_IGNORE_UNUSED, 0), 3571 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys", 3572 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3573 5, CLK_IGNORE_UNUSED, 0), 3574 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys", 3575 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3576 4, CLK_IGNORE_UNUSED, 0), 3577 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys", 3578 "div_atclk_apollo", ENABLE_ACLK_APOLLO, 3579 3, CLK_IGNORE_UNUSED, 0), 3580 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci", 3581 "div_aclk_apollo", ENABLE_ACLK_APOLLO, 3582 2, CLK_IGNORE_UNUSED, 0), 3583 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop", 3584 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3585 1, CLK_IGNORE_UNUSED, 0), 3586 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200", 3587 "div_pclk_apollo", ENABLE_ACLK_APOLLO, 3588 0, CLK_IGNORE_UNUSED, 0), 3589 3590 /* ENABLE_PCLK_APOLLO */ 3591 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo", 3592 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO, 3593 2, CLK_IGNORE_UNUSED, 0), 3594 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo", 3595 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3596 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo", 3597 "div_pclk_apollo", ENABLE_PCLK_APOLLO, 3598 0, CLK_IGNORE_UNUSED, 0), 3599 3600 /* ENABLE_SCLK_APOLLO */ 3601 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo", 3602 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0), 3603 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo", 3604 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0), 3605 }; 3606 3607 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3608 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3609 ((pclk) << 12) | ((aclk) << 8)) 3610 3611 #define E5433_APOLLO_DIV1(hpm, copy) \ 3612 (((hpm) << 4) | ((copy) << 0)) 3613 3614 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = { 3615 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3616 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3617 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3618 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3619 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3620 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3621 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), }, 3622 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3623 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3624 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), }, 3625 { 0 }, 3626 }; 3627 3628 static void __init exynos5433_cmu_apollo_init(struct device_node *np) 3629 { 3630 void __iomem *reg_base; 3631 struct samsung_clk_provider *ctx; 3632 3633 reg_base = of_iomap(np, 0); 3634 if (!reg_base) { 3635 panic("%s: failed to map registers\n", __func__); 3636 return; 3637 } 3638 3639 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK); 3640 if (!ctx) { 3641 panic("%s: unable to allocate ctx\n", __func__); 3642 return; 3643 } 3644 3645 samsung_clk_register_pll(ctx, apollo_pll_clks, 3646 ARRAY_SIZE(apollo_pll_clks), reg_base); 3647 samsung_clk_register_mux(ctx, apollo_mux_clks, 3648 ARRAY_SIZE(apollo_mux_clks)); 3649 samsung_clk_register_div(ctx, apollo_div_clks, 3650 ARRAY_SIZE(apollo_div_clks)); 3651 samsung_clk_register_gate(ctx, apollo_gate_clks, 3652 ARRAY_SIZE(apollo_gate_clks)); 3653 3654 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk", 3655 mout_apollo_p[0], mout_apollo_p[1], 0x200, 3656 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d), 3657 CLK_CPU_HAS_E5433_REGS_LAYOUT); 3658 3659 samsung_clk_sleep_init(reg_base, apollo_clk_regs, 3660 ARRAY_SIZE(apollo_clk_regs)); 3661 3662 samsung_clk_of_add_provider(np, ctx); 3663 } 3664 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo", 3665 exynos5433_cmu_apollo_init); 3666 3667 /* 3668 * Register offset definitions for CMU_ATLAS 3669 */ 3670 #define ATLAS_PLL_LOCK 0x0000 3671 #define ATLAS_PLL_CON0 0x0100 3672 #define ATLAS_PLL_CON1 0x0104 3673 #define ATLAS_PLL_FREQ_DET 0x010c 3674 #define MUX_SEL_ATLAS0 0x0200 3675 #define MUX_SEL_ATLAS1 0x0204 3676 #define MUX_SEL_ATLAS2 0x0208 3677 #define MUX_ENABLE_ATLAS0 0x0300 3678 #define MUX_ENABLE_ATLAS1 0x0304 3679 #define MUX_ENABLE_ATLAS2 0x0308 3680 #define MUX_STAT_ATLAS0 0x0400 3681 #define MUX_STAT_ATLAS1 0x0404 3682 #define MUX_STAT_ATLAS2 0x0408 3683 #define DIV_ATLAS0 0x0600 3684 #define DIV_ATLAS1 0x0604 3685 #define DIV_ATLAS_PLL_FREQ_DET 0x0608 3686 #define DIV_STAT_ATLAS0 0x0700 3687 #define DIV_STAT_ATLAS1 0x0704 3688 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708 3689 #define ENABLE_ACLK_ATLAS 0x0800 3690 #define ENABLE_PCLK_ATLAS 0x0900 3691 #define ENABLE_SCLK_ATLAS 0x0a00 3692 #define ENABLE_IP_ATLAS0 0x0b00 3693 #define ENABLE_IP_ATLAS1 0x0b04 3694 #define CLKOUT_CMU_ATLAS 0x0c00 3695 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04 3696 #define ARMCLK_STOPCTRL 0x1000 3697 #define ATLAS_PWR_CTRL 0x1020 3698 #define ATLAS_PWR_CTRL2 0x1024 3699 #define ATLAS_INTR_SPREAD_ENABLE 0x1080 3700 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084 3701 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088 3702 3703 static const unsigned long atlas_clk_regs[] __initconst = { 3704 ATLAS_PLL_LOCK, 3705 ATLAS_PLL_CON0, 3706 ATLAS_PLL_CON1, 3707 ATLAS_PLL_FREQ_DET, 3708 MUX_SEL_ATLAS0, 3709 MUX_SEL_ATLAS1, 3710 MUX_SEL_ATLAS2, 3711 MUX_ENABLE_ATLAS0, 3712 MUX_ENABLE_ATLAS1, 3713 MUX_ENABLE_ATLAS2, 3714 DIV_ATLAS0, 3715 DIV_ATLAS1, 3716 DIV_ATLAS_PLL_FREQ_DET, 3717 ENABLE_ACLK_ATLAS, 3718 ENABLE_PCLK_ATLAS, 3719 ENABLE_SCLK_ATLAS, 3720 ENABLE_IP_ATLAS0, 3721 ENABLE_IP_ATLAS1, 3722 CLKOUT_CMU_ATLAS, 3723 CLKOUT_CMU_ATLAS_DIV_STAT, 3724 ARMCLK_STOPCTRL, 3725 ATLAS_PWR_CTRL, 3726 ATLAS_PWR_CTRL2, 3727 ATLAS_INTR_SPREAD_ENABLE, 3728 ATLAS_INTR_SPREAD_USE_STANDBYWFI, 3729 ATLAS_INTR_SPREAD_BLOCKING_DURATION, 3730 }; 3731 3732 /* list of all parent clock list */ 3733 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", }; 3734 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", }; 3735 PNAME(mout_atlas_p) = { "mout_atlas_pll", 3736 "mout_bus_pll_atlas_user", }; 3737 3738 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = { 3739 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk", 3740 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5443_pll_rates), 3741 }; 3742 3743 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = { 3744 /* MUX_SEL_ATLAS0 */ 3745 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p, 3746 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT | 3747 CLK_RECALC_NEW_RATES, 0), 3748 3749 /* MUX_SEL_ATLAS1 */ 3750 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user", 3751 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1), 3752 3753 /* MUX_SEL_ATLAS2 */ 3754 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2, 3755 0, 1, CLK_SET_RATE_PARENT, 0), 3756 }; 3757 3758 static const struct samsung_div_clock atlas_div_clks[] __initconst = { 3759 /* DIV_ATLAS0 */ 3760 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2", 3761 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE, 3762 CLK_DIVIDER_READ_ONLY), 3763 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas", 3764 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE, 3765 CLK_DIVIDER_READ_ONLY), 3766 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2", 3767 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE, 3768 CLK_DIVIDER_READ_ONLY), 3769 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2", 3770 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE, 3771 CLK_DIVIDER_READ_ONLY), 3772 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2", 3773 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE, 3774 CLK_DIVIDER_READ_ONLY), 3775 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1", 3776 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0), 3777 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas", 3778 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0), 3779 3780 /* DIV_ATLAS1 */ 3781 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas", 3782 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE, 3783 CLK_DIVIDER_READ_ONLY), 3784 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas", 3785 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE, 3786 CLK_DIVIDER_READ_ONLY), 3787 }; 3788 3789 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = { 3790 /* ENABLE_ACLK_ATLAS */ 3791 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys", 3792 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3793 9, CLK_IGNORE_UNUSED, 0), 3794 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys", 3795 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3796 8, CLK_IGNORE_UNUSED, 0), 3797 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys", 3798 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3799 7, CLK_IGNORE_UNUSED, 0), 3800 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys", 3801 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3802 6, CLK_IGNORE_UNUSED, 0), 3803 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys", 3804 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3805 5, CLK_IGNORE_UNUSED, 0), 3806 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss", 3807 "div_atclk_atlas", ENABLE_ACLK_ATLAS, 3808 4, CLK_IGNORE_UNUSED, 0), 3809 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix", 3810 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS, 3811 3, CLK_IGNORE_UNUSED, 0), 3812 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci", 3813 "div_aclk_atlas", ENABLE_ACLK_ATLAS, 3814 2, CLK_IGNORE_UNUSED, 0), 3815 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas", 3816 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3817 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas", 3818 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3819 3820 /* ENABLE_PCLK_ATLAS */ 3821 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys", 3822 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3823 5, CLK_IGNORE_UNUSED, 0), 3824 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys", 3825 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3826 4, CLK_IGNORE_UNUSED, 0), 3827 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys", 3828 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS, 3829 3, CLK_IGNORE_UNUSED, 0), 3830 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas", 3831 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3832 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas", 3833 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3834 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas", 3835 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0), 3836 3837 /* ENABLE_SCLK_ATLAS */ 3838 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas", 3839 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0), 3840 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas", 3841 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0), 3842 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas", 3843 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0), 3844 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas", 3845 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0), 3846 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas", 3847 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0), 3848 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas", 3849 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0), 3850 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas", 3851 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0), 3852 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas", 3853 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0), 3854 }; 3855 3856 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \ 3857 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \ 3858 ((pclk) << 12) | ((aclk) << 8)) 3859 3860 #define E5433_ATLAS_DIV1(hpm, copy) \ 3861 (((hpm) << 4) | ((copy) << 0)) 3862 3863 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = { 3864 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3865 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3866 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3867 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), }, 3868 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3869 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3870 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3871 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3872 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3873 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), }, 3874 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3875 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3876 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3877 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3878 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), }, 3879 { 0 }, 3880 }; 3881 3882 static void __init exynos5433_cmu_atlas_init(struct device_node *np) 3883 { 3884 void __iomem *reg_base; 3885 struct samsung_clk_provider *ctx; 3886 3887 reg_base = of_iomap(np, 0); 3888 if (!reg_base) { 3889 panic("%s: failed to map registers\n", __func__); 3890 return; 3891 } 3892 3893 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK); 3894 if (!ctx) { 3895 panic("%s: unable to allocate ctx\n", __func__); 3896 return; 3897 } 3898 3899 samsung_clk_register_pll(ctx, atlas_pll_clks, 3900 ARRAY_SIZE(atlas_pll_clks), reg_base); 3901 samsung_clk_register_mux(ctx, atlas_mux_clks, 3902 ARRAY_SIZE(atlas_mux_clks)); 3903 samsung_clk_register_div(ctx, atlas_div_clks, 3904 ARRAY_SIZE(atlas_div_clks)); 3905 samsung_clk_register_gate(ctx, atlas_gate_clks, 3906 ARRAY_SIZE(atlas_gate_clks)); 3907 3908 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk", 3909 mout_atlas_p[0], mout_atlas_p[1], 0x200, 3910 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d), 3911 CLK_CPU_HAS_E5433_REGS_LAYOUT); 3912 3913 samsung_clk_sleep_init(reg_base, atlas_clk_regs, 3914 ARRAY_SIZE(atlas_clk_regs)); 3915 3916 samsung_clk_of_add_provider(np, ctx); 3917 } 3918 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas", 3919 exynos5433_cmu_atlas_init); 3920 3921 /* 3922 * Register offset definitions for CMU_MSCL 3923 */ 3924 #define MUX_SEL_MSCL0 0x0200 3925 #define MUX_SEL_MSCL1 0x0204 3926 #define MUX_ENABLE_MSCL0 0x0300 3927 #define MUX_ENABLE_MSCL1 0x0304 3928 #define MUX_STAT_MSCL0 0x0400 3929 #define MUX_STAT_MSCL1 0x0404 3930 #define DIV_MSCL 0x0600 3931 #define DIV_STAT_MSCL 0x0700 3932 #define ENABLE_ACLK_MSCL 0x0800 3933 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804 3934 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808 3935 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c 3936 #define ENABLE_PCLK_MSCL 0x0900 3937 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904 3938 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908 3939 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c 3940 #define ENABLE_SCLK_MSCL 0x0a00 3941 #define ENABLE_IP_MSCL0 0x0b00 3942 #define ENABLE_IP_MSCL1 0x0b04 3943 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08 3944 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c 3945 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10 3946 3947 static const unsigned long mscl_clk_regs[] __initconst = { 3948 MUX_SEL_MSCL0, 3949 MUX_SEL_MSCL1, 3950 MUX_ENABLE_MSCL0, 3951 MUX_ENABLE_MSCL1, 3952 DIV_MSCL, 3953 ENABLE_ACLK_MSCL, 3954 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 3955 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 3956 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 3957 ENABLE_PCLK_MSCL, 3958 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 3959 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 3960 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 3961 ENABLE_SCLK_MSCL, 3962 ENABLE_IP_MSCL0, 3963 ENABLE_IP_MSCL1, 3964 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0, 3965 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1, 3966 ENABLE_IP_MSCL_SECURE_SMMU_JPEG, 3967 }; 3968 3969 /* list of all parent clock list */ 3970 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", }; 3971 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; 3972 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user", 3973 "mout_aclk_mscl_400_user", }; 3974 3975 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = { 3976 /* MUX_SEL_MSCL0 */ 3977 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user", 3978 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1), 3979 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user", 3980 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1), 3981 3982 /* MUX_SEL_MSCL1 */ 3983 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p, 3984 MUX_SEL_MSCL1, 0, 1), 3985 }; 3986 3987 static const struct samsung_div_clock mscl_div_clks[] __initconst = { 3988 /* DIV_MSCL */ 3989 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user", 3990 DIV_MSCL, 0, 3), 3991 }; 3992 3993 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = { 3994 /* ENABLE_ACLK_MSCL */ 3995 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user", 3996 ENABLE_ACLK_MSCL, 9, 0, 0), 3997 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1", 3998 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0), 3999 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0", 4000 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0), 4001 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl", 4002 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0), 4003 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user", 4004 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0), 4005 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl", 4006 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4007 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user", 4008 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4009 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user", 4010 ENABLE_ACLK_MSCL, 2, 0, 0), 4011 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user", 4012 ENABLE_ACLK_MSCL, 1, 0, 0), 4013 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user", 4014 ENABLE_ACLK_MSCL, 0, 0, 0), 4015 4016 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4017 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0", 4018 "mout_aclk_mscl_400_user", 4019 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0, 4020 0, CLK_IGNORE_UNUSED, 0), 4021 4022 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4023 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1", 4024 "mout_aclk_mscl_400_user", 4025 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1, 4026 0, CLK_IGNORE_UNUSED, 0), 4027 4028 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */ 4029 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user", 4030 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG, 4031 0, CLK_IGNORE_UNUSED, 0), 4032 4033 /* ENABLE_PCLK_MSCL */ 4034 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl", 4035 ENABLE_PCLK_MSCL, 7, 0, 0), 4036 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl", 4037 ENABLE_PCLK_MSCL, 6, 0, 0), 4038 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl", 4039 ENABLE_PCLK_MSCL, 5, 0, 0), 4040 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl", 4041 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0), 4042 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl", 4043 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0), 4044 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl", 4045 ENABLE_PCLK_MSCL, 2, 0, 0), 4046 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl", 4047 ENABLE_PCLK_MSCL, 1, 0, 0), 4048 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl", 4049 ENABLE_PCLK_MSCL, 0, 0, 0), 4050 4051 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */ 4052 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl", 4053 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0, 4054 0, CLK_IGNORE_UNUSED, 0), 4055 4056 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */ 4057 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl", 4058 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1, 4059 0, CLK_IGNORE_UNUSED, 0), 4060 4061 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */ 4062 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl", 4063 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG, 4064 0, CLK_IGNORE_UNUSED, 0), 4065 4066 /* ENABLE_SCLK_MSCL */ 4067 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0, 4068 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 4069 }; 4070 4071 static const struct samsung_cmu_info mscl_cmu_info __initconst = { 4072 .mux_clks = mscl_mux_clks, 4073 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks), 4074 .div_clks = mscl_div_clks, 4075 .nr_div_clks = ARRAY_SIZE(mscl_div_clks), 4076 .gate_clks = mscl_gate_clks, 4077 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks), 4078 .nr_clk_ids = MSCL_NR_CLK, 4079 .clk_regs = mscl_clk_regs, 4080 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 4081 }; 4082 4083 static void __init exynos5433_cmu_mscl_init(struct device_node *np) 4084 { 4085 samsung_cmu_register_one(np, &mscl_cmu_info); 4086 } 4087 CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl", 4088 exynos5433_cmu_mscl_init); 4089 4090 /* 4091 * Register offset definitions for CMU_MFC 4092 */ 4093 #define MUX_SEL_MFC 0x0200 4094 #define MUX_ENABLE_MFC 0x0300 4095 #define MUX_STAT_MFC 0x0400 4096 #define DIV_MFC 0x0600 4097 #define DIV_STAT_MFC 0x0700 4098 #define ENABLE_ACLK_MFC 0x0800 4099 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804 4100 #define ENABLE_PCLK_MFC 0x0900 4101 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904 4102 #define ENABLE_IP_MFC0 0x0b00 4103 #define ENABLE_IP_MFC1 0x0b04 4104 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08 4105 4106 static const unsigned long mfc_clk_regs[] __initconst = { 4107 MUX_SEL_MFC, 4108 MUX_ENABLE_MFC, 4109 DIV_MFC, 4110 ENABLE_ACLK_MFC, 4111 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4112 ENABLE_PCLK_MFC, 4113 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4114 ENABLE_IP_MFC0, 4115 ENABLE_IP_MFC1, 4116 ENABLE_IP_MFC_SECURE_SMMU_MFC, 4117 }; 4118 4119 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; 4120 4121 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 4122 /* MUX_SEL_MFC */ 4123 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user", 4124 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0), 4125 }; 4126 4127 static const struct samsung_div_clock mfc_div_clks[] __initconst = { 4128 /* DIV_MFC */ 4129 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user", 4130 DIV_MFC, 0, 2), 4131 }; 4132 4133 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 4134 /* ENABLE_ACLK_MFC */ 4135 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user", 4136 ENABLE_ACLK_MFC, 6, 0, 0), 4137 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user", 4138 ENABLE_ACLK_MFC, 5, 0, 0), 4139 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc", 4140 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4141 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user", 4142 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0), 4143 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc", 4144 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4145 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user", 4146 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4147 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user", 4148 ENABLE_ACLK_MFC, 0, 0, 0), 4149 4150 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */ 4151 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user", 4152 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4153 1, CLK_IGNORE_UNUSED, 0), 4154 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user", 4155 ENABLE_ACLK_MFC_SECURE_SMMU_MFC, 4156 0, CLK_IGNORE_UNUSED, 0), 4157 4158 /* ENABLE_PCLK_MFC */ 4159 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc", 4160 ENABLE_PCLK_MFC, 4, 0, 0), 4161 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc", 4162 ENABLE_PCLK_MFC, 3, 0, 0), 4163 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc", 4164 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0), 4165 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc", 4166 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0), 4167 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc", 4168 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0), 4169 4170 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */ 4171 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc", 4172 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4173 1, CLK_IGNORE_UNUSED, 0), 4174 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc", 4175 ENABLE_PCLK_MFC_SECURE_SMMU_MFC, 4176 0, CLK_IGNORE_UNUSED, 0), 4177 }; 4178 4179 static const struct samsung_cmu_info mfc_cmu_info __initconst = { 4180 .mux_clks = mfc_mux_clks, 4181 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 4182 .div_clks = mfc_div_clks, 4183 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 4184 .gate_clks = mfc_gate_clks, 4185 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 4186 .nr_clk_ids = MFC_NR_CLK, 4187 .clk_regs = mfc_clk_regs, 4188 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 4189 }; 4190 4191 static void __init exynos5433_cmu_mfc_init(struct device_node *np) 4192 { 4193 samsung_cmu_register_one(np, &mfc_cmu_info); 4194 } 4195 CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc", 4196 exynos5433_cmu_mfc_init); 4197 4198 /* 4199 * Register offset definitions for CMU_HEVC 4200 */ 4201 #define MUX_SEL_HEVC 0x0200 4202 #define MUX_ENABLE_HEVC 0x0300 4203 #define MUX_STAT_HEVC 0x0400 4204 #define DIV_HEVC 0x0600 4205 #define DIV_STAT_HEVC 0x0700 4206 #define ENABLE_ACLK_HEVC 0x0800 4207 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804 4208 #define ENABLE_PCLK_HEVC 0x0900 4209 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904 4210 #define ENABLE_IP_HEVC0 0x0b00 4211 #define ENABLE_IP_HEVC1 0x0b04 4212 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08 4213 4214 static const unsigned long hevc_clk_regs[] __initconst = { 4215 MUX_SEL_HEVC, 4216 MUX_ENABLE_HEVC, 4217 DIV_HEVC, 4218 ENABLE_ACLK_HEVC, 4219 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4220 ENABLE_PCLK_HEVC, 4221 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4222 ENABLE_IP_HEVC0, 4223 ENABLE_IP_HEVC1, 4224 ENABLE_IP_HEVC_SECURE_SMMU_HEVC, 4225 }; 4226 4227 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; 4228 4229 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = { 4230 /* MUX_SEL_HEVC */ 4231 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user", 4232 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0), 4233 }; 4234 4235 static const struct samsung_div_clock hevc_div_clks[] __initconst = { 4236 /* DIV_HEVC */ 4237 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user", 4238 DIV_HEVC, 0, 2), 4239 }; 4240 4241 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = { 4242 /* ENABLE_ACLK_HEVC */ 4243 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user", 4244 ENABLE_ACLK_HEVC, 6, 0, 0), 4245 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user", 4246 ENABLE_ACLK_HEVC, 5, 0, 0), 4247 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc", 4248 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4249 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user", 4250 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0), 4251 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc", 4252 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4253 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user", 4254 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4255 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user", 4256 ENABLE_ACLK_HEVC, 0, 0, 0), 4257 4258 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */ 4259 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1", 4260 "mout_aclk_hevc_400_user", 4261 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4262 1, CLK_IGNORE_UNUSED, 0), 4263 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0", 4264 "mout_aclk_hevc_400_user", 4265 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC, 4266 0, CLK_IGNORE_UNUSED, 0), 4267 4268 /* ENABLE_PCLK_HEVC */ 4269 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc", 4270 ENABLE_PCLK_HEVC, 4, 0, 0), 4271 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc", 4272 ENABLE_PCLK_HEVC, 3, 0, 0), 4273 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc", 4274 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0), 4275 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc", 4276 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0), 4277 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc", 4278 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0), 4279 4280 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */ 4281 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc", 4282 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4283 1, CLK_IGNORE_UNUSED, 0), 4284 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc", 4285 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC, 4286 0, CLK_IGNORE_UNUSED, 0), 4287 }; 4288 4289 static const struct samsung_cmu_info hevc_cmu_info __initconst = { 4290 .mux_clks = hevc_mux_clks, 4291 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks), 4292 .div_clks = hevc_div_clks, 4293 .nr_div_clks = ARRAY_SIZE(hevc_div_clks), 4294 .gate_clks = hevc_gate_clks, 4295 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks), 4296 .nr_clk_ids = HEVC_NR_CLK, 4297 .clk_regs = hevc_clk_regs, 4298 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), 4299 }; 4300 4301 static void __init exynos5433_cmu_hevc_init(struct device_node *np) 4302 { 4303 samsung_cmu_register_one(np, &hevc_cmu_info); 4304 } 4305 CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc", 4306 exynos5433_cmu_hevc_init); 4307 4308 /* 4309 * Register offset definitions for CMU_ISP 4310 */ 4311 #define MUX_SEL_ISP 0x0200 4312 #define MUX_ENABLE_ISP 0x0300 4313 #define MUX_STAT_ISP 0x0400 4314 #define DIV_ISP 0x0600 4315 #define DIV_STAT_ISP 0x0700 4316 #define ENABLE_ACLK_ISP0 0x0800 4317 #define ENABLE_ACLK_ISP1 0x0804 4318 #define ENABLE_ACLK_ISP2 0x0808 4319 #define ENABLE_PCLK_ISP 0x0900 4320 #define ENABLE_SCLK_ISP 0x0a00 4321 #define ENABLE_IP_ISP0 0x0b00 4322 #define ENABLE_IP_ISP1 0x0b04 4323 #define ENABLE_IP_ISP2 0x0b08 4324 #define ENABLE_IP_ISP3 0x0b0c 4325 4326 static const unsigned long isp_clk_regs[] __initconst = { 4327 MUX_SEL_ISP, 4328 MUX_ENABLE_ISP, 4329 DIV_ISP, 4330 ENABLE_ACLK_ISP0, 4331 ENABLE_ACLK_ISP1, 4332 ENABLE_ACLK_ISP2, 4333 ENABLE_PCLK_ISP, 4334 ENABLE_SCLK_ISP, 4335 ENABLE_IP_ISP0, 4336 ENABLE_IP_ISP1, 4337 ENABLE_IP_ISP2, 4338 ENABLE_IP_ISP3, 4339 }; 4340 4341 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; 4342 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; 4343 4344 static const struct samsung_mux_clock isp_mux_clks[] __initconst = { 4345 /* MUX_SEL_ISP */ 4346 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user", 4347 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0), 4348 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user", 4349 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0), 4350 }; 4351 4352 static const struct samsung_div_clock isp_div_clks[] __initconst = { 4353 /* DIV_ISP */ 4354 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis", 4355 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3), 4356 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user", 4357 DIV_ISP, 8, 3), 4358 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200", 4359 "mout_aclk_isp_400_user", DIV_ISP, 4, 3), 4360 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200", 4361 "mout_aclk_isp_400_user", DIV_ISP, 0, 3), 4362 }; 4363 4364 static const struct samsung_gate_clock isp_gate_clks[] __initconst = { 4365 /* ENABLE_ACLK_ISP0 */ 4366 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user", 4367 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0), 4368 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user", 4369 ENABLE_ACLK_ISP0, 5, 0, 0), 4370 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user", 4371 ENABLE_ACLK_ISP0, 4, 0, 0), 4372 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user", 4373 ENABLE_ACLK_ISP0, 3, 0, 0), 4374 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user", 4375 ENABLE_ACLK_ISP0, 2, 0, 0), 4376 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user", 4377 ENABLE_ACLK_ISP0, 1, 0, 0), 4378 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user", 4379 ENABLE_ACLK_ISP0, 0, 0, 0), 4380 4381 /* ENABLE_ACLK_ISP1 */ 4382 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp", 4383 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4384 17, CLK_IGNORE_UNUSED, 0), 4385 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc", 4386 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4387 16, CLK_IGNORE_UNUSED, 0), 4388 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc", 4389 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4390 15, CLK_IGNORE_UNUSED, 0), 4391 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p", 4392 "div_pclk_isp", ENABLE_ACLK_ISP1, 4393 14, CLK_IGNORE_UNUSED, 0), 4394 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p", 4395 "div_pclk_isp", ENABLE_ACLK_ISP1, 4396 13, CLK_IGNORE_UNUSED, 0), 4397 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1", 4398 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4399 12, CLK_IGNORE_UNUSED, 0), 4400 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0", 4401 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1, 4402 11, CLK_IGNORE_UNUSED, 0), 4403 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1", 4404 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4405 10, CLK_IGNORE_UNUSED, 0), 4406 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0", 4407 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1, 4408 9, CLK_IGNORE_UNUSED, 0), 4409 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p", 4410 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4411 8, CLK_IGNORE_UNUSED, 0), 4412 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p", 4413 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4414 7, CLK_IGNORE_UNUSED, 0), 4415 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp", 4416 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0), 4417 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp", 4418 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0), 4419 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p", 4420 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1, 4421 4, CLK_IGNORE_UNUSED, 0), 4422 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p", 4423 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1, 4424 3, CLK_IGNORE_UNUSED, 0), 4425 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user", 4426 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0), 4427 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user", 4428 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4429 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user", 4430 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0), 4431 4432 /* ENABLE_ACLK_ISP2 */ 4433 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp", 4434 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4435 13, CLK_IGNORE_UNUSED, 0), 4436 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user", 4437 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0), 4438 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user", 4439 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0), 4440 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user", 4441 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0), 4442 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc", 4443 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4444 9, CLK_IGNORE_UNUSED, 0), 4445 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user", 4446 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0), 4447 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user", 4448 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0), 4449 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp", 4450 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4451 6, CLK_IGNORE_UNUSED, 0), 4452 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user", 4453 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0), 4454 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user", 4455 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0), 4456 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user", 4457 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0), 4458 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc", 4459 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2, 4460 2, CLK_IGNORE_UNUSED, 0), 4461 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user", 4462 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0), 4463 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user", 4464 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0), 4465 4466 /* ENABLE_PCLK_ISP */ 4467 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200", 4468 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0), 4469 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200", 4470 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0), 4471 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200", 4472 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0), 4473 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200", 4474 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0), 4475 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200", 4476 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0), 4477 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200", 4478 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0), 4479 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200", 4480 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0), 4481 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp", 4482 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0), 4483 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp", 4484 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0), 4485 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp", 4486 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0), 4487 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp", 4488 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0), 4489 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp", 4490 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0), 4491 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp", 4492 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0), 4493 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp", 4494 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0), 4495 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp", 4496 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0), 4497 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp", 4498 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0), 4499 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp", 4500 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0), 4501 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp", 4502 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0), 4503 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local", 4504 "div_aclk_isp_c_200", ENABLE_PCLK_ISP, 4505 7, CLK_IGNORE_UNUSED, 0), 4506 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200", 4507 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0), 4508 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200", 4509 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0), 4510 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis", 4511 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0), 4512 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200", 4513 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0), 4514 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200", 4515 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0), 4516 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200", 4517 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0), 4518 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200", 4519 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0), 4520 4521 /* ENABLE_SCLK_ISP */ 4522 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis", 4523 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4524 5, CLK_IGNORE_UNUSED, 0), 4525 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis", 4526 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP, 4527 4, CLK_IGNORE_UNUSED, 0), 4528 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp", 4529 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4530 3, CLK_IGNORE_UNUSED, 0), 4531 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd", 4532 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4533 2, CLK_IGNORE_UNUSED, 0), 4534 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc", 4535 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4536 1, CLK_IGNORE_UNUSED, 0), 4537 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc", 4538 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP, 4539 0, CLK_IGNORE_UNUSED, 0), 4540 }; 4541 4542 static const struct samsung_cmu_info isp_cmu_info __initconst = { 4543 .mux_clks = isp_mux_clks, 4544 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 4545 .div_clks = isp_div_clks, 4546 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 4547 .gate_clks = isp_gate_clks, 4548 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 4549 .nr_clk_ids = ISP_NR_CLK, 4550 .clk_regs = isp_clk_regs, 4551 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 4552 }; 4553 4554 static void __init exynos5433_cmu_isp_init(struct device_node *np) 4555 { 4556 samsung_cmu_register_one(np, &isp_cmu_info); 4557 } 4558 CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp", 4559 exynos5433_cmu_isp_init); 4560 4561 /* 4562 * Register offset definitions for CMU_CAM0 4563 */ 4564 #define MUX_SEL_CAM00 0x0200 4565 #define MUX_SEL_CAM01 0x0204 4566 #define MUX_SEL_CAM02 0x0208 4567 #define MUX_SEL_CAM03 0x020c 4568 #define MUX_SEL_CAM04 0x0210 4569 #define MUX_ENABLE_CAM00 0x0300 4570 #define MUX_ENABLE_CAM01 0x0304 4571 #define MUX_ENABLE_CAM02 0x0308 4572 #define MUX_ENABLE_CAM03 0x030c 4573 #define MUX_ENABLE_CAM04 0x0310 4574 #define MUX_STAT_CAM00 0x0400 4575 #define MUX_STAT_CAM01 0x0404 4576 #define MUX_STAT_CAM02 0x0408 4577 #define MUX_STAT_CAM03 0x040c 4578 #define MUX_STAT_CAM04 0x0410 4579 #define MUX_IGNORE_CAM01 0x0504 4580 #define DIV_CAM00 0x0600 4581 #define DIV_CAM01 0x0604 4582 #define DIV_CAM02 0x0608 4583 #define DIV_CAM03 0x060c 4584 #define DIV_STAT_CAM00 0x0700 4585 #define DIV_STAT_CAM01 0x0704 4586 #define DIV_STAT_CAM02 0x0708 4587 #define DIV_STAT_CAM03 0x070c 4588 #define ENABLE_ACLK_CAM00 0X0800 4589 #define ENABLE_ACLK_CAM01 0X0804 4590 #define ENABLE_ACLK_CAM02 0X0808 4591 #define ENABLE_PCLK_CAM0 0X0900 4592 #define ENABLE_SCLK_CAM0 0X0a00 4593 #define ENABLE_IP_CAM00 0X0b00 4594 #define ENABLE_IP_CAM01 0X0b04 4595 #define ENABLE_IP_CAM02 0X0b08 4596 #define ENABLE_IP_CAM03 0X0b0C 4597 4598 static const unsigned long cam0_clk_regs[] __initconst = { 4599 MUX_SEL_CAM00, 4600 MUX_SEL_CAM01, 4601 MUX_SEL_CAM02, 4602 MUX_SEL_CAM03, 4603 MUX_SEL_CAM04, 4604 MUX_ENABLE_CAM00, 4605 MUX_ENABLE_CAM01, 4606 MUX_ENABLE_CAM02, 4607 MUX_ENABLE_CAM03, 4608 MUX_ENABLE_CAM04, 4609 MUX_IGNORE_CAM01, 4610 DIV_CAM00, 4611 DIV_CAM01, 4612 DIV_CAM02, 4613 DIV_CAM03, 4614 ENABLE_ACLK_CAM00, 4615 ENABLE_ACLK_CAM01, 4616 ENABLE_ACLK_CAM02, 4617 ENABLE_PCLK_CAM0, 4618 ENABLE_SCLK_CAM0, 4619 ENABLE_IP_CAM00, 4620 ENABLE_IP_CAM01, 4621 ENABLE_IP_CAM02, 4622 ENABLE_IP_CAM03, 4623 }; 4624 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", }; 4625 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", }; 4626 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", }; 4627 4628 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk", 4629 "phyclk_rxbyteclkhs0_s4_phy", }; 4630 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk", 4631 "phyclk_rxbyteclkhs0_s2a_phy", }; 4632 4633 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a", 4634 "mout_aclk_cam0_333_user", }; 4635 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user", 4636 "mout_aclk_cam0_400_user", }; 4637 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a", 4638 "mout_aclk_cam0_333_user", }; 4639 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user", 4640 "mout_aclk_cam0_400_user", }; 4641 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a", 4642 "mout_aclk_cam0_333_user", }; 4643 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user", 4644 "mout_aclk_cam0_400_user", }; 4645 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user", 4646 "mout_aclk_cam0_333_user", }; 4647 4648 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a", 4649 "mout_aclk_cam0_333_user" }; 4650 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user", 4651 "mout_aclk_cam0_400_user", }; 4652 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a", 4653 "mout_aclk_cam0_333_user", }; 4654 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user", 4655 "mout_aclk-cam0_400_user", }; 4656 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a", 4657 "mout_aclk_cam0_333_user", }; 4658 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user", 4659 "mout_aclk_cam0_400_user", }; 4660 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a", 4661 "mout_aclk_cam0_333_user", }; 4662 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user", 4663 "mout_aclk_cam0_400_user", }; 4664 4665 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b", 4666 "div_pclk_lite_d", }; 4667 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a", 4668 "div_pclk_pixelasync_lite_c", }; 4669 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a", 4670 "div_pclk_lite_b", }; 4671 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a", 4672 "mout_aclk_cam0_333_user", }; 4673 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user", 4674 "mout_aclk_cam0_400_user", }; 4675 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = { 4676 "mout_sclk_pixelasync_lite_c_init_a", 4677 "mout_aclk_cam0_400_user", }; 4678 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = { 4679 "mout_aclk_cam0_552_user", 4680 "mout_aclk_cam0_400_user", }; 4681 4682 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = { 4683 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy", 4684 NULL, 0, 100000000), 4685 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy", 4686 NULL, 0, 100000000), 4687 }; 4688 4689 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = { 4690 /* MUX_SEL_CAM00 */ 4691 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user", 4692 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1), 4693 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user", 4694 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1), 4695 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user", 4696 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1), 4697 4698 /* MUX_SEL_CAM01 */ 4699 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER, 4700 "mout_phyclk_rxbyteclkhs0_s4_user", 4701 mout_phyclk_rxbyteclkhs0_s4_user_p, 4702 MUX_SEL_CAM01, 4, 1), 4703 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER, 4704 "mout_phyclk_rxbyteclkhs0_s2a_user", 4705 mout_phyclk_rxbyteclkhs0_s2a_user_p, 4706 MUX_SEL_CAM01, 0, 1), 4707 4708 /* MUX_SEL_CAM02 */ 4709 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p, 4710 MUX_SEL_CAM02, 24, 1), 4711 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p, 4712 MUX_SEL_CAM02, 20, 1), 4713 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p, 4714 MUX_SEL_CAM02, 16, 1), 4715 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p, 4716 MUX_SEL_CAM02, 12, 1), 4717 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p, 4718 MUX_SEL_CAM02, 8, 1), 4719 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p, 4720 MUX_SEL_CAM02, 4, 1), 4721 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p, 4722 MUX_SEL_CAM02, 0, 1), 4723 4724 /* MUX_SEL_CAM03 */ 4725 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p, 4726 MUX_SEL_CAM03, 28, 1), 4727 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p, 4728 MUX_SEL_CAM03, 24, 1), 4729 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p, 4730 MUX_SEL_CAM03, 20, 1), 4731 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p, 4732 MUX_SEL_CAM03, 16, 1), 4733 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p, 4734 MUX_SEL_CAM03, 12, 1), 4735 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p, 4736 MUX_SEL_CAM03, 8, 1), 4737 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p, 4738 MUX_SEL_CAM03, 4, 1), 4739 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p, 4740 MUX_SEL_CAM03, 0, 1), 4741 4742 /* MUX_SEL_CAM04 */ 4743 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c", 4744 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1), 4745 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b", 4746 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1), 4747 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a", 4748 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1), 4749 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b", 4750 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1), 4751 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a", 4752 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1), 4753 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B, 4754 "mout_sclk_pixelasync_lite_c_init_b", 4755 mout_sclk_pixelasync_lite_c_init_b_p, 4756 MUX_SEL_CAM04, 4, 1), 4757 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A, 4758 "mout_sclk_pixelasync_lite_c_init_a", 4759 mout_sclk_pixelasync_lite_c_init_a_p, 4760 MUX_SEL_CAM04, 0, 1), 4761 }; 4762 4763 static const struct samsung_div_clock cam0_div_clks[] __initconst = { 4764 /* DIV_CAM00 */ 4765 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200", 4766 DIV_CAM00, 8, 2), 4767 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400", 4768 DIV_CAM00, 4, 3), 4769 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400", 4770 "mout_aclk_cam0_400", DIV_CAM00, 0, 3), 4771 4772 /* DIV_CAM01 */ 4773 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d", 4774 DIV_CAM01, 20, 2), 4775 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b", 4776 DIV_CAM01, 16, 3), 4777 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b", 4778 DIV_CAM01, 12, 2), 4779 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b", 4780 DIV_CAM01, 8, 3), 4781 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a", 4782 DIV_CAM01, 4, 2), 4783 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b", 4784 DIV_CAM01, 0, 3), 4785 4786 /* DIV_CAM02 */ 4787 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b", 4788 DIV_CAM02, 20, 3), 4789 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b", 4790 DIV_CAM02, 16, 3), 4791 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1", 4792 DIV_CAM02, 12, 2), 4793 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b", 4794 DIV_CAM02, 8, 3), 4795 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0", 4796 DIV_CAM02, 4, 2), 4797 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b", 4798 DIV_CAM02, 0, 3), 4799 4800 /* DIV_CAM03 */ 4801 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c", 4802 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3), 4803 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c", 4804 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2), 4805 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT, 4806 "div_sclk_pixelasync_lite_c_init", 4807 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3), 4808 }; 4809 4810 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = { 4811 /* ENABLE_ACLK_CAM00 */ 4812 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00, 4813 6, 0, 0), 4814 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00, 4815 5, 0, 0), 4816 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00, 4817 4, 0, 0), 4818 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00, 4819 3, 0, 0), 4820 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d", 4821 ENABLE_ACLK_CAM00, 2, 0, 0), 4822 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b", 4823 ENABLE_ACLK_CAM00, 1, 0, 0), 4824 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a", 4825 ENABLE_ACLK_CAM00, 0, 0, 0), 4826 4827 /* ENABLE_ACLK_CAM01 */ 4828 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200", 4829 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0), 4830 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400", 4831 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0), 4832 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400", 4833 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0), 4834 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400", 4835 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0), 4836 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1", 4837 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0), 4838 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1", 4839 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0), 4840 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0", 4841 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0), 4842 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0", 4843 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0), 4844 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d", 4845 "div_pclk_lite_d", ENABLE_ACLK_CAM01, 4846 23, CLK_IGNORE_UNUSED, 0), 4847 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d", 4848 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4849 22, CLK_IGNORE_UNUSED, 0), 4850 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b", 4851 "div_pclk_lite_b", ENABLE_ACLK_CAM01, 4852 21, CLK_IGNORE_UNUSED, 0), 4853 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b", 4854 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4855 20, CLK_IGNORE_UNUSED, 0), 4856 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a", 4857 "div_pclk_lite_a", ENABLE_ACLK_CAM01, 4858 19, CLK_IGNORE_UNUSED, 0), 4859 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a", 4860 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4861 18, CLK_IGNORE_UNUSED, 0), 4862 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p", 4863 "div_aclk_cam0_200", ENABLE_ACLK_CAM01, 4864 17, CLK_IGNORE_UNUSED, 0), 4865 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1", 4866 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4867 16, CLK_IGNORE_UNUSED, 0), 4868 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1", 4869 "div_aclk_3aa1", ENABLE_ACLK_CAM01, 4870 15, CLK_IGNORE_UNUSED, 0), 4871 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0", 4872 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4873 14, CLK_IGNORE_UNUSED, 0), 4874 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0", 4875 "div_aclk_3aa0", ENABLE_ACLK_CAM01, 4876 13, CLK_IGNORE_UNUSED, 0), 4877 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d", 4878 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4879 12, CLK_IGNORE_UNUSED, 0), 4880 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d", 4881 "div_aclk_lite_d", ENABLE_ACLK_CAM01, 4882 11, CLK_IGNORE_UNUSED, 0), 4883 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b", 4884 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4885 10, CLK_IGNORE_UNUSED, 0), 4886 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b", 4887 "div_aclk_lite_b", ENABLE_ACLK_CAM01, 4888 9, CLK_IGNORE_UNUSED, 0), 4889 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a", 4890 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01, 4891 8, CLK_IGNORE_UNUSED, 0), 4892 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a", 4893 "div_aclk_lite_a", ENABLE_ACLK_CAM01, 4894 7, CLK_IGNORE_UNUSED, 0), 4895 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp", 4896 "div_pclk_cam0_50", ENABLE_ACLK_CAM01, 4897 6, CLK_IGNORE_UNUSED, 0), 4898 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200", 4899 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0), 4900 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200", 4901 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0), 4902 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200", 4903 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0), 4904 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400", 4905 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0), 4906 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200", 4907 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0), 4908 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400", 4909 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0), 4910 4911 /* ENABLE_ACLK_CAM02 */ 4912 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400", 4913 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0), 4914 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400", 4915 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0), 4916 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400", 4917 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0), 4918 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400", 4919 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0), 4920 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400", 4921 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0), 4922 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400", 4923 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0), 4924 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400", 4925 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0), 4926 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400", 4927 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0), 4928 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400", 4929 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0), 4930 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400", 4931 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0), 4932 4933 /* ENABLE_PCLK_CAM0 */ 4934 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200", 4935 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0), 4936 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200", 4937 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0), 4938 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200", 4939 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0), 4940 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200", 4941 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0), 4942 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200", 4943 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0), 4944 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50", 4945 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0), 4946 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50", 4947 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0), 4948 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50", 4949 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0), 4950 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50", 4951 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0), 4952 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50", 4953 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0), 4954 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50", 4955 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0), 4956 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50", 4957 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0), 4958 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50", 4959 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0), 4960 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d", 4961 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4962 12, CLK_IGNORE_UNUSED, 0), 4963 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b", 4964 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4965 11, CLK_IGNORE_UNUSED, 0), 4966 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a", 4967 "div_pclk_cam0_50", ENABLE_PCLK_CAM0, 4968 10, CLK_IGNORE_UNUSED, 0), 4969 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50", 4970 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0), 4971 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50", 4972 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0), 4973 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local", 4974 "div_aclk_cam0_200", ENABLE_PCLK_CAM0, 4975 7, CLK_IGNORE_UNUSED, 0), 4976 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200", 4977 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0), 4978 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200", 4979 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0), 4980 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1", 4981 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0), 4982 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0", 4983 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0), 4984 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d", 4985 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0), 4986 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b", 4987 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0), 4988 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a", 4989 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0), 4990 4991 /* ENABLE_SCLK_CAM0 */ 4992 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4", 4993 "mout_phyclk_rxbyteclkhs0_s4_user", 4994 ENABLE_SCLK_CAM0, 8, 0, 0), 4995 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a", 4996 "mout_phyclk_rxbyteclkhs0_s2a_user", 4997 ENABLE_SCLK_CAM0, 7, 0, 0), 4998 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt", 4999 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0), 5000 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1", 5001 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0), 5002 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0", 5003 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0), 5004 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0", 5005 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0), 5006 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c", 5007 "div_sclk_pixelasync_lite_c", 5008 ENABLE_SCLK_CAM0, 2, 0, 0), 5009 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init", 5010 "div_sclk_pixelasync_lite_c_init", 5011 ENABLE_SCLK_CAM0, 1, 0, 0), 5012 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init", 5013 "div_sclk_pixelasync_lite_c", 5014 ENABLE_SCLK_CAM0, 0, 0, 0), 5015 }; 5016 5017 static const struct samsung_cmu_info cam0_cmu_info __initconst = { 5018 .mux_clks = cam0_mux_clks, 5019 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks), 5020 .div_clks = cam0_div_clks, 5021 .nr_div_clks = ARRAY_SIZE(cam0_div_clks), 5022 .gate_clks = cam0_gate_clks, 5023 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks), 5024 .fixed_clks = cam0_fixed_clks, 5025 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks), 5026 .nr_clk_ids = CAM0_NR_CLK, 5027 .clk_regs = cam0_clk_regs, 5028 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), 5029 }; 5030 5031 static void __init exynos5433_cmu_cam0_init(struct device_node *np) 5032 { 5033 samsung_cmu_register_one(np, &cam0_cmu_info); 5034 } 5035 CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0", 5036 exynos5433_cmu_cam0_init); 5037 5038 /* 5039 * Register offset definitions for CMU_CAM1 5040 */ 5041 #define MUX_SEL_CAM10 0x0200 5042 #define MUX_SEL_CAM11 0x0204 5043 #define MUX_SEL_CAM12 0x0208 5044 #define MUX_ENABLE_CAM10 0x0300 5045 #define MUX_ENABLE_CAM11 0x0304 5046 #define MUX_ENABLE_CAM12 0x0308 5047 #define MUX_STAT_CAM10 0x0400 5048 #define MUX_STAT_CAM11 0x0404 5049 #define MUX_STAT_CAM12 0x0408 5050 #define MUX_IGNORE_CAM11 0x0504 5051 #define DIV_CAM10 0x0600 5052 #define DIV_CAM11 0x0604 5053 #define DIV_STAT_CAM10 0x0700 5054 #define DIV_STAT_CAM11 0x0704 5055 #define ENABLE_ACLK_CAM10 0X0800 5056 #define ENABLE_ACLK_CAM11 0X0804 5057 #define ENABLE_ACLK_CAM12 0X0808 5058 #define ENABLE_PCLK_CAM1 0X0900 5059 #define ENABLE_SCLK_CAM1 0X0a00 5060 #define ENABLE_IP_CAM10 0X0b00 5061 #define ENABLE_IP_CAM11 0X0b04 5062 #define ENABLE_IP_CAM12 0X0b08 5063 5064 static const unsigned long cam1_clk_regs[] __initconst = { 5065 MUX_SEL_CAM10, 5066 MUX_SEL_CAM11, 5067 MUX_SEL_CAM12, 5068 MUX_ENABLE_CAM10, 5069 MUX_ENABLE_CAM11, 5070 MUX_ENABLE_CAM12, 5071 MUX_IGNORE_CAM11, 5072 DIV_CAM10, 5073 DIV_CAM11, 5074 ENABLE_ACLK_CAM10, 5075 ENABLE_ACLK_CAM11, 5076 ENABLE_ACLK_CAM12, 5077 ENABLE_PCLK_CAM1, 5078 ENABLE_SCLK_CAM1, 5079 ENABLE_IP_CAM10, 5080 ENABLE_IP_CAM11, 5081 ENABLE_IP_CAM12, 5082 }; 5083 5084 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", }; 5085 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", }; 5086 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", }; 5087 5088 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", }; 5089 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", }; 5090 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", }; 5091 5092 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk", 5093 "phyclk_rxbyteclkhs0_s2b_phy", }; 5094 5095 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a", 5096 "mout_aclk_cam1_333_user", }; 5097 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user", 5098 "mout_aclk_cam1_400_user", }; 5099 5100 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a", 5101 "mout_aclk_cam1_333_user", }; 5102 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user", 5103 "mout_aclk_cam1_400_user", }; 5104 5105 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a", 5106 "mout_aclk_cam1_333_user", }; 5107 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user", 5108 "mout_aclk_cam1_400_user", }; 5109 5110 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = { 5111 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL, 5112 0, 100000000), 5113 }; 5114 5115 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = { 5116 /* MUX_SEL_CAM10 */ 5117 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user", 5118 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1), 5119 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user", 5120 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1), 5121 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user", 5122 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1), 5123 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user", 5124 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1), 5125 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user", 5126 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1), 5127 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user", 5128 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1), 5129 5130 /* MUX_SEL_CAM11 */ 5131 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER, 5132 "mout_phyclk_rxbyteclkhs0_s2b_user", 5133 mout_phyclk_rxbyteclkhs0_s2b_user_p, 5134 MUX_SEL_CAM11, 0, 1), 5135 5136 /* MUX_SEL_CAM12 */ 5137 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p, 5138 MUX_SEL_CAM12, 20, 1), 5139 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p, 5140 MUX_SEL_CAM12, 16, 1), 5141 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p, 5142 MUX_SEL_CAM12, 12, 1), 5143 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p, 5144 MUX_SEL_CAM12, 8, 1), 5145 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p, 5146 MUX_SEL_CAM12, 4, 1), 5147 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p, 5148 MUX_SEL_CAM12, 0, 1), 5149 }; 5150 5151 static const struct samsung_div_clock cam1_div_clks[] __initconst = { 5152 /* DIV_CAM10 */ 5153 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm", 5154 "div_pclk_cam1_83", DIV_CAM10, 16, 2), 5155 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83", 5156 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2), 5157 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166", 5158 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2), 5159 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1", 5160 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3), 5161 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user", 5162 DIV_CAM10, 0, 3), 5163 5164 /* DIV_CAM11 */ 5165 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b", 5166 DIV_CAM11, 16, 3), 5167 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2), 5168 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3), 5169 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c", 5170 DIV_CAM11, 4, 2), 5171 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b", 5172 DIV_CAM11, 0, 3), 5173 }; 5174 5175 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = { 5176 /* ENABLE_ACLK_CAM10 */ 5177 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user", 5178 ENABLE_ACLK_CAM10, 4, 0, 0), 5179 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd", 5180 ENABLE_ACLK_CAM10, 3, 0, 0), 5181 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c", 5182 ENABLE_ACLK_CAM10, 1, 0, 0), 5183 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2", 5184 ENABLE_ACLK_CAM10, 0, 0, 0), 5185 5186 /* ENABLE_ACLK_CAM11 */ 5187 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd", 5188 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0), 5189 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166", 5190 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0), 5191 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c", 5192 "div_pclk_lite_c", ENABLE_ACLK_CAM11, 5193 27, CLK_IGNORE_UNUSED, 0), 5194 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c", 5195 "div_pclk_cam1_166", ENABLE_ACLK_CAM11, 5196 26, CLK_IGNORE_UNUSED, 0), 5197 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2", 5198 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5199 25, CLK_IGNORE_UNUSED, 0), 5200 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1", 5201 "div_pclk_cam1_83", ENABLE_ACLK_CAM11, 5202 24, CLK_IGNORE_UNUSED, 0), 5203 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5", 5204 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5205 23, CLK_IGNORE_UNUSED, 0), 5206 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5", 5207 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11, 5208 22, CLK_IGNORE_UNUSED, 0), 5209 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2", 5210 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5211 21, CLK_IGNORE_UNUSED, 0), 5212 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1", 5213 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5214 20, CLK_IGNORE_UNUSED, 0), 5215 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0", 5216 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5217 19, CLK_IGNORE_UNUSED, 0), 5218 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex", 5219 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5220 18, CLK_IGNORE_UNUSED, 0), 5221 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p", 5222 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5223 17, CLK_IGNORE_UNUSED, 0), 5224 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p", 5225 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5226 16, CLK_IGNORE_UNUSED, 0), 5227 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd", 5228 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5229 15, CLK_IGNORE_UNUSED, 0), 5230 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd", 5231 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0), 5232 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c", 5233 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11, 5234 13, CLK_IGNORE_UNUSED, 0), 5235 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c", 5236 "div_aclk_lite_c", ENABLE_ACLK_CAM11, 5237 12, CLK_IGNORE_UNUSED, 0), 5238 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83", 5239 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0), 5240 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83", 5241 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0), 5242 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p", 5243 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11, 5244 9, CLK_IGNORE_UNUSED, 0), 5245 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83", 5246 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0), 5247 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166", 5248 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0), 5249 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166", 5250 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0), 5251 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user", 5252 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0), 5253 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user", 5254 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0), 5255 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user", 5256 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0), 5257 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user", 5258 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0), 5259 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user", 5260 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0), 5261 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user", 5262 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0), 5263 5264 /* ENABLE_ACLK_CAM12 */ 5265 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu", 5266 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5267 10, CLK_IGNORE_UNUSED, 0), 5268 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user", 5269 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0), 5270 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c", 5271 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5272 8, CLK_IGNORE_UNUSED, 0), 5273 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user", 5274 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0), 5275 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user", 5276 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0), 5277 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user", 5278 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0), 5279 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h", 5280 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5281 4, CLK_IGNORE_UNUSED, 0), 5282 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p", 5283 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12, 5284 3, CLK_IGNORE_UNUSED, 0), 5285 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p", 5286 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5287 2, CLK_IGNORE_UNUSED, 0), 5288 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user", 5289 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0), 5290 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c", 5291 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12, 5292 0, CLK_IGNORE_UNUSED, 0), 5293 5294 /* ENABLE_PCLK_CAM1 */ 5295 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166", 5296 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0), 5297 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166", 5298 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0), 5299 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166", 5300 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0), 5301 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83", 5302 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0), 5303 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83", 5304 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0), 5305 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83", 5306 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0), 5307 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166", 5308 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0), 5309 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex", 5310 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5311 20, CLK_IGNORE_UNUSED, 0), 5312 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p", 5313 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5314 19, CLK_IGNORE_UNUSED, 0), 5315 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83", 5316 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0), 5317 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c", 5318 "div_pclk_cam1_83", ENABLE_PCLK_CAM1, 5319 17, CLK_IGNORE_UNUSED, 0), 5320 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83", 5321 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0), 5322 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83", 5323 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0), 5324 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local", 5325 "div_pclk_cam1_166", ENABLE_PCLK_CAM1, 5326 14, CLK_IGNORE_UNUSED, 0), 5327 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83", 5328 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0), 5329 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83", 5330 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0), 5331 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83", 5332 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0), 5333 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83", 5334 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0), 5335 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83", 5336 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0), 5337 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83", 5338 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0), 5339 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83", 5340 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0), 5341 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83", 5342 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0), 5343 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83", 5344 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0), 5345 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83", 5346 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0), 5347 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83", 5348 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5349 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd", 5350 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0), 5351 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c", 5352 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0), 5353 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166", 5354 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0), 5355 5356 /* ENABLE_SCLK_CAM1 */ 5357 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1, 5358 15, 0, 0), 5359 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1, 5360 14, 0, 0), 5361 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1, 5362 13, 0, 0), 5363 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1, 5364 12, 0, 0), 5365 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b", 5366 "mout_phyclk_rxbyteclkhs0_s2b_user", 5367 ENABLE_SCLK_CAM1, 11, 0, 0), 5368 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c", 5369 ENABLE_SCLK_CAM1, 10, 0, 0), 5370 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd", 5371 ENABLE_SCLK_CAM1, 9, 0, 0), 5372 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1", 5373 ENABLE_SCLK_CAM1, 7, 0, 0), 5374 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user", 5375 ENABLE_SCLK_CAM1, 6, 0, 0), 5376 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user", 5377 ENABLE_SCLK_CAM1, 5, 0, 0), 5378 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user", 5379 ENABLE_SCLK_CAM1, 4, 0, 0), 5380 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm", 5381 ENABLE_SCLK_CAM1, 3, 0, 0), 5382 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1", 5383 ENABLE_SCLK_CAM1, 2, 0, 0), 5384 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1", 5385 ENABLE_SCLK_CAM1, 1, 0, 0), 5386 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user", 5387 ENABLE_SCLK_CAM1, 0, 0, 0), 5388 }; 5389 5390 static const struct samsung_cmu_info cam1_cmu_info __initconst = { 5391 .mux_clks = cam1_mux_clks, 5392 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks), 5393 .div_clks = cam1_div_clks, 5394 .nr_div_clks = ARRAY_SIZE(cam1_div_clks), 5395 .gate_clks = cam1_gate_clks, 5396 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks), 5397 .fixed_clks = cam1_fixed_clks, 5398 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks), 5399 .nr_clk_ids = CAM1_NR_CLK, 5400 .clk_regs = cam1_clk_regs, 5401 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), 5402 }; 5403 5404 static void __init exynos5433_cmu_cam1_init(struct device_node *np) 5405 { 5406 samsung_cmu_register_one(np, &cam1_cmu_info); 5407 } 5408 CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1", 5409 exynos5433_cmu_cam1_init); 5410