1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Authors: Thomas Abraham <thomas.ab@samsung.com> 4 * Chander Kashyap <k.chander@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5420 SoC. 11 */ 12 13 #include <dt-bindings/clock/exynos5420.h> 14 #include <linux/clk.h> 15 #include <linux/clkdev.h> 16 #include <linux/clk-provider.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 20 #include "clk.h" 21 22 #define APLL_LOCK 0x0 23 #define APLL_CON0 0x100 24 #define SRC_CPU 0x200 25 #define DIV_CPU0 0x500 26 #define DIV_CPU1 0x504 27 #define GATE_BUS_CPU 0x700 28 #define GATE_SCLK_CPU 0x800 29 #define CPLL_LOCK 0x10020 30 #define DPLL_LOCK 0x10030 31 #define EPLL_LOCK 0x10040 32 #define RPLL_LOCK 0x10050 33 #define IPLL_LOCK 0x10060 34 #define SPLL_LOCK 0x10070 35 #define VPLL_LOCK 0x10070 36 #define MPLL_LOCK 0x10090 37 #define CPLL_CON0 0x10120 38 #define DPLL_CON0 0x10128 39 #define EPLL_CON0 0x10130 40 #define RPLL_CON0 0x10140 41 #define IPLL_CON0 0x10150 42 #define SPLL_CON0 0x10160 43 #define VPLL_CON0 0x10170 44 #define MPLL_CON0 0x10180 45 #define SRC_TOP0 0x10200 46 #define SRC_TOP1 0x10204 47 #define SRC_TOP2 0x10208 48 #define SRC_TOP3 0x1020c 49 #define SRC_TOP4 0x10210 50 #define SRC_TOP5 0x10214 51 #define SRC_TOP6 0x10218 52 #define SRC_TOP7 0x1021c 53 #define SRC_DISP10 0x1022c 54 #define SRC_MAU 0x10240 55 #define SRC_FSYS 0x10244 56 #define SRC_PERIC0 0x10250 57 #define SRC_PERIC1 0x10254 58 #define SRC_TOP10 0x10280 59 #define SRC_TOP11 0x10284 60 #define SRC_TOP12 0x10288 61 #define SRC_MASK_DISP10 0x1032c 62 #define SRC_MASK_FSYS 0x10340 63 #define SRC_MASK_PERIC0 0x10350 64 #define SRC_MASK_PERIC1 0x10354 65 #define DIV_TOP0 0x10500 66 #define DIV_TOP1 0x10504 67 #define DIV_TOP2 0x10508 68 #define DIV_DISP10 0x1052c 69 #define DIV_MAU 0x10544 70 #define DIV_FSYS0 0x10548 71 #define DIV_FSYS1 0x1054c 72 #define DIV_FSYS2 0x10550 73 #define DIV_PERIC0 0x10558 74 #define DIV_PERIC1 0x1055c 75 #define DIV_PERIC2 0x10560 76 #define DIV_PERIC3 0x10564 77 #define DIV_PERIC4 0x10568 78 #define GATE_BUS_TOP 0x10700 79 #define GATE_BUS_FSYS0 0x10740 80 #define GATE_BUS_PERIC 0x10750 81 #define GATE_BUS_PERIC1 0x10754 82 #define GATE_BUS_PERIS0 0x10760 83 #define GATE_BUS_PERIS1 0x10764 84 #define GATE_IP_GSCL0 0x10910 85 #define GATE_IP_GSCL1 0x10920 86 #define GATE_IP_MFC 0x1092c 87 #define GATE_IP_DISP1 0x10928 88 #define GATE_IP_G3D 0x10930 89 #define GATE_IP_GEN 0x10934 90 #define GATE_IP_MSCL 0x10970 91 #define GATE_TOP_SCLK_GSCL 0x10820 92 #define GATE_TOP_SCLK_DISP1 0x10828 93 #define GATE_TOP_SCLK_MAU 0x1083c 94 #define GATE_TOP_SCLK_FSYS 0x10840 95 #define GATE_TOP_SCLK_PERIC 0x10850 96 #define BPLL_LOCK 0x20010 97 #define BPLL_CON0 0x20110 98 #define SRC_CDREX 0x20200 99 #define KPLL_LOCK 0x28000 100 #define KPLL_CON0 0x28100 101 #define SRC_KFC 0x28200 102 #define DIV_KFC0 0x28500 103 104 /* list of PLLs */ 105 enum exynos5420_plls { 106 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 107 bpll, kpll, 108 nr_plls /* number of PLLs */ 109 }; 110 111 /* 112 * list of controller registers to be saved and restored during a 113 * suspend/resume cycle. 114 */ 115 static unsigned long exynos5420_clk_regs[] __initdata = { 116 SRC_CPU, 117 DIV_CPU0, 118 DIV_CPU1, 119 GATE_BUS_CPU, 120 GATE_SCLK_CPU, 121 SRC_TOP0, 122 SRC_TOP1, 123 SRC_TOP2, 124 SRC_TOP3, 125 SRC_TOP4, 126 SRC_TOP5, 127 SRC_TOP6, 128 SRC_TOP7, 129 SRC_DISP10, 130 SRC_MAU, 131 SRC_FSYS, 132 SRC_PERIC0, 133 SRC_PERIC1, 134 SRC_TOP10, 135 SRC_TOP11, 136 SRC_TOP12, 137 SRC_MASK_DISP10, 138 SRC_MASK_FSYS, 139 SRC_MASK_PERIC0, 140 SRC_MASK_PERIC1, 141 DIV_TOP0, 142 DIV_TOP1, 143 DIV_TOP2, 144 DIV_DISP10, 145 DIV_MAU, 146 DIV_FSYS0, 147 DIV_FSYS1, 148 DIV_FSYS2, 149 DIV_PERIC0, 150 DIV_PERIC1, 151 DIV_PERIC2, 152 DIV_PERIC3, 153 DIV_PERIC4, 154 GATE_BUS_TOP, 155 GATE_BUS_FSYS0, 156 GATE_BUS_PERIC, 157 GATE_BUS_PERIC1, 158 GATE_BUS_PERIS0, 159 GATE_BUS_PERIS1, 160 GATE_IP_GSCL0, 161 GATE_IP_GSCL1, 162 GATE_IP_MFC, 163 GATE_IP_DISP1, 164 GATE_IP_G3D, 165 GATE_IP_GEN, 166 GATE_IP_MSCL, 167 GATE_TOP_SCLK_GSCL, 168 GATE_TOP_SCLK_DISP1, 169 GATE_TOP_SCLK_MAU, 170 GATE_TOP_SCLK_FSYS, 171 GATE_TOP_SCLK_PERIC, 172 SRC_CDREX, 173 SRC_KFC, 174 DIV_KFC0, 175 }; 176 177 /* list of all parent clocks */ 178 PNAME(mspll_cpu_p) = { "sclk_cpll", "sclk_dpll", 179 "sclk_mpll", "sclk_spll" }; 180 PNAME(cpu_p) = { "mout_apll" , "mout_mspll_cpu" }; 181 PNAME(kfc_p) = { "mout_kpll" , "mout_mspll_kfc" }; 182 PNAME(apll_p) = { "fin_pll", "fout_apll", }; 183 PNAME(bpll_p) = { "fin_pll", "fout_bpll", }; 184 PNAME(cpll_p) = { "fin_pll", "fout_cpll", }; 185 PNAME(dpll_p) = { "fin_pll", "fout_dpll", }; 186 PNAME(epll_p) = { "fin_pll", "fout_epll", }; 187 PNAME(ipll_p) = { "fin_pll", "fout_ipll", }; 188 PNAME(kpll_p) = { "fin_pll", "fout_kpll", }; 189 PNAME(mpll_p) = { "fin_pll", "fout_mpll", }; 190 PNAME(rpll_p) = { "fin_pll", "fout_rpll", }; 191 PNAME(spll_p) = { "fin_pll", "fout_spll", }; 192 PNAME(vpll_p) = { "fin_pll", "fout_vpll", }; 193 194 PNAME(group1_p) = { "sclk_cpll", "sclk_dpll", "sclk_mpll" }; 195 PNAME(group2_p) = { "fin_pll", "sclk_cpll", "sclk_dpll", "sclk_mpll", 196 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 197 PNAME(group3_p) = { "sclk_rpll", "sclk_spll" }; 198 PNAME(group4_p) = { "sclk_ipll", "sclk_dpll", "sclk_mpll" }; 199 PNAME(group5_p) = { "sclk_vpll", "sclk_dpll" }; 200 201 PNAME(sw_aclk66_p) = { "dout_aclk66", "sclk_spll" }; 202 PNAME(aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66" }; 203 204 PNAME(sw_aclk200_fsys_p) = { "dout_aclk200_fsys", "sclk_spll"}; 205 PNAME(user_aclk200_fsys_p) = { "fin_pll", "mout_sw_aclk200_fsys" }; 206 207 PNAME(sw_aclk200_fsys2_p) = { "dout_aclk200_fsys2", "sclk_spll"}; 208 PNAME(user_aclk200_fsys2_p) = { "fin_pll", "mout_sw_aclk200_fsys2" }; 209 210 PNAME(sw_aclk200_p) = { "dout_aclk200", "sclk_spll"}; 211 PNAME(aclk200_disp1_p) = { "fin_pll", "mout_sw_aclk200" }; 212 213 PNAME(sw_aclk400_mscl_p) = { "dout_aclk400_mscl", "sclk_spll"}; 214 PNAME(user_aclk400_mscl_p) = { "fin_pll", "mout_sw_aclk400_mscl" }; 215 216 PNAME(sw_aclk333_p) = { "dout_aclk333", "sclk_spll"}; 217 PNAME(user_aclk333_p) = { "fin_pll", "mout_sw_aclk333" }; 218 219 PNAME(sw_aclk166_p) = { "dout_aclk166", "sclk_spll"}; 220 PNAME(user_aclk166_p) = { "fin_pll", "mout_sw_aclk166" }; 221 222 PNAME(sw_aclk266_p) = { "dout_aclk266", "sclk_spll"}; 223 PNAME(user_aclk266_p) = { "fin_pll", "mout_sw_aclk266" }; 224 225 PNAME(sw_aclk333_432_gscl_p) = { "dout_aclk333_432_gscl", "sclk_spll"}; 226 PNAME(user_aclk333_432_gscl_p) = { "fin_pll", "mout_sw_aclk333_432_gscl" }; 227 228 PNAME(sw_aclk300_gscl_p) = { "dout_aclk300_gscl", "sclk_spll"}; 229 PNAME(user_aclk300_gscl_p) = { "fin_pll", "mout_sw_aclk300_gscl" }; 230 231 PNAME(sw_aclk300_disp1_p) = { "dout_aclk300_disp1", "sclk_spll"}; 232 PNAME(user_aclk300_disp1_p) = { "fin_pll", "mout_sw_aclk300_disp1" }; 233 234 PNAME(sw_aclk300_jpeg_p) = { "dout_aclk300_jpeg", "sclk_spll"}; 235 PNAME(user_aclk300_jpeg_p) = { "fin_pll", "mout_sw_aclk300_jpeg" }; 236 237 PNAME(sw_aclk_g3d_p) = { "dout_aclk_g3d", "sclk_spll"}; 238 PNAME(user_aclk_g3d_p) = { "fin_pll", "mout_sw_aclk_g3d" }; 239 240 PNAME(sw_aclk266_g2d_p) = { "dout_aclk266_g2d", "sclk_spll"}; 241 PNAME(user_aclk266_g2d_p) = { "fin_pll", "mout_sw_aclk266_g2d" }; 242 243 PNAME(sw_aclk333_g2d_p) = { "dout_aclk333_g2d", "sclk_spll"}; 244 PNAME(user_aclk333_g2d_p) = { "fin_pll", "mout_sw_aclk333_g2d" }; 245 246 PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll", 247 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 248 PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll", 249 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 250 PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", 251 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 252 PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", 253 "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 254 PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; 255 PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", 256 "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; 257 258 /* fixed rate clocks generated outside the soc */ 259 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { 260 FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), 261 }; 262 263 /* fixed rate clocks generated inside the soc */ 264 static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { 265 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), 266 FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), 267 FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), 268 FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), 269 FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), 270 }; 271 272 static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { 273 FFACTOR(0, "sclk_hsic_12m", "fin_pll", 1, 2, 0), 274 }; 275 276 static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 277 MUX(0, "mout_mspll_kfc", mspll_cpu_p, SRC_TOP7, 8, 2), 278 MUX(0, "mout_mspll_cpu", mspll_cpu_p, SRC_TOP7, 12, 2), 279 MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1), 280 MUX(0, "mout_cpu", cpu_p, SRC_CPU, 16, 1), 281 MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1), 282 MUX(0, "mout_cpu_kfc", kfc_p, SRC_KFC, 16, 1), 283 284 MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1), 285 286 MUX_A(0, "mout_aclk400_mscl", group1_p, 287 SRC_TOP0, 4, 2, "aclk400_mscl"), 288 MUX(0, "mout_aclk200", group1_p, SRC_TOP0, 8, 2), 289 MUX(0, "mout_aclk200_fsys2", group1_p, SRC_TOP0, 12, 2), 290 MUX(0, "mout_aclk200_fsys", group1_p, SRC_TOP0, 28, 2), 291 292 MUX(0, "mout_aclk333_432_gscl", group4_p, SRC_TOP1, 0, 2), 293 MUX(0, "mout_aclk66", group1_p, SRC_TOP1, 8, 2), 294 MUX(0, "mout_aclk266", group1_p, SRC_TOP1, 20, 2), 295 MUX(0, "mout_aclk166", group1_p, SRC_TOP1, 24, 2), 296 MUX(0, "mout_aclk333", group1_p, SRC_TOP1, 28, 2), 297 298 MUX(0, "mout_aclk333_g2d", group1_p, SRC_TOP2, 8, 2), 299 MUX(0, "mout_aclk266_g2d", group1_p, SRC_TOP2, 12, 2), 300 MUX(0, "mout_aclk_g3d", group5_p, SRC_TOP2, 16, 1), 301 MUX(0, "mout_aclk300_jpeg", group1_p, SRC_TOP2, 20, 2), 302 MUX(0, "mout_aclk300_disp1", group1_p, SRC_TOP2, 24, 2), 303 MUX(0, "mout_aclk300_gscl", group1_p, SRC_TOP2, 28, 2), 304 305 MUX(0, "mout_user_aclk400_mscl", user_aclk400_mscl_p, 306 SRC_TOP3, 4, 1), 307 MUX_A(0, "mout_aclk200_disp1", aclk200_disp1_p, 308 SRC_TOP3, 8, 1, "aclk200_disp1"), 309 MUX(0, "mout_user_aclk200_fsys2", user_aclk200_fsys2_p, 310 SRC_TOP3, 12, 1), 311 MUX(0, "mout_user_aclk200_fsys", user_aclk200_fsys_p, 312 SRC_TOP3, 28, 1), 313 314 MUX(0, "mout_user_aclk333_432_gscl", user_aclk333_432_gscl_p, 315 SRC_TOP4, 0, 1), 316 MUX(0, "mout_aclk66_peric", aclk66_peric_p, SRC_TOP4, 8, 1), 317 MUX(0, "mout_user_aclk266", user_aclk266_p, SRC_TOP4, 20, 1), 318 MUX(0, "mout_user_aclk166", user_aclk166_p, SRC_TOP4, 24, 1), 319 MUX(0, "mout_user_aclk333", user_aclk333_p, SRC_TOP4, 28, 1), 320 321 MUX(0, "mout_aclk66_psgen", aclk66_peric_p, SRC_TOP5, 4, 1), 322 MUX(0, "mout_user_aclk333_g2d", user_aclk333_g2d_p, SRC_TOP5, 8, 1), 323 MUX(0, "mout_user_aclk266_g2d", user_aclk266_g2d_p, SRC_TOP5, 12, 1), 324 MUX_A(0, "mout_user_aclk_g3d", user_aclk_g3d_p, 325 SRC_TOP5, 16, 1, "aclkg3d"), 326 MUX(0, "mout_user_aclk300_jpeg", user_aclk300_jpeg_p, 327 SRC_TOP5, 20, 1), 328 MUX(0, "mout_user_aclk300_disp1", user_aclk300_disp1_p, 329 SRC_TOP5, 24, 1), 330 MUX(0, "mout_user_aclk300_gscl", user_aclk300_gscl_p, 331 SRC_TOP5, 28, 1), 332 333 MUX(0, "sclk_mpll", mpll_p, SRC_TOP6, 0, 1), 334 MUX(0, "sclk_vpll", vpll_p, SRC_TOP6, 4, 1), 335 MUX(0, "sclk_spll", spll_p, SRC_TOP6, 8, 1), 336 MUX(0, "sclk_ipll", ipll_p, SRC_TOP6, 12, 1), 337 MUX(0, "sclk_rpll", rpll_p, SRC_TOP6, 16, 1), 338 MUX(0, "sclk_epll", epll_p, SRC_TOP6, 20, 1), 339 MUX(0, "sclk_dpll", dpll_p, SRC_TOP6, 24, 1), 340 MUX(0, "sclk_cpll", cpll_p, SRC_TOP6, 28, 1), 341 342 MUX(0, "mout_sw_aclk400_mscl", sw_aclk400_mscl_p, SRC_TOP10, 4, 1), 343 MUX(0, "mout_sw_aclk200", sw_aclk200_p, SRC_TOP10, 8, 1), 344 MUX(0, "mout_sw_aclk200_fsys2", sw_aclk200_fsys2_p, 345 SRC_TOP10, 12, 1), 346 MUX(0, "mout_sw_aclk200_fsys", sw_aclk200_fsys_p, SRC_TOP10, 28, 1), 347 348 MUX(0, "mout_sw_aclk333_432_gscl", sw_aclk333_432_gscl_p, 349 SRC_TOP11, 0, 1), 350 MUX(0, "mout_sw_aclk66", sw_aclk66_p, SRC_TOP11, 8, 1), 351 MUX(0, "mout_sw_aclk266", sw_aclk266_p, SRC_TOP11, 20, 1), 352 MUX(0, "mout_sw_aclk166", sw_aclk166_p, SRC_TOP11, 24, 1), 353 MUX(0, "mout_sw_aclk333", sw_aclk333_p, SRC_TOP11, 28, 1), 354 355 MUX(0, "mout_sw_aclk333_g2d", sw_aclk333_g2d_p, SRC_TOP12, 8, 1), 356 MUX(0, "mout_sw_aclk266_g2d", sw_aclk266_g2d_p, SRC_TOP12, 12, 1), 357 MUX(0, "mout_sw_aclk_g3d", sw_aclk_g3d_p, SRC_TOP12, 16, 1), 358 MUX(0, "mout_sw_aclk300_jpeg", sw_aclk300_jpeg_p, SRC_TOP12, 20, 1), 359 MUX(0, "mout_sw_aclk300_disp1", sw_aclk300_disp1_p, 360 SRC_TOP12, 24, 1), 361 MUX(0, "mout_sw_aclk300_gscl", sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 362 363 /* DISP1 Block */ 364 MUX(0, "mout_fimd1", group3_p, SRC_DISP10, 4, 1), 365 MUX(0, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), 366 MUX(0, "mout_dp1", group2_p, SRC_DISP10, 20, 3), 367 MUX(0, "mout_pixel", group2_p, SRC_DISP10, 24, 3), 368 MUX(CLK_MOUT_HDMI, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), 369 370 /* MAU Block */ 371 MUX(0, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3), 372 373 /* FSYS Block */ 374 MUX(0, "mout_usbd301", group2_p, SRC_FSYS, 4, 3), 375 MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 8, 3), 376 MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 12, 3), 377 MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 16, 3), 378 MUX(0, "mout_usbd300", group2_p, SRC_FSYS, 20, 3), 379 MUX(0, "mout_unipro", group2_p, SRC_FSYS, 24, 3), 380 381 /* PERIC Block */ 382 MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 4, 3), 383 MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 8, 3), 384 MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 12, 3), 385 MUX(0, "mout_uart3", group2_p, SRC_PERIC0, 16, 3), 386 MUX(0, "mout_pwm", group2_p, SRC_PERIC0, 24, 3), 387 MUX(0, "mout_spdif", spdif_p, SRC_PERIC0, 28, 3), 388 MUX(0, "mout_audio0", audio0_p, SRC_PERIC1, 8, 3), 389 MUX(0, "mout_audio1", audio1_p, SRC_PERIC1, 12, 3), 390 MUX(0, "mout_audio2", audio2_p, SRC_PERIC1, 16, 3), 391 MUX(0, "mout_spi0", group2_p, SRC_PERIC1, 20, 3), 392 MUX(0, "mout_spi1", group2_p, SRC_PERIC1, 24, 3), 393 MUX(0, "mout_spi2", group2_p, SRC_PERIC1, 28, 3), 394 }; 395 396 static struct samsung_div_clock exynos5420_div_clks[] __initdata = { 397 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 398 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 399 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 400 DIV(0, "div_kfc", "mout_cpu_kfc", DIV_KFC0, 0, 3), 401 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 402 403 DIV(0, "dout_aclk400_mscl", "mout_aclk400_mscl", DIV_TOP0, 4, 3), 404 DIV(0, "dout_aclk200", "mout_aclk200", DIV_TOP0, 8, 3), 405 DIV(0, "dout_aclk200_fsys2", "mout_aclk200_fsys2", DIV_TOP0, 12, 3), 406 DIV(0, "dout_pclk200_fsys", "mout_pclk200_fsys", DIV_TOP0, 24, 3), 407 DIV(0, "dout_aclk200_fsys", "mout_aclk200_fsys", DIV_TOP0, 28, 3), 408 409 DIV(0, "dout_aclk333_432_gscl", "mout_aclk333_432_gscl", 410 DIV_TOP1, 0, 3), 411 DIV(0, "dout_aclk66", "mout_aclk66", DIV_TOP1, 8, 6), 412 DIV(0, "dout_aclk266", "mout_aclk266", DIV_TOP1, 20, 3), 413 DIV(0, "dout_aclk166", "mout_aclk166", DIV_TOP1, 24, 3), 414 DIV(0, "dout_aclk333", "mout_aclk333", DIV_TOP1, 28, 3), 415 416 DIV(0, "dout_aclk333_g2d", "mout_aclk333_g2d", DIV_TOP2, 8, 3), 417 DIV(0, "dout_aclk266_g2d", "mout_aclk266_g2d", DIV_TOP2, 12, 3), 418 DIV(0, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 16, 3), 419 DIV(0, "dout_aclk300_jpeg", "mout_aclk300_jpeg", DIV_TOP2, 20, 3), 420 DIV_A(0, "dout_aclk300_disp1", "mout_aclk300_disp1", 421 DIV_TOP2, 24, 3, "aclk300_disp1"), 422 DIV(0, "dout_aclk300_gscl", "mout_aclk300_gscl", DIV_TOP2, 28, 3), 423 424 /* DISP1 Block */ 425 DIV(0, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), 426 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 427 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 428 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 429 430 /* Audio Block */ 431 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 432 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 433 434 /* USB3.0 */ 435 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 436 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 437 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 438 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 439 440 /* MMC */ 441 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 442 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 443 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 444 445 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 446 447 /* UART and PWM */ 448 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 449 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 450 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 451 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 452 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 453 454 /* SPI */ 455 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 456 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 457 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 458 459 /* PCM */ 460 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 461 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 462 463 /* Audio - I2S */ 464 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 465 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 466 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 467 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 468 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 469 470 /* SPI Pre-Ratio */ 471 DIV(0, "dout_pre_spi0", "dout_spi0", DIV_PERIC4, 8, 8), 472 DIV(0, "dout_pre_spi1", "dout_spi1", DIV_PERIC4, 16, 8), 473 DIV(0, "dout_pre_spi2", "dout_spi2", DIV_PERIC4, 24, 8), 474 }; 475 476 static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { 477 /* TODO: Re-verify the CG bits for all the gate clocks */ 478 GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, 479 "mct"), 480 481 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 482 GATE_BUS_FSYS0, 9, CLK_IGNORE_UNUSED, 0), 483 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 484 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 485 486 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 487 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 488 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 489 GATE_BUS_TOP, 1, CLK_IGNORE_UNUSED, 0), 490 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 491 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 492 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 493 GATE_BUS_TOP, 6, CLK_IGNORE_UNUSED, 0), 494 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 495 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 496 GATE(0, "pclk66_gpio", "mout_sw_aclk66", 497 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 498 GATE(0, "aclk66_psgen", "mout_aclk66_psgen", 499 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 500 GATE(0, "aclk66_peric", "mout_aclk66_peric", 501 GATE_BUS_TOP, 11, 0, 0), 502 GATE(0, "aclk166", "mout_user_aclk166", 503 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 504 GATE(0, "aclk333", "mout_aclk333", 505 GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), 506 507 /* sclk */ 508 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 509 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 510 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 511 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 512 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 513 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 514 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 515 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 516 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_pre_spi0", 517 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 518 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_pre_spi1", 519 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 520 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_pre_spi2", 521 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 522 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 523 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 524 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 525 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 526 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 527 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 528 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 529 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 530 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 531 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 532 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 533 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 534 535 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 536 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 537 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 538 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 539 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 540 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 541 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 542 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 543 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 544 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 545 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 546 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 547 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 548 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 549 550 GATE(CLK_SCLK_USBD301, "sclk_unipro", "dout_unipro", 551 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 552 553 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "aclK333_432_gscl", 554 GATE_TOP_SCLK_GSCL, 6, CLK_SET_RATE_PARENT, 0), 555 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "aclk333_432_gscl", 556 GATE_TOP_SCLK_GSCL, 7, CLK_SET_RATE_PARENT, 0), 557 558 /* Display */ 559 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 560 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 561 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 562 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 563 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 564 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), 565 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 566 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 567 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 568 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 569 570 /* Maudio Block */ 571 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 572 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 573 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 574 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 575 /* FSYS */ 576 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 577 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 578 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 579 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 580 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_BUS_FSYS0, 5, 0, 0), 581 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_BUS_FSYS0, 12, 0, 0), 582 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_BUS_FSYS0, 13, 0, 0), 583 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_BUS_FSYS0, 14, 0, 0), 584 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 585 GATE_BUS_FSYS0, 19, CLK_IGNORE_UNUSED, 0), 586 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_BUS_FSYS0, 20, 0, 0), 587 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_BUS_FSYS0, 21, 0, 0), 588 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_BUS_FSYS0, 28, 0, 0), 589 590 /* UART */ 591 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_BUS_PERIC, 4, 0, 0), 592 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_BUS_PERIC, 5, 0, 0), 593 GATE_A(CLK_UART2, "uart2", "aclk66_peric", 594 GATE_BUS_PERIC, 6, CLK_IGNORE_UNUSED, 0, "uart2"), 595 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_BUS_PERIC, 7, 0, 0), 596 /* I2C */ 597 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_BUS_PERIC, 9, 0, 0), 598 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_BUS_PERIC, 10, 0, 0), 599 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_BUS_PERIC, 11, 0, 0), 600 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_BUS_PERIC, 12, 0, 0), 601 GATE(CLK_I2C4, "i2c4", "aclk66_peric", GATE_BUS_PERIC, 13, 0, 0), 602 GATE(CLK_I2C5, "i2c5", "aclk66_peric", GATE_BUS_PERIC, 14, 0, 0), 603 GATE(CLK_I2C6, "i2c6", "aclk66_peric", GATE_BUS_PERIC, 15, 0, 0), 604 GATE(CLK_I2C7, "i2c7", "aclk66_peric", GATE_BUS_PERIC, 16, 0, 0), 605 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_BUS_PERIC, 17, 0, 606 0), 607 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_BUS_PERIC, 18, 0, 0), 608 /* SPI */ 609 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_BUS_PERIC, 19, 0, 0), 610 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_BUS_PERIC, 20, 0, 0), 611 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_BUS_PERIC, 21, 0, 0), 612 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 613 /* I2S */ 614 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_BUS_PERIC, 23, 0, 0), 615 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_BUS_PERIC, 24, 0, 0), 616 /* PCM */ 617 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_BUS_PERIC, 25, 0, 0), 618 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_BUS_PERIC, 26, 0, 0), 619 /* PWM */ 620 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_BUS_PERIC, 27, 0, 0), 621 /* SPDIF */ 622 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_BUS_PERIC, 29, 0, 0), 623 624 GATE(CLK_I2C8, "i2c8", "aclk66_peric", GATE_BUS_PERIC1, 0, 0, 0), 625 GATE(CLK_I2C9, "i2c9", "aclk66_peric", GATE_BUS_PERIC1, 1, 0, 0), 626 GATE(CLK_I2C10, "i2c10", "aclk66_peric", GATE_BUS_PERIC1, 2, 0, 0), 627 628 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 629 GATE_BUS_PERIS0, 12, CLK_IGNORE_UNUSED, 0), 630 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 631 GATE_BUS_PERIS0, 13, CLK_IGNORE_UNUSED, 0), 632 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_BUS_PERIS0, 18, 0, 0), 633 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_BUS_PERIS0, 19, 0, 0), 634 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_BUS_PERIS0, 20, 0, 0), 635 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_BUS_PERIS0, 21, 0, 0), 636 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_BUS_PERIS0, 22, 0, 0), 637 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_BUS_PERIS0, 23, 0, 0), 638 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_BUS_PERIS0, 24, 0, 0), 639 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_BUS_PERIS0, 25, 0, 0), 640 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_BUS_PERIS0, 26, 0, 0), 641 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_BUS_PERIS0, 27, 0, 0), 642 643 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_BUS_PERIS1, 0, 0, 644 0), 645 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 646 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_BUS_PERIS1, 3, 0, 0), 647 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_BUS_PERIS1, 4, 0, 0), 648 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_BUS_PERIS1, 5, 0, 0), 649 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_BUS_PERIS1, 6, 0, 0), 650 651 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 652 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 653 GATE(CLK_CLK_3AA, "clk_3aa", "aclk300_gscl", GATE_IP_GSCL0, 4, 0, 0), 654 655 GATE(CLK_SMMU_3AA, "smmu_3aa", "aclk333_432_gscl", GATE_IP_GSCL1, 2, 0, 656 0), 657 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "aclk333_432_gscl", 658 GATE_IP_GSCL1, 3, 0, 0), 659 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "aclk333_432_gscl", 660 GATE_IP_GSCL1, 4, 0, 0), 661 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "aclk300_gscl", GATE_IP_GSCL1, 6, 0, 662 0), 663 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "aclk300_gscl", GATE_IP_GSCL1, 7, 0, 664 0), 665 GATE(CLK_GSCL_WA, "gscl_wa", "aclk300_gscl", GATE_IP_GSCL1, 12, 0, 0), 666 GATE(CLK_GSCL_WB, "gscl_wb", "aclk300_gscl", GATE_IP_GSCL1, 13, 0, 0), 667 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "aclk333_432_gscl", 668 GATE_IP_GSCL1, 16, 0, 0), 669 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 670 GATE_IP_GSCL1, 17, 0, 0), 671 672 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 673 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 674 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 675 GATE(CLK_MIXER, "mixer", "aclk166", GATE_IP_DISP1, 5, 0, 0), 676 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 677 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk300_disp1", GATE_IP_DISP1, 8, 0, 678 0), 679 680 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 681 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), 682 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), 683 684 GATE(CLK_G3D, "g3d", "aclkg3d", GATE_IP_G3D, 9, 0, 0), 685 686 GATE(CLK_ROTATOR, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), 687 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 688 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 689 GATE(CLK_MDMA1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), 690 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk266", GATE_IP_GEN, 6, 0, 0), 691 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk300_jpeg", GATE_IP_GEN, 7, 0, 0), 692 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "aclk266", GATE_IP_GEN, 9, 0, 0), 693 694 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 695 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 696 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 697 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 698 0), 699 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 700 0), 701 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 702 0), 703 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 704 0), 705 }; 706 707 static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = { 708 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 709 APLL_CON0, NULL), 710 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 711 CPLL_CON0, NULL), 712 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 713 DPLL_CON0, NULL), 714 [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 715 EPLL_CON0, NULL), 716 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 717 RPLL_CON0, NULL), 718 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 719 IPLL_CON0, NULL), 720 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 721 SPLL_CON0, NULL), 722 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 723 VPLL_CON0, NULL), 724 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 725 MPLL_CON0, NULL), 726 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 727 BPLL_CON0, NULL), 728 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 729 KPLL_CON0, NULL), 730 }; 731 732 static struct of_device_id ext_clk_match[] __initdata = { 733 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 734 { }, 735 }; 736 737 /* register exynos5420 clocks */ 738 static void __init exynos5420_clk_init(struct device_node *np) 739 { 740 void __iomem *reg_base; 741 742 if (np) { 743 reg_base = of_iomap(np, 0); 744 if (!reg_base) 745 panic("%s: failed to map registers\n", __func__); 746 } else { 747 panic("%s: unable to determine soc\n", __func__); 748 } 749 750 samsung_clk_init(np, reg_base, CLK_NR_CLKS, 751 exynos5420_clk_regs, ARRAY_SIZE(exynos5420_clk_regs), 752 NULL, 0); 753 samsung_clk_of_register_fixed_ext(exynos5420_fixed_rate_ext_clks, 754 ARRAY_SIZE(exynos5420_fixed_rate_ext_clks), 755 ext_clk_match); 756 samsung_clk_register_pll(exynos5420_plls, ARRAY_SIZE(exynos5420_plls), 757 reg_base); 758 samsung_clk_register_fixed_rate(exynos5420_fixed_rate_clks, 759 ARRAY_SIZE(exynos5420_fixed_rate_clks)); 760 samsung_clk_register_fixed_factor(exynos5420_fixed_factor_clks, 761 ARRAY_SIZE(exynos5420_fixed_factor_clks)); 762 samsung_clk_register_mux(exynos5420_mux_clks, 763 ARRAY_SIZE(exynos5420_mux_clks)); 764 samsung_clk_register_div(exynos5420_div_clks, 765 ARRAY_SIZE(exynos5420_div_clks)); 766 samsung_clk_register_gate(exynos5420_gate_clks, 767 ARRAY_SIZE(exynos5420_gate_clks)); 768 } 769 CLK_OF_DECLARE(exynos5420_clk, "samsung,exynos5420-clock", exynos5420_clk_init); 770