1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Authors: Thomas Abraham <thomas.ab@samsung.com> 5 * Chander Kashyap <k.chander@samsung.com> 6 * 7 * Common Clock Framework support for Exynos5420 SoC. 8 */ 9 10 #include <dt-bindings/clock/exynos5420.h> 11 #include <linux/slab.h> 12 #include <linux/clk-provider.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/clk.h> 16 17 #include "clk.h" 18 #include "clk-cpu.h" 19 #include "clk-exynos5-subcmu.h" 20 21 #define APLL_LOCK 0x0 22 #define APLL_CON0 0x100 23 #define SRC_CPU 0x200 24 #define DIV_CPU0 0x500 25 #define DIV_CPU1 0x504 26 #define GATE_BUS_CPU 0x700 27 #define GATE_SCLK_CPU 0x800 28 #define CLKOUT_CMU_CPU 0xa00 29 #define SRC_MASK_CPERI 0x4300 30 #define GATE_IP_G2D 0x8800 31 #define CPLL_LOCK 0x10020 32 #define DPLL_LOCK 0x10030 33 #define EPLL_LOCK 0x10040 34 #define RPLL_LOCK 0x10050 35 #define IPLL_LOCK 0x10060 36 #define SPLL_LOCK 0x10070 37 #define VPLL_LOCK 0x10080 38 #define MPLL_LOCK 0x10090 39 #define CPLL_CON0 0x10120 40 #define DPLL_CON0 0x10128 41 #define EPLL_CON0 0x10130 42 #define EPLL_CON1 0x10134 43 #define EPLL_CON2 0x10138 44 #define RPLL_CON0 0x10140 45 #define RPLL_CON1 0x10144 46 #define RPLL_CON2 0x10148 47 #define IPLL_CON0 0x10150 48 #define SPLL_CON0 0x10160 49 #define VPLL_CON0 0x10170 50 #define MPLL_CON0 0x10180 51 #define SRC_TOP0 0x10200 52 #define SRC_TOP1 0x10204 53 #define SRC_TOP2 0x10208 54 #define SRC_TOP3 0x1020c 55 #define SRC_TOP4 0x10210 56 #define SRC_TOP5 0x10214 57 #define SRC_TOP6 0x10218 58 #define SRC_TOP7 0x1021c 59 #define SRC_TOP8 0x10220 /* 5800 specific */ 60 #define SRC_TOP9 0x10224 /* 5800 specific */ 61 #define SRC_DISP10 0x1022c 62 #define SRC_MAU 0x10240 63 #define SRC_FSYS 0x10244 64 #define SRC_PERIC0 0x10250 65 #define SRC_PERIC1 0x10254 66 #define SRC_ISP 0x10270 67 #define SRC_CAM 0x10274 /* 5800 specific */ 68 #define SRC_TOP10 0x10280 69 #define SRC_TOP11 0x10284 70 #define SRC_TOP12 0x10288 71 #define SRC_TOP13 0x1028c /* 5800 specific */ 72 #define SRC_MASK_TOP0 0x10300 73 #define SRC_MASK_TOP1 0x10304 74 #define SRC_MASK_TOP2 0x10308 75 #define SRC_MASK_TOP7 0x1031c 76 #define SRC_MASK_DISP10 0x1032c 77 #define SRC_MASK_MAU 0x10334 78 #define SRC_MASK_FSYS 0x10340 79 #define SRC_MASK_PERIC0 0x10350 80 #define SRC_MASK_PERIC1 0x10354 81 #define SRC_MASK_ISP 0x10370 82 #define DIV_TOP0 0x10500 83 #define DIV_TOP1 0x10504 84 #define DIV_TOP2 0x10508 85 #define DIV_TOP8 0x10520 /* 5800 specific */ 86 #define DIV_TOP9 0x10524 /* 5800 specific */ 87 #define DIV_DISP10 0x1052c 88 #define DIV_MAU 0x10544 89 #define DIV_FSYS0 0x10548 90 #define DIV_FSYS1 0x1054c 91 #define DIV_FSYS2 0x10550 92 #define DIV_PERIC0 0x10558 93 #define DIV_PERIC1 0x1055c 94 #define DIV_PERIC2 0x10560 95 #define DIV_PERIC3 0x10564 96 #define DIV_PERIC4 0x10568 97 #define DIV_CAM 0x10574 /* 5800 specific */ 98 #define SCLK_DIV_ISP0 0x10580 99 #define SCLK_DIV_ISP1 0x10584 100 #define DIV2_RATIO0 0x10590 101 #define DIV4_RATIO 0x105a0 102 #define GATE_BUS_TOP 0x10700 103 #define GATE_BUS_DISP1 0x10728 104 #define GATE_BUS_GEN 0x1073c 105 #define GATE_BUS_FSYS0 0x10740 106 #define GATE_BUS_FSYS2 0x10748 107 #define GATE_BUS_PERIC 0x10750 108 #define GATE_BUS_PERIC1 0x10754 109 #define GATE_BUS_PERIS0 0x10760 110 #define GATE_BUS_PERIS1 0x10764 111 #define GATE_BUS_NOC 0x10770 112 #define GATE_TOP_SCLK_ISP 0x10870 113 #define GATE_IP_GSCL0 0x10910 114 #define GATE_IP_GSCL1 0x10920 115 #define GATE_IP_CAM 0x10924 /* 5800 specific */ 116 #define GATE_IP_MFC 0x1092c 117 #define GATE_IP_DISP1 0x10928 118 #define GATE_IP_G3D 0x10930 119 #define GATE_IP_GEN 0x10934 120 #define GATE_IP_FSYS 0x10944 121 #define GATE_IP_PERIC 0x10950 122 #define GATE_IP_PERIS 0x10960 123 #define GATE_IP_MSCL 0x10970 124 #define GATE_TOP_SCLK_GSCL 0x10820 125 #define GATE_TOP_SCLK_DISP1 0x10828 126 #define GATE_TOP_SCLK_MAU 0x1083c 127 #define GATE_TOP_SCLK_FSYS 0x10840 128 #define GATE_TOP_SCLK_PERIC 0x10850 129 #define TOP_SPARE2 0x10b08 130 #define BPLL_LOCK 0x20010 131 #define BPLL_CON0 0x20110 132 #define SRC_CDREX 0x20200 133 #define DIV_CDREX0 0x20500 134 #define DIV_CDREX1 0x20504 135 #define GATE_BUS_CDREX0 0x20700 136 #define GATE_BUS_CDREX1 0x20704 137 #define KPLL_LOCK 0x28000 138 #define KPLL_CON0 0x28100 139 #define SRC_KFC 0x28200 140 #define DIV_KFC0 0x28500 141 142 /* Exynos5x SoC type */ 143 enum exynos5x_soc { 144 EXYNOS5420, 145 EXYNOS5800, 146 }; 147 148 /* list of PLLs */ 149 enum exynos5x_plls { 150 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 151 bpll, kpll, 152 nr_plls /* number of PLLs */ 153 }; 154 155 static void __iomem *reg_base; 156 static enum exynos5x_soc exynos5x_soc; 157 158 /* 159 * list of controller registers to be saved and restored during a 160 * suspend/resume cycle. 161 */ 162 static const unsigned long exynos5x_clk_regs[] __initconst = { 163 SRC_CPU, 164 DIV_CPU0, 165 DIV_CPU1, 166 GATE_BUS_CPU, 167 GATE_SCLK_CPU, 168 CLKOUT_CMU_CPU, 169 APLL_CON0, 170 KPLL_CON0, 171 CPLL_CON0, 172 DPLL_CON0, 173 EPLL_CON0, 174 EPLL_CON1, 175 EPLL_CON2, 176 RPLL_CON0, 177 RPLL_CON1, 178 RPLL_CON2, 179 IPLL_CON0, 180 SPLL_CON0, 181 VPLL_CON0, 182 MPLL_CON0, 183 SRC_TOP0, 184 SRC_TOP1, 185 SRC_TOP2, 186 SRC_TOP3, 187 SRC_TOP4, 188 SRC_TOP5, 189 SRC_TOP6, 190 SRC_TOP7, 191 SRC_DISP10, 192 SRC_MAU, 193 SRC_FSYS, 194 SRC_PERIC0, 195 SRC_PERIC1, 196 SRC_TOP10, 197 SRC_TOP11, 198 SRC_TOP12, 199 SRC_MASK_TOP2, 200 SRC_MASK_TOP7, 201 SRC_MASK_DISP10, 202 SRC_MASK_FSYS, 203 SRC_MASK_PERIC0, 204 SRC_MASK_PERIC1, 205 SRC_MASK_TOP0, 206 SRC_MASK_TOP1, 207 SRC_MASK_MAU, 208 SRC_MASK_ISP, 209 SRC_ISP, 210 DIV_TOP0, 211 DIV_TOP1, 212 DIV_TOP2, 213 DIV_DISP10, 214 DIV_MAU, 215 DIV_FSYS0, 216 DIV_FSYS1, 217 DIV_FSYS2, 218 DIV_PERIC0, 219 DIV_PERIC1, 220 DIV_PERIC2, 221 DIV_PERIC3, 222 DIV_PERIC4, 223 SCLK_DIV_ISP0, 224 SCLK_DIV_ISP1, 225 DIV2_RATIO0, 226 DIV4_RATIO, 227 GATE_BUS_DISP1, 228 GATE_BUS_TOP, 229 GATE_BUS_GEN, 230 GATE_BUS_FSYS0, 231 GATE_BUS_FSYS2, 232 GATE_BUS_PERIC, 233 GATE_BUS_PERIC1, 234 GATE_BUS_PERIS0, 235 GATE_BUS_PERIS1, 236 GATE_BUS_NOC, 237 GATE_TOP_SCLK_ISP, 238 GATE_IP_GSCL0, 239 GATE_IP_GSCL1, 240 GATE_IP_MFC, 241 GATE_IP_DISP1, 242 GATE_IP_G3D, 243 GATE_IP_GEN, 244 GATE_IP_FSYS, 245 GATE_IP_PERIC, 246 GATE_IP_PERIS, 247 GATE_IP_MSCL, 248 GATE_TOP_SCLK_GSCL, 249 GATE_TOP_SCLK_DISP1, 250 GATE_TOP_SCLK_MAU, 251 GATE_TOP_SCLK_FSYS, 252 GATE_TOP_SCLK_PERIC, 253 TOP_SPARE2, 254 SRC_CDREX, 255 DIV_CDREX0, 256 DIV_CDREX1, 257 SRC_KFC, 258 DIV_KFC0, 259 GATE_BUS_CDREX0, 260 GATE_BUS_CDREX1, 261 }; 262 263 static const unsigned long exynos5800_clk_regs[] __initconst = { 264 SRC_TOP8, 265 SRC_TOP9, 266 SRC_CAM, 267 SRC_TOP1, 268 DIV_TOP8, 269 DIV_TOP9, 270 DIV_CAM, 271 GATE_IP_CAM, 272 }; 273 274 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 275 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 276 { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 277 { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 278 { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 279 { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 280 { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 281 { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 282 { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 283 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 284 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 285 { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 286 { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 287 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 288 { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 289 { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, 290 }; 291 292 /* list of all parent clocks */ 293 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 294 "mout_sclk_mpll", "mout_sclk_spll"}; 295 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 296 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 297 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 298 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 299 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 300 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 301 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 302 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 303 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 304 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 305 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 306 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 307 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 308 309 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 310 "mout_sclk_mpll"}; 311 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 312 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 313 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 314 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 315 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 316 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 317 318 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 319 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 320 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 321 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 322 323 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 324 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 325 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 326 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 327 328 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 329 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 330 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 331 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 332 333 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 334 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 335 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 336 337 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 338 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 339 340 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 341 "mout_sclk_spll"}; 342 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 343 344 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 345 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 346 347 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 348 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 349 350 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 351 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 352 353 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 354 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 355 356 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 357 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 358 359 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 360 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 361 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 362 363 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 364 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 365 366 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 367 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 368 369 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 370 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 371 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 372 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 373 374 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 375 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 376 377 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 378 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 379 380 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 381 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 382 383 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 384 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 385 386 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 387 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 388 "mout_sclk_epll", "mout_sclk_rpll"}; 389 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 390 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 391 "mout_sclk_epll", "mout_sclk_rpll"}; 392 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 393 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 394 "mout_sclk_epll", "mout_sclk_rpll"}; 395 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 396 "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 397 "mout_sclk_epll", "mout_sclk_rpll"}; 398 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 399 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 400 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 401 "mout_sclk_epll", "mout_sclk_rpll"}; 402 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 403 "mout_sclk_mpll", "mout_sclk_spll"}; 404 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 405 406 /* List of parents specific to exynos5800 */ 407 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 408 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 409 "mout_sclk_mpll", "ff_dout_spll2" }; 410 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 411 "mout_sclk_mpll", "ff_dout_spll2", 412 "mout_epll2", "mout_sclk_ipll" }; 413 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 414 "mout_sclk_mpll", "ff_dout_spll2", 415 "mout_epll2" }; 416 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 417 "mout_sclk_mpll", "mout_sclk_spll" }; 418 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 419 "mout_sclk_mpll", "ff_dout_spll2" }; 420 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 421 "mout_sclk_mpll", "mout_sclk_spll", 422 "mout_epll2", "mout_sclk_ipll" }; 423 PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 424 "mout_sclk_mpll", "ff_dout_spll2", 425 "mout_sclk_spll", "mout_sclk_epll"}; 426 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 427 "mout_sclk_mpll", 428 "ff_dout_spll2" }; 429 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 430 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 431 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 432 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 433 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 434 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 435 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 436 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 437 PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 438 PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", 439 "mout_sclk_mpll", "ff_dout_spll2", 440 "mout_sclk_spll", "mout_sclk_epll"}; 441 442 /* fixed rate clocks generated outside the soc */ 443 static struct samsung_fixed_rate_clock 444 exynos5x_fixed_rate_ext_clks[] __initdata = { 445 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 446 }; 447 448 /* fixed rate clocks generated inside the soc */ 449 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 450 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 451 FRATE(0, "sclk_pwi", NULL, 0, 24000000), 452 FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 453 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 454 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 455 }; 456 457 static const struct samsung_fixed_factor_clock 458 exynos5x_fixed_factor_clks[] __initconst = { 459 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 460 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 461 }; 462 463 static const struct samsung_fixed_factor_clock 464 exynos5800_fixed_factor_clks[] __initconst = { 465 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 466 FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 467 }; 468 469 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 470 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 471 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 472 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 473 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 474 475 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 476 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 477 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 478 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 479 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 480 481 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 482 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 483 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 484 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 485 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 486 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 487 488 MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", 489 mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), 490 491 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 492 mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), 493 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 494 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 495 MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 496 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 497 498 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 499 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 500 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 501 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 502 503 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 504 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 505 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 506 SRC_TOP9, 16, 1), 507 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 508 SRC_TOP9, 20, 1), 509 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 510 SRC_TOP9, 24, 1), 511 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 512 SRC_TOP9, 28, 1), 513 514 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 515 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 516 SRC_TOP13, 20, 1), 517 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 518 SRC_TOP13, 24, 1), 519 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 520 SRC_TOP13, 28, 1), 521 522 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 523 }; 524 525 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 526 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 527 "mout_aclk400_wcore", DIV_TOP0, 16, 3), 528 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 529 DIV_TOP8, 16, 3), 530 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 531 DIV_TOP8, 20, 3), 532 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 533 DIV_TOP8, 24, 3), 534 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 535 DIV_TOP8, 28, 3), 536 537 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 538 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 539 }; 540 541 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 542 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 543 GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0), 544 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 545 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 546 }; 547 548 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 549 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 550 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 551 TOP_SPARE2, 4, 1), 552 553 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 554 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 555 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 556 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 557 558 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 559 MUX(0, "mout_aclk333_432_isp", mout_group4_p, 560 SRC_TOP1, 4, 2), 561 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 562 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 563 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 564 565 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 566 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 567 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 568 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 569 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 570 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 571 572 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 573 mout_group5_5800_p, SRC_TOP7, 16, 2), 574 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 575 CLK_SET_RATE_PARENT, 0), 576 577 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 578 }; 579 580 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 581 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 582 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 583 }; 584 585 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 586 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 587 /* Maudio Block */ 588 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 589 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 590 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 591 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 592 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 593 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 594 }; 595 596 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 597 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 598 SRC_TOP7, 4, 1), 599 MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p, 600 SRC_TOP7, 8, 2), 601 MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p, 602 SRC_TOP7, 12, 2), 603 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 604 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 605 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 606 MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 607 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 608 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 609 610 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 611 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 612 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 613 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 614 615 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 616 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 617 618 MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1, 619 CLK_SET_RATE_PARENT, 0), 620 621 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 622 SRC_TOP3, 0, 1), 623 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 624 SRC_TOP3, 4, 1), 625 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 626 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 627 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 628 SRC_TOP3, 12, 1), 629 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 630 SRC_TOP3, 16, 1), 631 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 632 SRC_TOP3, 20, 1), 633 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 634 SRC_TOP3, 24, 1), 635 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 636 SRC_TOP3, 28, 1), 637 638 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 639 SRC_TOP4, 0, 1), 640 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 641 SRC_TOP4, 4, 1), 642 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 643 SRC_TOP4, 8, 1), 644 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 645 SRC_TOP4, 12, 1), 646 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 647 SRC_TOP4, 16, 1), 648 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 649 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 650 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 651 SRC_TOP4, 28, 1), 652 653 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 654 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 655 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 656 SRC_TOP5, 4, 1), 657 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 658 SRC_TOP5, 8, 1), 659 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 660 SRC_TOP5, 12, 1), 661 MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 662 SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0), 663 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 664 SRC_TOP5, 20, 1), 665 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 666 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 667 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 668 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 669 670 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 671 MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1, 672 CLK_SET_RATE_PARENT, 0), 673 MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 674 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 675 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 676 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 677 CLK_SET_RATE_PARENT, 0), 678 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 679 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 680 681 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 682 SRC_TOP10, 0, 1), 683 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 684 SRC_TOP10, 4, 1), 685 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 686 SRC_TOP10, 8, 1), 687 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 688 SRC_TOP10, 12, 1), 689 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 690 SRC_TOP10, 16, 1), 691 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 692 SRC_TOP10, 20, 1), 693 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 694 SRC_TOP10, 24, 1), 695 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 696 SRC_TOP10, 28, 1), 697 698 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 699 SRC_TOP11, 0, 1), 700 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 701 SRC_TOP11, 4, 1), 702 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 703 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 704 SRC_TOP11, 12, 1), 705 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 706 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 707 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 708 SRC_TOP11, 28, 1), 709 710 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 711 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 712 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 713 SRC_TOP12, 8, 1), 714 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 715 SRC_TOP12, 12, 1), 716 MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, 717 SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0), 718 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 719 SRC_TOP12, 20, 1), 720 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 721 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 722 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 723 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 724 725 /* DISP1 Block */ 726 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 727 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 728 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 729 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 730 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 731 732 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 733 734 /* CDREX block */ 735 MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 736 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 737 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 738 CLK_SET_RATE_PARENT, 0), 739 740 /* MAU Block */ 741 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 742 743 /* FSYS Block */ 744 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 745 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 746 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 747 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 748 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 749 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 750 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 751 752 /* PERIC Block */ 753 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 754 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 755 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 756 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 757 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 758 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 759 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 760 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 761 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 762 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 763 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 764 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 765 766 /* ISP Block */ 767 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 768 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 769 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 770 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 771 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 772 }; 773 774 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 775 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 776 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 777 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 778 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 779 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 780 781 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 782 DIV_TOP0, 0, 3), 783 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 784 DIV_TOP0, 4, 3), 785 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 786 DIV_TOP0, 8, 3), 787 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 788 DIV_TOP0, 12, 3), 789 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 790 DIV_TOP0, 20, 3), 791 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 792 DIV_TOP0, 24, 3), 793 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 794 DIV_TOP0, 28, 3), 795 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 796 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 797 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 798 "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 799 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 800 DIV_TOP1, 8, 6), 801 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 802 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 803 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 804 DIV_TOP1, 20, 3), 805 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 806 DIV_TOP1, 24, 3), 807 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 808 DIV_TOP1, 28, 3), 809 810 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 811 DIV_TOP2, 8, 3), 812 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 813 DIV_TOP2, 12, 3), 814 DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 815 16, 3, CLK_SET_RATE_PARENT, 0), 816 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 817 DIV_TOP2, 20, 3), 818 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 819 "mout_aclk300_disp1", DIV_TOP2, 24, 3), 820 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 821 DIV_TOP2, 28, 3), 822 823 /* DISP1 Block */ 824 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 825 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 826 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 827 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 828 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 829 "mout_aclk400_disp1", DIV_TOP2, 4, 3), 830 831 /* CDREX Block */ 832 /* 833 * The three clocks below are controlled using the same register and 834 * bits. They are put into one because there is a need of 835 * synchronization between the BUS and DREXs (two external memory 836 * interfaces). 837 * They are put here to show this HW assumption and for clock 838 * information summary completeness. 839 */ 840 DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 841 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 842 DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0", 843 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 844 DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0", 845 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 846 847 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 848 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 849 DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 850 DIV_CDREX0, 16, 3), 851 DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 852 DIV_CDREX0, 8, 3), 853 DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 854 DIV_CDREX0, 3, 5), 855 856 DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 857 DIV_CDREX1, 8, 3), 858 859 /* Audio Block */ 860 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 861 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 862 863 /* USB3.0 */ 864 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 865 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 866 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 867 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 868 869 /* MMC */ 870 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 871 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 872 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 873 874 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 875 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 876 877 /* UART and PWM */ 878 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 879 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 880 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 881 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 882 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 883 884 /* SPI */ 885 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 886 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 887 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 888 889 890 /* PCM */ 891 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 892 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 893 894 /* Audio - I2S */ 895 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 896 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 897 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 898 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 899 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 900 901 /* SPI Pre-Ratio */ 902 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 903 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 904 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 905 906 /* GSCL Block */ 907 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 908 909 /* PSGEN */ 910 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 911 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 912 913 /* ISP Block */ 914 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 915 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 916 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 917 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 918 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 919 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 920 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 921 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 922 CLK_SET_RATE_PARENT, 0), 923 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 924 CLK_SET_RATE_PARENT, 0), 925 }; 926 927 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 928 /* G2D */ 929 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 930 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 931 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 932 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 933 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 934 935 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 936 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 937 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 938 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 939 940 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 941 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 942 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 943 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 944 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 945 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 946 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 947 GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0), 948 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 949 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 950 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 951 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 952 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 953 GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0), 954 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 955 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 956 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 957 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 958 GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 959 GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0), 960 GATE(0, "aclk166", "mout_user_aclk166", 961 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 962 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 963 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 964 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 965 GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0), 966 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 967 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 968 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 969 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 970 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 971 GATE_BUS_TOP, 28, 0, 0), 972 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 973 GATE_BUS_TOP, 29, 0, 0), 974 975 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 976 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 977 978 /* sclk */ 979 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 980 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 981 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 982 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 983 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 984 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 985 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 986 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 987 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 988 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 989 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 990 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 991 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 992 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 993 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 994 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 995 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 996 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 997 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 998 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 999 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 1000 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 1001 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 1002 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 1003 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 1004 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 1005 1006 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 1007 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 1008 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 1009 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1010 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 1011 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1012 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 1013 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1014 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 1015 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1016 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 1017 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1018 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 1019 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 1020 1021 /* Display */ 1022 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 1023 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1024 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 1025 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1026 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1027 GATE_TOP_SCLK_DISP1, 9, 0, 0), 1028 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 1029 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1030 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 1031 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 1032 1033 /* FSYS Block */ 1034 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1035 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1036 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1037 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 1038 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 1039 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 1040 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 1041 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1042 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 1043 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 1044 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 1045 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 1046 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 1047 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 1048 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1049 1050 /* PERIC Block */ 1051 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 1052 GATE_IP_PERIC, 0, 0, 0), 1053 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 1054 GATE_IP_PERIC, 1, 0, 0), 1055 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 1056 GATE_IP_PERIC, 2, 0, 0), 1057 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 1058 GATE_IP_PERIC, 3, 0, 0), 1059 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 1060 GATE_IP_PERIC, 6, 0, 0), 1061 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 1062 GATE_IP_PERIC, 7, 0, 0), 1063 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 1064 GATE_IP_PERIC, 8, 0, 0), 1065 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 1066 GATE_IP_PERIC, 9, 0, 0), 1067 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 1068 GATE_IP_PERIC, 10, 0, 0), 1069 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 1070 GATE_IP_PERIC, 11, 0, 0), 1071 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 1072 GATE_IP_PERIC, 12, 0, 0), 1073 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 1074 GATE_IP_PERIC, 13, 0, 0), 1075 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 1076 GATE_IP_PERIC, 14, 0, 0), 1077 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 1078 GATE_IP_PERIC, 15, 0, 0), 1079 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 1080 GATE_IP_PERIC, 16, 0, 0), 1081 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 1082 GATE_IP_PERIC, 17, 0, 0), 1083 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 1084 GATE_IP_PERIC, 18, 0, 0), 1085 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 1086 GATE_IP_PERIC, 20, 0, 0), 1087 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 1088 GATE_IP_PERIC, 21, 0, 0), 1089 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 1090 GATE_IP_PERIC, 22, 0, 0), 1091 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 1092 GATE_IP_PERIC, 23, 0, 0), 1093 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 1094 GATE_IP_PERIC, 24, 0, 0), 1095 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 1096 GATE_IP_PERIC, 26, 0, 0), 1097 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 1098 GATE_IP_PERIC, 28, 0, 0), 1099 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 1100 GATE_IP_PERIC, 30, 0, 0), 1101 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 1102 GATE_IP_PERIC, 31, 0, 0), 1103 1104 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 1105 GATE_BUS_PERIC, 22, 0, 0), 1106 1107 /* PERIS Block */ 1108 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1109 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1110 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1111 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1112 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 1113 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 1114 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 1115 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 1116 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 1117 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 1118 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 1119 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 1120 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 1121 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 1122 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 1123 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 1124 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 1125 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 1126 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 1127 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 1128 1129 /* GEN Block */ 1130 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 1131 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 1132 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 1133 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 1134 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 1135 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 1136 GATE_IP_GEN, 6, 0, 0), 1137 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 1138 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 1139 GATE_IP_GEN, 9, 0, 0), 1140 1141 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 1142 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 1143 GATE_BUS_GEN, 28, 0, 0), 1144 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 1145 1146 /* GSCL Block */ 1147 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 1148 GATE_TOP_SCLK_GSCL, 6, 0, 0), 1149 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 1150 GATE_TOP_SCLK_GSCL, 7, 0, 0), 1151 1152 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 1153 GATE_IP_GSCL0, 4, 0, 0), 1154 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 1155 GATE_IP_GSCL0, 5, 0, 0), 1156 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 1157 GATE_IP_GSCL0, 6, 0, 0), 1158 1159 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 1160 GATE_IP_GSCL1, 2, 0, 0), 1161 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 1162 GATE_IP_GSCL1, 3, 0, 0), 1163 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 1164 GATE_IP_GSCL1, 4, 0, 0), 1165 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 1166 CLK_IS_CRITICAL, 0), 1167 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 1168 CLK_IS_CRITICAL, 0), 1169 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333", 1170 GATE_IP_GSCL1, 16, 0, 0), 1171 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1172 GATE_IP_GSCL1, 17, 0, 0), 1173 1174 /* ISP */ 1175 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 1176 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 1177 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 1178 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 1179 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 1180 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 1181 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 1182 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 1183 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 1184 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 1185 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 1186 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 1187 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 1188 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 1189 1190 /* CDREX */ 1191 GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", 1192 GATE_BUS_CDREX0, 0, 0, 0), 1193 GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", 1194 GATE_BUS_CDREX0, 1, 0, 0), 1195 GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", 1196 SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), 1197 1198 GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", 1199 GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), 1200 GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", 1201 GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), 1202 GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", 1203 GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), 1204 GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", 1205 GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), 1206 1207 GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", 1208 GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), 1209 GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", 1210 GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), 1211 GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", 1212 GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), 1213 GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", 1214 GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), 1215 }; 1216 1217 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1218 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1219 }; 1220 1221 static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1222 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1223 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1224 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1225 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1226 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1227 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1228 GATE_IP_DISP1, 7, 0, 0), 1229 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1230 GATE_IP_DISP1, 8, 0, 0), 1231 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1232 GATE_IP_DISP1, 9, 0, 0), 1233 }; 1234 1235 static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1236 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1237 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1238 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1239 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1240 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1241 }; 1242 1243 static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1244 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1245 DIV2_RATIO0, 4, 2), 1246 }; 1247 1248 static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1249 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1250 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1251 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1252 GATE_IP_GSCL1, 6, 0, 0), 1253 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1254 GATE_IP_GSCL1, 7, 0, 0), 1255 }; 1256 1257 static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1258 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1259 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1260 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1261 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1262 }; 1263 1264 static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = { 1265 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 1266 CLK_SET_RATE_PARENT, 0), 1267 }; 1268 1269 static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = { 1270 { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */ 1271 { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */ 1272 }; 1273 1274 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1275 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1276 }; 1277 1278 static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1279 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1280 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 1281 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1282 }; 1283 1284 static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1285 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1286 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1287 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1288 }; 1289 1290 static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = { 1291 /* MSCL Block */ 1292 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1293 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1294 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1295 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1296 GATE_IP_MSCL, 8, 0, 0), 1297 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1298 GATE_IP_MSCL, 9, 0, 0), 1299 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1300 GATE_IP_MSCL, 10, 0, 0), 1301 }; 1302 1303 static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = { 1304 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 1305 }; 1306 1307 static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = { 1308 { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */ 1309 { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */ 1310 { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */ 1311 }; 1312 1313 static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = { 1314 GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 1315 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 1316 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 1317 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1318 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1319 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1320 }; 1321 1322 static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = { 1323 { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */ 1324 }; 1325 1326 static const struct exynos5_subcmu_info exynos5x_disp_subcmu = { 1327 .div_clks = exynos5x_disp_div_clks, 1328 .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1329 .gate_clks = exynos5x_disp_gate_clks, 1330 .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1331 .suspend_regs = exynos5x_disp_suspend_regs, 1332 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1333 .pd_name = "DISP", 1334 }; 1335 1336 static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = { 1337 .div_clks = exynos5x_gsc_div_clks, 1338 .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1339 .gate_clks = exynos5x_gsc_gate_clks, 1340 .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1341 .suspend_regs = exynos5x_gsc_suspend_regs, 1342 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1343 .pd_name = "GSC", 1344 }; 1345 1346 static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = { 1347 .gate_clks = exynos5x_g3d_gate_clks, 1348 .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks), 1349 .suspend_regs = exynos5x_g3d_suspend_regs, 1350 .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs), 1351 .pd_name = "G3D", 1352 }; 1353 1354 static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = { 1355 .div_clks = exynos5x_mfc_div_clks, 1356 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1357 .gate_clks = exynos5x_mfc_gate_clks, 1358 .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1359 .suspend_regs = exynos5x_mfc_suspend_regs, 1360 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1361 .pd_name = "MFC", 1362 }; 1363 1364 static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = { 1365 .div_clks = exynos5x_mscl_div_clks, 1366 .nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks), 1367 .gate_clks = exynos5x_mscl_gate_clks, 1368 .nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks), 1369 .suspend_regs = exynos5x_mscl_suspend_regs, 1370 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs), 1371 .pd_name = "MSC", 1372 }; 1373 1374 static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { 1375 .gate_clks = exynos5800_mau_gate_clks, 1376 .nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks), 1377 .suspend_regs = exynos5800_mau_suspend_regs, 1378 .nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs), 1379 .pd_name = "MAU", 1380 }; 1381 1382 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { 1383 &exynos5x_disp_subcmu, 1384 &exynos5x_gsc_subcmu, 1385 &exynos5x_g3d_subcmu, 1386 &exynos5x_mfc_subcmu, 1387 &exynos5x_mscl_subcmu, 1388 }; 1389 1390 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { 1391 &exynos5x_disp_subcmu, 1392 &exynos5x_gsc_subcmu, 1393 &exynos5x_g3d_subcmu, 1394 &exynos5x_mfc_subcmu, 1395 &exynos5x_mscl_subcmu, 1396 &exynos5800_mau_subcmu, 1397 }; 1398 1399 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 1400 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 1401 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 1402 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 1403 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 1404 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 1405 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 1406 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 1407 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 1408 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 1409 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 1410 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 1411 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 1412 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 1413 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 1414 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 1415 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 1416 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 1417 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 1418 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1419 }; 1420 1421 static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { 1422 PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), 1423 PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), 1424 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), 1425 PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), 1426 PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), 1427 PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), 1428 PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), 1429 PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), 1430 }; 1431 1432 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 1433 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 1434 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 1435 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 1436 PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 1437 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 1438 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 1439 PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 1440 PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 1441 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 1442 PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), 1443 PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), 1444 PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 1445 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 1446 PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), 1447 PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 1448 }; 1449 1450 static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = { 1451 PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2), 1452 PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2), 1453 PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2), 1454 PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2), 1455 PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2), 1456 PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3), 1457 PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3), 1458 PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4), 1459 }; 1460 1461 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1462 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1463 APLL_CON0, NULL), 1464 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1465 CPLL_CON0, NULL), 1466 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 1467 DPLL_CON0, NULL), 1468 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 1469 EPLL_CON0, NULL), 1470 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 1471 RPLL_CON0, NULL), 1472 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 1473 IPLL_CON0, NULL), 1474 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 1475 SPLL_CON0, NULL), 1476 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 1477 VPLL_CON0, NULL), 1478 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 1479 MPLL_CON0, NULL), 1480 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 1481 BPLL_CON0, NULL), 1482 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 1483 KPLL_CON0, NULL), 1484 }; 1485 1486 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1487 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1488 ((cpud) << 4))) 1489 1490 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1491 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1492 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1493 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1494 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1495 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1496 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1497 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1498 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1499 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1500 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1501 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1502 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1503 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1504 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1505 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1506 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1507 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1508 { 0 }, 1509 }; 1510 1511 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 1512 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1513 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1514 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1515 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1516 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1517 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1518 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1519 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1520 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1521 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1522 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1523 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1524 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1525 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1526 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 1527 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1528 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1529 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1530 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1531 { 0 }, 1532 }; 1533 1534 #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1535 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1536 1537 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 1538 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1539 { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1540 { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1541 { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1542 { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1543 { 900000, E5420_KFC_DIV(3, 5, 2), }, 1544 { 800000, E5420_KFC_DIV(3, 5, 2), }, 1545 { 700000, E5420_KFC_DIV(3, 4, 2), }, 1546 { 600000, E5420_KFC_DIV(3, 4, 2), }, 1547 { 500000, E5420_KFC_DIV(3, 4, 2), }, 1548 { 400000, E5420_KFC_DIV(3, 3, 2), }, 1549 { 300000, E5420_KFC_DIV(3, 3, 2), }, 1550 { 200000, E5420_KFC_DIV(3, 3, 2), }, 1551 { 0 }, 1552 }; 1553 1554 static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = { 1555 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200, 1556 exynos5420_eglclk_d), 1557 CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200, 1558 exynos5420_kfcclk_d), 1559 }; 1560 1561 static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = { 1562 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200, 1563 exynos5800_eglclk_d), 1564 CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200, 1565 exynos5420_kfcclk_d), 1566 }; 1567 1568 static const struct of_device_id ext_clk_match[] __initconst = { 1569 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1570 { }, 1571 }; 1572 1573 /* register exynos5420 clocks */ 1574 static void __init exynos5x_clk_init(struct device_node *np, 1575 enum exynos5x_soc soc) 1576 { 1577 struct samsung_clk_provider *ctx; 1578 struct clk_hw **hws; 1579 1580 if (np) { 1581 reg_base = of_iomap(np, 0); 1582 if (!reg_base) 1583 panic("%s: failed to map registers\n", __func__); 1584 } else { 1585 panic("%s: unable to determine soc\n", __func__); 1586 } 1587 1588 exynos5x_soc = soc; 1589 1590 ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS); 1591 hws = ctx->clk_data.hws; 1592 1593 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1594 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1595 ext_clk_match); 1596 1597 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { 1598 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1599 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1600 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1601 exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; 1602 } 1603 1604 if (soc == EXYNOS5420) 1605 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1606 else 1607 exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; 1608 1609 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls)); 1610 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1611 ARRAY_SIZE(exynos5x_fixed_rate_clks)); 1612 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 1613 ARRAY_SIZE(exynos5x_fixed_factor_clks)); 1614 samsung_clk_register_mux(ctx, exynos5x_mux_clks, 1615 ARRAY_SIZE(exynos5x_mux_clks)); 1616 samsung_clk_register_div(ctx, exynos5x_div_clks, 1617 ARRAY_SIZE(exynos5x_div_clks)); 1618 samsung_clk_register_gate(ctx, exynos5x_gate_clks, 1619 ARRAY_SIZE(exynos5x_gate_clks)); 1620 1621 if (soc == EXYNOS5420) { 1622 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1623 ARRAY_SIZE(exynos5420_mux_clks)); 1624 samsung_clk_register_div(ctx, exynos5420_div_clks, 1625 ARRAY_SIZE(exynos5420_div_clks)); 1626 samsung_clk_register_gate(ctx, exynos5420_gate_clks, 1627 ARRAY_SIZE(exynos5420_gate_clks)); 1628 } else { 1629 samsung_clk_register_fixed_factor( 1630 ctx, exynos5800_fixed_factor_clks, 1631 ARRAY_SIZE(exynos5800_fixed_factor_clks)); 1632 samsung_clk_register_mux(ctx, exynos5800_mux_clks, 1633 ARRAY_SIZE(exynos5800_mux_clks)); 1634 samsung_clk_register_div(ctx, exynos5800_div_clks, 1635 ARRAY_SIZE(exynos5800_div_clks)); 1636 samsung_clk_register_gate(ctx, exynos5800_gate_clks, 1637 ARRAY_SIZE(exynos5800_gate_clks)); 1638 } 1639 1640 if (soc == EXYNOS5420) { 1641 samsung_clk_register_cpu(ctx, exynos5420_cpu_clks, 1642 ARRAY_SIZE(exynos5420_cpu_clks)); 1643 } else { 1644 samsung_clk_register_cpu(ctx, exynos5800_cpu_clks, 1645 ARRAY_SIZE(exynos5800_cpu_clks)); 1646 } 1647 1648 samsung_clk_extended_sleep_init(reg_base, 1649 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), 1650 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); 1651 1652 if (soc == EXYNOS5800) { 1653 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, 1654 ARRAY_SIZE(exynos5800_clk_regs)); 1655 1656 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus), 1657 exynos5800_subcmus); 1658 } else { 1659 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1660 exynos5x_subcmus); 1661 } 1662 1663 /* 1664 * Keep top part of G3D clock path enabled permanently to ensure 1665 * that the internal busses get their clock regardless of the 1666 * main G3D clock enablement status. 1667 */ 1668 clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk); 1669 /* 1670 * Keep top BPLL mux enabled permanently to ensure that DRAM operates 1671 * properly. 1672 */ 1673 clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk); 1674 1675 samsung_clk_of_add_provider(np, ctx); 1676 } 1677 1678 static void __init exynos5420_clk_init(struct device_node *np) 1679 { 1680 exynos5x_clk_init(np, EXYNOS5420); 1681 } 1682 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1683 exynos5420_clk_init); 1684 1685 static void __init exynos5800_clk_init(struct device_node *np) 1686 { 1687 exynos5x_clk_init(np, EXYNOS5800); 1688 } 1689 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1690 exynos5800_clk_init); 1691