1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Authors: Thomas Abraham <thomas.ab@samsung.com> 5 * Chander Kashyap <k.chander@samsung.com> 6 * 7 * Common Clock Framework support for Exynos5420 SoC. 8 */ 9 10 #include <dt-bindings/clock/exynos5420.h> 11 #include <linux/slab.h> 12 #include <linux/clk-provider.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/clk.h> 16 17 #include "clk.h" 18 #include "clk-cpu.h" 19 #include "clk-exynos5-subcmu.h" 20 21 #define APLL_LOCK 0x0 22 #define APLL_CON0 0x100 23 #define SRC_CPU 0x200 24 #define DIV_CPU0 0x500 25 #define DIV_CPU1 0x504 26 #define GATE_BUS_CPU 0x700 27 #define GATE_SCLK_CPU 0x800 28 #define CLKOUT_CMU_CPU 0xa00 29 #define SRC_MASK_CPERI 0x4300 30 #define GATE_IP_G2D 0x8800 31 #define CPLL_LOCK 0x10020 32 #define DPLL_LOCK 0x10030 33 #define EPLL_LOCK 0x10040 34 #define RPLL_LOCK 0x10050 35 #define IPLL_LOCK 0x10060 36 #define SPLL_LOCK 0x10070 37 #define VPLL_LOCK 0x10080 38 #define MPLL_LOCK 0x10090 39 #define CPLL_CON0 0x10120 40 #define DPLL_CON0 0x10128 41 #define EPLL_CON0 0x10130 42 #define EPLL_CON1 0x10134 43 #define EPLL_CON2 0x10138 44 #define RPLL_CON0 0x10140 45 #define RPLL_CON1 0x10144 46 #define RPLL_CON2 0x10148 47 #define IPLL_CON0 0x10150 48 #define SPLL_CON0 0x10160 49 #define VPLL_CON0 0x10170 50 #define MPLL_CON0 0x10180 51 #define SRC_TOP0 0x10200 52 #define SRC_TOP1 0x10204 53 #define SRC_TOP2 0x10208 54 #define SRC_TOP3 0x1020c 55 #define SRC_TOP4 0x10210 56 #define SRC_TOP5 0x10214 57 #define SRC_TOP6 0x10218 58 #define SRC_TOP7 0x1021c 59 #define SRC_TOP8 0x10220 /* 5800 specific */ 60 #define SRC_TOP9 0x10224 /* 5800 specific */ 61 #define SRC_DISP10 0x1022c 62 #define SRC_MAU 0x10240 63 #define SRC_FSYS 0x10244 64 #define SRC_PERIC0 0x10250 65 #define SRC_PERIC1 0x10254 66 #define SRC_ISP 0x10270 67 #define SRC_CAM 0x10274 /* 5800 specific */ 68 #define SRC_TOP10 0x10280 69 #define SRC_TOP11 0x10284 70 #define SRC_TOP12 0x10288 71 #define SRC_TOP13 0x1028c /* 5800 specific */ 72 #define SRC_MASK_TOP0 0x10300 73 #define SRC_MASK_TOP1 0x10304 74 #define SRC_MASK_TOP2 0x10308 75 #define SRC_MASK_TOP7 0x1031c 76 #define SRC_MASK_DISP10 0x1032c 77 #define SRC_MASK_MAU 0x10334 78 #define SRC_MASK_FSYS 0x10340 79 #define SRC_MASK_PERIC0 0x10350 80 #define SRC_MASK_PERIC1 0x10354 81 #define SRC_MASK_ISP 0x10370 82 #define DIV_TOP0 0x10500 83 #define DIV_TOP1 0x10504 84 #define DIV_TOP2 0x10508 85 #define DIV_TOP8 0x10520 /* 5800 specific */ 86 #define DIV_TOP9 0x10524 /* 5800 specific */ 87 #define DIV_DISP10 0x1052c 88 #define DIV_MAU 0x10544 89 #define DIV_FSYS0 0x10548 90 #define DIV_FSYS1 0x1054c 91 #define DIV_FSYS2 0x10550 92 #define DIV_PERIC0 0x10558 93 #define DIV_PERIC1 0x1055c 94 #define DIV_PERIC2 0x10560 95 #define DIV_PERIC3 0x10564 96 #define DIV_PERIC4 0x10568 97 #define DIV_CAM 0x10574 /* 5800 specific */ 98 #define SCLK_DIV_ISP0 0x10580 99 #define SCLK_DIV_ISP1 0x10584 100 #define DIV2_RATIO0 0x10590 101 #define DIV4_RATIO 0x105a0 102 #define GATE_BUS_TOP 0x10700 103 #define GATE_BUS_DISP1 0x10728 104 #define GATE_BUS_GEN 0x1073c 105 #define GATE_BUS_FSYS0 0x10740 106 #define GATE_BUS_FSYS2 0x10748 107 #define GATE_BUS_PERIC 0x10750 108 #define GATE_BUS_PERIC1 0x10754 109 #define GATE_BUS_PERIS0 0x10760 110 #define GATE_BUS_PERIS1 0x10764 111 #define GATE_BUS_NOC 0x10770 112 #define GATE_TOP_SCLK_ISP 0x10870 113 #define GATE_IP_GSCL0 0x10910 114 #define GATE_IP_GSCL1 0x10920 115 #define GATE_IP_CAM 0x10924 /* 5800 specific */ 116 #define GATE_IP_MFC 0x1092c 117 #define GATE_IP_DISP1 0x10928 118 #define GATE_IP_G3D 0x10930 119 #define GATE_IP_GEN 0x10934 120 #define GATE_IP_FSYS 0x10944 121 #define GATE_IP_PERIC 0x10950 122 #define GATE_IP_PERIS 0x10960 123 #define GATE_IP_MSCL 0x10970 124 #define GATE_TOP_SCLK_GSCL 0x10820 125 #define GATE_TOP_SCLK_DISP1 0x10828 126 #define GATE_TOP_SCLK_MAU 0x1083c 127 #define GATE_TOP_SCLK_FSYS 0x10840 128 #define GATE_TOP_SCLK_PERIC 0x10850 129 #define TOP_SPARE2 0x10b08 130 #define BPLL_LOCK 0x20010 131 #define BPLL_CON0 0x20110 132 #define SRC_CDREX 0x20200 133 #define DIV_CDREX0 0x20500 134 #define DIV_CDREX1 0x20504 135 #define GATE_BUS_CDREX0 0x20700 136 #define GATE_BUS_CDREX1 0x20704 137 #define KPLL_LOCK 0x28000 138 #define KPLL_CON0 0x28100 139 #define SRC_KFC 0x28200 140 #define DIV_KFC0 0x28500 141 142 /* NOTE: Must be equal to the last clock ID increased by one */ 143 #define CLKS_NR (CLK_DOUT_PCLK_DREX1 + 1) 144 145 /* Exynos5x SoC type */ 146 enum exynos5x_soc { 147 EXYNOS5420, 148 EXYNOS5800, 149 }; 150 151 /* list of PLLs */ 152 enum exynos5x_plls { 153 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, 154 bpll, kpll, 155 nr_plls /* number of PLLs */ 156 }; 157 158 static void __iomem *reg_base; 159 static enum exynos5x_soc exynos5x_soc; 160 161 /* 162 * list of controller registers to be saved and restored during a 163 * suspend/resume cycle. 164 */ 165 static const unsigned long exynos5x_clk_regs[] __initconst = { 166 SRC_CPU, 167 DIV_CPU0, 168 DIV_CPU1, 169 GATE_BUS_CPU, 170 GATE_SCLK_CPU, 171 CLKOUT_CMU_CPU, 172 APLL_CON0, 173 KPLL_CON0, 174 CPLL_CON0, 175 DPLL_CON0, 176 EPLL_CON0, 177 EPLL_CON1, 178 EPLL_CON2, 179 RPLL_CON0, 180 RPLL_CON1, 181 RPLL_CON2, 182 IPLL_CON0, 183 SPLL_CON0, 184 VPLL_CON0, 185 MPLL_CON0, 186 SRC_TOP0, 187 SRC_TOP1, 188 SRC_TOP2, 189 SRC_TOP3, 190 SRC_TOP4, 191 SRC_TOP5, 192 SRC_TOP6, 193 SRC_TOP7, 194 SRC_DISP10, 195 SRC_MAU, 196 SRC_FSYS, 197 SRC_PERIC0, 198 SRC_PERIC1, 199 SRC_TOP10, 200 SRC_TOP11, 201 SRC_TOP12, 202 SRC_MASK_TOP2, 203 SRC_MASK_TOP7, 204 SRC_MASK_DISP10, 205 SRC_MASK_FSYS, 206 SRC_MASK_PERIC0, 207 SRC_MASK_PERIC1, 208 SRC_MASK_TOP0, 209 SRC_MASK_TOP1, 210 SRC_MASK_MAU, 211 SRC_MASK_ISP, 212 SRC_ISP, 213 DIV_TOP0, 214 DIV_TOP1, 215 DIV_TOP2, 216 DIV_DISP10, 217 DIV_MAU, 218 DIV_FSYS0, 219 DIV_FSYS1, 220 DIV_FSYS2, 221 DIV_PERIC0, 222 DIV_PERIC1, 223 DIV_PERIC2, 224 DIV_PERIC3, 225 DIV_PERIC4, 226 SCLK_DIV_ISP0, 227 SCLK_DIV_ISP1, 228 DIV2_RATIO0, 229 DIV4_RATIO, 230 GATE_BUS_DISP1, 231 GATE_BUS_TOP, 232 GATE_BUS_GEN, 233 GATE_BUS_FSYS0, 234 GATE_BUS_FSYS2, 235 GATE_BUS_PERIC, 236 GATE_BUS_PERIC1, 237 GATE_BUS_PERIS0, 238 GATE_BUS_PERIS1, 239 GATE_BUS_NOC, 240 GATE_TOP_SCLK_ISP, 241 GATE_IP_GSCL0, 242 GATE_IP_GSCL1, 243 GATE_IP_MFC, 244 GATE_IP_DISP1, 245 GATE_IP_G3D, 246 GATE_IP_GEN, 247 GATE_IP_FSYS, 248 GATE_IP_PERIC, 249 GATE_IP_PERIS, 250 GATE_IP_MSCL, 251 GATE_TOP_SCLK_GSCL, 252 GATE_TOP_SCLK_DISP1, 253 GATE_TOP_SCLK_MAU, 254 GATE_TOP_SCLK_FSYS, 255 GATE_TOP_SCLK_PERIC, 256 TOP_SPARE2, 257 SRC_CDREX, 258 DIV_CDREX0, 259 DIV_CDREX1, 260 SRC_KFC, 261 DIV_KFC0, 262 GATE_BUS_CDREX0, 263 GATE_BUS_CDREX1, 264 }; 265 266 static const unsigned long exynos5800_clk_regs[] __initconst = { 267 SRC_TOP8, 268 SRC_TOP9, 269 SRC_CAM, 270 SRC_TOP1, 271 DIV_TOP8, 272 DIV_TOP9, 273 DIV_CAM, 274 GATE_IP_CAM, 275 }; 276 277 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = { 278 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, }, 279 { .offset = SRC_MASK_TOP0, .value = 0x11111111, }, 280 { .offset = SRC_MASK_TOP1, .value = 0x11101111, }, 281 { .offset = SRC_MASK_TOP2, .value = 0x11111110, }, 282 { .offset = SRC_MASK_TOP7, .value = 0x00111100, }, 283 { .offset = SRC_MASK_DISP10, .value = 0x11111110, }, 284 { .offset = SRC_MASK_MAU, .value = 0x10000000, }, 285 { .offset = SRC_MASK_FSYS, .value = 0x11111110, }, 286 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, }, 287 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, }, 288 { .offset = SRC_MASK_ISP, .value = 0x11111000, }, 289 { .offset = GATE_BUS_TOP, .value = 0xffffffff, }, 290 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, }, 291 { .offset = GATE_IP_PERIC, .value = 0xffffffff, }, 292 { .offset = GATE_IP_PERIS, .value = 0xffffffff, }, 293 }; 294 295 /* list of all parent clocks */ 296 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 297 "mout_sclk_mpll", "mout_sclk_spll"}; 298 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"}; 299 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"}; 300 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"}; 301 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"}; 302 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"}; 303 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"}; 304 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"}; 305 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"}; 306 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"}; 307 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"}; 308 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"}; 309 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"}; 310 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"}; 311 312 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll", 313 "mout_sclk_mpll"}; 314 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll", 315 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll", 316 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"}; 317 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"}; 318 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"}; 319 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"}; 320 321 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"}; 322 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"}; 323 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"}; 324 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"}; 325 326 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"}; 327 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"}; 328 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"}; 329 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"}; 330 331 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"}; 332 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"}; 333 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"}; 334 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"}; 335 336 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"}; 337 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"}; 338 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"}; 339 340 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"}; 341 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"}; 342 343 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0", 344 "mout_sclk_spll"}; 345 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"}; 346 347 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"}; 348 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"}; 349 350 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"}; 351 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"}; 352 353 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"}; 354 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"}; 355 356 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"}; 357 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"}; 358 359 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"}; 360 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"}; 361 362 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"}; 363 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"}; 364 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"}; 365 366 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"}; 367 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"}; 368 369 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"}; 370 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"}; 371 372 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"}; 373 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"}; 374 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"}; 375 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"}; 376 377 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"}; 378 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"}; 379 380 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"}; 381 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"}; 382 383 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"}; 384 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"}; 385 386 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"}; 387 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"}; 388 389 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll", 390 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 391 "mout_sclk_epll", "mout_sclk_rpll"}; 392 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll", 393 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 394 "mout_sclk_epll", "mout_sclk_rpll"}; 395 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll", 396 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 397 "mout_sclk_epll", "mout_sclk_rpll"}; 398 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1", 399 "dout_audio2", "spdif_extclk", "mout_sclk_ipll", 400 "mout_sclk_epll", "mout_sclk_rpll"}; 401 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"}; 402 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll", 403 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll", 404 "mout_sclk_epll", "mout_sclk_rpll"}; 405 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll", 406 "mout_sclk_mpll", "mout_sclk_spll"}; 407 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"}; 408 409 /* List of parents specific to exynos5800 */ 410 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" }; 411 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 412 "mout_sclk_mpll", "ff_dout_spll2" }; 413 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 414 "mout_sclk_mpll", "ff_dout_spll2", 415 "mout_epll2", "mout_sclk_ipll" }; 416 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 417 "mout_sclk_mpll", "ff_dout_spll2", 418 "mout_epll2" }; 419 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 420 "mout_sclk_mpll", "mout_sclk_spll" }; 421 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll", 422 "mout_sclk_mpll", "ff_dout_spll2" }; 423 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll", 424 "mout_sclk_mpll", "mout_sclk_spll", 425 "mout_epll2", "mout_sclk_ipll" }; 426 PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll", 427 "mout_sclk_mpll", "ff_dout_spll2", 428 "mout_sclk_spll", "mout_sclk_epll"}; 429 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", 430 "mout_sclk_mpll", 431 "ff_dout_spll2" }; 432 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; 433 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; 434 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; 435 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; 436 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; 437 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; 438 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; 439 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; 440 PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; 441 PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll", 442 "mout_sclk_mpll", "ff_dout_spll2", 443 "mout_sclk_spll", "mout_sclk_epll"}; 444 445 /* fixed rate clocks generated outside the soc */ 446 static struct samsung_fixed_rate_clock 447 exynos5x_fixed_rate_ext_clks[] __initdata = { 448 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 449 }; 450 451 /* fixed rate clocks generated inside the soc */ 452 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = { 453 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 454 FRATE(0, "sclk_pwi", NULL, 0, 24000000), 455 FRATE(0, "sclk_usbh20", NULL, 0, 48000000), 456 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000), 457 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000), 458 }; 459 460 static const struct samsung_fixed_factor_clock 461 exynos5x_fixed_factor_clks[] __initconst = { 462 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), 463 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0), 464 }; 465 466 static const struct samsung_fixed_factor_clock 467 exynos5800_fixed_factor_clks[] __initconst = { 468 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), 469 FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 470 }; 471 472 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { 473 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 474 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 475 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 476 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2), 477 478 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2), 479 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2), 480 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2), 481 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2), 482 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2), 483 484 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3), 485 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2), 486 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2), 487 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2), 488 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), 489 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), 490 491 MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", 492 mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), 493 494 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 495 mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), 496 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, 497 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), 498 MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), 499 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), 500 501 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), 502 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3), 503 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2), 504 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2), 505 506 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p, 507 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0), 508 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p, 509 SRC_TOP9, 16, 1), 510 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p, 511 SRC_TOP9, 20, 1), 512 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p, 513 SRC_TOP9, 24, 1), 514 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p, 515 SRC_TOP9, 28, 1), 516 517 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1), 518 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p, 519 SRC_TOP13, 20, 1), 520 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p, 521 SRC_TOP13, 24, 1), 522 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p, 523 SRC_TOP13, 28, 1), 524 525 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 526 }; 527 528 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = { 529 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 530 "mout_aclk400_wcore", DIV_TOP0, 16, 3), 531 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 532 DIV_TOP8, 16, 3), 533 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam", 534 DIV_TOP8, 20, 3), 535 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam", 536 DIV_TOP8, 24, 3), 537 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler", 538 DIV_TOP8, 28, 3), 539 540 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3), 541 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 542 }; 543 544 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = { 545 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 546 GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0), 547 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 548 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0), 549 }; 550 551 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 552 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 553 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 554 TOP_SPARE2, 4, 1), 555 556 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 557 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2), 558 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 559 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 560 561 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2), 562 MUX(0, "mout_aclk333_432_isp", mout_group4_p, 563 SRC_TOP1, 4, 2), 564 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2), 565 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2), 566 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2), 567 568 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2), 569 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2), 570 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2), 571 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2), 572 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2), 573 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2), 574 575 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", 576 mout_group5_5800_p, SRC_TOP7, 16, 2), 577 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2, 578 CLK_SET_RATE_PARENT, 0), 579 580 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 581 }; 582 583 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { 584 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore", 585 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3), 586 }; 587 588 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { 589 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), 590 /* Maudio Block */ 591 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", 592 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 593 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 594 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 595 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 596 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 597 }; 598 599 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { 600 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p, 601 SRC_TOP7, 4, 1), 602 MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p, 603 SRC_TOP7, 8, 2), 604 MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p, 605 SRC_TOP7, 12, 2), 606 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 607 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 608 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 609 MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1, 610 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), 611 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1), 612 613 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2), 614 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2), 615 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2), 616 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2), 617 618 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2), 619 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2), 620 621 MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1, 622 CLK_SET_RATE_PARENT, 0), 623 624 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p, 625 SRC_TOP3, 0, 1), 626 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p, 627 SRC_TOP3, 4, 1), 628 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1", 629 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1), 630 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p, 631 SRC_TOP3, 12, 1), 632 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p, 633 SRC_TOP3, 16, 1), 634 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p, 635 SRC_TOP3, 20, 1), 636 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p, 637 SRC_TOP3, 24, 1), 638 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p, 639 SRC_TOP3, 28, 1), 640 641 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p, 642 SRC_TOP4, 0, 1), 643 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p, 644 SRC_TOP4, 4, 1), 645 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p, 646 SRC_TOP4, 8, 1), 647 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p, 648 SRC_TOP4, 12, 1), 649 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p, 650 SRC_TOP4, 16, 1), 651 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1), 652 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1), 653 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p, 654 SRC_TOP4, 28, 1), 655 656 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1", 657 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1), 658 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p, 659 SRC_TOP5, 4, 1), 660 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p, 661 SRC_TOP5, 8, 1), 662 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p, 663 SRC_TOP5, 12, 1), 664 MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p, 665 SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0), 666 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p, 667 SRC_TOP5, 20, 1), 668 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", 669 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), 670 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", 671 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), 672 673 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), 674 MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1, 675 CLK_SET_RATE_PARENT, 0), 676 MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), 677 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), 678 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), 679 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, 680 CLK_SET_RATE_PARENT, 0), 681 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1), 682 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1), 683 684 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p, 685 SRC_TOP10, 0, 1), 686 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p, 687 SRC_TOP10, 4, 1), 688 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p, 689 SRC_TOP10, 8, 1), 690 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p, 691 SRC_TOP10, 12, 1), 692 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p, 693 SRC_TOP10, 16, 1), 694 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p, 695 SRC_TOP10, 20, 1), 696 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p, 697 SRC_TOP10, 24, 1), 698 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p, 699 SRC_TOP10, 28, 1), 700 701 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p, 702 SRC_TOP11, 0, 1), 703 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p, 704 SRC_TOP11, 4, 1), 705 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1), 706 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p, 707 SRC_TOP11, 12, 1), 708 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1), 709 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1), 710 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p, 711 SRC_TOP11, 28, 1), 712 713 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1", 714 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1), 715 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p, 716 SRC_TOP12, 8, 1), 717 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p, 718 SRC_TOP12, 12, 1), 719 MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, 720 SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0), 721 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p, 722 SRC_TOP12, 20, 1), 723 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", 724 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), 725 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", 726 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), 727 728 /* DISP1 Block */ 729 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), 730 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3), 731 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3), 732 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1), 733 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3), 734 735 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1), 736 737 /* CDREX block */ 738 MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p, 739 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0), 740 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1, 741 CLK_SET_RATE_PARENT, 0), 742 743 /* MAU Block */ 744 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3), 745 746 /* FSYS Block */ 747 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3), 748 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3), 749 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3), 750 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3), 751 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3), 752 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3), 753 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3), 754 755 /* PERIC Block */ 756 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3), 757 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3), 758 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3), 759 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3), 760 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3), 761 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3), 762 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3), 763 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3), 764 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3), 765 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3), 766 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3), 767 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3), 768 769 /* ISP Block */ 770 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3), 771 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3), 772 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3), 773 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3), 774 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3), 775 }; 776 777 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { 778 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 779 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3), 780 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3), 781 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3), 782 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3), 783 784 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp", 785 DIV_TOP0, 0, 3), 786 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl", 787 DIV_TOP0, 4, 3), 788 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200", 789 DIV_TOP0, 8, 3), 790 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2", 791 DIV_TOP0, 12, 3), 792 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc", 793 DIV_TOP0, 20, 3), 794 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys", 795 DIV_TOP0, 24, 3), 796 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys", 797 DIV_TOP0, 28, 3), 798 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl", 799 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3), 800 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp", 801 "mout_aclk333_432_isp", DIV_TOP1, 4, 3), 802 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66", 803 DIV_TOP1, 8, 6), 804 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0", 805 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3), 806 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266", 807 DIV_TOP1, 20, 3), 808 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166", 809 DIV_TOP1, 24, 3), 810 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333", 811 DIV_TOP1, 28, 3), 812 813 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d", 814 DIV_TOP2, 8, 3), 815 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d", 816 DIV_TOP2, 12, 3), 817 DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2, 818 16, 3, CLK_SET_RATE_PARENT, 0), 819 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg", 820 DIV_TOP2, 20, 3), 821 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1", 822 "mout_aclk300_disp1", DIV_TOP2, 24, 3), 823 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl", 824 DIV_TOP2, 28, 3), 825 826 /* DISP1 Block */ 827 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4), 828 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), 829 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), 830 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), 831 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1", 832 "mout_aclk400_disp1", DIV_TOP2, 4, 3), 833 834 /* CDREX Block */ 835 /* 836 * The three clocks below are controlled using the same register and 837 * bits. They are put into one because there is a need of 838 * synchronization between the BUS and DREXs (two external memory 839 * interfaces). 840 * They are put here to show this HW assumption and for clock 841 * information summary completeness. 842 */ 843 DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1", 844 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 845 DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0", 846 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 847 DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0", 848 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0), 849 850 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex", 851 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0), 852 DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0", 853 DIV_CDREX0, 16, 3), 854 DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", 855 DIV_CDREX0, 8, 3), 856 DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", 857 DIV_CDREX0, 3, 5), 858 859 DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", 860 DIV_CDREX1, 8, 3), 861 862 /* Audio Block */ 863 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), 864 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8), 865 866 /* USB3.0 */ 867 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4), 868 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4), 869 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4), 870 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4), 871 872 /* MMC */ 873 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10), 874 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10), 875 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10), 876 877 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8), 878 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8), 879 880 /* UART and PWM */ 881 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4), 882 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4), 883 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4), 884 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4), 885 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4), 886 887 /* SPI */ 888 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4), 889 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4), 890 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4), 891 892 893 /* PCM */ 894 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8), 895 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8), 896 897 /* Audio - I2S */ 898 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6), 899 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6), 900 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4), 901 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4), 902 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4), 903 904 /* SPI Pre-Ratio */ 905 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8), 906 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8), 907 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8), 908 909 /* GSCL Block */ 910 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2), 911 912 /* PSGEN */ 913 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1), 914 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1), 915 916 /* ISP Block */ 917 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8), 918 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8), 919 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8), 920 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4), 921 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4), 922 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4), 923 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4), 924 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8, 925 CLK_SET_RATE_PARENT, 0), 926 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8, 927 CLK_SET_RATE_PARENT, 0), 928 }; 929 930 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 931 /* G2D */ 932 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0), 933 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), 934 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0), 935 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0), 936 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0), 937 938 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys", 939 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0), 940 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2", 941 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0), 942 943 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d", 944 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0), 945 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d", 946 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0), 947 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg", 948 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0), 949 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0", 950 GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0), 951 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl", 952 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0), 953 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl", 954 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0), 955 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp", 956 GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0), 957 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio", 958 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 959 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 960 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 961 GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 962 GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0), 963 GATE(0, "aclk166", "mout_user_aclk166", 964 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), 965 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333", 966 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0), 967 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 968 GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0), 969 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 970 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), 971 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 972 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 973 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 974 GATE_BUS_TOP, 28, 0, 0), 975 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m", 976 GATE_BUS_TOP, 29, 0, 0), 977 978 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1", 979 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0), 980 981 /* sclk */ 982 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0", 983 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0), 984 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1", 985 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0), 986 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2", 987 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0), 988 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3", 989 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0), 990 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre", 991 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0), 992 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre", 993 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0), 994 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre", 995 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0), 996 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 997 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0), 998 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm", 999 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0), 1000 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1", 1001 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0), 1002 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2", 1003 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0), 1004 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1", 1005 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0), 1006 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2", 1007 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0), 1008 1009 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0", 1010 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 1011 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1", 1012 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), 1013 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2", 1014 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), 1015 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", 1016 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), 1017 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300", 1018 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 1019 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300", 1020 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), 1021 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301", 1022 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0), 1023 1024 /* Display */ 1025 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1", 1026 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0), 1027 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1", 1028 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), 1029 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 1030 GATE_TOP_SCLK_DISP1, 9, 0, 0), 1031 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel", 1032 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), 1033 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1", 1034 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), 1035 1036 /* FSYS Block */ 1037 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0), 1038 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0), 1039 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0), 1040 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0), 1041 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0), 1042 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0), 1043 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0), 1044 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0), 1045 GATE(CLK_SROMC, "sromc", "aclk200_fsys2", 1046 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0), 1047 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0), 1048 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0), 1049 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0), 1050 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro", 1051 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 1052 1053 /* PERIC Block */ 1054 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric", 1055 GATE_IP_PERIC, 0, 0, 0), 1056 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric", 1057 GATE_IP_PERIC, 1, 0, 0), 1058 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric", 1059 GATE_IP_PERIC, 2, 0, 0), 1060 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric", 1061 GATE_IP_PERIC, 3, 0, 0), 1062 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric", 1063 GATE_IP_PERIC, 6, 0, 0), 1064 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric", 1065 GATE_IP_PERIC, 7, 0, 0), 1066 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric", 1067 GATE_IP_PERIC, 8, 0, 0), 1068 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric", 1069 GATE_IP_PERIC, 9, 0, 0), 1070 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric", 1071 GATE_IP_PERIC, 10, 0, 0), 1072 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric", 1073 GATE_IP_PERIC, 11, 0, 0), 1074 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric", 1075 GATE_IP_PERIC, 12, 0, 0), 1076 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric", 1077 GATE_IP_PERIC, 13, 0, 0), 1078 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric", 1079 GATE_IP_PERIC, 14, 0, 0), 1080 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric", 1081 GATE_IP_PERIC, 15, 0, 0), 1082 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric", 1083 GATE_IP_PERIC, 16, 0, 0), 1084 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric", 1085 GATE_IP_PERIC, 17, 0, 0), 1086 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric", 1087 GATE_IP_PERIC, 18, 0, 0), 1088 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric", 1089 GATE_IP_PERIC, 20, 0, 0), 1090 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric", 1091 GATE_IP_PERIC, 21, 0, 0), 1092 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric", 1093 GATE_IP_PERIC, 22, 0, 0), 1094 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric", 1095 GATE_IP_PERIC, 23, 0, 0), 1096 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric", 1097 GATE_IP_PERIC, 24, 0, 0), 1098 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric", 1099 GATE_IP_PERIC, 26, 0, 0), 1100 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric", 1101 GATE_IP_PERIC, 28, 0, 0), 1102 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric", 1103 GATE_IP_PERIC, 30, 0, 0), 1104 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric", 1105 GATE_IP_PERIC, 31, 0, 0), 1106 1107 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric", 1108 GATE_BUS_PERIC, 22, 0, 0), 1109 1110 /* PERIS Block */ 1111 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1112 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0), 1113 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen", 1114 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 1115 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0), 1116 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0), 1117 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0), 1118 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0), 1119 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0), 1120 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0), 1121 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0), 1122 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0), 1123 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0), 1124 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0), 1125 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0), 1126 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0), 1127 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0), 1128 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0), 1129 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), 1130 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), 1131 1132 /* GEN Block */ 1133 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), 1134 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0), 1135 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0), 1136 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0), 1137 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0), 1138 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk", 1139 GATE_IP_GEN, 6, 0, 0), 1140 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0), 1141 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk", 1142 GATE_IP_GEN, 9, 0, 0), 1143 1144 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */ 1145 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk", 1146 GATE_BUS_GEN, 28, 0, 0), 1147 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0), 1148 1149 /* GSCL Block */ 1150 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl", 1151 GATE_TOP_SCLK_GSCL, 6, 0, 0), 1152 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl", 1153 GATE_TOP_SCLK_GSCL, 7, 0, 0), 1154 1155 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl", 1156 GATE_IP_GSCL0, 4, 0, 0), 1157 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl", 1158 GATE_IP_GSCL0, 5, 0, 0), 1159 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl", 1160 GATE_IP_GSCL0, 6, 0, 0), 1161 1162 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333", 1163 GATE_IP_GSCL1, 2, 0, 0), 1164 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333", 1165 GATE_IP_GSCL1, 3, 0, 0), 1166 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333", 1167 GATE_IP_GSCL1, 4, 0, 0), 1168 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 1169 CLK_IS_CRITICAL, 0), 1170 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 1171 CLK_IS_CRITICAL, 0), 1172 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3", "dout_gscl_blk_333", 1173 GATE_IP_GSCL1, 16, 0, 0), 1174 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl", 1175 GATE_IP_GSCL1, 17, 0, 0), 1176 1177 /* ISP */ 1178 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp", 1179 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0), 1180 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre", 1181 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0), 1182 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre", 1183 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0), 1184 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp", 1185 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0), 1186 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0", 1187 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0), 1188 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1", 1189 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 1190 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2", 1191 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), 1192 1193 /* CDREX */ 1194 GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", 1195 GATE_BUS_CDREX0, 0, 0, 0), 1196 GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", 1197 GATE_BUS_CDREX0, 1, 0, 0), 1198 GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", 1199 SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), 1200 1201 GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", 1202 GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), 1203 GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", 1204 GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), 1205 GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", 1206 GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), 1207 GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", 1208 GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), 1209 1210 GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", 1211 GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), 1212 GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", 1213 GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), 1214 GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", 1215 GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), 1216 GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", 1217 GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), 1218 }; 1219 1220 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { 1221 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2), 1222 }; 1223 1224 static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = { 1225 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0), 1226 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0), 1227 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0), 1228 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), 1229 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), 1230 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk", 1231 GATE_IP_DISP1, 7, 0, 0), 1232 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk", 1233 GATE_IP_DISP1, 8, 0, 0), 1234 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1", 1235 GATE_IP_DISP1, 9, 0, 0), 1236 }; 1237 1238 static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = { 1239 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 1240 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */ 1241 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */ 1242 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */ 1243 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */ 1244 }; 1245 1246 static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = { 1247 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl", 1248 DIV2_RATIO0, 4, 2), 1249 }; 1250 1251 static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = { 1252 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0), 1253 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0), 1254 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300", 1255 GATE_IP_GSCL1, 6, 0, 0), 1256 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300", 1257 GATE_IP_GSCL1, 7, 0, 0), 1258 }; 1259 1260 static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { 1261 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */ 1262 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */ 1263 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */ 1264 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */ 1265 }; 1266 1267 static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = { 1268 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 1269 CLK_SET_RATE_PARENT, 0), 1270 }; 1271 1272 static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = { 1273 { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */ 1274 { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */ 1275 }; 1276 1277 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = { 1278 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2), 1279 }; 1280 1281 static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = { 1282 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), 1283 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0), 1284 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0), 1285 }; 1286 1287 static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = { 1288 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */ 1289 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */ 1290 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */ 1291 }; 1292 1293 static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = { 1294 /* MSCL Block */ 1295 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0), 1296 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0), 1297 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0), 1298 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk", 1299 GATE_IP_MSCL, 8, 0, 0), 1300 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk", 1301 GATE_IP_MSCL, 9, 0, 0), 1302 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk", 1303 GATE_IP_MSCL, 10, 0, 0), 1304 }; 1305 1306 static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = { 1307 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2), 1308 }; 1309 1310 static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = { 1311 { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */ 1312 { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */ 1313 { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */ 1314 }; 1315 1316 static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = { 1317 GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll", 1318 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), 1319 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0", 1320 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0), 1321 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0", 1322 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0), 1323 }; 1324 1325 static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = { 1326 { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */ 1327 }; 1328 1329 static const struct exynos5_subcmu_info exynos5x_disp_subcmu = { 1330 .div_clks = exynos5x_disp_div_clks, 1331 .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks), 1332 .gate_clks = exynos5x_disp_gate_clks, 1333 .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks), 1334 .suspend_regs = exynos5x_disp_suspend_regs, 1335 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs), 1336 .pd_name = "DISP", 1337 }; 1338 1339 static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = { 1340 .div_clks = exynos5x_gsc_div_clks, 1341 .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks), 1342 .gate_clks = exynos5x_gsc_gate_clks, 1343 .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks), 1344 .suspend_regs = exynos5x_gsc_suspend_regs, 1345 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs), 1346 .pd_name = "GSC", 1347 }; 1348 1349 static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = { 1350 .gate_clks = exynos5x_g3d_gate_clks, 1351 .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks), 1352 .suspend_regs = exynos5x_g3d_suspend_regs, 1353 .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs), 1354 .pd_name = "G3D", 1355 }; 1356 1357 static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = { 1358 .div_clks = exynos5x_mfc_div_clks, 1359 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks), 1360 .gate_clks = exynos5x_mfc_gate_clks, 1361 .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks), 1362 .suspend_regs = exynos5x_mfc_suspend_regs, 1363 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs), 1364 .pd_name = "MFC", 1365 }; 1366 1367 static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = { 1368 .div_clks = exynos5x_mscl_div_clks, 1369 .nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks), 1370 .gate_clks = exynos5x_mscl_gate_clks, 1371 .nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks), 1372 .suspend_regs = exynos5x_mscl_suspend_regs, 1373 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs), 1374 .pd_name = "MSC", 1375 }; 1376 1377 static const struct exynos5_subcmu_info exynos5800_mau_subcmu = { 1378 .gate_clks = exynos5800_mau_gate_clks, 1379 .nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks), 1380 .suspend_regs = exynos5800_mau_suspend_regs, 1381 .nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs), 1382 .pd_name = "MAU", 1383 }; 1384 1385 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = { 1386 &exynos5x_disp_subcmu, 1387 &exynos5x_gsc_subcmu, 1388 &exynos5x_g3d_subcmu, 1389 &exynos5x_mfc_subcmu, 1390 &exynos5x_mscl_subcmu, 1391 }; 1392 1393 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = { 1394 &exynos5x_disp_subcmu, 1395 &exynos5x_gsc_subcmu, 1396 &exynos5x_g3d_subcmu, 1397 &exynos5x_mfc_subcmu, 1398 &exynos5x_mscl_subcmu, 1399 &exynos5800_mau_subcmu, 1400 }; 1401 1402 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = { 1403 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0), 1404 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0), 1405 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0), 1406 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 1407 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 1408 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 1409 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 1410 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 1411 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1), 1412 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 1413 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 1414 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1), 1415 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 1416 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 1417 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2), 1418 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 1419 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 1420 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3), 1421 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 1422 }; 1423 1424 static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { 1425 PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), 1426 PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), 1427 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), 1428 PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), 1429 PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), 1430 PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), 1431 PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), 1432 PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), 1433 }; 1434 1435 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 1436 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), 1437 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), 1438 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690), 1439 PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671), 1440 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0), 1441 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690), 1442 PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671), 1443 PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719), 1444 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0), 1445 PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923), 1446 PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762), 1447 PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719), 1448 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690), 1449 PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762), 1450 PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719), 1451 }; 1452 1453 static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = { 1454 PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2), 1455 PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2), 1456 PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2), 1457 PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2), 1458 PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2), 1459 PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3), 1460 PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3), 1461 PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4), 1462 }; 1463 1464 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { 1465 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 1466 APLL_CON0, NULL), 1467 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 1468 CPLL_CON0, NULL), 1469 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, 1470 DPLL_CON0, NULL), 1471 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 1472 EPLL_CON0, NULL), 1473 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, 1474 RPLL_CON0, NULL), 1475 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK, 1476 IPLL_CON0, NULL), 1477 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK, 1478 SPLL_CON0, NULL), 1479 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK, 1480 VPLL_CON0, NULL), 1481 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 1482 MPLL_CON0, NULL), 1483 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 1484 BPLL_CON0, NULL), 1485 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK, 1486 KPLL_CON0, NULL), 1487 }; 1488 1489 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \ 1490 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 1491 ((cpud) << 4))) 1492 1493 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { 1494 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1495 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1496 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1497 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1498 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1499 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1500 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1501 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1502 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1503 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), }, 1504 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1505 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), }, 1506 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), }, 1507 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1508 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1509 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1510 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), }, 1511 { 0 }, 1512 }; 1513 1514 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { 1515 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1516 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1517 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, 1518 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1519 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1520 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1521 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, 1522 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1523 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1524 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, 1525 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1526 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, 1527 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1528 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, 1529 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, 1530 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1531 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1532 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1533 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, 1534 { 0 }, 1535 }; 1536 1537 #define E5420_KFC_DIV(kpll, pclk, aclk) \ 1538 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) 1539 1540 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { 1541 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ 1542 { 1300000, E5420_KFC_DIV(3, 5, 2), }, 1543 { 1200000, E5420_KFC_DIV(3, 5, 2), }, 1544 { 1100000, E5420_KFC_DIV(3, 5, 2), }, 1545 { 1000000, E5420_KFC_DIV(3, 5, 2), }, 1546 { 900000, E5420_KFC_DIV(3, 5, 2), }, 1547 { 800000, E5420_KFC_DIV(3, 5, 2), }, 1548 { 700000, E5420_KFC_DIV(3, 4, 2), }, 1549 { 600000, E5420_KFC_DIV(3, 4, 2), }, 1550 { 500000, E5420_KFC_DIV(3, 4, 2), }, 1551 { 400000, E5420_KFC_DIV(3, 3, 2), }, 1552 { 300000, E5420_KFC_DIV(3, 3, 2), }, 1553 { 200000, E5420_KFC_DIV(3, 3, 2), }, 1554 { 0 }, 1555 }; 1556 1557 static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = { 1558 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 1559 0x0, CPUCLK_LAYOUT_E4210, exynos5420_eglclk_d), 1560 CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 1561 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d), 1562 }; 1563 1564 static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = { 1565 CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 1566 0x0, CPUCLK_LAYOUT_E4210, exynos5800_eglclk_d), 1567 CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 1568 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d), 1569 }; 1570 1571 static const struct of_device_id ext_clk_match[] __initconst = { 1572 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, }, 1573 { }, 1574 }; 1575 1576 /* register exynos5420 clocks */ 1577 static void __init exynos5x_clk_init(struct device_node *np, 1578 enum exynos5x_soc soc) 1579 { 1580 struct samsung_clk_provider *ctx; 1581 struct clk_hw **hws; 1582 1583 if (np) { 1584 reg_base = of_iomap(np, 0); 1585 if (!reg_base) 1586 panic("%s: failed to map registers\n", __func__); 1587 } else { 1588 panic("%s: unable to determine soc\n", __func__); 1589 } 1590 1591 exynos5x_soc = soc; 1592 1593 ctx = samsung_clk_init(NULL, reg_base, CLKS_NR); 1594 hws = ctx->clk_data.hws; 1595 1596 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks, 1597 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks), 1598 ext_clk_match); 1599 1600 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { 1601 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1602 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; 1603 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1604 exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl; 1605 } 1606 1607 if (soc == EXYNOS5420) 1608 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; 1609 else 1610 exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; 1611 1612 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls)); 1613 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks, 1614 ARRAY_SIZE(exynos5x_fixed_rate_clks)); 1615 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks, 1616 ARRAY_SIZE(exynos5x_fixed_factor_clks)); 1617 samsung_clk_register_mux(ctx, exynos5x_mux_clks, 1618 ARRAY_SIZE(exynos5x_mux_clks)); 1619 samsung_clk_register_div(ctx, exynos5x_div_clks, 1620 ARRAY_SIZE(exynos5x_div_clks)); 1621 samsung_clk_register_gate(ctx, exynos5x_gate_clks, 1622 ARRAY_SIZE(exynos5x_gate_clks)); 1623 1624 if (soc == EXYNOS5420) { 1625 samsung_clk_register_mux(ctx, exynos5420_mux_clks, 1626 ARRAY_SIZE(exynos5420_mux_clks)); 1627 samsung_clk_register_div(ctx, exynos5420_div_clks, 1628 ARRAY_SIZE(exynos5420_div_clks)); 1629 samsung_clk_register_gate(ctx, exynos5420_gate_clks, 1630 ARRAY_SIZE(exynos5420_gate_clks)); 1631 } else { 1632 samsung_clk_register_fixed_factor( 1633 ctx, exynos5800_fixed_factor_clks, 1634 ARRAY_SIZE(exynos5800_fixed_factor_clks)); 1635 samsung_clk_register_mux(ctx, exynos5800_mux_clks, 1636 ARRAY_SIZE(exynos5800_mux_clks)); 1637 samsung_clk_register_div(ctx, exynos5800_div_clks, 1638 ARRAY_SIZE(exynos5800_div_clks)); 1639 samsung_clk_register_gate(ctx, exynos5800_gate_clks, 1640 ARRAY_SIZE(exynos5800_gate_clks)); 1641 } 1642 1643 if (soc == EXYNOS5420) { 1644 samsung_clk_register_cpu(ctx, exynos5420_cpu_clks, 1645 ARRAY_SIZE(exynos5420_cpu_clks)); 1646 } else { 1647 samsung_clk_register_cpu(ctx, exynos5800_cpu_clks, 1648 ARRAY_SIZE(exynos5800_cpu_clks)); 1649 } 1650 1651 samsung_clk_extended_sleep_init(reg_base, 1652 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs), 1653 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc)); 1654 1655 if (soc == EXYNOS5800) { 1656 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs, 1657 ARRAY_SIZE(exynos5800_clk_regs)); 1658 1659 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus), 1660 exynos5800_subcmus); 1661 } else { 1662 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus), 1663 exynos5x_subcmus); 1664 } 1665 1666 /* 1667 * Keep top part of G3D clock path enabled permanently to ensure 1668 * that the internal busses get their clock regardless of the 1669 * main G3D clock enablement status. 1670 */ 1671 clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk); 1672 /* 1673 * Keep top BPLL mux enabled permanently to ensure that DRAM operates 1674 * properly. 1675 */ 1676 clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk); 1677 1678 samsung_clk_of_add_provider(np, ctx); 1679 } 1680 1681 static void __init exynos5420_clk_init(struct device_node *np) 1682 { 1683 exynos5x_clk_init(np, EXYNOS5420); 1684 } 1685 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock", 1686 exynos5420_clk_init); 1687 1688 static void __init exynos5800_clk_init(struct device_node *np) 1689 { 1690 exynos5x_clk_init(np, EXYNOS5800); 1691 } 1692 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock", 1693 exynos5800_clk_init); 1694