1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Rahul Sharma <rahul.sharma@samsung.com> 5 * 6 * Common Clock Framework support for Exynos5260 SoC. 7 */ 8 9 #include "clk-exynos5260.h" 10 #include "clk.h" 11 #include "clk-pll.h" 12 13 #include <dt-bindings/clock/exynos5260-clk.h> 14 15 /* NOTE: Must be equal to the last clock ID increased by one */ 16 #define CLKS_NR_TOP (PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1) 17 #define CLKS_NR_EGL (EGL_DOUT_EGL1 + 1) 18 #define CLKS_NR_KFC (KFC_DOUT_KFC1 + 1) 19 #define CLKS_NR_MIF (MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1) 20 #define CLKS_NR_G3D (G3D_CLK_G3D + 1) 21 #define CLKS_NR_AUD (AUD_SCLK_I2S + 1) 22 #define CLKS_NR_MFC (MFC_CLK_SMMU2_MFCM0 + 1) 23 #define CLKS_NR_GSCL (GSCL_SCLK_CSIS0_WRAP + 1) 24 #define CLKS_NR_FSYS (FSYS_PHYCLK_USBHOST20 + 1) 25 #define CLKS_NR_PERI (PERI_SCLK_PCM1 + 1) 26 #define CLKS_NR_DISP (DISP_MOUT_HDMI_PHY_PIXEL_USER + 1) 27 #define CLKS_NR_G2D (G2D_CLK_SMMU3_G2D + 1) 28 #define CLKS_NR_ISP (ISP_SCLK_UART_EXT + 1) 29 30 /* 31 * Applicable for all 2550 Type PLLS for Exynos5260, listed below 32 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL. 33 */ 34 static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = { 35 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 36 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 37 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 38 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 39 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 40 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1), 41 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 42 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 43 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1), 44 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1), 45 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 46 PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1), 47 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 48 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1), 49 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), 50 PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2), 51 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2), 52 PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2), 53 PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2), 54 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 55 PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2), 56 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 57 PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2), 58 PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3), 59 PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3), 60 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 61 PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3), 62 }; 63 64 /* 65 * Applicable for 2650 Type PLL for AUD_PLL. 66 */ 67 static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = { 68 PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0), 69 PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0), 70 PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0), 71 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0), 72 PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0), 73 PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0), 74 PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0), 75 PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0), 76 PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0), 77 PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282), 78 PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0), 79 PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0), 80 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0), 81 PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0), 82 PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0), 83 PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0), 84 PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0), 85 PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0), 86 }; 87 88 /* CMU_AUD */ 89 90 static const unsigned long aud_clk_regs[] __initconst = { 91 MUX_SEL_AUD, 92 DIV_AUD0, 93 DIV_AUD1, 94 EN_ACLK_AUD, 95 EN_PCLK_AUD, 96 EN_SCLK_AUD, 97 EN_IP_AUD, 98 }; 99 100 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"}; 101 PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"}; 102 PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"}; 103 104 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 105 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p, 106 MUX_SEL_AUD, 0, 1), 107 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, 108 MUX_SEL_AUD, 4, 1), 109 MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, 110 MUX_SEL_AUD, 8, 1), 111 }; 112 113 static const struct samsung_div_clock aud_div_clks[] __initconst = { 114 DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user", 115 DIV_AUD0, 0, 4), 116 117 DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s", 118 DIV_AUD1, 0, 4), 119 DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm", 120 DIV_AUD1, 4, 8), 121 DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user", 122 DIV_AUD1, 12, 4), 123 }; 124 125 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 126 GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s", 127 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0), 128 GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", 129 EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0), 130 GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart", 131 EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0), 132 133 GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD, 134 0, 0, 0), 135 GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131", 136 EN_IP_AUD, 1, 0, 0), 137 GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0), 138 GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0), 139 GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131", 140 EN_IP_AUD, 4, 0, 0), 141 }; 142 143 static const struct samsung_cmu_info aud_cmu __initconst = { 144 .mux_clks = aud_mux_clks, 145 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 146 .div_clks = aud_div_clks, 147 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 148 .gate_clks = aud_gate_clks, 149 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 150 .nr_clk_ids = CLKS_NR_AUD, 151 .clk_regs = aud_clk_regs, 152 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 153 }; 154 155 static void __init exynos5260_clk_aud_init(struct device_node *np) 156 { 157 samsung_cmu_register_one(np, &aud_cmu); 158 } 159 160 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud", 161 exynos5260_clk_aud_init); 162 163 164 /* CMU_DISP */ 165 166 static const unsigned long disp_clk_regs[] __initconst = { 167 MUX_SEL_DISP0, 168 MUX_SEL_DISP1, 169 MUX_SEL_DISP2, 170 MUX_SEL_DISP3, 171 MUX_SEL_DISP4, 172 DIV_DISP, 173 EN_ACLK_DISP, 174 EN_PCLK_DISP, 175 EN_SCLK_DISP0, 176 EN_SCLK_DISP1, 177 EN_IP_DISP, 178 EN_IP_DISP_BUS, 179 }; 180 181 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll", 182 "phyclk_dptx_phy_ch3_txd_clk"}; 183 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll", 184 "phyclk_dptx_phy_ch2_txd_clk"}; 185 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll", 186 "phyclk_dptx_phy_ch1_txd_clk"}; 187 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll", 188 "phyclk_dptx_phy_ch0_txd_clk"}; 189 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"}; 190 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"}; 191 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"}; 192 PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll", 193 "phyclk_hdmi_phy_tmds_clko"}; 194 PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll", 195 "phyclk_hdmi_phy_ref_clko"}; 196 PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll", 197 "phyclk_hdmi_phy_pixel_clko"}; 198 PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll", 199 "phyclk_hdmi_link_o_tmds_clkhi"}; 200 PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll", 201 "phyclk_mipi_dphy_4l_m_txbyte_clkhs"}; 202 PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll", 203 "phyclk_dptx_phy_o_ref_clk_24m"}; 204 PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll", 205 "phyclk_dptx_phy_clk_div2"}; 206 PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user", 207 "mout_aclk_disp_222_user"}; 208 PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll", 209 "phyclk_mipi_dphy_4l_m_rxclkesc0"}; 210 PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", 211 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; 212 213 static const struct samsung_mux_clock disp_mux_clks[] __initconst = { 214 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 215 mout_aclk_disp_333_user_p, 216 MUX_SEL_DISP0, 0, 1), 217 MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user", 218 mout_sclk_disp_pixel_user_p, 219 MUX_SEL_DISP0, 4, 1), 220 MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user", 221 mout_aclk_disp_222_user_p, 222 MUX_SEL_DISP0, 8, 1), 223 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER, 224 "mout_phyclk_dptx_phy_ch0_txd_clk_user", 225 mout_phyclk_dptx_phy_ch0_txd_clk_user_p, 226 MUX_SEL_DISP0, 16, 1), 227 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER, 228 "mout_phyclk_dptx_phy_ch1_txd_clk_user", 229 mout_phyclk_dptx_phy_ch1_txd_clk_user_p, 230 MUX_SEL_DISP0, 20, 1), 231 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER, 232 "mout_phyclk_dptx_phy_ch2_txd_clk_user", 233 mout_phyclk_dptx_phy_ch2_txd_clk_user_p, 234 MUX_SEL_DISP0, 24, 1), 235 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER, 236 "mout_phyclk_dptx_phy_ch3_txd_clk_user", 237 mout_phyclk_dptx_phy_ch3_txd_clk_user_p, 238 MUX_SEL_DISP0, 28, 1), 239 240 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER, 241 "mout_phyclk_dptx_phy_clk_div2_user", 242 mout_phyclk_dptx_phy_clk_div2_user_p, 243 MUX_SEL_DISP1, 0, 1), 244 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER, 245 "mout_phyclk_dptx_phy_o_ref_clk_24m_user", 246 mout_phyclk_dptx_phy_o_ref_clk_24m_user_p, 247 MUX_SEL_DISP1, 4, 1), 248 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS, 249 "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs", 250 mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, 251 MUX_SEL_DISP1, 8, 1), 252 MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER, 253 "mout_phyclk_hdmi_link_o_tmds_clkhi_user", 254 mout_phyclk_hdmi_link_o_tmds_clkhi_user_p, 255 MUX_SEL_DISP1, 16, 1), 256 MUX(DISP_MOUT_HDMI_PHY_PIXEL, 257 "mout_phyclk_hdmi_phy_pixel_clko_user", 258 mout_phyclk_hdmi_phy_pixel_clko_user_p, 259 MUX_SEL_DISP1, 20, 1), 260 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER, 261 "mout_phyclk_hdmi_phy_ref_clko_user", 262 mout_phyclk_hdmi_phy_ref_clko_user_p, 263 MUX_SEL_DISP1, 24, 1), 264 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER, 265 "mout_phyclk_hdmi_phy_tmds_clko_user", 266 mout_phyclk_hdmi_phy_tmds_clko_user_p, 267 MUX_SEL_DISP1, 28, 1), 268 269 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER, 270 "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user", 271 mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p, 272 MUX_SEL_DISP2, 0, 1), 273 MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel", 274 mout_sclk_hdmi_pixel_p, 275 MUX_SEL_DISP2, 4, 1), 276 277 MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 278 mout_sclk_hdmi_spdif_p, 279 MUX_SEL_DISP4, 4, 2), 280 }; 281 282 static const struct samsung_div_clock disp_div_clks[] __initconst = { 283 DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111", 284 "mout_aclk_disp_222_user", 285 DIV_DISP, 8, 4), 286 DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll", 287 "mout_sclk_disp_pixel_user", 288 DIV_DISP, 12, 4), 289 DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI, 290 "dout_sclk_hdmi_phy_pixel_clki", 291 "mout_sclk_hdmi_pixel", 292 DIV_DISP, 16, 4), 293 }; 294 295 static const struct samsung_gate_clock disp_gate_clks[] __initconst = { 296 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel", 297 "mout_phyclk_hdmi_phy_pixel_clko_user", 298 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0), 299 GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki", 300 "dout_sclk_hdmi_phy_pixel_clki", 301 EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0), 302 303 GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user", 304 EN_IP_DISP, 4, 0, 0), 305 GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user", 306 EN_IP_DISP, 5, 0, 0), 307 GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user", 308 EN_IP_DISP, 6, 0, 0), 309 GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user", 310 EN_IP_DISP, 7, 0, 0), 311 GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user", 312 EN_IP_DISP, 8, 0, 0), 313 GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user", 314 EN_IP_DISP, 9, 0, 0), 315 GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user", 316 EN_IP_DISP, 10, 0, 0), 317 GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user", 318 EN_IP_DISP, 11, 0, 0), 319 GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user", 320 EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0), 321 GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user", 322 EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0), 323 GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0", 324 "mout_aclk_disp_222_user", 325 EN_IP_DISP, 22, 0, 0), 326 GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1", 327 "mout_aclk_disp_222_user", 328 EN_IP_DISP, 23, 0, 0), 329 GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user", 330 EN_IP_DISP, 25, 0, 0), 331 }; 332 333 static const struct samsung_cmu_info disp_cmu __initconst = { 334 .mux_clks = disp_mux_clks, 335 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), 336 .div_clks = disp_div_clks, 337 .nr_div_clks = ARRAY_SIZE(disp_div_clks), 338 .gate_clks = disp_gate_clks, 339 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), 340 .nr_clk_ids = CLKS_NR_DISP, 341 .clk_regs = disp_clk_regs, 342 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 343 }; 344 345 static void __init exynos5260_clk_disp_init(struct device_node *np) 346 { 347 samsung_cmu_register_one(np, &disp_cmu); 348 } 349 350 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp", 351 exynos5260_clk_disp_init); 352 353 354 /* CMU_EGL */ 355 356 static const unsigned long egl_clk_regs[] __initconst = { 357 EGL_PLL_LOCK, 358 EGL_PLL_CON0, 359 EGL_PLL_CON1, 360 EGL_PLL_FREQ_DET, 361 MUX_SEL_EGL, 362 MUX_ENABLE_EGL, 363 DIV_EGL, 364 DIV_EGL_PLL_FDET, 365 EN_ACLK_EGL, 366 EN_PCLK_EGL, 367 EN_SCLK_EGL, 368 }; 369 370 PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; 371 PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; 372 373 static const struct samsung_mux_clock egl_mux_clks[] __initconst = { 374 MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p, 375 MUX_SEL_EGL, 4, 1), 376 MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), 377 }; 378 379 static const struct samsung_div_clock egl_div_clks[] __initconst = { 380 DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), 381 DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), 382 DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), 383 DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk", 384 DIV_EGL, 12, 3), 385 DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3), 386 DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk", 387 DIV_EGL, 20, 3), 388 DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3), 389 }; 390 391 static const struct samsung_pll_clock egl_pll_clks[] __initconst = { 392 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll", 393 EGL_PLL_LOCK, EGL_PLL_CON0, 394 pll2550_24mhz_tbl), 395 }; 396 397 static const struct samsung_cmu_info egl_cmu __initconst = { 398 .pll_clks = egl_pll_clks, 399 .nr_pll_clks = ARRAY_SIZE(egl_pll_clks), 400 .mux_clks = egl_mux_clks, 401 .nr_mux_clks = ARRAY_SIZE(egl_mux_clks), 402 .div_clks = egl_div_clks, 403 .nr_div_clks = ARRAY_SIZE(egl_div_clks), 404 .nr_clk_ids = CLKS_NR_EGL, 405 .clk_regs = egl_clk_regs, 406 .nr_clk_regs = ARRAY_SIZE(egl_clk_regs), 407 }; 408 409 static void __init exynos5260_clk_egl_init(struct device_node *np) 410 { 411 samsung_cmu_register_one(np, &egl_cmu); 412 } 413 414 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl", 415 exynos5260_clk_egl_init); 416 417 418 /* CMU_FSYS */ 419 420 static const unsigned long fsys_clk_regs[] __initconst = { 421 MUX_SEL_FSYS0, 422 MUX_SEL_FSYS1, 423 EN_ACLK_FSYS, 424 EN_ACLK_FSYS_SECURE_RTIC, 425 EN_ACLK_FSYS_SECURE_SMMU_RTIC, 426 EN_SCLK_FSYS, 427 EN_IP_FSYS, 428 EN_IP_FSYS_SECURE_RTIC, 429 EN_IP_FSYS_SECURE_SMMU_RTIC, 430 }; 431 432 PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll", 433 "phyclk_usbhost20_phy_phyclock"}; 434 PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll", 435 "phyclk_usbhost20_phy_freeclk"}; 436 PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll", 437 "phyclk_usbhost20_phy_clk48mohci"}; 438 PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll", 439 "phyclk_usbdrd30_udrd30_pipe_pclk"}; 440 PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", 441 "phyclk_usbdrd30_udrd30_phyclock"}; 442 443 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 444 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER, 445 "mout_phyclk_usbdrd30_phyclock_user", 446 mout_phyclk_usbdrd30_phyclock_user_p, 447 MUX_SEL_FSYS1, 0, 1), 448 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER, 449 "mout_phyclk_usbdrd30_pipe_pclk_user", 450 mout_phyclk_usbdrd30_pipe_pclk_user_p, 451 MUX_SEL_FSYS1, 4, 1), 452 MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER, 453 "mout_phyclk_usbhost20_clk48mohci_user", 454 mout_phyclk_usbhost20_clk48mohci_user_p, 455 MUX_SEL_FSYS1, 8, 1), 456 MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER, 457 "mout_phyclk_usbhost20_freeclk_user", 458 mout_phyclk_usbhost20_freeclk_user_p, 459 MUX_SEL_FSYS1, 12, 1), 460 MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER, 461 "mout_phyclk_usbhost20_phyclk_user", 462 mout_phyclk_usbhost20_phyclk_user_p, 463 MUX_SEL_FSYS1, 16, 1), 464 }; 465 466 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 467 GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", 468 "mout_phyclk_usbdrd30_phyclock_user", 469 EN_SCLK_FSYS, 1, 0, 0), 470 GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g", 471 "mout_phyclk_usbdrd30_phyclock_user", 472 EN_SCLK_FSYS, 7, 0, 0), 473 474 GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200", 475 EN_IP_FSYS, 6, 0, 0), 476 GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200", 477 EN_IP_FSYS, 7, 0, 0), 478 GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200", 479 EN_IP_FSYS, 8, 0, 0), 480 GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200", 481 EN_IP_FSYS, 9, 0, 0), 482 GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200", 483 EN_IP_FSYS, 13, 0, 0), 484 GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200", 485 EN_IP_FSYS, 14, 0, 0), 486 GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200", 487 EN_IP_FSYS, 15, 0, 0), 488 GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200", 489 EN_IP_FSYS, 18, 0, 0), 490 GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200", 491 EN_IP_FSYS, 20, 0, 0), 492 493 GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200", 494 EN_IP_FSYS_SECURE_RTIC, 11, 0, 0), 495 GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200", 496 EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0), 497 }; 498 499 static const struct samsung_cmu_info fsys_cmu __initconst = { 500 .mux_clks = fsys_mux_clks, 501 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 502 .gate_clks = fsys_gate_clks, 503 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 504 .nr_clk_ids = CLKS_NR_FSYS, 505 .clk_regs = fsys_clk_regs, 506 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 507 }; 508 509 static void __init exynos5260_clk_fsys_init(struct device_node *np) 510 { 511 samsung_cmu_register_one(np, &fsys_cmu); 512 } 513 514 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys", 515 exynos5260_clk_fsys_init); 516 517 518 /* CMU_G2D */ 519 520 static const unsigned long g2d_clk_regs[] __initconst = { 521 MUX_SEL_G2D, 522 MUX_STAT_G2D, 523 DIV_G2D, 524 EN_ACLK_G2D, 525 EN_ACLK_G2D_SECURE_SSS, 526 EN_ACLK_G2D_SECURE_SLIM_SSS, 527 EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS, 528 EN_ACLK_G2D_SECURE_SMMU_SSS, 529 EN_ACLK_G2D_SECURE_SMMU_MDMA, 530 EN_ACLK_G2D_SECURE_SMMU_G2D, 531 EN_PCLK_G2D, 532 EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS, 533 EN_PCLK_G2D_SECURE_SMMU_SSS, 534 EN_PCLK_G2D_SECURE_SMMU_MDMA, 535 EN_PCLK_G2D_SECURE_SMMU_G2D, 536 EN_IP_G2D, 537 EN_IP_G2D_SECURE_SSS, 538 EN_IP_G2D_SECURE_SLIM_SSS, 539 EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 540 EN_IP_G2D_SECURE_SMMU_SSS, 541 EN_IP_G2D_SECURE_SMMU_MDMA, 542 EN_IP_G2D_SECURE_SMMU_G2D, 543 }; 544 545 PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; 546 547 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { 548 MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user", 549 mout_aclk_g2d_333_user_p, 550 MUX_SEL_G2D, 0, 1), 551 }; 552 553 static const struct samsung_div_clock g2d_div_clks[] __initconst = { 554 DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", 555 DIV_G2D, 0, 3), 556 }; 557 558 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { 559 GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user", 560 EN_IP_G2D, 4, 0, 0), 561 GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user", 562 EN_IP_G2D, 5, 0, 0), 563 GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user", 564 EN_IP_G2D, 6, 0, 0), 565 GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user", 566 EN_IP_G2D, 16, 0, 0), 567 568 GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user", 569 EN_IP_G2D_SECURE_SSS, 17, 0, 0), 570 571 GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user", 572 EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0), 573 574 GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss", 575 "mout_aclk_g2d_333_user", 576 EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0), 577 578 GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user", 579 EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0), 580 581 GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user", 582 EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0), 583 584 GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user", 585 EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0), 586 }; 587 588 static const struct samsung_cmu_info g2d_cmu __initconst = { 589 .mux_clks = g2d_mux_clks, 590 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 591 .div_clks = g2d_div_clks, 592 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 593 .gate_clks = g2d_gate_clks, 594 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 595 .nr_clk_ids = CLKS_NR_G2D, 596 .clk_regs = g2d_clk_regs, 597 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 598 }; 599 600 static void __init exynos5260_clk_g2d_init(struct device_node *np) 601 { 602 samsung_cmu_register_one(np, &g2d_cmu); 603 } 604 605 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d", 606 exynos5260_clk_g2d_init); 607 608 609 /* CMU_G3D */ 610 611 static const unsigned long g3d_clk_regs[] __initconst = { 612 G3D_PLL_LOCK, 613 G3D_PLL_CON0, 614 G3D_PLL_CON1, 615 G3D_PLL_FDET, 616 MUX_SEL_G3D, 617 DIV_G3D, 618 DIV_G3D_PLL_FDET, 619 EN_ACLK_G3D, 620 EN_PCLK_G3D, 621 EN_SCLK_G3D, 622 EN_IP_G3D, 623 }; 624 625 PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; 626 627 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 628 MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 629 MUX_SEL_G3D, 0, 1), 630 }; 631 632 static const struct samsung_div_clock g3d_div_clks[] __initconst = { 633 DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), 634 DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), 635 }; 636 637 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 638 GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0), 639 GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d", 640 EN_IP_G3D, 3, 0, 0), 641 }; 642 643 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 644 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll", 645 G3D_PLL_LOCK, G3D_PLL_CON0, 646 pll2550_24mhz_tbl), 647 }; 648 649 static const struct samsung_cmu_info g3d_cmu __initconst = { 650 .pll_clks = g3d_pll_clks, 651 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 652 .mux_clks = g3d_mux_clks, 653 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 654 .div_clks = g3d_div_clks, 655 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 656 .gate_clks = g3d_gate_clks, 657 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 658 .nr_clk_ids = CLKS_NR_G3D, 659 .clk_regs = g3d_clk_regs, 660 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 661 }; 662 663 static void __init exynos5260_clk_g3d_init(struct device_node *np) 664 { 665 samsung_cmu_register_one(np, &g3d_cmu); 666 } 667 668 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d", 669 exynos5260_clk_g3d_init); 670 671 672 /* CMU_GSCL */ 673 674 static const unsigned long gscl_clk_regs[] __initconst = { 675 MUX_SEL_GSCL, 676 DIV_GSCL, 677 EN_ACLK_GSCL, 678 EN_ACLK_GSCL_FIMC, 679 EN_ACLK_GSCL_SECURE_SMMU_GSCL0, 680 EN_ACLK_GSCL_SECURE_SMMU_GSCL1, 681 EN_ACLK_GSCL_SECURE_SMMU_MSCL0, 682 EN_ACLK_GSCL_SECURE_SMMU_MSCL1, 683 EN_PCLK_GSCL, 684 EN_PCLK_GSCL_FIMC, 685 EN_PCLK_GSCL_SECURE_SMMU_GSCL0, 686 EN_PCLK_GSCL_SECURE_SMMU_GSCL1, 687 EN_PCLK_GSCL_SECURE_SMMU_MSCL0, 688 EN_PCLK_GSCL_SECURE_SMMU_MSCL1, 689 EN_SCLK_GSCL, 690 EN_SCLK_GSCL_FIMC, 691 EN_IP_GSCL, 692 EN_IP_GSCL_FIMC, 693 EN_IP_GSCL_SECURE_SMMU_GSCL0, 694 EN_IP_GSCL_SECURE_SMMU_GSCL1, 695 EN_IP_GSCL_SECURE_SMMU_MSCL0, 696 EN_IP_GSCL_SECURE_SMMU_MSCL1, 697 }; 698 699 PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"}; 700 PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; 701 PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; 702 PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; 703 704 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { 705 MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 706 mout_aclk_gscl_333_user_p, 707 MUX_SEL_GSCL, 0, 1), 708 MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user", 709 mout_aclk_m2m_400_user_p, 710 MUX_SEL_GSCL, 4, 1), 711 MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user", 712 mout_aclk_gscl_fimc_user_p, 713 MUX_SEL_GSCL, 8, 1), 714 MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p, 715 MUX_SEL_GSCL, 24, 1), 716 }; 717 718 static const struct samsung_div_clock gscl_div_clks[] __initconst = { 719 DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100", 720 "mout_aclk_m2m_400_user", 721 DIV_GSCL, 0, 3), 722 DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200", 723 "mout_aclk_m2m_400_user", 724 DIV_GSCL, 4, 3), 725 }; 726 727 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { 728 GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200", 729 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0), 730 GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200", 731 EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0), 732 733 GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user", 734 EN_IP_GSCL, 2, 0, 0), 735 GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user", 736 EN_IP_GSCL, 3, 0, 0), 737 GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user", 738 EN_IP_GSCL, 4, 0, 0), 739 GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user", 740 EN_IP_GSCL, 5, 0, 0), 741 GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0", 742 "mout_aclk_gscl_333_user", 743 EN_IP_GSCL, 8, 0, 0), 744 GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1", 745 "mout_aclk_gscl_333_user", 746 EN_IP_GSCL, 9, 0, 0), 747 748 GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a", 749 "mout_aclk_gscl_fimc_user", 750 EN_IP_GSCL_FIMC, 5, 0, 0), 751 GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b", 752 "mout_aclk_gscl_fimc_user", 753 EN_IP_GSCL_FIMC, 6, 0, 0), 754 GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d", 755 "mout_aclk_gscl_fimc_user", 756 EN_IP_GSCL_FIMC, 7, 0, 0), 757 GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user", 758 EN_IP_GSCL_FIMC, 8, 0, 0), 759 GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user", 760 EN_IP_GSCL_FIMC, 9, 0, 0), 761 GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a", 762 "mout_aclk_gscl_fimc_user", 763 EN_IP_GSCL_FIMC, 10, 0, 0), 764 GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b", 765 "mout_aclk_gscl_fimc_user", 766 EN_IP_GSCL_FIMC, 11, 0, 0), 767 GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d", 768 "mout_aclk_gscl_fimc_user", 769 EN_IP_GSCL_FIMC, 12, 0, 0), 770 771 GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0", 772 "mout_aclk_gscl_333_user", 773 EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0), 774 GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user", 775 EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0), 776 GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0", 777 "mout_aclk_m2m_400_user", 778 EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0), 779 GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1", 780 "mout_aclk_m2m_400_user", 781 EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0), 782 }; 783 784 static const struct samsung_cmu_info gscl_cmu __initconst = { 785 .mux_clks = gscl_mux_clks, 786 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 787 .div_clks = gscl_div_clks, 788 .nr_div_clks = ARRAY_SIZE(gscl_div_clks), 789 .gate_clks = gscl_gate_clks, 790 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), 791 .nr_clk_ids = CLKS_NR_GSCL, 792 .clk_regs = gscl_clk_regs, 793 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 794 }; 795 796 static void __init exynos5260_clk_gscl_init(struct device_node *np) 797 { 798 samsung_cmu_register_one(np, &gscl_cmu); 799 } 800 801 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl", 802 exynos5260_clk_gscl_init); 803 804 805 /* CMU_ISP */ 806 807 static const unsigned long isp_clk_regs[] __initconst = { 808 MUX_SEL_ISP0, 809 MUX_SEL_ISP1, 810 DIV_ISP, 811 EN_ACLK_ISP0, 812 EN_ACLK_ISP1, 813 EN_PCLK_ISP0, 814 EN_PCLK_ISP1, 815 EN_SCLK_ISP, 816 EN_IP_ISP0, 817 EN_IP_ISP1, 818 }; 819 820 PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; 821 PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; 822 823 static const struct samsung_mux_clock isp_mux_clks[] __initconst = { 824 MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p, 825 MUX_SEL_ISP0, 0, 1), 826 MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p, 827 MUX_SEL_ISP0, 4, 1), 828 }; 829 830 static const struct samsung_div_clock isp_div_clks[] __initconst = { 831 DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc", 832 DIV_ISP, 0, 3), 833 DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc", 834 DIV_ISP, 4, 4), 835 DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc", 836 DIV_ISP, 12, 3), 837 DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc", 838 DIV_ISP, 16, 4), 839 DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), 840 }; 841 842 static const struct samsung_gate_clock isp_gate_clks[] __initconst = { 843 GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266", 844 EN_IP_ISP0, 15, 0, 0), 845 846 GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266", 847 EN_IP_ISP1, 1, 0, 0), 848 GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266", 849 EN_IP_ISP1, 2, 0, 0), 850 GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266", 851 EN_IP_ISP1, 3, 0, 0), 852 GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266", 853 EN_IP_ISP1, 4, 0, 0), 854 GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc", 855 "mout_aclk_isp1_266", 856 EN_IP_ISP1, 5, 0, 0), 857 GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp", 858 "mout_aclk_isp1_266", 859 EN_IP_ISP1, 6, 0, 0), 860 GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266", 861 EN_IP_ISP1, 7, 0, 0), 862 GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266", 863 EN_IP_ISP1, 8, 0, 0), 864 GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266", 865 EN_IP_ISP1, 9, 0, 0), 866 GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266", 867 EN_IP_ISP1, 10, 0, 0), 868 GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266", 869 EN_IP_ISP1, 11, 0, 0), 870 GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266", 871 EN_IP_ISP1, 14, 0, 0), 872 GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266", 873 EN_IP_ISP1, 21, 0, 0), 874 GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266", 875 EN_IP_ISP1, 22, 0, 0), 876 GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266", 877 EN_IP_ISP1, 23, 0, 0), 878 GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266", 879 EN_IP_ISP1, 24, 0, 0), 880 GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc", 881 "mout_aclk_isp1_266", 882 EN_IP_ISP1, 25, 0, 0), 883 GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp", 884 "mout_aclk_isp1_266", 885 EN_IP_ISP1, 26, 0, 0), 886 GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266", 887 EN_IP_ISP1, 27, 0, 0), 888 GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266", 889 EN_IP_ISP1, 28, 0, 0), 890 GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266", 891 EN_IP_ISP1, 31, 0, 0), 892 GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266", 893 EN_IP_ISP1, 30, 0, 0), 894 895 GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll", 896 EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0), 897 GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll", 898 EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 899 GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll", 900 EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0), 901 }; 902 903 static const struct samsung_cmu_info isp_cmu __initconst = { 904 .mux_clks = isp_mux_clks, 905 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 906 .div_clks = isp_div_clks, 907 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 908 .gate_clks = isp_gate_clks, 909 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 910 .nr_clk_ids = CLKS_NR_ISP, 911 .clk_regs = isp_clk_regs, 912 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 913 }; 914 915 static void __init exynos5260_clk_isp_init(struct device_node *np) 916 { 917 samsung_cmu_register_one(np, &isp_cmu); 918 } 919 920 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp", 921 exynos5260_clk_isp_init); 922 923 924 /* CMU_KFC */ 925 926 static const unsigned long kfc_clk_regs[] __initconst = { 927 KFC_PLL_LOCK, 928 KFC_PLL_CON0, 929 KFC_PLL_CON1, 930 KFC_PLL_FDET, 931 MUX_SEL_KFC0, 932 MUX_SEL_KFC2, 933 DIV_KFC, 934 DIV_KFC_PLL_FDET, 935 EN_ACLK_KFC, 936 EN_PCLK_KFC, 937 EN_SCLK_KFC, 938 EN_IP_KFC, 939 }; 940 941 PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; 942 PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; 943 944 static const struct samsung_mux_clock kfc_mux_clks[] __initconst = { 945 MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p, 946 MUX_SEL_KFC0, 0, 1), 947 MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), 948 }; 949 950 static const struct samsung_div_clock kfc_div_clks[] __initconst = { 951 DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), 952 DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), 953 DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), 954 DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2", 955 DIV_KFC, 12, 3), 956 DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3), 957 DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3), 958 DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3), 959 }; 960 961 static const struct samsung_pll_clock kfc_pll_clks[] __initconst = { 962 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll", 963 KFC_PLL_LOCK, KFC_PLL_CON0, 964 pll2550_24mhz_tbl), 965 }; 966 967 static const struct samsung_cmu_info kfc_cmu __initconst = { 968 .pll_clks = kfc_pll_clks, 969 .nr_pll_clks = ARRAY_SIZE(kfc_pll_clks), 970 .mux_clks = kfc_mux_clks, 971 .nr_mux_clks = ARRAY_SIZE(kfc_mux_clks), 972 .div_clks = kfc_div_clks, 973 .nr_div_clks = ARRAY_SIZE(kfc_div_clks), 974 .nr_clk_ids = CLKS_NR_KFC, 975 .clk_regs = kfc_clk_regs, 976 .nr_clk_regs = ARRAY_SIZE(kfc_clk_regs), 977 }; 978 979 static void __init exynos5260_clk_kfc_init(struct device_node *np) 980 { 981 samsung_cmu_register_one(np, &kfc_cmu); 982 } 983 984 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc", 985 exynos5260_clk_kfc_init); 986 987 988 /* CMU_MFC */ 989 990 static const unsigned long mfc_clk_regs[] __initconst = { 991 MUX_SEL_MFC, 992 DIV_MFC, 993 EN_ACLK_MFC, 994 EN_ACLK_SECURE_SMMU2_MFC, 995 EN_PCLK_MFC, 996 EN_PCLK_SECURE_SMMU2_MFC, 997 EN_IP_MFC, 998 EN_IP_MFC_SECURE_SMMU2_MFC, 999 }; 1000 1001 PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; 1002 1003 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 1004 MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user", 1005 mout_aclk_mfc_333_user_p, 1006 MUX_SEL_MFC, 0, 1), 1007 }; 1008 1009 static const struct samsung_div_clock mfc_div_clks[] __initconst = { 1010 DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", 1011 DIV_MFC, 0, 3), 1012 }; 1013 1014 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 1015 GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user", 1016 EN_IP_MFC, 1, 0, 0), 1017 GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user", 1018 EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0), 1019 GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user", 1020 EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0), 1021 }; 1022 1023 static const struct samsung_cmu_info mfc_cmu __initconst = { 1024 .mux_clks = mfc_mux_clks, 1025 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 1026 .div_clks = mfc_div_clks, 1027 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 1028 .gate_clks = mfc_gate_clks, 1029 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 1030 .nr_clk_ids = CLKS_NR_MFC, 1031 .clk_regs = mfc_clk_regs, 1032 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 1033 }; 1034 1035 static void __init exynos5260_clk_mfc_init(struct device_node *np) 1036 { 1037 samsung_cmu_register_one(np, &mfc_cmu); 1038 } 1039 1040 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc", 1041 exynos5260_clk_mfc_init); 1042 1043 1044 /* CMU_MIF */ 1045 1046 static const unsigned long mif_clk_regs[] __initconst = { 1047 MEM_PLL_LOCK, 1048 BUS_PLL_LOCK, 1049 MEDIA_PLL_LOCK, 1050 MEM_PLL_CON0, 1051 MEM_PLL_CON1, 1052 MEM_PLL_FDET, 1053 BUS_PLL_CON0, 1054 BUS_PLL_CON1, 1055 BUS_PLL_FDET, 1056 MEDIA_PLL_CON0, 1057 MEDIA_PLL_CON1, 1058 MEDIA_PLL_FDET, 1059 MUX_SEL_MIF, 1060 DIV_MIF, 1061 DIV_MIF_PLL_FDET, 1062 EN_ACLK_MIF, 1063 EN_ACLK_MIF_SECURE_DREX1_TZ, 1064 EN_ACLK_MIF_SECURE_DREX0_TZ, 1065 EN_ACLK_MIF_SECURE_INTMEM, 1066 EN_PCLK_MIF, 1067 EN_PCLK_MIF_SECURE_MONOCNT, 1068 EN_PCLK_MIF_SECURE_RTC_APBIF, 1069 EN_PCLK_MIF_SECURE_DREX1_TZ, 1070 EN_PCLK_MIF_SECURE_DREX0_TZ, 1071 EN_SCLK_MIF, 1072 EN_IP_MIF, 1073 EN_IP_MIF_SECURE_MONOCNT, 1074 EN_IP_MIF_SECURE_RTC_APBIF, 1075 EN_IP_MIF_SECURE_DREX1_TZ, 1076 EN_IP_MIF_SECURE_DREX0_TZ, 1077 EN_IP_MIF_SECURE_INTEMEM, 1078 }; 1079 1080 PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"}; 1081 PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"}; 1082 PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"}; 1083 PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"}; 1084 PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"}; 1085 PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; 1086 PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; 1087 1088 static const struct samsung_mux_clock mif_mux_clks[] __initconst = { 1089 MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p, 1090 MUX_SEL_MIF, 0, 1), 1091 MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, 1092 MUX_SEL_MIF, 4, 1), 1093 MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p, 1094 MUX_SEL_MIF, 8, 1), 1095 MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p, 1096 MUX_SEL_MIF, 12, 1), 1097 MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p, 1098 MUX_SEL_MIF, 16, 1), 1099 MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p, 1100 MUX_SEL_MIF, 20, 1), 1101 MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p, 1102 MUX_SEL_MIF, 24, 1), 1103 }; 1104 1105 static const struct samsung_div_clock mif_div_clks[] __initconst = { 1106 DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll", 1107 DIV_MIF, 0, 3), 1108 DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll", 1109 DIV_MIF, 4, 3), 1110 DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1111 DIV_MIF, 8, 3), 1112 DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy", 1113 DIV_MIF, 12, 3), 1114 DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy", 1115 DIV_MIF, 16, 4), 1116 DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy", 1117 DIV_MIF, 20, 3), 1118 DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll", 1119 DIV_MIF, 24, 3), 1120 DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll", 1121 DIV_MIF, 28, 4), 1122 }; 1123 1124 static const struct samsung_gate_clock mif_gate_clks[] __initconst = { 1125 GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy", 1126 EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0), 1127 GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy", 1128 EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0), 1129 1130 GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100", 1131 EN_IP_MIF_SECURE_MONOCNT, 22, 1132 CLK_IGNORE_UNUSED, 0), 1133 1134 GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100", 1135 EN_IP_MIF_SECURE_RTC_APBIF, 23, 1136 CLK_IGNORE_UNUSED, 0), 1137 1138 GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466", 1139 EN_IP_MIF_SECURE_DREX1_TZ, 9, 1140 CLK_IGNORE_UNUSED, 0), 1141 1142 GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466", 1143 EN_IP_MIF_SECURE_DREX0_TZ, 9, 1144 CLK_IGNORE_UNUSED, 0), 1145 1146 GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200", 1147 EN_IP_MIF_SECURE_INTEMEM, 11, 1148 CLK_IGNORE_UNUSED, 0), 1149 1150 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0", 1151 "dout_clkm_phy", EN_SCLK_MIF, 0, 1152 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1153 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1", 1154 "dout_clkm_phy", EN_SCLK_MIF, 1, 1155 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1156 }; 1157 1158 static const struct samsung_pll_clock mif_pll_clks[] __initconst = { 1159 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll", 1160 MEM_PLL_LOCK, MEM_PLL_CON0, 1161 pll2550_24mhz_tbl), 1162 PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll", 1163 BUS_PLL_LOCK, BUS_PLL_CON0, 1164 pll2550_24mhz_tbl), 1165 PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll", 1166 MEDIA_PLL_LOCK, MEDIA_PLL_CON0, 1167 pll2550_24mhz_tbl), 1168 }; 1169 1170 static const struct samsung_cmu_info mif_cmu __initconst = { 1171 .pll_clks = mif_pll_clks, 1172 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1173 .mux_clks = mif_mux_clks, 1174 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), 1175 .div_clks = mif_div_clks, 1176 .nr_div_clks = ARRAY_SIZE(mif_div_clks), 1177 .gate_clks = mif_gate_clks, 1178 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1179 .nr_clk_ids = CLKS_NR_MIF, 1180 .clk_regs = mif_clk_regs, 1181 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1182 }; 1183 1184 static void __init exynos5260_clk_mif_init(struct device_node *np) 1185 { 1186 samsung_cmu_register_one(np, &mif_cmu); 1187 } 1188 1189 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif", 1190 exynos5260_clk_mif_init); 1191 1192 1193 /* CMU_PERI */ 1194 1195 static const unsigned long peri_clk_regs[] __initconst = { 1196 MUX_SEL_PERI, 1197 MUX_SEL_PERI1, 1198 DIV_PERI, 1199 EN_PCLK_PERI0, 1200 EN_PCLK_PERI1, 1201 EN_PCLK_PERI2, 1202 EN_PCLK_PERI3, 1203 EN_PCLK_PERI_SECURE_CHIPID, 1204 EN_PCLK_PERI_SECURE_PROVKEY0, 1205 EN_PCLK_PERI_SECURE_PROVKEY1, 1206 EN_PCLK_PERI_SECURE_SECKEY, 1207 EN_PCLK_PERI_SECURE_ANTIRBKCNT, 1208 EN_PCLK_PERI_SECURE_TOP_RTC, 1209 EN_PCLK_PERI_SECURE_TZPC, 1210 EN_SCLK_PERI, 1211 EN_SCLK_PERI_SECURE_TOP_RTC, 1212 EN_IP_PERI0, 1213 EN_IP_PERI1, 1214 EN_IP_PERI2, 1215 EN_IP_PERI_SECURE_CHIPID, 1216 EN_IP_PERI_SECURE_PROVKEY0, 1217 EN_IP_PERI_SECURE_PROVKEY1, 1218 EN_IP_PERI_SECURE_SECKEY, 1219 EN_IP_PERI_SECURE_ANTIRBKCNT, 1220 EN_IP_PERI_SECURE_TOP_RTC, 1221 EN_IP_PERI_SECURE_TZPC, 1222 }; 1223 1224 PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud", 1225 "phyclk_hdmi_phy_ref_cko"}; 1226 PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud", 1227 "phyclk_hdmi_phy_ref_cko"}; 1228 PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll", 1229 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; 1230 1231 static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 1232 MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p, 1233 MUX_SEL_PERI1, 4, 2), 1234 MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p, 1235 MUX_SEL_PERI1, 12, 2), 1236 MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 1237 MUX_SEL_PERI1, 20, 2), 1238 }; 1239 1240 static const struct samsung_div_clock peri_div_clks[] __initconst = { 1241 DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), 1242 DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6), 1243 }; 1244 1245 static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 1246 GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, 1247 CLK_SET_RATE_PARENT, 0), 1248 GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, 1249 CLK_SET_RATE_PARENT, 0), 1250 GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b", 1251 EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0), 1252 GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b", 1253 EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0), 1254 GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b", 1255 EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0), 1256 GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b", 1257 EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0), 1258 GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0", 1259 EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0), 1260 GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1", 1261 EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0), 1262 GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2", 1263 EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0), 1264 1265 GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66", 1266 EN_IP_PERI0, 1, 0, 0), 1267 GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66", 1268 EN_IP_PERI0, 5, 0, 0), 1269 GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66", 1270 EN_IP_PERI0, 6, 0, 0), 1271 GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66", 1272 EN_IP_PERI0, 7, 0, 0), 1273 GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66", 1274 EN_IP_PERI0, 8, 0, 0), 1275 GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66", 1276 EN_IP_PERI0, 9, 0, 0), 1277 GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66", 1278 EN_IP_PERI0, 10, 0, 0), 1279 GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66", 1280 EN_IP_PERI0, 11, 0, 0), 1281 GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66", 1282 EN_IP_PERI0, 12, 0, 0), 1283 GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66", 1284 EN_IP_PERI0, 13, 0, 0), 1285 GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66", 1286 EN_IP_PERI0, 14, 0, 0), 1287 GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66", 1288 EN_IP_PERI0, 15, 0, 0), 1289 GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66", 1290 EN_IP_PERI0, 16, 0, 0), 1291 GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66", 1292 EN_IP_PERI0, 17, 0, 0), 1293 GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66", 1294 EN_IP_PERI0, 18, 0, 0), 1295 GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66", 1296 EN_IP_PERI0, 20, 0, 0), 1297 GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66", 1298 EN_IP_PERI0, 21, 0, 0), 1299 GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66", 1300 EN_IP_PERI0, 22, 0, 0), 1301 GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66", 1302 EN_IP_PERI0, 23, 0, 0), 1303 GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66", 1304 EN_IP_PERI0, 24, 0, 0), 1305 GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66", 1306 EN_IP_PERI0, 25, 0, 0), 1307 1308 GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66", 1309 EN_IP_PERI2, 0, 0, 0), 1310 GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66", 1311 EN_IP_PERI2, 3, 0, 0), 1312 GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66", 1313 EN_IP_PERI2, 6, 0, 0), 1314 GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66", 1315 EN_IP_PERI2, 7, 0, 0), 1316 GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66", 1317 EN_IP_PERI2, 8, 0, 0), 1318 GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66", 1319 EN_IP_PERI2, 9, 0, 0), 1320 GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66", 1321 EN_IP_PERI2, 10, 0, 0), 1322 GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66", 1323 EN_IP_PERI2, 11, 0, 0), 1324 GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66", 1325 EN_IP_PERI2, 12, 0, 0), 1326 GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66", 1327 EN_IP_PERI2, 13, 0, 0), 1328 GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66", 1329 EN_IP_PERI2, 14, 0, 0), 1330 GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66", 1331 EN_IP_PERI2, 18, 0, 0), 1332 GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66", 1333 EN_IP_PERI2, 19, 0, 0), 1334 GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66", 1335 EN_IP_PERI2, 20, 0, 0), 1336 GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66", 1337 EN_IP_PERI2, 21, 0, 0), 1338 1339 GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66", 1340 EN_IP_PERI_SECURE_CHIPID, 2, 0, 0), 1341 1342 GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66", 1343 EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0), 1344 1345 GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66", 1346 EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0), 1347 1348 GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66", 1349 EN_IP_PERI_SECURE_SECKEY, 5, 0, 0), 1350 1351 GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66", 1352 EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0), 1353 1354 GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66", 1355 EN_IP_PERI_SECURE_TZPC, 10, 0, 0), 1356 GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66", 1357 EN_IP_PERI_SECURE_TZPC, 11, 0, 0), 1358 GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66", 1359 EN_IP_PERI_SECURE_TZPC, 12, 0, 0), 1360 GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66", 1361 EN_IP_PERI_SECURE_TZPC, 13, 0, 0), 1362 GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66", 1363 EN_IP_PERI_SECURE_TZPC, 14, 0, 0), 1364 GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66", 1365 EN_IP_PERI_SECURE_TZPC, 15, 0, 0), 1366 GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66", 1367 EN_IP_PERI_SECURE_TZPC, 16, 0, 0), 1368 GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66", 1369 EN_IP_PERI_SECURE_TZPC, 17, 0, 0), 1370 GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66", 1371 EN_IP_PERI_SECURE_TZPC, 18, 0, 0), 1372 GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66", 1373 EN_IP_PERI_SECURE_TZPC, 19, 0, 0), 1374 GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66", 1375 EN_IP_PERI_SECURE_TZPC, 20, 0, 0), 1376 }; 1377 1378 static const struct samsung_cmu_info peri_cmu __initconst = { 1379 .mux_clks = peri_mux_clks, 1380 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 1381 .div_clks = peri_div_clks, 1382 .nr_div_clks = ARRAY_SIZE(peri_div_clks), 1383 .gate_clks = peri_gate_clks, 1384 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 1385 .nr_clk_ids = CLKS_NR_PERI, 1386 .clk_regs = peri_clk_regs, 1387 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 1388 }; 1389 1390 static void __init exynos5260_clk_peri_init(struct device_node *np) 1391 { 1392 samsung_cmu_register_one(np, &peri_cmu); 1393 } 1394 1395 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri", 1396 exynos5260_clk_peri_init); 1397 1398 1399 /* CMU_TOP */ 1400 1401 static const unsigned long top_clk_regs[] __initconst = { 1402 DISP_PLL_LOCK, 1403 AUD_PLL_LOCK, 1404 DISP_PLL_CON0, 1405 DISP_PLL_CON1, 1406 DISP_PLL_FDET, 1407 AUD_PLL_CON0, 1408 AUD_PLL_CON1, 1409 AUD_PLL_CON2, 1410 AUD_PLL_FDET, 1411 MUX_SEL_TOP_PLL0, 1412 MUX_SEL_TOP_MFC, 1413 MUX_SEL_TOP_G2D, 1414 MUX_SEL_TOP_GSCL, 1415 MUX_SEL_TOP_ISP10, 1416 MUX_SEL_TOP_ISP11, 1417 MUX_SEL_TOP_DISP0, 1418 MUX_SEL_TOP_DISP1, 1419 MUX_SEL_TOP_BUS, 1420 MUX_SEL_TOP_PERI0, 1421 MUX_SEL_TOP_PERI1, 1422 MUX_SEL_TOP_FSYS, 1423 DIV_TOP_G2D_MFC, 1424 DIV_TOP_GSCL_ISP0, 1425 DIV_TOP_ISP10, 1426 DIV_TOP_ISP11, 1427 DIV_TOP_DISP, 1428 DIV_TOP_BUS, 1429 DIV_TOP_PERI0, 1430 DIV_TOP_PERI1, 1431 DIV_TOP_PERI2, 1432 DIV_TOP_FSYS0, 1433 DIV_TOP_FSYS1, 1434 DIV_TOP_HPM, 1435 DIV_TOP_PLL_FDET, 1436 EN_ACLK_TOP, 1437 EN_SCLK_TOP, 1438 EN_IP_TOP, 1439 }; 1440 1441 /* fixed rate clocks generated inside the soc */ 1442 static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = { 1443 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL, 1444 0, 270000000), 1445 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL, 1446 0, 270000000), 1447 FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL, 1448 0, 270000000), 1449 FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL, 1450 0, 270000000), 1451 FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL, 1452 0, 250000000), 1453 FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL, 1454 0, 1660000000), 1455 FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi", 1456 NULL, 0, 125000000), 1457 FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS, 1458 "phyclk_mipi_dphy_4l_m_txbyte_clkhs", NULL, 1459 0, 187500000), 1460 FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m", 1461 NULL, 0, 24000000), 1462 FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL, 1463 0, 135000000), 1464 FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0, 1465 "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000), 1466 FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock", 1467 NULL, 0, 60000000), 1468 FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk", 1469 NULL, 0, 60000000), 1470 FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI, 1471 "phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000), 1472 FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 1473 "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000), 1474 FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 1475 "phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000), 1476 }; 1477 1478 PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"}; 1479 PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"}; 1480 PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"}; 1481 PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"}; 1482 PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"}; 1483 PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"}; 1484 PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1485 PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"}; 1486 PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1487 PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"}; 1488 PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1489 PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user", 1490 "mout_gscl_bustop_333"}; 1491 PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; 1492 PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user", 1493 "mout_m2m_mediatop_400"}; 1494 PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1495 PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user", 1496 "mout_gscl_bustop_fimc"}; 1497 PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user", 1498 "mout_memtop_pll_user"}; 1499 PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"}; 1500 PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; 1501 PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"}; 1502 PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"}; 1503 PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"}; 1504 PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"}; 1505 PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; 1506 PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"}; 1507 PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; 1508 PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"}; 1509 PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user", 1510 "mout_bustop_pll_user"}; 1511 PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"}; 1512 PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; 1513 PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; 1514 PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"}; 1515 PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"}; 1516 PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"}; 1517 PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"}; 1518 PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a", 1519 "mout_mediatop_pll_user"}; 1520 PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a", 1521 "mout_mediatop_pll_user"}; 1522 PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", 1523 "mout_mediatop_pll_user"}; 1524 1525 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 1526 MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user", 1527 mout_mediatop_pll_user_p, 1528 MUX_SEL_TOP_PLL0, 0, 1), 1529 MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user", 1530 mout_memtop_pll_user_p, 1531 MUX_SEL_TOP_PLL0, 4, 1), 1532 MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user", 1533 mout_bustop_pll_user_p, 1534 MUX_SEL_TOP_PLL0, 8, 1), 1535 MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, 1536 MUX_SEL_TOP_PLL0, 12, 1), 1537 MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 1538 MUX_SEL_TOP_PLL0, 16, 1), 1539 MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user", 1540 mout_audtop_pll_user_p, 1541 MUX_SEL_TOP_PLL0, 24, 1), 1542 1543 MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p, 1544 MUX_SEL_TOP_DISP0, 0, 1), 1545 MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p, 1546 MUX_SEL_TOP_DISP0, 8, 1), 1547 MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p, 1548 MUX_SEL_TOP_DISP0, 12, 1), 1549 MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p, 1550 MUX_SEL_TOP_DISP0, 20, 1), 1551 1552 MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p, 1553 MUX_SEL_TOP_DISP1, 0, 1), 1554 MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel", 1555 mout_disp_media_pixel_p, 1556 MUX_SEL_TOP_DISP1, 8, 1), 1557 1558 MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk", 1559 mout_sclk_peri_spi_clk_p, 1560 MUX_SEL_TOP_PERI1, 0, 1), 1561 MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk", 1562 mout_sclk_peri_spi_clk_p, 1563 MUX_SEL_TOP_PERI1, 4, 1), 1564 MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk", 1565 mout_sclk_peri_spi_clk_p, 1566 MUX_SEL_TOP_PERI1, 8, 1), 1567 MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk", 1568 mout_sclk_peri_uart_uclk_p, 1569 MUX_SEL_TOP_PERI1, 12, 1), 1570 MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk", 1571 mout_sclk_peri_uart_uclk_p, 1572 MUX_SEL_TOP_PERI1, 16, 1), 1573 MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk", 1574 mout_sclk_peri_uart_uclk_p, 1575 MUX_SEL_TOP_PERI1, 20, 1), 1576 1577 1578 MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400", 1579 mout_bus_bustop_400_p, 1580 MUX_SEL_TOP_BUS, 0, 1), 1581 MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100", 1582 mout_bus_bustop_100_p, 1583 MUX_SEL_TOP_BUS, 4, 1), 1584 MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100", 1585 mout_bus_bustop_100_p, 1586 MUX_SEL_TOP_BUS, 8, 1), 1587 MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400", 1588 mout_bus_bustop_400_p, 1589 MUX_SEL_TOP_BUS, 12, 1), 1590 MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400", 1591 mout_bus_bustop_400_p, 1592 MUX_SEL_TOP_BUS, 16, 1), 1593 MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100", 1594 mout_bus_bustop_100_p, 1595 MUX_SEL_TOP_BUS, 20, 1), 1596 MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400", 1597 mout_bus_bustop_400_p, 1598 MUX_SEL_TOP_BUS, 24, 1), 1599 MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100", 1600 mout_bus_bustop_100_p, 1601 MUX_SEL_TOP_BUS, 28, 1), 1602 1603 MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb", 1604 mout_sclk_fsys_usb_p, 1605 MUX_SEL_TOP_FSYS, 0, 1), 1606 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a", 1607 mout_sclk_fsys_mmc_sdclkin_a_p, 1608 MUX_SEL_TOP_FSYS, 4, 1), 1609 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b", 1610 mout_sclk_fsys_mmc2_sdclkin_b_p, 1611 MUX_SEL_TOP_FSYS, 8, 1), 1612 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a", 1613 mout_sclk_fsys_mmc_sdclkin_a_p, 1614 MUX_SEL_TOP_FSYS, 12, 1), 1615 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b", 1616 mout_sclk_fsys_mmc1_sdclkin_b_p, 1617 MUX_SEL_TOP_FSYS, 16, 1), 1618 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a", 1619 mout_sclk_fsys_mmc_sdclkin_a_p, 1620 MUX_SEL_TOP_FSYS, 20, 1), 1621 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b", 1622 mout_sclk_fsys_mmc0_sdclkin_b_p, 1623 MUX_SEL_TOP_FSYS, 24, 1), 1624 1625 MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400", 1626 mout_isp1_media_400_p, 1627 MUX_SEL_TOP_ISP10, 4, 1), 1628 MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p, 1629 MUX_SEL_TOP_ISP10, 8, 1), 1630 MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266", 1631 mout_isp1_media_266_p, 1632 MUX_SEL_TOP_ISP10, 16, 1), 1633 MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p, 1634 MUX_SEL_TOP_ISP10, 20, 1), 1635 1636 MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p, 1637 MUX_SEL_TOP_ISP11, 4, 1), 1638 MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p, 1639 MUX_SEL_TOP_ISP11, 8, 1), 1640 MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart", 1641 mout_sclk_isp_uart_p, 1642 MUX_SEL_TOP_ISP11, 12, 1), 1643 MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0", 1644 mout_sclk_isp_sensor_p, 1645 MUX_SEL_TOP_ISP11, 16, 1), 1646 MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1", 1647 mout_sclk_isp_sensor_p, 1648 MUX_SEL_TOP_ISP11, 20, 1), 1649 MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2", 1650 mout_sclk_isp_sensor_p, 1651 MUX_SEL_TOP_ISP11, 24, 1), 1652 1653 MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333", 1654 mout_mfc_bustop_333_p, 1655 MUX_SEL_TOP_MFC, 4, 1), 1656 MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p, 1657 MUX_SEL_TOP_MFC, 8, 1), 1658 1659 MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333", 1660 mout_g2d_bustop_333_p, 1661 MUX_SEL_TOP_G2D, 4, 1), 1662 MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p, 1663 MUX_SEL_TOP_G2D, 8, 1), 1664 1665 MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400", 1666 mout_m2m_mediatop_400_p, 1667 MUX_SEL_TOP_GSCL, 0, 1), 1668 MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400", 1669 mout_aclk_gscl_400_p, 1670 MUX_SEL_TOP_GSCL, 4, 1), 1671 MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333", 1672 mout_gscl_bustop_333_p, 1673 MUX_SEL_TOP_GSCL, 8, 1), 1674 MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 1675 mout_aclk_gscl_333_p, 1676 MUX_SEL_TOP_GSCL, 12, 1), 1677 MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc", 1678 mout_gscl_bustop_fimc_p, 1679 MUX_SEL_TOP_GSCL, 16, 1), 1680 MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc", 1681 mout_aclk_gscl_fimc_p, 1682 MUX_SEL_TOP_GSCL, 20, 1), 1683 }; 1684 1685 static const struct samsung_div_clock top_div_clks[] __initconst = { 1686 DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333", 1687 DIV_TOP_G2D_MFC, 0, 3), 1688 DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333", 1689 DIV_TOP_G2D_MFC, 4, 3), 1690 1691 DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333", 1692 DIV_TOP_GSCL_ISP0, 0, 3), 1693 DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400", 1694 DIV_TOP_GSCL_ISP0, 4, 3), 1695 DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc", 1696 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3), 1697 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a", 1698 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4), 1699 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a", 1700 "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4), 1701 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a", 1702 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4), 1703 1704 DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266", 1705 DIV_TOP_ISP10, 0, 3), 1706 DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400", 1707 DIV_TOP_ISP10, 4, 3), 1708 DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a", 1709 "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4), 1710 DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b", 1711 "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8), 1712 1713 DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a", 1714 "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4), 1715 DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b", 1716 "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8), 1717 DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart", 1718 "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4), 1719 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b", 1720 "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4), 1721 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b", 1722 "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4), 1723 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b", 1724 "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4), 1725 1726 DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk", 1727 "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3), 1728 1729 DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333", 1730 DIV_TOP_DISP, 0, 3), 1731 DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222", 1732 DIV_TOP_DISP, 4, 3), 1733 DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel", 1734 "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3), 1735 1736 DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400", 1737 "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3), 1738 DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100", 1739 "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4), 1740 DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400", 1741 "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3), 1742 DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100", 1743 "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4), 1744 DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400", 1745 "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3), 1746 DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100", 1747 "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4), 1748 DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400", 1749 "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3), 1750 DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100", 1751 "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4), 1752 1753 DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a", 1754 "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4), 1755 DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b", 1756 "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8), 1757 DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a", 1758 "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4), 1759 DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b", 1760 "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8), 1761 1762 DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a", 1763 "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4), 1764 DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b", 1765 "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8), 1766 DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1", 1767 "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4), 1768 DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2", 1769 "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4), 1770 DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0", 1771 "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4), 1772 1773 DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user", 1774 DIV_TOP_PERI2, 20, 4), 1775 DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud", 1776 "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3), 1777 1778 DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200", 1779 "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3), 1780 DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK, 1781 "dout_sclk_fsys_usbdrd30_suspend_clk", 1782 "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4), 1783 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a", 1784 "mout_sclk_fsys_mmc0_sdclkin_b", 1785 DIV_TOP_FSYS0, 12, 4), 1786 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b", 1787 "dout_sclk_fsys_mmc0_sdclkin_a", 1788 DIV_TOP_FSYS0, 16, 8), 1789 1790 1791 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a", 1792 "mout_sclk_fsys_mmc1_sdclkin_b", 1793 DIV_TOP_FSYS1, 0, 4), 1794 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b", 1795 "dout_sclk_fsys_mmc1_sdclkin_a", 1796 DIV_TOP_FSYS1, 4, 8), 1797 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a", 1798 "mout_sclk_fsys_mmc2_sdclkin_b", 1799 DIV_TOP_FSYS1, 12, 4), 1800 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b", 1801 "dout_sclk_fsys_mmc2_sdclkin_a", 1802 DIV_TOP_FSYS1, 16, 8), 1803 1804 }; 1805 1806 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 1807 GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", 1808 "dout_sclk_fsys_mmc0_sdclkin_b", 1809 EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0), 1810 GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin", 1811 "dout_sclk_fsys_mmc1_sdclkin_b", 1812 EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0), 1813 GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin", 1814 "dout_sclk_fsys_mmc2_sdclkin_b", 1815 EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0), 1816 GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel", 1817 EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED | 1818 CLK_SET_RATE_PARENT, 0), 1819 }; 1820 1821 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 1822 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", 1823 DISP_PLL_LOCK, DISP_PLL_CON0, 1824 pll2550_24mhz_tbl), 1825 PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", 1826 AUD_PLL_LOCK, AUD_PLL_CON0, 1827 pll2650_24mhz_tbl), 1828 }; 1829 1830 static const struct samsung_cmu_info top_cmu __initconst = { 1831 .pll_clks = top_pll_clks, 1832 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 1833 .mux_clks = top_mux_clks, 1834 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 1835 .div_clks = top_div_clks, 1836 .nr_div_clks = ARRAY_SIZE(top_div_clks), 1837 .gate_clks = top_gate_clks, 1838 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 1839 .fixed_clks = fixed_rate_clks, 1840 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks), 1841 .nr_clk_ids = CLKS_NR_TOP, 1842 .clk_regs = top_clk_regs, 1843 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 1844 }; 1845 1846 static void __init exynos5260_clk_top_init(struct device_node *np) 1847 { 1848 samsung_cmu_register_one(np, &top_cmu); 1849 } 1850 1851 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top", 1852 exynos5260_clk_top_init); 1853