1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 4 * Author: Rahul Sharma <rahul.sharma@samsung.com> 5 * 6 * Common Clock Framework support for Exynos5260 SoC. 7 */ 8 9 #include <linux/of.h> 10 #include <linux/of_address.h> 11 12 #include "clk-exynos5260.h" 13 #include "clk.h" 14 #include "clk-pll.h" 15 16 #include <dt-bindings/clock/exynos5260-clk.h> 17 18 /* 19 * Applicable for all 2550 Type PLLS for Exynos5260, listed below 20 * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL. 21 */ 22 static const struct samsung_pll_rate_table pll2550_24mhz_tbl[] __initconst = { 23 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 24 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 25 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 26 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 27 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 28 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1), 29 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1), 30 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1), 31 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1), 32 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1), 33 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1), 34 PLL_35XX_RATE(24 * MHZ, 733000000, 733, 12, 1), 35 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 36 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1), 37 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), 38 PLL_35XX_RATE(24 * MHZ, 620000000, 310, 3, 2), 39 PLL_35XX_RATE(24 * MHZ, 600000000, 400, 4, 2), 40 PLL_35XX_RATE(24 * MHZ, 543000000, 362, 4, 2), 41 PLL_35XX_RATE(24 * MHZ, 533000000, 533, 6, 2), 42 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2), 43 PLL_35XX_RATE(24 * MHZ, 450000000, 300, 4, 2), 44 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2), 45 PLL_35XX_RATE(24 * MHZ, 350000000, 175, 3, 2), 46 PLL_35XX_RATE(24 * MHZ, 300000000, 400, 4, 3), 47 PLL_35XX_RATE(24 * MHZ, 266000000, 266, 3, 3), 48 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), 49 PLL_35XX_RATE(24 * MHZ, 160000000, 160, 3, 3), 50 }; 51 52 /* 53 * Applicable for 2650 Type PLL for AUD_PLL. 54 */ 55 static const struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initconst = { 56 PLL_36XX_RATE(24 * MHZ, 1600000000, 200, 3, 0, 0), 57 PLL_36XX_RATE(24 * MHZ, 1200000000, 100, 2, 0, 0), 58 PLL_36XX_RATE(24 * MHZ, 1000000000, 250, 3, 1, 0), 59 PLL_36XX_RATE(24 * MHZ, 800000000, 200, 3, 1, 0), 60 PLL_36XX_RATE(24 * MHZ, 600000000, 100, 2, 1, 0), 61 PLL_36XX_RATE(24 * MHZ, 532000000, 266, 3, 2, 0), 62 PLL_36XX_RATE(24 * MHZ, 480000000, 160, 2, 2, 0), 63 PLL_36XX_RATE(24 * MHZ, 432000000, 144, 2, 2, 0), 64 PLL_36XX_RATE(24 * MHZ, 400000000, 200, 3, 2, 0), 65 PLL_36XX_RATE(24 * MHZ, 394073128, 459, 7, 2, 49282), 66 PLL_36XX_RATE(24 * MHZ, 333000000, 111, 2, 2, 0), 67 PLL_36XX_RATE(24 * MHZ, 300000000, 100, 2, 2, 0), 68 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0), 69 PLL_36XX_RATE(24 * MHZ, 200000000, 200, 3, 3, 0), 70 PLL_36XX_RATE(24 * MHZ, 166000000, 166, 3, 3, 0), 71 PLL_36XX_RATE(24 * MHZ, 133000000, 266, 3, 4, 0), 72 PLL_36XX_RATE(24 * MHZ, 100000000, 200, 3, 4, 0), 73 PLL_36XX_RATE(24 * MHZ, 66000000, 176, 2, 5, 0), 74 }; 75 76 /* CMU_AUD */ 77 78 static const unsigned long aud_clk_regs[] __initconst = { 79 MUX_SEL_AUD, 80 DIV_AUD0, 81 DIV_AUD1, 82 EN_ACLK_AUD, 83 EN_PCLK_AUD, 84 EN_SCLK_AUD, 85 EN_IP_AUD, 86 }; 87 88 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"}; 89 PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"}; 90 PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"}; 91 92 static const struct samsung_mux_clock aud_mux_clks[] __initconst = { 93 MUX(AUD_MOUT_AUD_PLL_USER, "mout_aud_pll_user", mout_aud_pll_user_p, 94 MUX_SEL_AUD, 0, 1), 95 MUX(AUD_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_i2s_p, 96 MUX_SEL_AUD, 4, 1), 97 MUX(AUD_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p, 98 MUX_SEL_AUD, 8, 1), 99 }; 100 101 static const struct samsung_div_clock aud_div_clks[] __initconst = { 102 DIV(AUD_DOUT_ACLK_AUD_131, "dout_aclk_aud_131", "mout_aud_pll_user", 103 DIV_AUD0, 0, 4), 104 105 DIV(AUD_DOUT_SCLK_AUD_I2S, "dout_sclk_aud_i2s", "mout_sclk_aud_i2s", 106 DIV_AUD1, 0, 4), 107 DIV(AUD_DOUT_SCLK_AUD_PCM, "dout_sclk_aud_pcm", "mout_sclk_aud_pcm", 108 DIV_AUD1, 4, 8), 109 DIV(AUD_DOUT_SCLK_AUD_UART, "dout_sclk_aud_uart", "mout_aud_pll_user", 110 DIV_AUD1, 12, 4), 111 }; 112 113 static const struct samsung_gate_clock aud_gate_clks[] __initconst = { 114 GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s", 115 EN_SCLK_AUD, 0, CLK_SET_RATE_PARENT, 0), 116 GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm", 117 EN_SCLK_AUD, 1, CLK_SET_RATE_PARENT, 0), 118 GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart", 119 EN_SCLK_AUD, 2, CLK_SET_RATE_PARENT, 0), 120 121 GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD, 122 0, 0, 0), 123 GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131", 124 EN_IP_AUD, 1, 0, 0), 125 GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0), 126 GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0), 127 GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131", 128 EN_IP_AUD, 4, 0, 0), 129 }; 130 131 static const struct samsung_cmu_info aud_cmu __initconst = { 132 .mux_clks = aud_mux_clks, 133 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks), 134 .div_clks = aud_div_clks, 135 .nr_div_clks = ARRAY_SIZE(aud_div_clks), 136 .gate_clks = aud_gate_clks, 137 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks), 138 .nr_clk_ids = AUD_NR_CLK, 139 .clk_regs = aud_clk_regs, 140 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 141 }; 142 143 static void __init exynos5260_clk_aud_init(struct device_node *np) 144 { 145 samsung_cmu_register_one(np, &aud_cmu); 146 } 147 148 CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud", 149 exynos5260_clk_aud_init); 150 151 152 /* CMU_DISP */ 153 154 static const unsigned long disp_clk_regs[] __initconst = { 155 MUX_SEL_DISP0, 156 MUX_SEL_DISP1, 157 MUX_SEL_DISP2, 158 MUX_SEL_DISP3, 159 MUX_SEL_DISP4, 160 DIV_DISP, 161 EN_ACLK_DISP, 162 EN_PCLK_DISP, 163 EN_SCLK_DISP0, 164 EN_SCLK_DISP1, 165 EN_IP_DISP, 166 EN_IP_DISP_BUS, 167 }; 168 169 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll", 170 "phyclk_dptx_phy_ch3_txd_clk"}; 171 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll", 172 "phyclk_dptx_phy_ch2_txd_clk"}; 173 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll", 174 "phyclk_dptx_phy_ch1_txd_clk"}; 175 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll", 176 "phyclk_dptx_phy_ch0_txd_clk"}; 177 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"}; 178 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"}; 179 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"}; 180 PNAME(mout_phyclk_hdmi_phy_tmds_clko_user_p) = {"fin_pll", 181 "phyclk_hdmi_phy_tmds_clko"}; 182 PNAME(mout_phyclk_hdmi_phy_ref_clko_user_p) = {"fin_pll", 183 "phyclk_hdmi_phy_ref_clko"}; 184 PNAME(mout_phyclk_hdmi_phy_pixel_clko_user_p) = {"fin_pll", 185 "phyclk_hdmi_phy_pixel_clko"}; 186 PNAME(mout_phyclk_hdmi_link_o_tmds_clkhi_user_p) = {"fin_pll", 187 "phyclk_hdmi_link_o_tmds_clkhi"}; 188 PNAME(mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p) = {"fin_pll", 189 "phyclk_mipi_dphy_4l_m_txbyte_clkhs"}; 190 PNAME(mout_phyclk_dptx_phy_o_ref_clk_24m_user_p) = {"fin_pll", 191 "phyclk_dptx_phy_o_ref_clk_24m"}; 192 PNAME(mout_phyclk_dptx_phy_clk_div2_user_p) = {"fin_pll", 193 "phyclk_dptx_phy_clk_div2"}; 194 PNAME(mout_sclk_hdmi_pixel_p) = {"mout_sclk_disp_pixel_user", 195 "mout_aclk_disp_222_user"}; 196 PNAME(mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p) = {"fin_pll", 197 "phyclk_mipi_dphy_4l_m_rxclkesc0"}; 198 PNAME(mout_sclk_hdmi_spdif_p) = {"fin_pll", "ioclk_spdif_extclk", 199 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; 200 201 static const struct samsung_mux_clock disp_mux_clks[] __initconst = { 202 MUX(DISP_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user", 203 mout_aclk_disp_333_user_p, 204 MUX_SEL_DISP0, 0, 1), 205 MUX(DISP_MOUT_SCLK_DISP_PIXEL_USER, "mout_sclk_disp_pixel_user", 206 mout_sclk_disp_pixel_user_p, 207 MUX_SEL_DISP0, 4, 1), 208 MUX(DISP_MOUT_ACLK_DISP_222_USER, "mout_aclk_disp_222_user", 209 mout_aclk_disp_222_user_p, 210 MUX_SEL_DISP0, 8, 1), 211 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH0_TXD_CLK_USER, 212 "mout_phyclk_dptx_phy_ch0_txd_clk_user", 213 mout_phyclk_dptx_phy_ch0_txd_clk_user_p, 214 MUX_SEL_DISP0, 16, 1), 215 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH1_TXD_CLK_USER, 216 "mout_phyclk_dptx_phy_ch1_txd_clk_user", 217 mout_phyclk_dptx_phy_ch1_txd_clk_user_p, 218 MUX_SEL_DISP0, 20, 1), 219 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH2_TXD_CLK_USER, 220 "mout_phyclk_dptx_phy_ch2_txd_clk_user", 221 mout_phyclk_dptx_phy_ch2_txd_clk_user_p, 222 MUX_SEL_DISP0, 24, 1), 223 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CH3_TXD_CLK_USER, 224 "mout_phyclk_dptx_phy_ch3_txd_clk_user", 225 mout_phyclk_dptx_phy_ch3_txd_clk_user_p, 226 MUX_SEL_DISP0, 28, 1), 227 228 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_CLK_DIV2_USER, 229 "mout_phyclk_dptx_phy_clk_div2_user", 230 mout_phyclk_dptx_phy_clk_div2_user_p, 231 MUX_SEL_DISP1, 0, 1), 232 MUX(DISP_MOUT_PHYCLK_DPTX_PHY_O_REF_CLK_24M_USER, 233 "mout_phyclk_dptx_phy_o_ref_clk_24m_user", 234 mout_phyclk_dptx_phy_o_ref_clk_24m_user_p, 235 MUX_SEL_DISP1, 4, 1), 236 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4L_M_TXBYTE_CLKHS, 237 "mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs", 238 mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, 239 MUX_SEL_DISP1, 8, 1), 240 MUX(DISP_MOUT_PHYCLK_HDMI_LINK_O_TMDS_CLKHI_USER, 241 "mout_phyclk_hdmi_link_o_tmds_clkhi_user", 242 mout_phyclk_hdmi_link_o_tmds_clkhi_user_p, 243 MUX_SEL_DISP1, 16, 1), 244 MUX(DISP_MOUT_HDMI_PHY_PIXEL, 245 "mout_phyclk_hdmi_phy_pixel_clko_user", 246 mout_phyclk_hdmi_phy_pixel_clko_user_p, 247 MUX_SEL_DISP1, 20, 1), 248 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_REF_CLKO_USER, 249 "mout_phyclk_hdmi_phy_ref_clko_user", 250 mout_phyclk_hdmi_phy_ref_clko_user_p, 251 MUX_SEL_DISP1, 24, 1), 252 MUX(DISP_MOUT_PHYCLK_HDMI_PHY_TMDS_CLKO_USER, 253 "mout_phyclk_hdmi_phy_tmds_clko_user", 254 mout_phyclk_hdmi_phy_tmds_clko_user_p, 255 MUX_SEL_DISP1, 28, 1), 256 257 MUX(DISP_MOUT_PHYCLK_MIPI_DPHY_4LMRXCLK_ESC0_USER, 258 "mout_phyclk_mipi_dphy_4lmrxclk_esc0_user", 259 mout_phyclk_mipi_dphy_4lmrxclk_esc0_user_p, 260 MUX_SEL_DISP2, 0, 1), 261 MUX(DISP_MOUT_SCLK_HDMI_PIXEL, "mout_sclk_hdmi_pixel", 262 mout_sclk_hdmi_pixel_p, 263 MUX_SEL_DISP2, 4, 1), 264 265 MUX(DISP_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif", 266 mout_sclk_hdmi_spdif_p, 267 MUX_SEL_DISP4, 4, 2), 268 }; 269 270 static const struct samsung_div_clock disp_div_clks[] __initconst = { 271 DIV(DISP_DOUT_PCLK_DISP_111, "dout_pclk_disp_111", 272 "mout_aclk_disp_222_user", 273 DIV_DISP, 8, 4), 274 DIV(DISP_DOUT_SCLK_FIMD1_EXTCLKPLL, "dout_sclk_fimd1_extclkpll", 275 "mout_sclk_disp_pixel_user", 276 DIV_DISP, 12, 4), 277 DIV(DISP_DOUT_SCLK_HDMI_PHY_PIXEL_CLKI, 278 "dout_sclk_hdmi_phy_pixel_clki", 279 "mout_sclk_hdmi_pixel", 280 DIV_DISP, 16, 4), 281 }; 282 283 static const struct samsung_gate_clock disp_gate_clks[] __initconst = { 284 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel", 285 "mout_phyclk_hdmi_phy_pixel_clko_user", 286 EN_SCLK_DISP0, 26, CLK_SET_RATE_PARENT, 0), 287 GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki", 288 "dout_sclk_hdmi_phy_pixel_clki", 289 EN_SCLK_DISP0, 29, CLK_SET_RATE_PARENT, 0), 290 291 GATE(DISP_CLK_DP, "clk_dptx_link", "mout_aclk_disp_222_user", 292 EN_IP_DISP, 4, 0, 0), 293 GATE(DISP_CLK_DPPHY, "clk_dptx_phy", "mout_aclk_disp_222_user", 294 EN_IP_DISP, 5, 0, 0), 295 GATE(DISP_CLK_DSIM1, "clk_dsim1", "mout_aclk_disp_222_user", 296 EN_IP_DISP, 6, 0, 0), 297 GATE(DISP_CLK_FIMD1, "clk_fimd1", "mout_aclk_disp_222_user", 298 EN_IP_DISP, 7, 0, 0), 299 GATE(DISP_CLK_HDMI, "clk_hdmi", "mout_aclk_disp_222_user", 300 EN_IP_DISP, 8, 0, 0), 301 GATE(DISP_CLK_HDMIPHY, "clk_hdmiphy", "mout_aclk_disp_222_user", 302 EN_IP_DISP, 9, 0, 0), 303 GATE(DISP_CLK_MIPIPHY, "clk_mipi_dphy", "mout_aclk_disp_222_user", 304 EN_IP_DISP, 10, 0, 0), 305 GATE(DISP_CLK_MIXER, "clk_mixer", "mout_aclk_disp_222_user", 306 EN_IP_DISP, 11, 0, 0), 307 GATE(DISP_CLK_PIXEL_DISP, "clk_pixel_disp", "mout_aclk_disp_222_user", 308 EN_IP_DISP, 12, CLK_IGNORE_UNUSED, 0), 309 GATE(DISP_CLK_PIXEL_MIXER, "clk_pixel_mixer", "mout_aclk_disp_222_user", 310 EN_IP_DISP, 13, CLK_IGNORE_UNUSED, 0), 311 GATE(DISP_CLK_SMMU_FIMD1M0, "clk_smmu3_fimd1m0", 312 "mout_aclk_disp_222_user", 313 EN_IP_DISP, 22, 0, 0), 314 GATE(DISP_CLK_SMMU_FIMD1M1, "clk_smmu3_fimd1m1", 315 "mout_aclk_disp_222_user", 316 EN_IP_DISP, 23, 0, 0), 317 GATE(DISP_CLK_SMMU_TV, "clk_smmu3_tv", "mout_aclk_disp_222_user", 318 EN_IP_DISP, 25, 0, 0), 319 }; 320 321 static const struct samsung_cmu_info disp_cmu __initconst = { 322 .mux_clks = disp_mux_clks, 323 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks), 324 .div_clks = disp_div_clks, 325 .nr_div_clks = ARRAY_SIZE(disp_div_clks), 326 .gate_clks = disp_gate_clks, 327 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks), 328 .nr_clk_ids = DISP_NR_CLK, 329 .clk_regs = disp_clk_regs, 330 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 331 }; 332 333 static void __init exynos5260_clk_disp_init(struct device_node *np) 334 { 335 samsung_cmu_register_one(np, &disp_cmu); 336 } 337 338 CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp", 339 exynos5260_clk_disp_init); 340 341 342 /* CMU_EGL */ 343 344 static const unsigned long egl_clk_regs[] __initconst = { 345 EGL_PLL_LOCK, 346 EGL_PLL_CON0, 347 EGL_PLL_CON1, 348 EGL_PLL_FREQ_DET, 349 MUX_SEL_EGL, 350 MUX_ENABLE_EGL, 351 DIV_EGL, 352 DIV_EGL_PLL_FDET, 353 EN_ACLK_EGL, 354 EN_PCLK_EGL, 355 EN_SCLK_EGL, 356 }; 357 358 PNAME(mout_egl_b_p) = {"mout_egl_pll", "dout_bus_pll"}; 359 PNAME(mout_egl_pll_p) = {"fin_pll", "fout_egl_pll"}; 360 361 static const struct samsung_mux_clock egl_mux_clks[] __initconst = { 362 MUX(EGL_MOUT_EGL_PLL, "mout_egl_pll", mout_egl_pll_p, 363 MUX_SEL_EGL, 4, 1), 364 MUX(EGL_MOUT_EGL_B, "mout_egl_b", mout_egl_b_p, MUX_SEL_EGL, 16, 1), 365 }; 366 367 static const struct samsung_div_clock egl_div_clks[] __initconst = { 368 DIV(EGL_DOUT_EGL1, "dout_egl1", "mout_egl_b", DIV_EGL, 0, 3), 369 DIV(EGL_DOUT_EGL2, "dout_egl2", "dout_egl1", DIV_EGL, 4, 3), 370 DIV(EGL_DOUT_ACLK_EGL, "dout_aclk_egl", "dout_egl2", DIV_EGL, 8, 3), 371 DIV(EGL_DOUT_PCLK_EGL, "dout_pclk_egl", "dout_egl_atclk", 372 DIV_EGL, 12, 3), 373 DIV(EGL_DOUT_EGL_ATCLK, "dout_egl_atclk", "dout_egl2", DIV_EGL, 16, 3), 374 DIV(EGL_DOUT_EGL_PCLK_DBG, "dout_egl_pclk_dbg", "dout_egl_atclk", 375 DIV_EGL, 20, 3), 376 DIV(EGL_DOUT_EGL_PLL, "dout_egl_pll", "mout_egl_b", DIV_EGL, 24, 3), 377 }; 378 379 static const struct samsung_pll_clock egl_pll_clks[] __initconst = { 380 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll", 381 EGL_PLL_LOCK, EGL_PLL_CON0, 382 pll2550_24mhz_tbl), 383 }; 384 385 static const struct samsung_cmu_info egl_cmu __initconst = { 386 .pll_clks = egl_pll_clks, 387 .nr_pll_clks = ARRAY_SIZE(egl_pll_clks), 388 .mux_clks = egl_mux_clks, 389 .nr_mux_clks = ARRAY_SIZE(egl_mux_clks), 390 .div_clks = egl_div_clks, 391 .nr_div_clks = ARRAY_SIZE(egl_div_clks), 392 .nr_clk_ids = EGL_NR_CLK, 393 .clk_regs = egl_clk_regs, 394 .nr_clk_regs = ARRAY_SIZE(egl_clk_regs), 395 }; 396 397 static void __init exynos5260_clk_egl_init(struct device_node *np) 398 { 399 samsung_cmu_register_one(np, &egl_cmu); 400 } 401 402 CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl", 403 exynos5260_clk_egl_init); 404 405 406 /* CMU_FSYS */ 407 408 static const unsigned long fsys_clk_regs[] __initconst = { 409 MUX_SEL_FSYS0, 410 MUX_SEL_FSYS1, 411 EN_ACLK_FSYS, 412 EN_ACLK_FSYS_SECURE_RTIC, 413 EN_ACLK_FSYS_SECURE_SMMU_RTIC, 414 EN_SCLK_FSYS, 415 EN_IP_FSYS, 416 EN_IP_FSYS_SECURE_RTIC, 417 EN_IP_FSYS_SECURE_SMMU_RTIC, 418 }; 419 420 PNAME(mout_phyclk_usbhost20_phyclk_user_p) = {"fin_pll", 421 "phyclk_usbhost20_phy_phyclock"}; 422 PNAME(mout_phyclk_usbhost20_freeclk_user_p) = {"fin_pll", 423 "phyclk_usbhost20_phy_freeclk"}; 424 PNAME(mout_phyclk_usbhost20_clk48mohci_user_p) = {"fin_pll", 425 "phyclk_usbhost20_phy_clk48mohci"}; 426 PNAME(mout_phyclk_usbdrd30_pipe_pclk_user_p) = {"fin_pll", 427 "phyclk_usbdrd30_udrd30_pipe_pclk"}; 428 PNAME(mout_phyclk_usbdrd30_phyclock_user_p) = {"fin_pll", 429 "phyclk_usbdrd30_udrd30_phyclock"}; 430 431 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = { 432 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PHYCLOCK_USER, 433 "mout_phyclk_usbdrd30_phyclock_user", 434 mout_phyclk_usbdrd30_phyclock_user_p, 435 MUX_SEL_FSYS1, 0, 1), 436 MUX(FSYS_MOUT_PHYCLK_USBDRD30_PIPE_PCLK_USER, 437 "mout_phyclk_usbdrd30_pipe_pclk_user", 438 mout_phyclk_usbdrd30_pipe_pclk_user_p, 439 MUX_SEL_FSYS1, 4, 1), 440 MUX(FSYS_MOUT_PHYCLK_USBHOST20_CLK48MOHCI_USER, 441 "mout_phyclk_usbhost20_clk48mohci_user", 442 mout_phyclk_usbhost20_clk48mohci_user_p, 443 MUX_SEL_FSYS1, 8, 1), 444 MUX(FSYS_MOUT_PHYCLK_USBHOST20_FREECLK_USER, 445 "mout_phyclk_usbhost20_freeclk_user", 446 mout_phyclk_usbhost20_freeclk_user_p, 447 MUX_SEL_FSYS1, 12, 1), 448 MUX(FSYS_MOUT_PHYCLK_USBHOST20_PHYCLK_USER, 449 "mout_phyclk_usbhost20_phyclk_user", 450 mout_phyclk_usbhost20_phyclk_user_p, 451 MUX_SEL_FSYS1, 16, 1), 452 }; 453 454 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = { 455 GATE(FSYS_PHYCLK_USBHOST20, "phyclk_usbhost20_phyclock", 456 "mout_phyclk_usbdrd30_phyclock_user", 457 EN_SCLK_FSYS, 1, 0, 0), 458 GATE(FSYS_PHYCLK_USBDRD30, "phyclk_usbdrd30_udrd30_phyclock_g", 459 "mout_phyclk_usbdrd30_phyclock_user", 460 EN_SCLK_FSYS, 7, 0, 0), 461 462 GATE(FSYS_CLK_MMC0, "clk_mmc0", "dout_aclk_fsys_200", 463 EN_IP_FSYS, 6, 0, 0), 464 GATE(FSYS_CLK_MMC1, "clk_mmc1", "dout_aclk_fsys_200", 465 EN_IP_FSYS, 7, 0, 0), 466 GATE(FSYS_CLK_MMC2, "clk_mmc2", "dout_aclk_fsys_200", 467 EN_IP_FSYS, 8, 0, 0), 468 GATE(FSYS_CLK_PDMA, "clk_pdma", "dout_aclk_fsys_200", 469 EN_IP_FSYS, 9, 0, 0), 470 GATE(FSYS_CLK_SROMC, "clk_sromc", "dout_aclk_fsys_200", 471 EN_IP_FSYS, 13, 0, 0), 472 GATE(FSYS_CLK_USBDRD30, "clk_usbdrd30", "dout_aclk_fsys_200", 473 EN_IP_FSYS, 14, 0, 0), 474 GATE(FSYS_CLK_USBHOST20, "clk_usbhost20", "dout_aclk_fsys_200", 475 EN_IP_FSYS, 15, 0, 0), 476 GATE(FSYS_CLK_USBLINK, "clk_usblink", "dout_aclk_fsys_200", 477 EN_IP_FSYS, 18, 0, 0), 478 GATE(FSYS_CLK_TSI, "clk_tsi", "dout_aclk_fsys_200", 479 EN_IP_FSYS, 20, 0, 0), 480 481 GATE(FSYS_CLK_RTIC, "clk_rtic", "dout_aclk_fsys_200", 482 EN_IP_FSYS_SECURE_RTIC, 11, 0, 0), 483 GATE(FSYS_CLK_SMMU_RTIC, "clk_smmu_rtic", "dout_aclk_fsys_200", 484 EN_IP_FSYS_SECURE_SMMU_RTIC, 12, 0, 0), 485 }; 486 487 static const struct samsung_cmu_info fsys_cmu __initconst = { 488 .mux_clks = fsys_mux_clks, 489 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks), 490 .gate_clks = fsys_gate_clks, 491 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks), 492 .nr_clk_ids = FSYS_NR_CLK, 493 .clk_regs = fsys_clk_regs, 494 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 495 }; 496 497 static void __init exynos5260_clk_fsys_init(struct device_node *np) 498 { 499 samsung_cmu_register_one(np, &fsys_cmu); 500 } 501 502 CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys", 503 exynos5260_clk_fsys_init); 504 505 506 /* CMU_G2D */ 507 508 static const unsigned long g2d_clk_regs[] __initconst = { 509 MUX_SEL_G2D, 510 MUX_STAT_G2D, 511 DIV_G2D, 512 EN_ACLK_G2D, 513 EN_ACLK_G2D_SECURE_SSS, 514 EN_ACLK_G2D_SECURE_SLIM_SSS, 515 EN_ACLK_G2D_SECURE_SMMU_SLIM_SSS, 516 EN_ACLK_G2D_SECURE_SMMU_SSS, 517 EN_ACLK_G2D_SECURE_SMMU_MDMA, 518 EN_ACLK_G2D_SECURE_SMMU_G2D, 519 EN_PCLK_G2D, 520 EN_PCLK_G2D_SECURE_SMMU_SLIM_SSS, 521 EN_PCLK_G2D_SECURE_SMMU_SSS, 522 EN_PCLK_G2D_SECURE_SMMU_MDMA, 523 EN_PCLK_G2D_SECURE_SMMU_G2D, 524 EN_IP_G2D, 525 EN_IP_G2D_SECURE_SSS, 526 EN_IP_G2D_SECURE_SLIM_SSS, 527 EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 528 EN_IP_G2D_SECURE_SMMU_SSS, 529 EN_IP_G2D_SECURE_SMMU_MDMA, 530 EN_IP_G2D_SECURE_SMMU_G2D, 531 }; 532 533 PNAME(mout_aclk_g2d_333_user_p) = {"fin_pll", "dout_aclk_g2d_333"}; 534 535 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = { 536 MUX(G2D_MOUT_ACLK_G2D_333_USER, "mout_aclk_g2d_333_user", 537 mout_aclk_g2d_333_user_p, 538 MUX_SEL_G2D, 0, 1), 539 }; 540 541 static const struct samsung_div_clock g2d_div_clks[] __initconst = { 542 DIV(G2D_DOUT_PCLK_G2D_83, "dout_pclk_g2d_83", "mout_aclk_g2d_333_user", 543 DIV_G2D, 0, 3), 544 }; 545 546 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = { 547 GATE(G2D_CLK_G2D, "clk_g2d", "mout_aclk_g2d_333_user", 548 EN_IP_G2D, 4, 0, 0), 549 GATE(G2D_CLK_JPEG, "clk_jpeg", "mout_aclk_g2d_333_user", 550 EN_IP_G2D, 5, 0, 0), 551 GATE(G2D_CLK_MDMA, "clk_mdma", "mout_aclk_g2d_333_user", 552 EN_IP_G2D, 6, 0, 0), 553 GATE(G2D_CLK_SMMU3_JPEG, "clk_smmu3_jpeg", "mout_aclk_g2d_333_user", 554 EN_IP_G2D, 16, 0, 0), 555 556 GATE(G2D_CLK_SSS, "clk_sss", "mout_aclk_g2d_333_user", 557 EN_IP_G2D_SECURE_SSS, 17, 0, 0), 558 559 GATE(G2D_CLK_SLIM_SSS, "clk_slim_sss", "mout_aclk_g2d_333_user", 560 EN_IP_G2D_SECURE_SLIM_SSS, 11, 0, 0), 561 562 GATE(G2D_CLK_SMMU_SLIM_SSS, "clk_smmu_slim_sss", 563 "mout_aclk_g2d_333_user", 564 EN_IP_G2D_SECURE_SMMU_SLIM_SSS, 13, 0, 0), 565 566 GATE(G2D_CLK_SMMU_SSS, "clk_smmu_sss", "mout_aclk_g2d_333_user", 567 EN_IP_G2D_SECURE_SMMU_SSS, 14, 0, 0), 568 569 GATE(G2D_CLK_SMMU_MDMA, "clk_smmu_mdma", "mout_aclk_g2d_333_user", 570 EN_IP_G2D_SECURE_SMMU_MDMA, 12, 0, 0), 571 572 GATE(G2D_CLK_SMMU3_G2D, "clk_smmu3_g2d", "mout_aclk_g2d_333_user", 573 EN_IP_G2D_SECURE_SMMU_G2D, 15, 0, 0), 574 }; 575 576 static const struct samsung_cmu_info g2d_cmu __initconst = { 577 .mux_clks = g2d_mux_clks, 578 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks), 579 .div_clks = g2d_div_clks, 580 .nr_div_clks = ARRAY_SIZE(g2d_div_clks), 581 .gate_clks = g2d_gate_clks, 582 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks), 583 .nr_clk_ids = G2D_NR_CLK, 584 .clk_regs = g2d_clk_regs, 585 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 586 }; 587 588 static void __init exynos5260_clk_g2d_init(struct device_node *np) 589 { 590 samsung_cmu_register_one(np, &g2d_cmu); 591 } 592 593 CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d", 594 exynos5260_clk_g2d_init); 595 596 597 /* CMU_G3D */ 598 599 static const unsigned long g3d_clk_regs[] __initconst = { 600 G3D_PLL_LOCK, 601 G3D_PLL_CON0, 602 G3D_PLL_CON1, 603 G3D_PLL_FDET, 604 MUX_SEL_G3D, 605 DIV_G3D, 606 DIV_G3D_PLL_FDET, 607 EN_ACLK_G3D, 608 EN_PCLK_G3D, 609 EN_SCLK_G3D, 610 EN_IP_G3D, 611 }; 612 613 PNAME(mout_g3d_pll_p) = {"fin_pll", "fout_g3d_pll"}; 614 615 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { 616 MUX(G3D_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, 617 MUX_SEL_G3D, 0, 1), 618 }; 619 620 static const struct samsung_div_clock g3d_div_clks[] __initconst = { 621 DIV(G3D_DOUT_PCLK_G3D, "dout_pclk_g3d", "dout_aclk_g3d", DIV_G3D, 0, 3), 622 DIV(G3D_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_g3d_pll", DIV_G3D, 4, 3), 623 }; 624 625 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { 626 GATE(G3D_CLK_G3D, "clk_g3d", "dout_aclk_g3d", EN_IP_G3D, 2, 0, 0), 627 GATE(G3D_CLK_G3D_HPM, "clk_g3d_hpm", "dout_aclk_g3d", 628 EN_IP_G3D, 3, 0, 0), 629 }; 630 631 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { 632 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll", 633 G3D_PLL_LOCK, G3D_PLL_CON0, 634 pll2550_24mhz_tbl), 635 }; 636 637 static const struct samsung_cmu_info g3d_cmu __initconst = { 638 .pll_clks = g3d_pll_clks, 639 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), 640 .mux_clks = g3d_mux_clks, 641 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), 642 .div_clks = g3d_div_clks, 643 .nr_div_clks = ARRAY_SIZE(g3d_div_clks), 644 .gate_clks = g3d_gate_clks, 645 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), 646 .nr_clk_ids = G3D_NR_CLK, 647 .clk_regs = g3d_clk_regs, 648 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 649 }; 650 651 static void __init exynos5260_clk_g3d_init(struct device_node *np) 652 { 653 samsung_cmu_register_one(np, &g3d_cmu); 654 } 655 656 CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d", 657 exynos5260_clk_g3d_init); 658 659 660 /* CMU_GSCL */ 661 662 static const unsigned long gscl_clk_regs[] __initconst = { 663 MUX_SEL_GSCL, 664 DIV_GSCL, 665 EN_ACLK_GSCL, 666 EN_ACLK_GSCL_FIMC, 667 EN_ACLK_GSCL_SECURE_SMMU_GSCL0, 668 EN_ACLK_GSCL_SECURE_SMMU_GSCL1, 669 EN_ACLK_GSCL_SECURE_SMMU_MSCL0, 670 EN_ACLK_GSCL_SECURE_SMMU_MSCL1, 671 EN_PCLK_GSCL, 672 EN_PCLK_GSCL_FIMC, 673 EN_PCLK_GSCL_SECURE_SMMU_GSCL0, 674 EN_PCLK_GSCL_SECURE_SMMU_GSCL1, 675 EN_PCLK_GSCL_SECURE_SMMU_MSCL0, 676 EN_PCLK_GSCL_SECURE_SMMU_MSCL1, 677 EN_SCLK_GSCL, 678 EN_SCLK_GSCL_FIMC, 679 EN_IP_GSCL, 680 EN_IP_GSCL_FIMC, 681 EN_IP_GSCL_SECURE_SMMU_GSCL0, 682 EN_IP_GSCL_SECURE_SMMU_GSCL1, 683 EN_IP_GSCL_SECURE_SMMU_MSCL0, 684 EN_IP_GSCL_SECURE_SMMU_MSCL1, 685 }; 686 687 PNAME(mout_aclk_gscl_333_user_p) = {"fin_pll", "dout_aclk_gscl_333"}; 688 PNAME(mout_aclk_m2m_400_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; 689 PNAME(mout_aclk_gscl_fimc_user_p) = {"fin_pll", "dout_aclk_gscl_400"}; 690 PNAME(mout_aclk_csis_p) = {"dout_aclk_csis_200", "mout_aclk_gscl_fimc_user"}; 691 692 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = { 693 MUX(GSCL_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user", 694 mout_aclk_gscl_333_user_p, 695 MUX_SEL_GSCL, 0, 1), 696 MUX(GSCL_MOUT_ACLK_M2M_400_USER, "mout_aclk_m2m_400_user", 697 mout_aclk_m2m_400_user_p, 698 MUX_SEL_GSCL, 4, 1), 699 MUX(GSCL_MOUT_ACLK_GSCL_FIMC_USER, "mout_aclk_gscl_fimc_user", 700 mout_aclk_gscl_fimc_user_p, 701 MUX_SEL_GSCL, 8, 1), 702 MUX(GSCL_MOUT_ACLK_CSIS, "mout_aclk_csis", mout_aclk_csis_p, 703 MUX_SEL_GSCL, 24, 1), 704 }; 705 706 static const struct samsung_div_clock gscl_div_clks[] __initconst = { 707 DIV(GSCL_DOUT_PCLK_M2M_100, "dout_pclk_m2m_100", 708 "mout_aclk_m2m_400_user", 709 DIV_GSCL, 0, 3), 710 DIV(GSCL_DOUT_ACLK_CSIS_200, "dout_aclk_csis_200", 711 "mout_aclk_m2m_400_user", 712 DIV_GSCL, 4, 3), 713 }; 714 715 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = { 716 GATE(GSCL_SCLK_CSIS0_WRAP, "sclk_csis0_wrap", "dout_aclk_csis_200", 717 EN_SCLK_GSCL_FIMC, 0, CLK_SET_RATE_PARENT, 0), 718 GATE(GSCL_SCLK_CSIS1_WRAP, "sclk_csis1_wrap", "dout_aclk_csis_200", 719 EN_SCLK_GSCL_FIMC, 1, CLK_SET_RATE_PARENT, 0), 720 721 GATE(GSCL_CLK_GSCL0, "clk_gscl0", "mout_aclk_gscl_333_user", 722 EN_IP_GSCL, 2, 0, 0), 723 GATE(GSCL_CLK_GSCL1, "clk_gscl1", "mout_aclk_gscl_333_user", 724 EN_IP_GSCL, 3, 0, 0), 725 GATE(GSCL_CLK_MSCL0, "clk_mscl0", "mout_aclk_gscl_333_user", 726 EN_IP_GSCL, 4, 0, 0), 727 GATE(GSCL_CLK_MSCL1, "clk_mscl1", "mout_aclk_gscl_333_user", 728 EN_IP_GSCL, 5, 0, 0), 729 GATE(GSCL_CLK_PIXEL_GSCL0, "clk_pixel_gscl0", 730 "mout_aclk_gscl_333_user", 731 EN_IP_GSCL, 8, 0, 0), 732 GATE(GSCL_CLK_PIXEL_GSCL1, "clk_pixel_gscl1", 733 "mout_aclk_gscl_333_user", 734 EN_IP_GSCL, 9, 0, 0), 735 736 GATE(GSCL_CLK_SMMU3_LITE_A, "clk_smmu3_lite_a", 737 "mout_aclk_gscl_fimc_user", 738 EN_IP_GSCL_FIMC, 5, 0, 0), 739 GATE(GSCL_CLK_SMMU3_LITE_B, "clk_smmu3_lite_b", 740 "mout_aclk_gscl_fimc_user", 741 EN_IP_GSCL_FIMC, 6, 0, 0), 742 GATE(GSCL_CLK_SMMU3_LITE_D, "clk_smmu3_lite_d", 743 "mout_aclk_gscl_fimc_user", 744 EN_IP_GSCL_FIMC, 7, 0, 0), 745 GATE(GSCL_CLK_CSIS0, "clk_csis0", "mout_aclk_gscl_fimc_user", 746 EN_IP_GSCL_FIMC, 8, 0, 0), 747 GATE(GSCL_CLK_CSIS1, "clk_csis1", "mout_aclk_gscl_fimc_user", 748 EN_IP_GSCL_FIMC, 9, 0, 0), 749 GATE(GSCL_CLK_FIMC_LITE_A, "clk_fimc_lite_a", 750 "mout_aclk_gscl_fimc_user", 751 EN_IP_GSCL_FIMC, 10, 0, 0), 752 GATE(GSCL_CLK_FIMC_LITE_B, "clk_fimc_lite_b", 753 "mout_aclk_gscl_fimc_user", 754 EN_IP_GSCL_FIMC, 11, 0, 0), 755 GATE(GSCL_CLK_FIMC_LITE_D, "clk_fimc_lite_d", 756 "mout_aclk_gscl_fimc_user", 757 EN_IP_GSCL_FIMC, 12, 0, 0), 758 759 GATE(GSCL_CLK_SMMU3_GSCL0, "clk_smmu3_gscl0", 760 "mout_aclk_gscl_333_user", 761 EN_IP_GSCL_SECURE_SMMU_GSCL0, 17, 0, 0), 762 GATE(GSCL_CLK_SMMU3_GSCL1, "clk_smmu3_gscl1", "mout_aclk_gscl_333_user", 763 EN_IP_GSCL_SECURE_SMMU_GSCL1, 18, 0, 0), 764 GATE(GSCL_CLK_SMMU3_MSCL0, "clk_smmu3_mscl0", 765 "mout_aclk_m2m_400_user", 766 EN_IP_GSCL_SECURE_SMMU_MSCL0, 19, 0, 0), 767 GATE(GSCL_CLK_SMMU3_MSCL1, "clk_smmu3_mscl1", 768 "mout_aclk_m2m_400_user", 769 EN_IP_GSCL_SECURE_SMMU_MSCL1, 20, 0, 0), 770 }; 771 772 static const struct samsung_cmu_info gscl_cmu __initconst = { 773 .mux_clks = gscl_mux_clks, 774 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks), 775 .div_clks = gscl_div_clks, 776 .nr_div_clks = ARRAY_SIZE(gscl_div_clks), 777 .gate_clks = gscl_gate_clks, 778 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks), 779 .nr_clk_ids = GSCL_NR_CLK, 780 .clk_regs = gscl_clk_regs, 781 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 782 }; 783 784 static void __init exynos5260_clk_gscl_init(struct device_node *np) 785 { 786 samsung_cmu_register_one(np, &gscl_cmu); 787 } 788 789 CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl", 790 exynos5260_clk_gscl_init); 791 792 793 /* CMU_ISP */ 794 795 static const unsigned long isp_clk_regs[] __initconst = { 796 MUX_SEL_ISP0, 797 MUX_SEL_ISP1, 798 DIV_ISP, 799 EN_ACLK_ISP0, 800 EN_ACLK_ISP1, 801 EN_PCLK_ISP0, 802 EN_PCLK_ISP1, 803 EN_SCLK_ISP, 804 EN_IP_ISP0, 805 EN_IP_ISP1, 806 }; 807 808 PNAME(mout_isp_400_user_p) = {"fin_pll", "dout_aclk_isp1_400"}; 809 PNAME(mout_isp_266_user_p) = {"fin_pll", "dout_aclk_isp1_266"}; 810 811 static const struct samsung_mux_clock isp_mux_clks[] __initconst = { 812 MUX(ISP_MOUT_ISP_266_USER, "mout_isp_266_user", mout_isp_266_user_p, 813 MUX_SEL_ISP0, 0, 1), 814 MUX(ISP_MOUT_ISP_400_USER, "mout_isp_400_user", mout_isp_400_user_p, 815 MUX_SEL_ISP0, 4, 1), 816 }; 817 818 static const struct samsung_div_clock isp_div_clks[] __initconst = { 819 DIV(ISP_DOUT_PCLK_ISP_66, "dout_pclk_isp_66", "mout_kfc", 820 DIV_ISP, 0, 3), 821 DIV(ISP_DOUT_PCLK_ISP_133, "dout_pclk_isp_133", "mout_kfc", 822 DIV_ISP, 4, 4), 823 DIV(ISP_DOUT_CA5_ATCLKIN, "dout_ca5_atclkin", "mout_kfc", 824 DIV_ISP, 12, 3), 825 DIV(ISP_DOUT_CA5_PCLKDBG, "dout_ca5_pclkdbg", "mout_kfc", 826 DIV_ISP, 16, 4), 827 DIV(ISP_DOUT_SCLK_MPWM, "dout_sclk_mpwm", "mout_kfc", DIV_ISP, 20, 2), 828 }; 829 830 static const struct samsung_gate_clock isp_gate_clks[] __initconst = { 831 GATE(ISP_CLK_GIC, "clk_isp_gic", "mout_aclk_isp1_266", 832 EN_IP_ISP0, 15, 0, 0), 833 834 GATE(ISP_CLK_CA5, "clk_isp_ca5", "mout_aclk_isp1_266", 835 EN_IP_ISP1, 1, 0, 0), 836 GATE(ISP_CLK_FIMC_DRC, "clk_isp_fimc_drc", "mout_aclk_isp1_266", 837 EN_IP_ISP1, 2, 0, 0), 838 GATE(ISP_CLK_FIMC_FD, "clk_isp_fimc_fd", "mout_aclk_isp1_266", 839 EN_IP_ISP1, 3, 0, 0), 840 GATE(ISP_CLK_FIMC, "clk_isp_fimc", "mout_aclk_isp1_266", 841 EN_IP_ISP1, 4, 0, 0), 842 GATE(ISP_CLK_FIMC_SCALERC, "clk_isp_fimc_scalerc", 843 "mout_aclk_isp1_266", 844 EN_IP_ISP1, 5, 0, 0), 845 GATE(ISP_CLK_FIMC_SCALERP, "clk_isp_fimc_scalerp", 846 "mout_aclk_isp1_266", 847 EN_IP_ISP1, 6, 0, 0), 848 GATE(ISP_CLK_I2C0, "clk_isp_i2c0", "mout_aclk_isp1_266", 849 EN_IP_ISP1, 7, 0, 0), 850 GATE(ISP_CLK_I2C1, "clk_isp_i2c1", "mout_aclk_isp1_266", 851 EN_IP_ISP1, 8, 0, 0), 852 GATE(ISP_CLK_MCUCTL, "clk_isp_mcuctl", "mout_aclk_isp1_266", 853 EN_IP_ISP1, 9, 0, 0), 854 GATE(ISP_CLK_MPWM, "clk_isp_mpwm", "mout_aclk_isp1_266", 855 EN_IP_ISP1, 10, 0, 0), 856 GATE(ISP_CLK_MTCADC, "clk_isp_mtcadc", "mout_aclk_isp1_266", 857 EN_IP_ISP1, 11, 0, 0), 858 GATE(ISP_CLK_PWM, "clk_isp_pwm", "mout_aclk_isp1_266", 859 EN_IP_ISP1, 14, 0, 0), 860 GATE(ISP_CLK_SMMU_DRC, "clk_smmu_drc", "mout_aclk_isp1_266", 861 EN_IP_ISP1, 21, 0, 0), 862 GATE(ISP_CLK_SMMU_FD, "clk_smmu_fd", "mout_aclk_isp1_266", 863 EN_IP_ISP1, 22, 0, 0), 864 GATE(ISP_CLK_SMMU_ISP, "clk_smmu_isp", "mout_aclk_isp1_266", 865 EN_IP_ISP1, 23, 0, 0), 866 GATE(ISP_CLK_SMMU_ISPCX, "clk_smmu_ispcx", "mout_aclk_isp1_266", 867 EN_IP_ISP1, 24, 0, 0), 868 GATE(ISP_CLK_SMMU_SCALERC, "clk_isp_smmu_scalerc", 869 "mout_aclk_isp1_266", 870 EN_IP_ISP1, 25, 0, 0), 871 GATE(ISP_CLK_SMMU_SCALERP, "clk_isp_smmu_scalerp", 872 "mout_aclk_isp1_266", 873 EN_IP_ISP1, 26, 0, 0), 874 GATE(ISP_CLK_SPI0, "clk_isp_spi0", "mout_aclk_isp1_266", 875 EN_IP_ISP1, 27, 0, 0), 876 GATE(ISP_CLK_SPI1, "clk_isp_spi1", "mout_aclk_isp1_266", 877 EN_IP_ISP1, 28, 0, 0), 878 GATE(ISP_CLK_WDT, "clk_isp_wdt", "mout_aclk_isp1_266", 879 EN_IP_ISP1, 31, 0, 0), 880 GATE(ISP_CLK_UART, "clk_isp_uart", "mout_aclk_isp1_266", 881 EN_IP_ISP1, 30, 0, 0), 882 883 GATE(ISP_SCLK_UART_EXT, "sclk_isp_uart_ext", "fin_pll", 884 EN_SCLK_ISP, 7, CLK_SET_RATE_PARENT, 0), 885 GATE(ISP_SCLK_SPI1_EXT, "sclk_isp_spi1_ext", "fin_pll", 886 EN_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0), 887 GATE(ISP_SCLK_SPI0_EXT, "sclk_isp_spi0_ext", "fin_pll", 888 EN_SCLK_ISP, 9, CLK_SET_RATE_PARENT, 0), 889 }; 890 891 static const struct samsung_cmu_info isp_cmu __initconst = { 892 .mux_clks = isp_mux_clks, 893 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks), 894 .div_clks = isp_div_clks, 895 .nr_div_clks = ARRAY_SIZE(isp_div_clks), 896 .gate_clks = isp_gate_clks, 897 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks), 898 .nr_clk_ids = ISP_NR_CLK, 899 .clk_regs = isp_clk_regs, 900 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 901 }; 902 903 static void __init exynos5260_clk_isp_init(struct device_node *np) 904 { 905 samsung_cmu_register_one(np, &isp_cmu); 906 } 907 908 CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp", 909 exynos5260_clk_isp_init); 910 911 912 /* CMU_KFC */ 913 914 static const unsigned long kfc_clk_regs[] __initconst = { 915 KFC_PLL_LOCK, 916 KFC_PLL_CON0, 917 KFC_PLL_CON1, 918 KFC_PLL_FDET, 919 MUX_SEL_KFC0, 920 MUX_SEL_KFC2, 921 DIV_KFC, 922 DIV_KFC_PLL_FDET, 923 EN_ACLK_KFC, 924 EN_PCLK_KFC, 925 EN_SCLK_KFC, 926 EN_IP_KFC, 927 }; 928 929 PNAME(mout_kfc_pll_p) = {"fin_pll", "fout_kfc_pll"}; 930 PNAME(mout_kfc_p) = {"mout_kfc_pll", "dout_media_pll"}; 931 932 static const struct samsung_mux_clock kfc_mux_clks[] __initconst = { 933 MUX(KFC_MOUT_KFC_PLL, "mout_kfc_pll", mout_kfc_pll_p, 934 MUX_SEL_KFC0, 0, 1), 935 MUX(KFC_MOUT_KFC, "mout_kfc", mout_kfc_p, MUX_SEL_KFC2, 0, 1), 936 }; 937 938 static const struct samsung_div_clock kfc_div_clks[] __initconst = { 939 DIV(KFC_DOUT_KFC1, "dout_kfc1", "mout_kfc", DIV_KFC, 0, 3), 940 DIV(KFC_DOUT_KFC2, "dout_kfc2", "dout_kfc1", DIV_KFC, 4, 3), 941 DIV(KFC_DOUT_KFC_ATCLK, "dout_kfc_atclk", "dout_kfc2", DIV_KFC, 8, 3), 942 DIV(KFC_DOUT_KFC_PCLK_DBG, "dout_kfc_pclk_dbg", "dout_kfc2", 943 DIV_KFC, 12, 3), 944 DIV(KFC_DOUT_ACLK_KFC, "dout_aclk_kfc", "dout_kfc2", DIV_KFC, 16, 3), 945 DIV(KFC_DOUT_PCLK_KFC, "dout_pclk_kfc", "dout_kfc2", DIV_KFC, 20, 3), 946 DIV(KFC_DOUT_KFC_PLL, "dout_kfc_pll", "mout_kfc", DIV_KFC, 24, 3), 947 }; 948 949 static const struct samsung_pll_clock kfc_pll_clks[] __initconst = { 950 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll", 951 KFC_PLL_LOCK, KFC_PLL_CON0, 952 pll2550_24mhz_tbl), 953 }; 954 955 static const struct samsung_cmu_info kfc_cmu __initconst = { 956 .pll_clks = kfc_pll_clks, 957 .nr_pll_clks = ARRAY_SIZE(kfc_pll_clks), 958 .mux_clks = kfc_mux_clks, 959 .nr_mux_clks = ARRAY_SIZE(kfc_mux_clks), 960 .div_clks = kfc_div_clks, 961 .nr_div_clks = ARRAY_SIZE(kfc_div_clks), 962 .nr_clk_ids = KFC_NR_CLK, 963 .clk_regs = kfc_clk_regs, 964 .nr_clk_regs = ARRAY_SIZE(kfc_clk_regs), 965 }; 966 967 static void __init exynos5260_clk_kfc_init(struct device_node *np) 968 { 969 samsung_cmu_register_one(np, &kfc_cmu); 970 } 971 972 CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc", 973 exynos5260_clk_kfc_init); 974 975 976 /* CMU_MFC */ 977 978 static const unsigned long mfc_clk_regs[] __initconst = { 979 MUX_SEL_MFC, 980 DIV_MFC, 981 EN_ACLK_MFC, 982 EN_ACLK_SECURE_SMMU2_MFC, 983 EN_PCLK_MFC, 984 EN_PCLK_SECURE_SMMU2_MFC, 985 EN_IP_MFC, 986 EN_IP_MFC_SECURE_SMMU2_MFC, 987 }; 988 989 PNAME(mout_aclk_mfc_333_user_p) = {"fin_pll", "dout_aclk_mfc_333"}; 990 991 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 992 MUX(MFC_MOUT_ACLK_MFC_333_USER, "mout_aclk_mfc_333_user", 993 mout_aclk_mfc_333_user_p, 994 MUX_SEL_MFC, 0, 1), 995 }; 996 997 static const struct samsung_div_clock mfc_div_clks[] __initconst = { 998 DIV(MFC_DOUT_PCLK_MFC_83, "dout_pclk_mfc_83", "mout_aclk_mfc_333_user", 999 DIV_MFC, 0, 3), 1000 }; 1001 1002 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { 1003 GATE(MFC_CLK_MFC, "clk_mfc", "mout_aclk_mfc_333_user", 1004 EN_IP_MFC, 1, 0, 0), 1005 GATE(MFC_CLK_SMMU2_MFCM0, "clk_smmu2_mfcm0", "mout_aclk_mfc_333_user", 1006 EN_IP_MFC_SECURE_SMMU2_MFC, 6, 0, 0), 1007 GATE(MFC_CLK_SMMU2_MFCM1, "clk_smmu2_mfcm1", "mout_aclk_mfc_333_user", 1008 EN_IP_MFC_SECURE_SMMU2_MFC, 7, 0, 0), 1009 }; 1010 1011 static const struct samsung_cmu_info mfc_cmu __initconst = { 1012 .mux_clks = mfc_mux_clks, 1013 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), 1014 .div_clks = mfc_div_clks, 1015 .nr_div_clks = ARRAY_SIZE(mfc_div_clks), 1016 .gate_clks = mfc_gate_clks, 1017 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), 1018 .nr_clk_ids = MFC_NR_CLK, 1019 .clk_regs = mfc_clk_regs, 1020 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 1021 }; 1022 1023 static void __init exynos5260_clk_mfc_init(struct device_node *np) 1024 { 1025 samsung_cmu_register_one(np, &mfc_cmu); 1026 } 1027 1028 CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc", 1029 exynos5260_clk_mfc_init); 1030 1031 1032 /* CMU_MIF */ 1033 1034 static const unsigned long mif_clk_regs[] __initconst = { 1035 MEM_PLL_LOCK, 1036 BUS_PLL_LOCK, 1037 MEDIA_PLL_LOCK, 1038 MEM_PLL_CON0, 1039 MEM_PLL_CON1, 1040 MEM_PLL_FDET, 1041 BUS_PLL_CON0, 1042 BUS_PLL_CON1, 1043 BUS_PLL_FDET, 1044 MEDIA_PLL_CON0, 1045 MEDIA_PLL_CON1, 1046 MEDIA_PLL_FDET, 1047 MUX_SEL_MIF, 1048 DIV_MIF, 1049 DIV_MIF_PLL_FDET, 1050 EN_ACLK_MIF, 1051 EN_ACLK_MIF_SECURE_DREX1_TZ, 1052 EN_ACLK_MIF_SECURE_DREX0_TZ, 1053 EN_ACLK_MIF_SECURE_INTMEM, 1054 EN_PCLK_MIF, 1055 EN_PCLK_MIF_SECURE_MONOCNT, 1056 EN_PCLK_MIF_SECURE_RTC_APBIF, 1057 EN_PCLK_MIF_SECURE_DREX1_TZ, 1058 EN_PCLK_MIF_SECURE_DREX0_TZ, 1059 EN_SCLK_MIF, 1060 EN_IP_MIF, 1061 EN_IP_MIF_SECURE_MONOCNT, 1062 EN_IP_MIF_SECURE_RTC_APBIF, 1063 EN_IP_MIF_SECURE_DREX1_TZ, 1064 EN_IP_MIF_SECURE_DREX0_TZ, 1065 EN_IP_MIF_SECURE_INTEMEM, 1066 }; 1067 1068 PNAME(mout_mem_pll_p) = {"fin_pll", "fout_mem_pll"}; 1069 PNAME(mout_bus_pll_p) = {"fin_pll", "fout_bus_pll"}; 1070 PNAME(mout_media_pll_p) = {"fin_pll", "fout_media_pll"}; 1071 PNAME(mout_mif_drex_p) = {"dout_mem_pll", "dout_bus_pll"}; 1072 PNAME(mout_mif_drex2x_p) = {"dout_mem_pll", "dout_bus_pll"}; 1073 PNAME(mout_clkm_phy_p) = {"mout_mif_drex", "dout_media_pll"}; 1074 PNAME(mout_clk2x_phy_p) = {"mout_mif_drex2x", "dout_media_pll"}; 1075 1076 static const struct samsung_mux_clock mif_mux_clks[] __initconst = { 1077 MUX(MIF_MOUT_MEM_PLL, "mout_mem_pll", mout_mem_pll_p, 1078 MUX_SEL_MIF, 0, 1), 1079 MUX(MIF_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, 1080 MUX_SEL_MIF, 4, 1), 1081 MUX(MIF_MOUT_MEDIA_PLL, "mout_media_pll", mout_media_pll_p, 1082 MUX_SEL_MIF, 8, 1), 1083 MUX(MIF_MOUT_MIF_DREX, "mout_mif_drex", mout_mif_drex_p, 1084 MUX_SEL_MIF, 12, 1), 1085 MUX(MIF_MOUT_CLKM_PHY, "mout_clkm_phy", mout_clkm_phy_p, 1086 MUX_SEL_MIF, 16, 1), 1087 MUX(MIF_MOUT_MIF_DREX2X, "mout_mif_drex2x", mout_mif_drex2x_p, 1088 MUX_SEL_MIF, 20, 1), 1089 MUX(MIF_MOUT_CLK2X_PHY, "mout_clk2x_phy", mout_clk2x_phy_p, 1090 MUX_SEL_MIF, 24, 1), 1091 }; 1092 1093 static const struct samsung_div_clock mif_div_clks[] __initconst = { 1094 DIV(MIF_DOUT_MEDIA_PLL, "dout_media_pll", "mout_media_pll", 1095 DIV_MIF, 0, 3), 1096 DIV(MIF_DOUT_MEM_PLL, "dout_mem_pll", "mout_mem_pll", 1097 DIV_MIF, 4, 3), 1098 DIV(MIF_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1099 DIV_MIF, 8, 3), 1100 DIV(MIF_DOUT_CLKM_PHY, "dout_clkm_phy", "mout_clkm_phy", 1101 DIV_MIF, 12, 3), 1102 DIV(MIF_DOUT_CLK2X_PHY, "dout_clk2x_phy", "mout_clk2x_phy", 1103 DIV_MIF, 16, 4), 1104 DIV(MIF_DOUT_ACLK_MIF_466, "dout_aclk_mif_466", "dout_clk2x_phy", 1105 DIV_MIF, 20, 3), 1106 DIV(MIF_DOUT_ACLK_BUS_200, "dout_aclk_bus_200", "dout_bus_pll", 1107 DIV_MIF, 24, 3), 1108 DIV(MIF_DOUT_ACLK_BUS_100, "dout_aclk_bus_100", "dout_bus_pll", 1109 DIV_MIF, 28, 4), 1110 }; 1111 1112 static const struct samsung_gate_clock mif_gate_clks[] __initconst = { 1113 GATE(MIF_CLK_LPDDR3PHY_WRAP0, "clk_lpddr3phy_wrap0", "dout_clk2x_phy", 1114 EN_IP_MIF, 12, CLK_IGNORE_UNUSED, 0), 1115 GATE(MIF_CLK_LPDDR3PHY_WRAP1, "clk_lpddr3phy_wrap1", "dout_clk2x_phy", 1116 EN_IP_MIF, 13, CLK_IGNORE_UNUSED, 0), 1117 1118 GATE(MIF_CLK_MONOCNT, "clk_monocnt", "dout_aclk_bus_100", 1119 EN_IP_MIF_SECURE_MONOCNT, 22, 1120 CLK_IGNORE_UNUSED, 0), 1121 1122 GATE(MIF_CLK_MIF_RTC, "clk_mif_rtc", "dout_aclk_bus_100", 1123 EN_IP_MIF_SECURE_RTC_APBIF, 23, 1124 CLK_IGNORE_UNUSED, 0), 1125 1126 GATE(MIF_CLK_DREX1, "clk_drex1", "dout_aclk_mif_466", 1127 EN_IP_MIF_SECURE_DREX1_TZ, 9, 1128 CLK_IGNORE_UNUSED, 0), 1129 1130 GATE(MIF_CLK_DREX0, "clk_drex0", "dout_aclk_mif_466", 1131 EN_IP_MIF_SECURE_DREX0_TZ, 9, 1132 CLK_IGNORE_UNUSED, 0), 1133 1134 GATE(MIF_CLK_INTMEM, "clk_intmem", "dout_aclk_bus_200", 1135 EN_IP_MIF_SECURE_INTEMEM, 11, 1136 CLK_IGNORE_UNUSED, 0), 1137 1138 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U0, "sclk_lpddr3phy_wrap_u0", 1139 "dout_clkm_phy", EN_SCLK_MIF, 0, 1140 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1141 GATE(MIF_SCLK_LPDDR3PHY_WRAP_U1, "sclk_lpddr3phy_wrap_u1", 1142 "dout_clkm_phy", EN_SCLK_MIF, 1, 1143 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0), 1144 }; 1145 1146 static const struct samsung_pll_clock mif_pll_clks[] __initconst = { 1147 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll", 1148 MEM_PLL_LOCK, MEM_PLL_CON0, 1149 pll2550_24mhz_tbl), 1150 PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll", 1151 BUS_PLL_LOCK, BUS_PLL_CON0, 1152 pll2550_24mhz_tbl), 1153 PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll", 1154 MEDIA_PLL_LOCK, MEDIA_PLL_CON0, 1155 pll2550_24mhz_tbl), 1156 }; 1157 1158 static const struct samsung_cmu_info mif_cmu __initconst = { 1159 .pll_clks = mif_pll_clks, 1160 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks), 1161 .mux_clks = mif_mux_clks, 1162 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks), 1163 .div_clks = mif_div_clks, 1164 .nr_div_clks = ARRAY_SIZE(mif_div_clks), 1165 .gate_clks = mif_gate_clks, 1166 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks), 1167 .nr_clk_ids = MIF_NR_CLK, 1168 .clk_regs = mif_clk_regs, 1169 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs), 1170 }; 1171 1172 static void __init exynos5260_clk_mif_init(struct device_node *np) 1173 { 1174 samsung_cmu_register_one(np, &mif_cmu); 1175 } 1176 1177 CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif", 1178 exynos5260_clk_mif_init); 1179 1180 1181 /* CMU_PERI */ 1182 1183 static const unsigned long peri_clk_regs[] __initconst = { 1184 MUX_SEL_PERI, 1185 MUX_SEL_PERI1, 1186 DIV_PERI, 1187 EN_PCLK_PERI0, 1188 EN_PCLK_PERI1, 1189 EN_PCLK_PERI2, 1190 EN_PCLK_PERI3, 1191 EN_PCLK_PERI_SECURE_CHIPID, 1192 EN_PCLK_PERI_SECURE_PROVKEY0, 1193 EN_PCLK_PERI_SECURE_PROVKEY1, 1194 EN_PCLK_PERI_SECURE_SECKEY, 1195 EN_PCLK_PERI_SECURE_ANTIRBKCNT, 1196 EN_PCLK_PERI_SECURE_TOP_RTC, 1197 EN_PCLK_PERI_SECURE_TZPC, 1198 EN_SCLK_PERI, 1199 EN_SCLK_PERI_SECURE_TOP_RTC, 1200 EN_IP_PERI0, 1201 EN_IP_PERI1, 1202 EN_IP_PERI2, 1203 EN_IP_PERI_SECURE_CHIPID, 1204 EN_IP_PERI_SECURE_PROVKEY0, 1205 EN_IP_PERI_SECURE_PROVKEY1, 1206 EN_IP_PERI_SECURE_SECKEY, 1207 EN_IP_PERI_SECURE_ANTIRBKCNT, 1208 EN_IP_PERI_SECURE_TOP_RTC, 1209 EN_IP_PERI_SECURE_TZPC, 1210 }; 1211 1212 PNAME(mout_sclk_pcm_p) = {"ioclk_pcm_extclk", "fin_pll", "dout_aclk_peri_aud", 1213 "phyclk_hdmi_phy_ref_cko"}; 1214 PNAME(mout_sclk_i2scod_p) = {"ioclk_i2s_cdclk", "fin_pll", "dout_aclk_peri_aud", 1215 "phyclk_hdmi_phy_ref_cko"}; 1216 PNAME(mout_sclk_spdif_p) = {"ioclk_spdif_extclk", "fin_pll", 1217 "dout_aclk_peri_aud", "phyclk_hdmi_phy_ref_cko"}; 1218 1219 static const struct samsung_mux_clock peri_mux_clks[] __initconst = { 1220 MUX(PERI_MOUT_SCLK_PCM, "mout_sclk_pcm", mout_sclk_pcm_p, 1221 MUX_SEL_PERI1, 4, 2), 1222 MUX(PERI_MOUT_SCLK_I2SCOD, "mout_sclk_i2scod", mout_sclk_i2scod_p, 1223 MUX_SEL_PERI1, 12, 2), 1224 MUX(PERI_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p, 1225 MUX_SEL_PERI1, 20, 2), 1226 }; 1227 1228 static const struct samsung_div_clock peri_div_clks[] __initconst = { 1229 DIV(PERI_DOUT_PCM, "dout_pcm", "mout_sclk_pcm", DIV_PERI, 0, 8), 1230 DIV(PERI_DOUT_I2S, "dout_i2s", "mout_sclk_i2scod", DIV_PERI, 8, 6), 1231 }; 1232 1233 static const struct samsung_gate_clock peri_gate_clks[] __initconst = { 1234 GATE(PERI_SCLK_PCM1, "sclk_pcm1", "dout_pcm", EN_SCLK_PERI, 0, 1235 CLK_SET_RATE_PARENT, 0), 1236 GATE(PERI_SCLK_I2S, "sclk_i2s", "dout_i2s", EN_SCLK_PERI, 1, 1237 CLK_SET_RATE_PARENT, 0), 1238 GATE(PERI_SCLK_SPDIF, "sclk_spdif", "dout_sclk_peri_spi0_b", 1239 EN_SCLK_PERI, 2, CLK_SET_RATE_PARENT, 0), 1240 GATE(PERI_SCLK_SPI0, "sclk_spi0", "dout_sclk_peri_spi0_b", 1241 EN_SCLK_PERI, 7, CLK_SET_RATE_PARENT, 0), 1242 GATE(PERI_SCLK_SPI1, "sclk_spi1", "dout_sclk_peri_spi1_b", 1243 EN_SCLK_PERI, 8, CLK_SET_RATE_PARENT, 0), 1244 GATE(PERI_SCLK_SPI2, "sclk_spi2", "dout_sclk_peri_spi2_b", 1245 EN_SCLK_PERI, 9, CLK_SET_RATE_PARENT, 0), 1246 GATE(PERI_SCLK_UART0, "sclk_uart0", "dout_sclk_peri_uart0", 1247 EN_SCLK_PERI, 10, CLK_SET_RATE_PARENT, 0), 1248 GATE(PERI_SCLK_UART1, "sclk_uart1", "dout_sclk_peri_uart1", 1249 EN_SCLK_PERI, 11, CLK_SET_RATE_PARENT, 0), 1250 GATE(PERI_SCLK_UART2, "sclk_uart2", "dout_sclk_peri_uart2", 1251 EN_SCLK_PERI, 12, CLK_SET_RATE_PARENT, 0), 1252 1253 GATE(PERI_CLK_ABB, "clk_abb", "dout_aclk_peri_66", 1254 EN_IP_PERI0, 1, 0, 0), 1255 GATE(PERI_CLK_EFUSE_WRITER, "clk_efuse_writer", "dout_aclk_peri_66", 1256 EN_IP_PERI0, 5, 0, 0), 1257 GATE(PERI_CLK_HDMICEC, "clk_hdmicec", "dout_aclk_peri_66", 1258 EN_IP_PERI0, 6, 0, 0), 1259 GATE(PERI_CLK_I2C10, "clk_i2c10", "dout_aclk_peri_66", 1260 EN_IP_PERI0, 7, 0, 0), 1261 GATE(PERI_CLK_I2C11, "clk_i2c11", "dout_aclk_peri_66", 1262 EN_IP_PERI0, 8, 0, 0), 1263 GATE(PERI_CLK_I2C8, "clk_i2c8", "dout_aclk_peri_66", 1264 EN_IP_PERI0, 9, 0, 0), 1265 GATE(PERI_CLK_I2C9, "clk_i2c9", "dout_aclk_peri_66", 1266 EN_IP_PERI0, 10, 0, 0), 1267 GATE(PERI_CLK_I2C4, "clk_i2c4", "dout_aclk_peri_66", 1268 EN_IP_PERI0, 11, 0, 0), 1269 GATE(PERI_CLK_I2C5, "clk_i2c5", "dout_aclk_peri_66", 1270 EN_IP_PERI0, 12, 0, 0), 1271 GATE(PERI_CLK_I2C6, "clk_i2c6", "dout_aclk_peri_66", 1272 EN_IP_PERI0, 13, 0, 0), 1273 GATE(PERI_CLK_I2C7, "clk_i2c7", "dout_aclk_peri_66", 1274 EN_IP_PERI0, 14, 0, 0), 1275 GATE(PERI_CLK_I2CHDMI, "clk_i2chdmi", "dout_aclk_peri_66", 1276 EN_IP_PERI0, 15, 0, 0), 1277 GATE(PERI_CLK_I2S, "clk_peri_i2s", "dout_aclk_peri_66", 1278 EN_IP_PERI0, 16, 0, 0), 1279 GATE(PERI_CLK_MCT, "clk_mct", "dout_aclk_peri_66", 1280 EN_IP_PERI0, 17, 0, 0), 1281 GATE(PERI_CLK_PCM, "clk_peri_pcm", "dout_aclk_peri_66", 1282 EN_IP_PERI0, 18, 0, 0), 1283 GATE(PERI_CLK_HSIC0, "clk_hsic0", "dout_aclk_peri_66", 1284 EN_IP_PERI0, 20, 0, 0), 1285 GATE(PERI_CLK_HSIC1, "clk_hsic1", "dout_aclk_peri_66", 1286 EN_IP_PERI0, 21, 0, 0), 1287 GATE(PERI_CLK_HSIC2, "clk_hsic2", "dout_aclk_peri_66", 1288 EN_IP_PERI0, 22, 0, 0), 1289 GATE(PERI_CLK_HSIC3, "clk_hsic3", "dout_aclk_peri_66", 1290 EN_IP_PERI0, 23, 0, 0), 1291 GATE(PERI_CLK_WDT_EGL, "clk_wdt_egl", "dout_aclk_peri_66", 1292 EN_IP_PERI0, 24, 0, 0), 1293 GATE(PERI_CLK_WDT_KFC, "clk_wdt_kfc", "dout_aclk_peri_66", 1294 EN_IP_PERI0, 25, 0, 0), 1295 1296 GATE(PERI_CLK_UART4, "clk_uart4", "dout_aclk_peri_66", 1297 EN_IP_PERI2, 0, 0, 0), 1298 GATE(PERI_CLK_PWM, "clk_pwm", "dout_aclk_peri_66", 1299 EN_IP_PERI2, 3, 0, 0), 1300 GATE(PERI_CLK_SPDIF, "clk_spdif", "dout_aclk_peri_66", 1301 EN_IP_PERI2, 6, 0, 0), 1302 GATE(PERI_CLK_SPI0, "clk_spi0", "dout_aclk_peri_66", 1303 EN_IP_PERI2, 7, 0, 0), 1304 GATE(PERI_CLK_SPI1, "clk_spi1", "dout_aclk_peri_66", 1305 EN_IP_PERI2, 8, 0, 0), 1306 GATE(PERI_CLK_SPI2, "clk_spi2", "dout_aclk_peri_66", 1307 EN_IP_PERI2, 9, 0, 0), 1308 GATE(PERI_CLK_TMU0, "clk_tmu0", "dout_aclk_peri_66", 1309 EN_IP_PERI2, 10, 0, 0), 1310 GATE(PERI_CLK_TMU1, "clk_tmu1", "dout_aclk_peri_66", 1311 EN_IP_PERI2, 11, 0, 0), 1312 GATE(PERI_CLK_TMU2, "clk_tmu2", "dout_aclk_peri_66", 1313 EN_IP_PERI2, 12, 0, 0), 1314 GATE(PERI_CLK_TMU3, "clk_tmu3", "dout_aclk_peri_66", 1315 EN_IP_PERI2, 13, 0, 0), 1316 GATE(PERI_CLK_TMU4, "clk_tmu4", "dout_aclk_peri_66", 1317 EN_IP_PERI2, 14, 0, 0), 1318 GATE(PERI_CLK_ADC, "clk_adc", "dout_aclk_peri_66", 1319 EN_IP_PERI2, 18, 0, 0), 1320 GATE(PERI_CLK_UART0, "clk_uart0", "dout_aclk_peri_66", 1321 EN_IP_PERI2, 19, 0, 0), 1322 GATE(PERI_CLK_UART1, "clk_uart1", "dout_aclk_peri_66", 1323 EN_IP_PERI2, 20, 0, 0), 1324 GATE(PERI_CLK_UART2, "clk_uart2", "dout_aclk_peri_66", 1325 EN_IP_PERI2, 21, 0, 0), 1326 1327 GATE(PERI_CLK_CHIPID, "clk_chipid", "dout_aclk_peri_66", 1328 EN_IP_PERI_SECURE_CHIPID, 2, 0, 0), 1329 1330 GATE(PERI_CLK_PROVKEY0, "clk_provkey0", "dout_aclk_peri_66", 1331 EN_IP_PERI_SECURE_PROVKEY0, 1, 0, 0), 1332 1333 GATE(PERI_CLK_PROVKEY1, "clk_provkey1", "dout_aclk_peri_66", 1334 EN_IP_PERI_SECURE_PROVKEY1, 2, 0, 0), 1335 1336 GATE(PERI_CLK_SECKEY, "clk_seckey", "dout_aclk_peri_66", 1337 EN_IP_PERI_SECURE_SECKEY, 5, 0, 0), 1338 1339 GATE(PERI_CLK_TOP_RTC, "clk_top_rtc", "dout_aclk_peri_66", 1340 EN_IP_PERI_SECURE_TOP_RTC, 5, 0, 0), 1341 1342 GATE(PERI_CLK_TZPC0, "clk_tzpc0", "dout_aclk_peri_66", 1343 EN_IP_PERI_SECURE_TZPC, 10, 0, 0), 1344 GATE(PERI_CLK_TZPC1, "clk_tzpc1", "dout_aclk_peri_66", 1345 EN_IP_PERI_SECURE_TZPC, 11, 0, 0), 1346 GATE(PERI_CLK_TZPC2, "clk_tzpc2", "dout_aclk_peri_66", 1347 EN_IP_PERI_SECURE_TZPC, 12, 0, 0), 1348 GATE(PERI_CLK_TZPC3, "clk_tzpc3", "dout_aclk_peri_66", 1349 EN_IP_PERI_SECURE_TZPC, 13, 0, 0), 1350 GATE(PERI_CLK_TZPC4, "clk_tzpc4", "dout_aclk_peri_66", 1351 EN_IP_PERI_SECURE_TZPC, 14, 0, 0), 1352 GATE(PERI_CLK_TZPC5, "clk_tzpc5", "dout_aclk_peri_66", 1353 EN_IP_PERI_SECURE_TZPC, 15, 0, 0), 1354 GATE(PERI_CLK_TZPC6, "clk_tzpc6", "dout_aclk_peri_66", 1355 EN_IP_PERI_SECURE_TZPC, 16, 0, 0), 1356 GATE(PERI_CLK_TZPC7, "clk_tzpc7", "dout_aclk_peri_66", 1357 EN_IP_PERI_SECURE_TZPC, 17, 0, 0), 1358 GATE(PERI_CLK_TZPC8, "clk_tzpc8", "dout_aclk_peri_66", 1359 EN_IP_PERI_SECURE_TZPC, 18, 0, 0), 1360 GATE(PERI_CLK_TZPC9, "clk_tzpc9", "dout_aclk_peri_66", 1361 EN_IP_PERI_SECURE_TZPC, 19, 0, 0), 1362 GATE(PERI_CLK_TZPC10, "clk_tzpc10", "dout_aclk_peri_66", 1363 EN_IP_PERI_SECURE_TZPC, 20, 0, 0), 1364 }; 1365 1366 static const struct samsung_cmu_info peri_cmu __initconst = { 1367 .mux_clks = peri_mux_clks, 1368 .nr_mux_clks = ARRAY_SIZE(peri_mux_clks), 1369 .div_clks = peri_div_clks, 1370 .nr_div_clks = ARRAY_SIZE(peri_div_clks), 1371 .gate_clks = peri_gate_clks, 1372 .nr_gate_clks = ARRAY_SIZE(peri_gate_clks), 1373 .nr_clk_ids = PERI_NR_CLK, 1374 .clk_regs = peri_clk_regs, 1375 .nr_clk_regs = ARRAY_SIZE(peri_clk_regs), 1376 }; 1377 1378 static void __init exynos5260_clk_peri_init(struct device_node *np) 1379 { 1380 samsung_cmu_register_one(np, &peri_cmu); 1381 } 1382 1383 CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri", 1384 exynos5260_clk_peri_init); 1385 1386 1387 /* CMU_TOP */ 1388 1389 static const unsigned long top_clk_regs[] __initconst = { 1390 DISP_PLL_LOCK, 1391 AUD_PLL_LOCK, 1392 DISP_PLL_CON0, 1393 DISP_PLL_CON1, 1394 DISP_PLL_FDET, 1395 AUD_PLL_CON0, 1396 AUD_PLL_CON1, 1397 AUD_PLL_CON2, 1398 AUD_PLL_FDET, 1399 MUX_SEL_TOP_PLL0, 1400 MUX_SEL_TOP_MFC, 1401 MUX_SEL_TOP_G2D, 1402 MUX_SEL_TOP_GSCL, 1403 MUX_SEL_TOP_ISP10, 1404 MUX_SEL_TOP_ISP11, 1405 MUX_SEL_TOP_DISP0, 1406 MUX_SEL_TOP_DISP1, 1407 MUX_SEL_TOP_BUS, 1408 MUX_SEL_TOP_PERI0, 1409 MUX_SEL_TOP_PERI1, 1410 MUX_SEL_TOP_FSYS, 1411 DIV_TOP_G2D_MFC, 1412 DIV_TOP_GSCL_ISP0, 1413 DIV_TOP_ISP10, 1414 DIV_TOP_ISP11, 1415 DIV_TOP_DISP, 1416 DIV_TOP_BUS, 1417 DIV_TOP_PERI0, 1418 DIV_TOP_PERI1, 1419 DIV_TOP_PERI2, 1420 DIV_TOP_FSYS0, 1421 DIV_TOP_FSYS1, 1422 DIV_TOP_HPM, 1423 DIV_TOP_PLL_FDET, 1424 EN_ACLK_TOP, 1425 EN_SCLK_TOP, 1426 EN_IP_TOP, 1427 }; 1428 1429 /* fixed rate clocks generated inside the soc */ 1430 static const struct samsung_fixed_rate_clock fixed_rate_clks[] __initconst = { 1431 FRATE(PHYCLK_DPTX_PHY_CH3_TXD_CLK, "phyclk_dptx_phy_ch3_txd_clk", NULL, 1432 0, 270000000), 1433 FRATE(PHYCLK_DPTX_PHY_CH2_TXD_CLK, "phyclk_dptx_phy_ch2_txd_clk", NULL, 1434 0, 270000000), 1435 FRATE(PHYCLK_DPTX_PHY_CH1_TXD_CLK, "phyclk_dptx_phy_ch1_txd_clk", NULL, 1436 0, 270000000), 1437 FRATE(PHYCLK_DPTX_PHY_CH0_TXD_CLK, "phyclk_dptx_phy_ch0_txd_clk", NULL, 1438 0, 270000000), 1439 FRATE(phyclk_hdmi_phy_tmds_clko, "phyclk_hdmi_phy_tmds_clko", NULL, 1440 0, 250000000), 1441 FRATE(PHYCLK_HDMI_PHY_PIXEL_CLKO, "phyclk_hdmi_phy_pixel_clko", NULL, 1442 0, 1660000000), 1443 FRATE(PHYCLK_HDMI_LINK_O_TMDS_CLKHI, "phyclk_hdmi_link_o_tmds_clkhi", 1444 NULL, 0, 125000000), 1445 FRATE(PHYCLK_MIPI_DPHY_4L_M_TXBYTECLKHS, 1446 "phyclk_mipi_dphy_4l_m_txbyte_clkhs" , NULL, 1447 0, 187500000), 1448 FRATE(PHYCLK_DPTX_PHY_O_REF_CLK_24M, "phyclk_dptx_phy_o_ref_clk_24m", 1449 NULL, 0, 24000000), 1450 FRATE(PHYCLK_DPTX_PHY_CLK_DIV2, "phyclk_dptx_phy_clk_div2", NULL, 1451 0, 135000000), 1452 FRATE(PHYCLK_MIPI_DPHY_4L_M_RXCLKESC0, 1453 "phyclk_mipi_dphy_4l_m_rxclkesc0", NULL, 0, 20000000), 1454 FRATE(PHYCLK_USBHOST20_PHY_PHYCLOCK, "phyclk_usbhost20_phy_phyclock", 1455 NULL, 0, 60000000), 1456 FRATE(PHYCLK_USBHOST20_PHY_FREECLK, "phyclk_usbhost20_phy_freeclk", 1457 NULL, 0, 60000000), 1458 FRATE(PHYCLK_USBHOST20_PHY_CLK48MOHCI, 1459 "phyclk_usbhost20_phy_clk48mohci", NULL, 0, 48000000), 1460 FRATE(PHYCLK_USBDRD30_UDRD30_PIPE_PCLK, 1461 "phyclk_usbdrd30_udrd30_pipe_pclk", NULL, 0, 125000000), 1462 FRATE(PHYCLK_USBDRD30_UDRD30_PHYCLOCK, 1463 "phyclk_usbdrd30_udrd30_phyclock", NULL, 0, 60000000), 1464 }; 1465 1466 PNAME(mout_memtop_pll_user_p) = {"fin_pll", "dout_mem_pll"}; 1467 PNAME(mout_bustop_pll_user_p) = {"fin_pll", "dout_bus_pll"}; 1468 PNAME(mout_mediatop_pll_user_p) = {"fin_pll", "dout_media_pll"}; 1469 PNAME(mout_audtop_pll_user_p) = {"fin_pll", "mout_aud_pll"}; 1470 PNAME(mout_aud_pll_p) = {"fin_pll", "fout_aud_pll"}; 1471 PNAME(mout_disp_pll_p) = {"fin_pll", "fout_disp_pll"}; 1472 PNAME(mout_mfc_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1473 PNAME(mout_aclk_mfc_333_p) = {"mout_mediatop_pll_user", "mout_mfc_bustop_333"}; 1474 PNAME(mout_g2d_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1475 PNAME(mout_aclk_g2d_333_p) = {"mout_mediatop_pll_user", "mout_g2d_bustop_333"}; 1476 PNAME(mout_gscl_bustop_333_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1477 PNAME(mout_aclk_gscl_333_p) = {"mout_mediatop_pll_user", 1478 "mout_gscl_bustop_333"}; 1479 PNAME(mout_m2m_mediatop_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; 1480 PNAME(mout_aclk_gscl_400_p) = {"mout_bustop_pll_user", 1481 "mout_m2m_mediatop_400"}; 1482 PNAME(mout_gscl_bustop_fimc_p) = {"mout_bustop_pll_user", "mout_disp_pll"}; 1483 PNAME(mout_aclk_gscl_fimc_p) = {"mout_mediatop_pll_user", 1484 "mout_gscl_bustop_fimc"}; 1485 PNAME(mout_isp1_media_266_p) = {"mout_mediatop_pll_user", 1486 "mout_memtop_pll_user"}; 1487 PNAME(mout_aclk_isp1_266_p) = {"mout_bustop_pll_user", "mout_isp1_media_266"}; 1488 PNAME(mout_isp1_media_400_p) = {"mout_mediatop_pll_user", "mout_disp_pll"}; 1489 PNAME(mout_aclk_isp1_400_p) = {"mout_bustop_pll_user", "mout_isp1_media_400"}; 1490 PNAME(mout_sclk_isp_spi_p) = {"fin_pll", "mout_bustop_pll_user"}; 1491 PNAME(mout_sclk_isp_uart_p) = {"fin_pll", "mout_bustop_pll_user"}; 1492 PNAME(mout_sclk_isp_sensor_p) = {"fin_pll", "mout_bustop_pll_user"}; 1493 PNAME(mout_disp_disp_333_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; 1494 PNAME(mout_aclk_disp_333_p) = {"mout_mediatop_pll_user", "mout_disp_disp_333"}; 1495 PNAME(mout_disp_disp_222_p) = {"mout_disp_pll", "mout_bustop_pll_user"}; 1496 PNAME(mout_aclk_disp_222_p) = {"mout_mediatop_pll_user", "mout_disp_disp_222"}; 1497 PNAME(mout_disp_media_pixel_p) = {"mout_mediatop_pll_user", 1498 "mout_bustop_pll_user"}; 1499 PNAME(mout_sclk_disp_pixel_p) = {"mout_disp_pll", "mout_disp_media_pixel"}; 1500 PNAME(mout_bus_bustop_400_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; 1501 PNAME(mout_bus_bustop_100_p) = {"mout_bustop_pll_user", "mout_memtop_pll_user"}; 1502 PNAME(mout_sclk_peri_spi_clk_p) = {"fin_pll", "mout_bustop_pll_user"}; 1503 PNAME(mout_sclk_peri_uart_uclk_p) = {"fin_pll", "mout_bustop_pll_user"}; 1504 PNAME(mout_sclk_fsys_usb_p) = {"fin_pll", "mout_bustop_pll_user"}; 1505 PNAME(mout_sclk_fsys_mmc_sdclkin_a_p) = {"fin_pll", "mout_bustop_pll_user"}; 1506 PNAME(mout_sclk_fsys_mmc0_sdclkin_b_p) = {"mout_sclk_fsys_mmc0_sdclkin_a", 1507 "mout_mediatop_pll_user"}; 1508 PNAME(mout_sclk_fsys_mmc1_sdclkin_b_p) = {"mout_sclk_fsys_mmc1_sdclkin_a", 1509 "mout_mediatop_pll_user"}; 1510 PNAME(mout_sclk_fsys_mmc2_sdclkin_b_p) = {"mout_sclk_fsys_mmc2_sdclkin_a", 1511 "mout_mediatop_pll_user"}; 1512 1513 static const struct samsung_mux_clock top_mux_clks[] __initconst = { 1514 MUX(TOP_MOUT_MEDIATOP_PLL_USER, "mout_mediatop_pll_user", 1515 mout_mediatop_pll_user_p, 1516 MUX_SEL_TOP_PLL0, 0, 1), 1517 MUX(TOP_MOUT_MEMTOP_PLL_USER, "mout_memtop_pll_user", 1518 mout_memtop_pll_user_p, 1519 MUX_SEL_TOP_PLL0, 4, 1), 1520 MUX(TOP_MOUT_BUSTOP_PLL_USER, "mout_bustop_pll_user", 1521 mout_bustop_pll_user_p, 1522 MUX_SEL_TOP_PLL0, 8, 1), 1523 MUX(TOP_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, 1524 MUX_SEL_TOP_PLL0, 12, 1), 1525 MUX(TOP_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, 1526 MUX_SEL_TOP_PLL0, 16, 1), 1527 MUX(TOP_MOUT_AUDTOP_PLL_USER, "mout_audtop_pll_user", 1528 mout_audtop_pll_user_p, 1529 MUX_SEL_TOP_PLL0, 24, 1), 1530 1531 MUX(TOP_MOUT_DISP_DISP_333, "mout_disp_disp_333", mout_disp_disp_333_p, 1532 MUX_SEL_TOP_DISP0, 0, 1), 1533 MUX(TOP_MOUT_ACLK_DISP_333, "mout_aclk_disp_333", mout_aclk_disp_333_p, 1534 MUX_SEL_TOP_DISP0, 8, 1), 1535 MUX(TOP_MOUT_DISP_DISP_222, "mout_disp_disp_222", mout_disp_disp_222_p, 1536 MUX_SEL_TOP_DISP0, 12, 1), 1537 MUX(TOP_MOUT_ACLK_DISP_222, "mout_aclk_disp_222", mout_aclk_disp_222_p, 1538 MUX_SEL_TOP_DISP0, 20, 1), 1539 1540 MUX(TOP_MOUT_FIMD1, "mout_sclk_disp_pixel", mout_sclk_disp_pixel_p, 1541 MUX_SEL_TOP_DISP1, 0, 1), 1542 MUX(TOP_MOUT_DISP_MEDIA_PIXEL, "mout_disp_media_pixel", 1543 mout_disp_media_pixel_p, 1544 MUX_SEL_TOP_DISP1, 8, 1), 1545 1546 MUX(TOP_MOUT_SCLK_PERI_SPI2_CLK, "mout_sclk_peri_spi2_clk", 1547 mout_sclk_peri_spi_clk_p, 1548 MUX_SEL_TOP_PERI1, 0, 1), 1549 MUX(TOP_MOUT_SCLK_PERI_SPI1_CLK, "mout_sclk_peri_spi1_clk", 1550 mout_sclk_peri_spi_clk_p, 1551 MUX_SEL_TOP_PERI1, 4, 1), 1552 MUX(TOP_MOUT_SCLK_PERI_SPI0_CLK, "mout_sclk_peri_spi0_clk", 1553 mout_sclk_peri_spi_clk_p, 1554 MUX_SEL_TOP_PERI1, 8, 1), 1555 MUX(TOP_MOUT_SCLK_PERI_UART1_UCLK, "mout_sclk_peri_uart1_uclk", 1556 mout_sclk_peri_uart_uclk_p, 1557 MUX_SEL_TOP_PERI1, 12, 1), 1558 MUX(TOP_MOUT_SCLK_PERI_UART2_UCLK, "mout_sclk_peri_uart2_uclk", 1559 mout_sclk_peri_uart_uclk_p, 1560 MUX_SEL_TOP_PERI1, 16, 1), 1561 MUX(TOP_MOUT_SCLK_PERI_UART0_UCLK, "mout_sclk_peri_uart0_uclk", 1562 mout_sclk_peri_uart_uclk_p, 1563 MUX_SEL_TOP_PERI1, 20, 1), 1564 1565 1566 MUX(TOP_MOUT_BUS1_BUSTOP_400, "mout_bus1_bustop_400", 1567 mout_bus_bustop_400_p, 1568 MUX_SEL_TOP_BUS, 0, 1), 1569 MUX(TOP_MOUT_BUS1_BUSTOP_100, "mout_bus1_bustop_100", 1570 mout_bus_bustop_100_p, 1571 MUX_SEL_TOP_BUS, 4, 1), 1572 MUX(TOP_MOUT_BUS2_BUSTOP_100, "mout_bus2_bustop_100", 1573 mout_bus_bustop_100_p, 1574 MUX_SEL_TOP_BUS, 8, 1), 1575 MUX(TOP_MOUT_BUS2_BUSTOP_400, "mout_bus2_bustop_400", 1576 mout_bus_bustop_400_p, 1577 MUX_SEL_TOP_BUS, 12, 1), 1578 MUX(TOP_MOUT_BUS3_BUSTOP_400, "mout_bus3_bustop_400", 1579 mout_bus_bustop_400_p, 1580 MUX_SEL_TOP_BUS, 16, 1), 1581 MUX(TOP_MOUT_BUS3_BUSTOP_100, "mout_bus3_bustop_100", 1582 mout_bus_bustop_100_p, 1583 MUX_SEL_TOP_BUS, 20, 1), 1584 MUX(TOP_MOUT_BUS4_BUSTOP_400, "mout_bus4_bustop_400", 1585 mout_bus_bustop_400_p, 1586 MUX_SEL_TOP_BUS, 24, 1), 1587 MUX(TOP_MOUT_BUS4_BUSTOP_100, "mout_bus4_bustop_100", 1588 mout_bus_bustop_100_p, 1589 MUX_SEL_TOP_BUS, 28, 1), 1590 1591 MUX(TOP_MOUT_SCLK_FSYS_USB, "mout_sclk_fsys_usb", 1592 mout_sclk_fsys_usb_p, 1593 MUX_SEL_TOP_FSYS, 0, 1), 1594 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "mout_sclk_fsys_mmc2_sdclkin_a", 1595 mout_sclk_fsys_mmc_sdclkin_a_p, 1596 MUX_SEL_TOP_FSYS, 4, 1), 1597 MUX(TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "mout_sclk_fsys_mmc2_sdclkin_b", 1598 mout_sclk_fsys_mmc2_sdclkin_b_p, 1599 MUX_SEL_TOP_FSYS, 8, 1), 1600 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "mout_sclk_fsys_mmc1_sdclkin_a", 1601 mout_sclk_fsys_mmc_sdclkin_a_p, 1602 MUX_SEL_TOP_FSYS, 12, 1), 1603 MUX(TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "mout_sclk_fsys_mmc1_sdclkin_b", 1604 mout_sclk_fsys_mmc1_sdclkin_b_p, 1605 MUX_SEL_TOP_FSYS, 16, 1), 1606 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "mout_sclk_fsys_mmc0_sdclkin_a", 1607 mout_sclk_fsys_mmc_sdclkin_a_p, 1608 MUX_SEL_TOP_FSYS, 20, 1), 1609 MUX(TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "mout_sclk_fsys_mmc0_sdclkin_b", 1610 mout_sclk_fsys_mmc0_sdclkin_b_p, 1611 MUX_SEL_TOP_FSYS, 24, 1), 1612 1613 MUX(TOP_MOUT_ISP1_MEDIA_400, "mout_isp1_media_400", 1614 mout_isp1_media_400_p, 1615 MUX_SEL_TOP_ISP10, 4, 1), 1616 MUX(TOP_MOUT_ACLK_ISP1_400, "mout_aclk_isp1_400", mout_aclk_isp1_400_p, 1617 MUX_SEL_TOP_ISP10, 8 , 1), 1618 MUX(TOP_MOUT_ISP1_MEDIA_266, "mout_isp1_media_266", 1619 mout_isp1_media_266_p, 1620 MUX_SEL_TOP_ISP10, 16, 1), 1621 MUX(TOP_MOUT_ACLK_ISP1_266, "mout_aclk_isp1_266", mout_aclk_isp1_266_p, 1622 MUX_SEL_TOP_ISP10, 20, 1), 1623 1624 MUX(TOP_MOUT_SCLK_ISP1_SPI0, "mout_sclk_isp1_spi0", mout_sclk_isp_spi_p, 1625 MUX_SEL_TOP_ISP11, 4, 1), 1626 MUX(TOP_MOUT_SCLK_ISP1_SPI1, "mout_sclk_isp1_spi1", mout_sclk_isp_spi_p, 1627 MUX_SEL_TOP_ISP11, 8, 1), 1628 MUX(TOP_MOUT_SCLK_ISP1_UART, "mout_sclk_isp1_uart", 1629 mout_sclk_isp_uart_p, 1630 MUX_SEL_TOP_ISP11, 12, 1), 1631 MUX(TOP_MOUT_SCLK_ISP1_SENSOR0, "mout_sclk_isp1_sensor0", 1632 mout_sclk_isp_sensor_p, 1633 MUX_SEL_TOP_ISP11, 16, 1), 1634 MUX(TOP_MOUT_SCLK_ISP1_SENSOR1, "mout_sclk_isp1_sensor1", 1635 mout_sclk_isp_sensor_p, 1636 MUX_SEL_TOP_ISP11, 20, 1), 1637 MUX(TOP_MOUT_SCLK_ISP1_SENSOR2, "mout_sclk_isp1_sensor2", 1638 mout_sclk_isp_sensor_p, 1639 MUX_SEL_TOP_ISP11, 24, 1), 1640 1641 MUX(TOP_MOUT_MFC_BUSTOP_333, "mout_mfc_bustop_333", 1642 mout_mfc_bustop_333_p, 1643 MUX_SEL_TOP_MFC, 4, 1), 1644 MUX(TOP_MOUT_ACLK_MFC_333, "mout_aclk_mfc_333", mout_aclk_mfc_333_p, 1645 MUX_SEL_TOP_MFC, 8, 1), 1646 1647 MUX(TOP_MOUT_G2D_BUSTOP_333, "mout_g2d_bustop_333", 1648 mout_g2d_bustop_333_p, 1649 MUX_SEL_TOP_G2D, 4, 1), 1650 MUX(TOP_MOUT_ACLK_G2D_333, "mout_aclk_g2d_333", mout_aclk_g2d_333_p, 1651 MUX_SEL_TOP_G2D, 8, 1), 1652 1653 MUX(TOP_MOUT_M2M_MEDIATOP_400, "mout_m2m_mediatop_400", 1654 mout_m2m_mediatop_400_p, 1655 MUX_SEL_TOP_GSCL, 0, 1), 1656 MUX(TOP_MOUT_ACLK_GSCL_400, "mout_aclk_gscl_400", 1657 mout_aclk_gscl_400_p, 1658 MUX_SEL_TOP_GSCL, 4, 1), 1659 MUX(TOP_MOUT_GSCL_BUSTOP_333, "mout_gscl_bustop_333", 1660 mout_gscl_bustop_333_p, 1661 MUX_SEL_TOP_GSCL, 8, 1), 1662 MUX(TOP_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333", 1663 mout_aclk_gscl_333_p, 1664 MUX_SEL_TOP_GSCL, 12, 1), 1665 MUX(TOP_MOUT_GSCL_BUSTOP_FIMC, "mout_gscl_bustop_fimc", 1666 mout_gscl_bustop_fimc_p, 1667 MUX_SEL_TOP_GSCL, 16, 1), 1668 MUX(TOP_MOUT_ACLK_GSCL_FIMC, "mout_aclk_gscl_fimc", 1669 mout_aclk_gscl_fimc_p, 1670 MUX_SEL_TOP_GSCL, 20, 1), 1671 }; 1672 1673 static const struct samsung_div_clock top_div_clks[] __initconst = { 1674 DIV(TOP_DOUT_ACLK_G2D_333, "dout_aclk_g2d_333", "mout_aclk_g2d_333", 1675 DIV_TOP_G2D_MFC, 0, 3), 1676 DIV(TOP_DOUT_ACLK_MFC_333, "dout_aclk_mfc_333", "mout_aclk_mfc_333", 1677 DIV_TOP_G2D_MFC, 4, 3), 1678 1679 DIV(TOP_DOUT_ACLK_GSCL_333, "dout_aclk_gscl_333", "mout_aclk_gscl_333", 1680 DIV_TOP_GSCL_ISP0, 0, 3), 1681 DIV(TOP_DOUT_ACLK_GSCL_400, "dout_aclk_gscl_400", "mout_aclk_gscl_400", 1682 DIV_TOP_GSCL_ISP0, 4, 3), 1683 DIV(TOP_DOUT_ACLK_GSCL_FIMC, "dout_aclk_gscl_fimc", 1684 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 8, 3), 1685 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_A, "dout_sclk_isp1_sensor0_a", 1686 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 16, 4), 1687 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_A, "dout_sclk_isp1_sensor1_a", 1688 "mout_aclk_gscl_400", DIV_TOP_GSCL_ISP0, 20, 4), 1689 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_A, "dout_sclk_isp1_sensor2_a", 1690 "mout_aclk_gscl_fimc", DIV_TOP_GSCL_ISP0, 24, 4), 1691 1692 DIV(TOP_DOUT_ACLK_ISP1_266, "dout_aclk_isp1_266", "mout_aclk_isp1_266", 1693 DIV_TOP_ISP10, 0, 3), 1694 DIV(TOP_DOUT_ACLK_ISP1_400, "dout_aclk_isp1_400", "mout_aclk_isp1_400", 1695 DIV_TOP_ISP10, 4, 3), 1696 DIV(TOP_DOUT_SCLK_ISP1_SPI0_A, "dout_sclk_isp1_spi0_a", 1697 "mout_sclk_isp1_spi0", DIV_TOP_ISP10, 12, 4), 1698 DIV(TOP_DOUT_SCLK_ISP1_SPI0_B, "dout_sclk_isp1_spi0_b", 1699 "dout_sclk_isp1_spi0_a", DIV_TOP_ISP10, 16, 8), 1700 1701 DIV(TOP_DOUT_SCLK_ISP1_SPI1_A, "dout_sclk_isp1_spi1_a", 1702 "mout_sclk_isp1_spi1", DIV_TOP_ISP11, 0, 4), 1703 DIV(TOP_DOUT_SCLK_ISP1_SPI1_B, "dout_sclk_isp1_spi1_b", 1704 "dout_sclk_isp1_spi1_a", DIV_TOP_ISP11, 4, 8), 1705 DIV(TOP_DOUT_SCLK_ISP1_UART, "dout_sclk_isp1_uart", 1706 "mout_sclk_isp1_uart", DIV_TOP_ISP11, 12, 4), 1707 DIV(TOP_DOUT_SCLK_ISP1_SENSOR0_B, "dout_sclk_isp1_sensor0_b", 1708 "dout_sclk_isp1_sensor0_a", DIV_TOP_ISP11, 16, 4), 1709 DIV(TOP_DOUT_SCLK_ISP1_SENSOR1_B, "dout_sclk_isp1_sensor1_b", 1710 "dout_sclk_isp1_sensor1_a", DIV_TOP_ISP11, 20, 4), 1711 DIV(TOP_DOUT_SCLK_ISP1_SENSOR2_B, "dout_sclk_isp1_sensor2_b", 1712 "dout_sclk_isp1_sensor2_a", DIV_TOP_ISP11, 24, 4), 1713 1714 DIV(TOP_DOUTTOP__SCLK_HPM_TARGETCLK, "dout_sclk_hpm_targetclk", 1715 "mout_bustop_pll_user", DIV_TOP_HPM, 0, 3), 1716 1717 DIV(TOP_DOUT_ACLK_DISP_333, "dout_aclk_disp_333", "mout_aclk_disp_333", 1718 DIV_TOP_DISP, 0, 3), 1719 DIV(TOP_DOUT_ACLK_DISP_222, "dout_aclk_disp_222", "mout_aclk_disp_222", 1720 DIV_TOP_DISP, 4, 3), 1721 DIV(TOP_DOUT_SCLK_DISP_PIXEL, "dout_sclk_disp_pixel", 1722 "mout_sclk_disp_pixel", DIV_TOP_DISP, 8, 3), 1723 1724 DIV(TOP_DOUT_ACLK_BUS1_400, "dout_aclk_bus1_400", 1725 "mout_bus1_bustop_400", DIV_TOP_BUS, 0, 3), 1726 DIV(TOP_DOUT_ACLK_BUS1_100, "dout_aclk_bus1_100", 1727 "mout_bus1_bustop_100", DIV_TOP_BUS, 4, 4), 1728 DIV(TOP_DOUT_ACLK_BUS2_400, "dout_aclk_bus2_400", 1729 "mout_bus2_bustop_400", DIV_TOP_BUS, 8, 3), 1730 DIV(TOP_DOUT_ACLK_BUS2_100, "dout_aclk_bus2_100", 1731 "mout_bus2_bustop_100", DIV_TOP_BUS, 12, 4), 1732 DIV(TOP_DOUT_ACLK_BUS3_400, "dout_aclk_bus3_400", 1733 "mout_bus3_bustop_400", DIV_TOP_BUS, 16, 3), 1734 DIV(TOP_DOUT_ACLK_BUS3_100, "dout_aclk_bus3_100", 1735 "mout_bus3_bustop_100", DIV_TOP_BUS, 20, 4), 1736 DIV(TOP_DOUT_ACLK_BUS4_400, "dout_aclk_bus4_400", 1737 "mout_bus4_bustop_400", DIV_TOP_BUS, 24, 3), 1738 DIV(TOP_DOUT_ACLK_BUS4_100, "dout_aclk_bus4_100", 1739 "mout_bus4_bustop_100", DIV_TOP_BUS, 28, 4), 1740 1741 DIV(TOP_DOUT_SCLK_PERI_SPI0_A, "dout_sclk_peri_spi0_a", 1742 "mout_sclk_peri_spi0_clk", DIV_TOP_PERI0, 4, 4), 1743 DIV(TOP_DOUT_SCLK_PERI_SPI0_B, "dout_sclk_peri_spi0_b", 1744 "dout_sclk_peri_spi0_a", DIV_TOP_PERI0, 8, 8), 1745 DIV(TOP_DOUT_SCLK_PERI_SPI1_A, "dout_sclk_peri_spi1_a", 1746 "mout_sclk_peri_spi1_clk", DIV_TOP_PERI0, 16, 4), 1747 DIV(TOP_DOUT_SCLK_PERI_SPI1_B, "dout_sclk_peri_spi1_b", 1748 "dout_sclk_peri_spi1_a", DIV_TOP_PERI0, 20, 8), 1749 1750 DIV(TOP_DOUT_SCLK_PERI_SPI2_A, "dout_sclk_peri_spi2_a", 1751 "mout_sclk_peri_spi2_clk", DIV_TOP_PERI1, 0, 4), 1752 DIV(TOP_DOUT_SCLK_PERI_SPI2_B, "dout_sclk_peri_spi2_b", 1753 "dout_sclk_peri_spi2_a", DIV_TOP_PERI1, 4, 8), 1754 DIV(TOP_DOUT_SCLK_PERI_UART1, "dout_sclk_peri_uart1", 1755 "mout_sclk_peri_uart1_uclk", DIV_TOP_PERI1, 16, 4), 1756 DIV(TOP_DOUT_SCLK_PERI_UART2, "dout_sclk_peri_uart2", 1757 "mout_sclk_peri_uart2_uclk", DIV_TOP_PERI1, 20, 4), 1758 DIV(TOP_DOUT_SCLK_PERI_UART0, "dout_sclk_peri_uart0", 1759 "mout_sclk_peri_uart0_uclk", DIV_TOP_PERI1, 24, 4), 1760 1761 DIV(TOP_DOUT_ACLK_PERI_66, "dout_aclk_peri_66", "mout_bustop_pll_user", 1762 DIV_TOP_PERI2, 20, 4), 1763 DIV(TOP_DOUT_ACLK_PERI_AUD, "dout_aclk_peri_aud", 1764 "mout_audtop_pll_user", DIV_TOP_PERI2, 24, 3), 1765 1766 DIV(TOP_DOUT_ACLK_FSYS_200, "dout_aclk_fsys_200", 1767 "mout_bustop_pll_user", DIV_TOP_FSYS0, 0, 3), 1768 DIV(TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK, 1769 "dout_sclk_fsys_usbdrd30_suspend_clk", 1770 "mout_sclk_fsys_usb", DIV_TOP_FSYS0, 4, 4), 1771 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A, "dout_sclk_fsys_mmc0_sdclkin_a", 1772 "mout_sclk_fsys_mmc0_sdclkin_b", 1773 DIV_TOP_FSYS0, 12, 4), 1774 DIV(TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B, "dout_sclk_fsys_mmc0_sdclkin_b", 1775 "dout_sclk_fsys_mmc0_sdclkin_a", 1776 DIV_TOP_FSYS0, 16, 8), 1777 1778 1779 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A, "dout_sclk_fsys_mmc1_sdclkin_a", 1780 "mout_sclk_fsys_mmc1_sdclkin_b", 1781 DIV_TOP_FSYS1, 0, 4), 1782 DIV(TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B, "dout_sclk_fsys_mmc1_sdclkin_b", 1783 "dout_sclk_fsys_mmc1_sdclkin_a", 1784 DIV_TOP_FSYS1, 4, 8), 1785 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A, "dout_sclk_fsys_mmc2_sdclkin_a", 1786 "mout_sclk_fsys_mmc2_sdclkin_b", 1787 DIV_TOP_FSYS1, 12, 4), 1788 DIV(TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B, "dout_sclk_fsys_mmc2_sdclkin_b", 1789 "dout_sclk_fsys_mmc2_sdclkin_a", 1790 DIV_TOP_FSYS1, 16, 8), 1791 1792 }; 1793 1794 static const struct samsung_gate_clock top_gate_clks[] __initconst = { 1795 GATE(TOP_SCLK_MMC0, "sclk_fsys_mmc0_sdclkin", 1796 "dout_sclk_fsys_mmc0_sdclkin_b", 1797 EN_SCLK_TOP, 7, CLK_SET_RATE_PARENT, 0), 1798 GATE(TOP_SCLK_MMC1, "sclk_fsys_mmc1_sdclkin", 1799 "dout_sclk_fsys_mmc1_sdclkin_b", 1800 EN_SCLK_TOP, 8, CLK_SET_RATE_PARENT, 0), 1801 GATE(TOP_SCLK_MMC2, "sclk_fsys_mmc2_sdclkin", 1802 "dout_sclk_fsys_mmc2_sdclkin_b", 1803 EN_SCLK_TOP, 9, CLK_SET_RATE_PARENT, 0), 1804 GATE(TOP_SCLK_FIMD1, "sclk_disp_pixel", "dout_sclk_disp_pixel", 1805 EN_ACLK_TOP, 10, CLK_IGNORE_UNUSED | 1806 CLK_SET_RATE_PARENT, 0), 1807 }; 1808 1809 static const struct samsung_pll_clock top_pll_clks[] __initconst = { 1810 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll", 1811 DISP_PLL_LOCK, DISP_PLL_CON0, 1812 pll2550_24mhz_tbl), 1813 PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", 1814 AUD_PLL_LOCK, AUD_PLL_CON0, 1815 pll2650_24mhz_tbl), 1816 }; 1817 1818 static const struct samsung_cmu_info top_cmu __initconst = { 1819 .pll_clks = top_pll_clks, 1820 .nr_pll_clks = ARRAY_SIZE(top_pll_clks), 1821 .mux_clks = top_mux_clks, 1822 .nr_mux_clks = ARRAY_SIZE(top_mux_clks), 1823 .div_clks = top_div_clks, 1824 .nr_div_clks = ARRAY_SIZE(top_div_clks), 1825 .gate_clks = top_gate_clks, 1826 .nr_gate_clks = ARRAY_SIZE(top_gate_clks), 1827 .fixed_clks = fixed_rate_clks, 1828 .nr_fixed_clks = ARRAY_SIZE(fixed_rate_clks), 1829 .nr_clk_ids = TOP_NR_CLK, 1830 .clk_regs = top_clk_regs, 1831 .nr_clk_regs = ARRAY_SIZE(top_clk_regs), 1832 }; 1833 1834 static void __init exynos5260_clk_top_init(struct device_node *np) 1835 { 1836 samsung_cmu_register_one(np, &top_cmu); 1837 } 1838 1839 CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top", 1840 exynos5260_clk_top_init); 1841