1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2013 Linaro Ltd. 4 * Author: Thomas Abraham <thomas.ab@samsung.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Common Clock Framework support for Exynos5250 SoC. 11 */ 12 13 #include <dt-bindings/clock/exynos5250.h> 14 #include <linux/clk-provider.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/syscore_ops.h> 18 19 #include "clk.h" 20 #include "clk-cpu.h" 21 #include "clk-exynos5-subcmu.h" 22 23 #define APLL_LOCK 0x0 24 #define APLL_CON0 0x100 25 #define SRC_CPU 0x200 26 #define DIV_CPU0 0x500 27 #define PWR_CTRL1 0x1020 28 #define PWR_CTRL2 0x1024 29 #define MPLL_LOCK 0x4000 30 #define MPLL_CON0 0x4100 31 #define SRC_CORE1 0x4204 32 #define GATE_IP_ACP 0x8800 33 #define GATE_IP_ISP0 0xc800 34 #define GATE_IP_ISP1 0xc804 35 #define CPLL_LOCK 0x10020 36 #define EPLL_LOCK 0x10030 37 #define VPLL_LOCK 0x10040 38 #define GPLL_LOCK 0x10050 39 #define CPLL_CON0 0x10120 40 #define EPLL_CON0 0x10130 41 #define VPLL_CON0 0x10140 42 #define GPLL_CON0 0x10150 43 #define SRC_TOP0 0x10210 44 #define SRC_TOP1 0x10214 45 #define SRC_TOP2 0x10218 46 #define SRC_TOP3 0x1021c 47 #define SRC_GSCL 0x10220 48 #define SRC_DISP1_0 0x1022c 49 #define SRC_MAU 0x10240 50 #define SRC_FSYS 0x10244 51 #define SRC_GEN 0x10248 52 #define SRC_PERIC0 0x10250 53 #define SRC_PERIC1 0x10254 54 #define SRC_MASK_GSCL 0x10320 55 #define SRC_MASK_DISP1_0 0x1032c 56 #define SRC_MASK_MAU 0x10334 57 #define SRC_MASK_FSYS 0x10340 58 #define SRC_MASK_GEN 0x10344 59 #define SRC_MASK_PERIC0 0x10350 60 #define SRC_MASK_PERIC1 0x10354 61 #define DIV_TOP0 0x10510 62 #define DIV_TOP1 0x10514 63 #define DIV_GSCL 0x10520 64 #define DIV_DISP1_0 0x1052c 65 #define DIV_GEN 0x1053c 66 #define DIV_MAU 0x10544 67 #define DIV_FSYS0 0x10548 68 #define DIV_FSYS1 0x1054c 69 #define DIV_FSYS2 0x10550 70 #define DIV_PERIC0 0x10558 71 #define DIV_PERIC1 0x1055c 72 #define DIV_PERIC2 0x10560 73 #define DIV_PERIC3 0x10564 74 #define DIV_PERIC4 0x10568 75 #define DIV_PERIC5 0x1056c 76 #define GATE_IP_GSCL 0x10920 77 #define GATE_IP_DISP1 0x10928 78 #define GATE_IP_MFC 0x1092c 79 #define GATE_IP_G3D 0x10930 80 #define GATE_IP_GEN 0x10934 81 #define GATE_IP_FSYS 0x10944 82 #define GATE_IP_PERIC 0x10950 83 #define GATE_IP_PERIS 0x10960 84 #define BPLL_LOCK 0x20010 85 #define BPLL_CON0 0x20110 86 #define SRC_CDREX 0x20200 87 #define PLL_DIV2_SEL 0x20a24 88 89 /*Below definitions are used for PWR_CTRL settings*/ 90 #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) 91 #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) 92 #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) 93 #define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) 94 #define PWR_CTRL1_USE_CORE1_WFE (1 << 5) 95 #define PWR_CTRL1_USE_CORE0_WFE (1 << 4) 96 #define PWR_CTRL1_USE_CORE1_WFI (1 << 1) 97 #define PWR_CTRL1_USE_CORE0_WFI (1 << 0) 98 99 #define PWR_CTRL2_DIV2_UP_EN (1 << 25) 100 #define PWR_CTRL2_DIV1_UP_EN (1 << 24) 101 #define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) 102 #define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) 103 #define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) 104 #define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) 105 106 /* list of PLLs to be registered */ 107 enum exynos5250_plls { 108 apll, mpll, cpll, epll, vpll, gpll, bpll, 109 nr_plls /* number of PLLs */ 110 }; 111 112 static void __iomem *reg_base; 113 114 #ifdef CONFIG_PM_SLEEP 115 static struct samsung_clk_reg_dump *exynos5250_save; 116 117 /* 118 * list of controller registers to be saved and restored during a 119 * suspend/resume cycle. 120 */ 121 static const unsigned long exynos5250_clk_regs[] __initconst = { 122 SRC_CPU, 123 DIV_CPU0, 124 PWR_CTRL1, 125 PWR_CTRL2, 126 SRC_CORE1, 127 SRC_TOP0, 128 SRC_TOP1, 129 SRC_TOP2, 130 SRC_TOP3, 131 SRC_GSCL, 132 SRC_DISP1_0, 133 SRC_MAU, 134 SRC_FSYS, 135 SRC_GEN, 136 SRC_PERIC0, 137 SRC_PERIC1, 138 SRC_MASK_GSCL, 139 SRC_MASK_DISP1_0, 140 SRC_MASK_MAU, 141 SRC_MASK_FSYS, 142 SRC_MASK_GEN, 143 SRC_MASK_PERIC0, 144 SRC_MASK_PERIC1, 145 DIV_TOP0, 146 DIV_TOP1, 147 DIV_GSCL, 148 DIV_DISP1_0, 149 DIV_GEN, 150 DIV_MAU, 151 DIV_FSYS0, 152 DIV_FSYS1, 153 DIV_FSYS2, 154 DIV_PERIC0, 155 DIV_PERIC1, 156 DIV_PERIC2, 157 DIV_PERIC3, 158 DIV_PERIC4, 159 DIV_PERIC5, 160 GATE_IP_GSCL, 161 GATE_IP_MFC, 162 GATE_IP_G3D, 163 GATE_IP_GEN, 164 GATE_IP_FSYS, 165 GATE_IP_PERIC, 166 GATE_IP_PERIS, 167 SRC_CDREX, 168 PLL_DIV2_SEL, 169 GATE_IP_DISP1, 170 GATE_IP_ACP, 171 GATE_IP_ISP0, 172 GATE_IP_ISP1, 173 }; 174 175 static int exynos5250_clk_suspend(void) 176 { 177 samsung_clk_save(reg_base, exynos5250_save, 178 ARRAY_SIZE(exynos5250_clk_regs)); 179 180 return 0; 181 } 182 183 static void exynos5250_clk_resume(void) 184 { 185 samsung_clk_restore(reg_base, exynos5250_save, 186 ARRAY_SIZE(exynos5250_clk_regs)); 187 } 188 189 static struct syscore_ops exynos5250_clk_syscore_ops = { 190 .suspend = exynos5250_clk_suspend, 191 .resume = exynos5250_clk_resume, 192 }; 193 194 static void __init exynos5250_clk_sleep_init(void) 195 { 196 exynos5250_save = samsung_clk_alloc_reg_dump(exynos5250_clk_regs, 197 ARRAY_SIZE(exynos5250_clk_regs)); 198 if (!exynos5250_save) { 199 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n", 200 __func__); 201 return; 202 } 203 204 register_syscore_ops(&exynos5250_clk_syscore_ops); 205 } 206 #else 207 static void __init exynos5250_clk_sleep_init(void) {} 208 #endif 209 210 /* list of all parent clock list */ 211 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", }; 212 PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", }; 213 PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" }; 214 PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" }; 215 PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" }; 216 PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" }; 217 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" }; 218 PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" }; 219 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" }; 220 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" }; 221 PNAME(mout_gpll_p) = { "fin_pll", "fout_gpll" }; 222 PNAME(mout_mpll_user_p) = { "fin_pll", "mout_mpll" }; 223 PNAME(mout_bpll_user_p) = { "fin_pll", "mout_bpll" }; 224 PNAME(mout_aclk166_p) = { "mout_cpll", "mout_mpll_user" }; 225 PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; 226 PNAME(mout_aclk300_p) = { "mout_aclk300_disp1_mid", 227 "mout_aclk300_disp1_mid1" }; 228 PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" }; 229 PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; 230 PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; 231 PNAME(mout_aclk300_sub_p) = { "fin_pll", "div_aclk300_disp" }; 232 PNAME(mout_aclk300_disp1_mid1_p) = { "mout_vpll", "mout_cpll" }; 233 PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; 234 PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" }; 235 PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; 236 PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; 237 PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", 238 "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", 239 "mout_mpll_user", "mout_epll", "mout_vpll", 240 "mout_cpll", "none", "none", 241 "none", "none", "none", 242 "none" }; 243 PNAME(mout_audio0_p) = { "cdclk0", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 244 "sclk_uhostphy", "fin_pll", 245 "mout_mpll_user", "mout_epll", "mout_vpll", 246 "mout_cpll", "none", "none", 247 "none", "none", "none", 248 "none" }; 249 PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 250 "sclk_uhostphy", "fin_pll", 251 "mout_mpll_user", "mout_epll", "mout_vpll", 252 "mout_cpll", "none", "none", 253 "none", "none", "none", 254 "none" }; 255 PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", 256 "sclk_uhostphy", "fin_pll", 257 "mout_mpll_user", "mout_epll", "mout_vpll", 258 "mout_cpll", "none", "none", 259 "none", "none", "none", 260 "none" }; 261 PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", 262 "spdif_extclk" }; 263 264 /* fixed rate clocks generated outside the soc */ 265 static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { 266 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), 267 }; 268 269 /* fixed rate clocks generated inside the soc */ 270 static const struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initconst = { 271 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), 272 FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000), 273 FRATE(0, "sclk_dptxphy", NULL, 0, 24000000), 274 FRATE(0, "sclk_uhostphy", NULL, 0, 48000000), 275 }; 276 277 static const struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initconst = { 278 FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0), 279 FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0), 280 }; 281 282 static const struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initconst = { 283 MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), 284 }; 285 286 static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = { 287 /* 288 * NOTE: Following table is sorted by (clock domain, register address, 289 * bitfield shift) triplet in ascending order. When adding new entries, 290 * please make sure that the order is kept, to avoid merge conflicts 291 * and make further work with defined data easier. 292 */ 293 294 /* 295 * CMU_CPU 296 */ 297 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 298 CLK_SET_RATE_PARENT, 0), 299 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), 300 301 /* 302 * CMU_CORE 303 */ 304 MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1), 305 306 /* 307 * CMU_TOP 308 */ 309 MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), 310 MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), 311 MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1), 312 MUX(0, "mout_aclk300", mout_aclk300_p, SRC_TOP0, 15, 1), 313 MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), 314 MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1), 315 316 MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_disp1_mid1_p, SRC_TOP1, 317 8, 1), 318 MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1), 319 MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1), 320 321 MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), 322 MUX(0, "mout_epll", mout_epll_p, SRC_TOP2, 12, 1), 323 MUX(0, "mout_vpll", mout_vpll_p, SRC_TOP2, 16, 1), 324 MUX(0, "mout_mpll_user", mout_mpll_user_p, SRC_TOP2, 20, 1), 325 MUX(0, "mout_bpll_user", mout_bpll_user_p, SRC_TOP2, 24, 1), 326 MUX(CLK_MOUT_GPLL, "mout_gpll", mout_gpll_p, SRC_TOP2, 28, 1), 327 328 MUX(CLK_MOUT_ACLK200_DISP1_SUB, "mout_aclk200_disp1_sub", 329 mout_aclk200_sub_p, SRC_TOP3, 4, 1), 330 MUX(CLK_MOUT_ACLK300_DISP1_SUB, "mout_aclk300_disp1_sub", 331 mout_aclk300_sub_p, SRC_TOP3, 6, 1), 332 MUX(0, "mout_aclk266_gscl_sub", mout_aclk266_sub_p, SRC_TOP3, 8, 1), 333 MUX(0, "mout_aclk_266_isp_sub", mout_aclk266_sub_p, SRC_TOP3, 16, 1), 334 MUX(0, "mout_aclk_400_isp_sub", mout_aclk400_isp_sub_p, 335 SRC_TOP3, 20, 1), 336 MUX(0, "mout_aclk333_sub", mout_aclk333_sub_p, SRC_TOP3, 24, 1), 337 338 MUX(0, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), 339 MUX(0, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), 340 MUX(0, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), 341 MUX(0, "mout_gscl_wa", mout_group1_p, SRC_GSCL, 24, 4), 342 MUX(0, "mout_gscl_wb", mout_group1_p, SRC_GSCL, 28, 4), 343 344 MUX(0, "mout_fimd1", mout_group1_p, SRC_DISP1_0, 0, 4), 345 MUX(0, "mout_mipi1", mout_group1_p, SRC_DISP1_0, 12, 4), 346 MUX(0, "mout_dp", mout_group1_p, SRC_DISP1_0, 16, 4), 347 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP1_0, 20, 1), 348 349 MUX(0, "mout_audio0", mout_audio0_p, SRC_MAU, 0, 4), 350 351 MUX(0, "mout_mmc0", mout_group1_p, SRC_FSYS, 0, 4), 352 MUX(0, "mout_mmc1", mout_group1_p, SRC_FSYS, 4, 4), 353 MUX(0, "mout_mmc2", mout_group1_p, SRC_FSYS, 8, 4), 354 MUX(0, "mout_mmc3", mout_group1_p, SRC_FSYS, 12, 4), 355 MUX(0, "mout_sata", mout_aclk200_p, SRC_FSYS, 24, 1), 356 MUX(0, "mout_usb3", mout_usb3_p, SRC_FSYS, 28, 1), 357 358 MUX(0, "mout_jpeg", mout_group1_p, SRC_GEN, 0, 4), 359 360 MUX(0, "mout_uart0", mout_group1_p, SRC_PERIC0, 0, 4), 361 MUX(0, "mout_uart1", mout_group1_p, SRC_PERIC0, 4, 4), 362 MUX(0, "mout_uart2", mout_group1_p, SRC_PERIC0, 8, 4), 363 MUX(0, "mout_uart3", mout_group1_p, SRC_PERIC0, 12, 4), 364 MUX(0, "mout_pwm", mout_group1_p, SRC_PERIC0, 24, 4), 365 366 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 0, 4), 367 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 4, 4), 368 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC1, 8, 2), 369 MUX(0, "mout_spi0", mout_group1_p, SRC_PERIC1, 16, 4), 370 MUX(0, "mout_spi1", mout_group1_p, SRC_PERIC1, 20, 4), 371 MUX(0, "mout_spi2", mout_group1_p, SRC_PERIC1, 24, 4), 372 373 /* 374 * CMU_CDREX 375 */ 376 MUX(0, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1), 377 378 MUX(0, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), 379 MUX(0, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), 380 }; 381 382 static const struct samsung_div_clock exynos5250_div_clks[] __initconst = { 383 /* 384 * NOTE: Following table is sorted by (clock domain, register address, 385 * bitfield shift) triplet in ascending order. When adding new entries, 386 * please make sure that the order is kept, to avoid merge conflicts 387 * and make further work with defined data easier. 388 */ 389 390 /* 391 * CMU_CPU 392 */ 393 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 394 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), 395 DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3), 396 397 /* 398 * CMU_TOP 399 */ 400 DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3), 401 DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3), 402 DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), 403 DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), 404 DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), 405 DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0, 406 24, 3), 407 DIV(0, "div_aclk300_disp", "mout_aclk300", DIV_TOP0, 28, 3), 408 409 DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3), 410 DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), 411 412 DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4), 413 DIV(0, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4), 414 DIV(0, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4), 415 DIV(0, "div_gscl_wa", "mout_gscl_wa", DIV_GSCL, 24, 4), 416 DIV(0, "div_gscl_wb", "mout_gscl_wb", DIV_GSCL, 28, 4), 417 418 DIV(0, "div_fimd1", "mout_fimd1", DIV_DISP1_0, 0, 4), 419 DIV(0, "div_mipi1", "mout_mipi1", DIV_DISP1_0, 16, 4), 420 DIV_F(0, "div_mipi1_pre", "div_mipi1", 421 DIV_DISP1_0, 20, 4, CLK_SET_RATE_PARENT, 0), 422 DIV(0, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), 423 DIV(CLK_SCLK_PIXEL, "div_hdmi_pixel", "mout_vpll", DIV_DISP1_0, 28, 4), 424 425 DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), 426 427 DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), 428 DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), 429 430 DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), 431 DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), 432 433 DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), 434 DIV_F(0, "div_mmc_pre0", "div_mmc0", 435 DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), 436 DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), 437 DIV_F(0, "div_mmc_pre1", "div_mmc1", 438 DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), 439 440 DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), 441 DIV_F(0, "div_mmc_pre2", "div_mmc2", 442 DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), 443 DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), 444 DIV_F(0, "div_mmc_pre3", "div_mmc3", 445 DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), 446 447 DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4), 448 DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4), 449 DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4), 450 DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4), 451 452 DIV(0, "div_spi0", "mout_spi0", DIV_PERIC1, 0, 4), 453 DIV_F(0, "div_spi_pre0", "div_spi0", 454 DIV_PERIC1, 8, 8, CLK_SET_RATE_PARENT, 0), 455 DIV(0, "div_spi1", "mout_spi1", DIV_PERIC1, 16, 4), 456 DIV_F(0, "div_spi_pre1", "div_spi1", 457 DIV_PERIC1, 24, 8, CLK_SET_RATE_PARENT, 0), 458 459 DIV(0, "div_spi2", "mout_spi2", DIV_PERIC2, 0, 4), 460 DIV_F(0, "div_spi_pre2", "div_spi2", 461 DIV_PERIC2, 8, 8, CLK_SET_RATE_PARENT, 0), 462 463 DIV(0, "div_pwm", "mout_pwm", DIV_PERIC3, 0, 4), 464 465 DIV(0, "div_audio1", "mout_audio1", DIV_PERIC4, 0, 4), 466 DIV(0, "div_pcm1", "sclk_audio1", DIV_PERIC4, 4, 8), 467 DIV(0, "div_audio2", "mout_audio2", DIV_PERIC4, 16, 4), 468 DIV(0, "div_pcm2", "sclk_audio2", DIV_PERIC4, 20, 8), 469 470 DIV(CLK_DIV_I2S1, "div_i2s1", "sclk_audio1", DIV_PERIC5, 0, 6), 471 DIV(CLK_DIV_I2S2, "div_i2s2", "sclk_audio2", DIV_PERIC5, 8, 6), 472 }; 473 474 static const struct samsung_gate_clock exynos5250_gate_clks[] __initconst = { 475 /* 476 * NOTE: Following table is sorted by (clock domain, register address, 477 * bitfield shift) triplet in ascending order. When adding new entries, 478 * please make sure that the order is kept, to avoid merge conflicts 479 * and make further work with defined data easier. 480 */ 481 482 /* 483 * CMU_ACP 484 */ 485 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), 486 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0), 487 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), 488 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), 489 490 /* 491 * CMU_TOP 492 */ 493 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer", 494 SRC_MASK_GSCL, 12, CLK_SET_RATE_PARENT, 0), 495 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", 496 SRC_MASK_GSCL, 16, CLK_SET_RATE_PARENT, 0), 497 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", 498 SRC_MASK_GSCL, 20, CLK_SET_RATE_PARENT, 0), 499 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa", 500 SRC_MASK_GSCL, 24, CLK_SET_RATE_PARENT, 0), 501 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb", 502 SRC_MASK_GSCL, 28, CLK_SET_RATE_PARENT, 0), 503 504 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", 505 SRC_MASK_DISP1_0, 0, CLK_SET_RATE_PARENT, 0), 506 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi1", 507 SRC_MASK_DISP1_0, 12, CLK_SET_RATE_PARENT, 0), 508 GATE(CLK_SCLK_DP, "sclk_dp", "div_dp", 509 SRC_MASK_DISP1_0, 16, CLK_SET_RATE_PARENT, 0), 510 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", 511 SRC_MASK_DISP1_0, 20, 0, 0), 512 513 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", 514 SRC_MASK_MAU, 0, CLK_SET_RATE_PARENT, 0), 515 516 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", 517 SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0), 518 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", 519 SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0), 520 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", 521 SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0), 522 GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", 523 SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0), 524 GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", 525 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 526 GATE(CLK_SCLK_USB3, "sclk_usb3", "div_usb3", 527 SRC_MASK_FSYS, 28, CLK_SET_RATE_PARENT, 0), 528 529 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "div_jpeg", 530 SRC_MASK_GEN, 0, CLK_SET_RATE_PARENT, 0), 531 532 GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", 533 SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0), 534 GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", 535 SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0), 536 GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", 537 SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0), 538 GATE(CLK_SCLK_UART3, "sclk_uart3", "div_uart3", 539 SRC_MASK_PERIC0, 12, CLK_SET_RATE_PARENT, 0), 540 GATE(CLK_SCLK_PWM, "sclk_pwm", "div_pwm", 541 SRC_MASK_PERIC0, 24, CLK_SET_RATE_PARENT, 0), 542 543 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", 544 SRC_MASK_PERIC1, 0, CLK_SET_RATE_PARENT, 0), 545 GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", 546 SRC_MASK_PERIC1, 4, CLK_SET_RATE_PARENT, 0), 547 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", 548 SRC_MASK_PERIC1, 4, 0, 0), 549 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", 550 SRC_MASK_PERIC1, 16, CLK_SET_RATE_PARENT, 0), 551 GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", 552 SRC_MASK_PERIC1, 20, CLK_SET_RATE_PARENT, 0), 553 GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", 554 SRC_MASK_PERIC1, 24, CLK_SET_RATE_PARENT, 0), 555 556 GATE(CLK_GSCL0, "gscl0", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 0, 0, 557 0), 558 GATE(CLK_GSCL1, "gscl1", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 1, 0, 559 0), 560 GATE(CLK_GSCL2, "gscl2", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 2, 0, 561 0), 562 GATE(CLK_GSCL3, "gscl3", "mout_aclk266_gscl_sub", GATE_IP_GSCL, 3, 0, 563 0), 564 GATE(CLK_CAMIF_TOP, "camif_top", "mout_aclk266_gscl_sub", 565 GATE_IP_GSCL, 4, 0, 0), 566 GATE(CLK_GSCL_WA, "gscl_wa", "div_gscl_wa", GATE_IP_GSCL, 5, 0, 0), 567 GATE(CLK_GSCL_WB, "gscl_wb", "div_gscl_wb", GATE_IP_GSCL, 6, 0, 0), 568 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "mout_aclk266_gscl_sub", 569 GATE_IP_GSCL, 7, 0, 0), 570 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "mout_aclk266_gscl_sub", 571 GATE_IP_GSCL, 8, 0, 0), 572 GATE(CLK_SMMU_GSCL2, "smmu_gscl2", "mout_aclk266_gscl_sub", 573 GATE_IP_GSCL, 9, 0, 0), 574 GATE(CLK_SMMU_GSCL3, "smmu_gscl3", "mout_aclk266_gscl_sub", 575 GATE_IP_GSCL, 10, 0, 0), 576 GATE(CLK_SMMU_FIMC_LITE0, "smmu_fimc_lite0", "mout_aclk266_gscl_sub", 577 GATE_IP_GSCL, 11, 0, 0), 578 GATE(CLK_SMMU_FIMC_LITE1, "smmu_fimc_lite1", "mout_aclk266_gscl_sub", 579 GATE_IP_GSCL, 12, 0, 0), 580 581 582 GATE(CLK_MFC, "mfc", "mout_aclk333_sub", GATE_IP_MFC, 0, 0, 0), 583 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "mout_aclk333_sub", GATE_IP_MFC, 1, 0, 584 0), 585 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0, 586 0), 587 GATE(CLK_G3D, "g3d", "div_aclk400_g3d", GATE_IP_G3D, 0, 588 CLK_SET_RATE_PARENT, 0), 589 GATE(CLK_ROTATOR, "rotator", "div_aclk266", GATE_IP_GEN, 1, 0, 0), 590 GATE(CLK_JPEG, "jpeg", "div_aclk166", GATE_IP_GEN, 2, 0, 0), 591 GATE(CLK_MDMA1, "mdma1", "div_aclk266", GATE_IP_GEN, 4, 0, 0), 592 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "div_aclk266", GATE_IP_GEN, 6, 0, 593 0), 594 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "div_aclk166", GATE_IP_GEN, 7, 0, 0), 595 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "div_aclk266", GATE_IP_GEN, 9, 0, 0), 596 597 GATE(CLK_PDMA0, "pdma0", "div_aclk200", GATE_IP_FSYS, 1, 0, 0), 598 GATE(CLK_PDMA1, "pdma1", "div_aclk200", GATE_IP_FSYS, 2, 0, 0), 599 GATE(CLK_SATA, "sata", "div_aclk200", GATE_IP_FSYS, 6, 0, 0), 600 GATE(CLK_USBOTG, "usbotg", "div_aclk200", GATE_IP_FSYS, 7, 0, 0), 601 GATE(CLK_MIPI_HSI, "mipi_hsi", "div_aclk200", GATE_IP_FSYS, 8, 0, 0), 602 GATE(CLK_SDMMC0, "sdmmc0", "div_aclk200", GATE_IP_FSYS, 12, 0, 0), 603 GATE(CLK_SDMMC1, "sdmmc1", "div_aclk200", GATE_IP_FSYS, 13, 0, 0), 604 GATE(CLK_SDMMC2, "sdmmc2", "div_aclk200", GATE_IP_FSYS, 14, 0, 0), 605 GATE(CLK_SDMMC3, "sdmmc3", "div_aclk200", GATE_IP_FSYS, 15, 0, 0), 606 GATE(CLK_SROMC, "sromc", "div_aclk200", GATE_IP_FSYS, 17, 0, 0), 607 GATE(CLK_USB2, "usb2", "div_aclk200", GATE_IP_FSYS, 18, 0, 0), 608 GATE(CLK_USB3, "usb3", "div_aclk200", GATE_IP_FSYS, 19, 0, 0), 609 GATE(CLK_SATA_PHYCTRL, "sata_phyctrl", "div_aclk200", 610 GATE_IP_FSYS, 24, 0, 0), 611 GATE(CLK_SATA_PHYI2C, "sata_phyi2c", "div_aclk200", GATE_IP_FSYS, 25, 0, 612 0), 613 614 GATE(CLK_UART0, "uart0", "div_aclk66", GATE_IP_PERIC, 0, 0, 0), 615 GATE(CLK_UART1, "uart1", "div_aclk66", GATE_IP_PERIC, 1, 0, 0), 616 GATE(CLK_UART2, "uart2", "div_aclk66", GATE_IP_PERIC, 2, 0, 0), 617 GATE(CLK_UART3, "uart3", "div_aclk66", GATE_IP_PERIC, 3, 0, 0), 618 GATE(CLK_UART4, "uart4", "div_aclk66", GATE_IP_PERIC, 4, 0, 0), 619 GATE(CLK_I2C0, "i2c0", "div_aclk66", GATE_IP_PERIC, 6, 0, 0), 620 GATE(CLK_I2C1, "i2c1", "div_aclk66", GATE_IP_PERIC, 7, 0, 0), 621 GATE(CLK_I2C2, "i2c2", "div_aclk66", GATE_IP_PERIC, 8, 0, 0), 622 GATE(CLK_I2C3, "i2c3", "div_aclk66", GATE_IP_PERIC, 9, 0, 0), 623 GATE(CLK_I2C4, "i2c4", "div_aclk66", GATE_IP_PERIC, 10, 0, 0), 624 GATE(CLK_I2C5, "i2c5", "div_aclk66", GATE_IP_PERIC, 11, 0, 0), 625 GATE(CLK_I2C6, "i2c6", "div_aclk66", GATE_IP_PERIC, 12, 0, 0), 626 GATE(CLK_I2C7, "i2c7", "div_aclk66", GATE_IP_PERIC, 13, 0, 0), 627 GATE(CLK_I2C_HDMI, "i2c_hdmi", "div_aclk66", GATE_IP_PERIC, 14, 0, 0), 628 GATE(CLK_ADC, "adc", "div_aclk66", GATE_IP_PERIC, 15, 0, 0), 629 GATE(CLK_SPI0, "spi0", "div_aclk66", GATE_IP_PERIC, 16, 0, 0), 630 GATE(CLK_SPI1, "spi1", "div_aclk66", GATE_IP_PERIC, 17, 0, 0), 631 GATE(CLK_SPI2, "spi2", "div_aclk66", GATE_IP_PERIC, 18, 0, 0), 632 GATE(CLK_I2S1, "i2s1", "div_aclk66", GATE_IP_PERIC, 20, 0, 0), 633 GATE(CLK_I2S2, "i2s2", "div_aclk66", GATE_IP_PERIC, 21, 0, 0), 634 GATE(CLK_PCM1, "pcm1", "div_aclk66", GATE_IP_PERIC, 22, 0, 0), 635 GATE(CLK_PCM2, "pcm2", "div_aclk66", GATE_IP_PERIC, 23, 0, 0), 636 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0), 637 GATE(CLK_SPDIF, "spdif", "div_aclk66", GATE_IP_PERIC, 26, 0, 0), 638 GATE(CLK_AC97, "ac97", "div_aclk66", GATE_IP_PERIC, 27, 0, 0), 639 GATE(CLK_HSI2C0, "hsi2c0", "div_aclk66", GATE_IP_PERIC, 28, 0, 0), 640 GATE(CLK_HSI2C1, "hsi2c1", "div_aclk66", GATE_IP_PERIC, 29, 0, 0), 641 GATE(CLK_HSI2C2, "hsi2c2", "div_aclk66", GATE_IP_PERIC, 30, 0, 0), 642 GATE(CLK_HSI2C3, "hsi2c3", "div_aclk66", GATE_IP_PERIC, 31, 0, 0), 643 644 GATE(CLK_CHIPID, "chipid", "div_aclk66", GATE_IP_PERIS, 0, 0, 0), 645 GATE(CLK_SYSREG, "sysreg", "div_aclk66", 646 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0), 647 GATE(CLK_PMU, "pmu", "div_aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 648 0), 649 GATE(CLK_CMU_TOP, "cmu_top", "div_aclk66", 650 GATE_IP_PERIS, 3, CLK_IGNORE_UNUSED, 0), 651 GATE(CLK_CMU_CORE, "cmu_core", "div_aclk66", 652 GATE_IP_PERIS, 4, CLK_IGNORE_UNUSED, 0), 653 GATE(CLK_CMU_MEM, "cmu_mem", "div_aclk66", 654 GATE_IP_PERIS, 5, CLK_IGNORE_UNUSED, 0), 655 GATE(CLK_TZPC0, "tzpc0", "div_aclk66", GATE_IP_PERIS, 6, 0, 0), 656 GATE(CLK_TZPC1, "tzpc1", "div_aclk66", GATE_IP_PERIS, 7, 0, 0), 657 GATE(CLK_TZPC2, "tzpc2", "div_aclk66", GATE_IP_PERIS, 8, 0, 0), 658 GATE(CLK_TZPC3, "tzpc3", "div_aclk66", GATE_IP_PERIS, 9, 0, 0), 659 GATE(CLK_TZPC4, "tzpc4", "div_aclk66", GATE_IP_PERIS, 10, 0, 0), 660 GATE(CLK_TZPC5, "tzpc5", "div_aclk66", GATE_IP_PERIS, 11, 0, 0), 661 GATE(CLK_TZPC6, "tzpc6", "div_aclk66", GATE_IP_PERIS, 12, 0, 0), 662 GATE(CLK_TZPC7, "tzpc7", "div_aclk66", GATE_IP_PERIS, 13, 0, 0), 663 GATE(CLK_TZPC8, "tzpc8", "div_aclk66", GATE_IP_PERIS, 14, 0, 0), 664 GATE(CLK_TZPC9, "tzpc9", "div_aclk66", GATE_IP_PERIS, 15, 0, 0), 665 GATE(CLK_HDMI_CEC, "hdmi_cec", "div_aclk66", GATE_IP_PERIS, 16, 0, 0), 666 GATE(CLK_MCT, "mct", "div_aclk66", GATE_IP_PERIS, 18, 0, 0), 667 GATE(CLK_WDT, "wdt", "div_aclk66", GATE_IP_PERIS, 19, 0, 0), 668 GATE(CLK_RTC, "rtc", "div_aclk66", GATE_IP_PERIS, 20, 0, 0), 669 GATE(CLK_TMU, "tmu", "div_aclk66", GATE_IP_PERIS, 21, 0, 0), 670 GATE(CLK_SMMU_2D, "smmu_2d", "div_aclk200", GATE_IP_ACP, 7, 0, 0), 671 GATE(CLK_SMMU_FIMC_ISP, "smmu_fimc_isp", "mout_aclk_266_isp_sub", 672 GATE_IP_ISP0, 8, 0, 0), 673 GATE(CLK_SMMU_FIMC_DRC, "smmu_fimc_drc", "mout_aclk_266_isp_sub", 674 GATE_IP_ISP0, 9, 0, 0), 675 GATE(CLK_SMMU_FIMC_FD, "smmu_fimc_fd", "mout_aclk_266_isp_sub", 676 GATE_IP_ISP0, 10, 0, 0), 677 GATE(CLK_SMMU_FIMC_SCC, "smmu_fimc_scc", "mout_aclk_266_isp_sub", 678 GATE_IP_ISP0, 11, 0, 0), 679 GATE(CLK_SMMU_FIMC_SCP, "smmu_fimc_scp", "mout_aclk_266_isp_sub", 680 GATE_IP_ISP0, 12, 0, 0), 681 GATE(CLK_SMMU_FIMC_MCU, "smmu_fimc_mcu", "mout_aclk_400_isp_sub", 682 GATE_IP_ISP0, 13, 0, 0), 683 GATE(CLK_SMMU_FIMC_ODC, "smmu_fimc_odc", "mout_aclk_266_isp_sub", 684 GATE_IP_ISP1, 4, 0, 0), 685 GATE(CLK_SMMU_FIMC_DIS0, "smmu_fimc_dis0", "mout_aclk_266_isp_sub", 686 GATE_IP_ISP1, 5, 0, 0), 687 GATE(CLK_SMMU_FIMC_DIS1, "smmu_fimc_dis1", "mout_aclk_266_isp_sub", 688 GATE_IP_ISP1, 6, 0, 0), 689 GATE(CLK_SMMU_FIMC_3DNR, "smmu_fimc_3dnr", "mout_aclk_266_isp_sub", 690 GATE_IP_ISP1, 7, 0, 0), 691 }; 692 693 static const struct samsung_gate_clock exynos5250_disp_gate_clks[] __initconst = { 694 GATE(CLK_FIMD1, "fimd1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 0, 0, 695 0), 696 GATE(CLK_MIE1, "mie1", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 1, 0, 697 0), 698 GATE(CLK_DSIM0, "dsim0", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 3, 0, 699 0), 700 GATE(CLK_DP, "dp", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 4, 0, 0), 701 GATE(CLK_MIXER, "mixer", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 5, 0, 702 0), 703 GATE(CLK_HDMI, "hdmi", "mout_aclk200_disp1_sub", GATE_IP_DISP1, 6, 0, 704 0), 705 GATE(CLK_SMMU_TV, "smmu_tv", "mout_aclk200_disp1_sub", 706 GATE_IP_DISP1, 9, 0, 0), 707 GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "mout_aclk200_disp1_sub", 708 GATE_IP_DISP1, 8, 0, 0), 709 }; 710 711 static struct exynos5_subcmu_reg_dump exynos5250_disp_suspend_regs[] = { 712 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */ 713 { SRC_TOP3, 0, BIT(4) }, /* MUX mout_aclk200_disp1_sub */ 714 { SRC_TOP3, 0, BIT(6) }, /* MUX mout_aclk300_disp1_sub */ 715 }; 716 717 static const struct exynos5_subcmu_info exynos5250_disp_subcmu = { 718 .gate_clks = exynos5250_disp_gate_clks, 719 .nr_gate_clks = ARRAY_SIZE(exynos5250_disp_gate_clks), 720 .suspend_regs = exynos5250_disp_suspend_regs, 721 .nr_suspend_regs = ARRAY_SIZE(exynos5250_disp_suspend_regs), 722 .pd_name = "DISP1", 723 }; 724 725 static const struct samsung_pll_rate_table vpll_24mhz_tbl[] __initconst = { 726 /* sorted in descending order */ 727 /* PLL_36XX_RATE(rate, m, p, s, k) */ 728 PLL_36XX_RATE(24 * MHZ, 266000000, 266, 3, 3, 0), 729 /* Not in UM, but need for eDP on snow */ 730 PLL_36XX_RATE(24 * MHZ, 70500000, 94, 2, 4, 0), 731 { }, 732 }; 733 734 static const struct samsung_pll_rate_table epll_24mhz_tbl[] __initconst = { 735 /* sorted in descending order */ 736 /* PLL_36XX_RATE(rate, m, p, s, k) */ 737 PLL_36XX_RATE(24 * MHZ, 192000000, 64, 2, 2, 0), 738 PLL_36XX_RATE(24 * MHZ, 180633605, 90, 3, 2, 20762), 739 PLL_36XX_RATE(24 * MHZ, 180000000, 90, 3, 2, 0), 740 PLL_36XX_RATE(24 * MHZ, 73728000, 98, 2, 4, 19923), 741 PLL_36XX_RATE(24 * MHZ, 67737602, 90, 2, 4, 20762), 742 PLL_36XX_RATE(24 * MHZ, 49152000, 98, 3, 4, 19923), 743 PLL_36XX_RATE(24 * MHZ, 45158401, 90, 3, 4, 20762), 744 PLL_36XX_RATE(24 * MHZ, 32768001, 131, 3, 5, 4719), 745 { }, 746 }; 747 748 static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = { 749 /* sorted in descending order */ 750 /* PLL_35XX_RATE(fin, rate, m, p, s) */ 751 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0), 752 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0), 753 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0), 754 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0), 755 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0), 756 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0), 757 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0), 758 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0), 759 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0), 760 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0), 761 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1), 762 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 4, 1), 763 PLL_35XX_RATE(24 * MHZ, 500000000, 125, 3, 1), 764 PLL_35XX_RATE(24 * MHZ, 400000000, 100, 3, 1), 765 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 4, 2), 766 PLL_35XX_RATE(24 * MHZ, 200000000, 100, 3, 2), 767 }; 768 769 static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 770 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, 771 APLL_CON0, NULL), 772 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK, 773 MPLL_CON0, NULL), 774 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 775 BPLL_CON0, NULL), 776 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK, 777 GPLL_CON0, NULL), 778 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK, 779 CPLL_CON0, NULL), 780 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, 781 EPLL_CON0, NULL), 782 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 783 VPLL_LOCK, VPLL_CON0, NULL), 784 }; 785 786 #define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \ 787 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ 788 ((periph) << 12) | ((acp) << 8) | ((cpud) << 4))) 789 #define E5250_CPU_DIV1(hpm, copy) \ 790 (((hpm) << 4) | (copy)) 791 792 static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = { 793 { 1700000, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, 794 { 1600000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, 795 { 1500000, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, 796 { 1400000, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, 797 { 1300000, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, 798 { 1200000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), }, 799 { 1100000, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), }, 800 { 1000000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 801 { 900000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 802 { 800000, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 803 { 700000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 804 { 600000, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 805 { 500000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 806 { 400000, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 807 { 300000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 808 { 200000, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), }, 809 { 0 }, 810 }; 811 812 static const struct of_device_id ext_clk_match[] __initconst = { 813 { .compatible = "samsung,clock-xxti", .data = (void *)0, }, 814 { }, 815 }; 816 817 /* register exynox5250 clocks */ 818 static void __init exynos5250_clk_init(struct device_node *np) 819 { 820 struct samsung_clk_provider *ctx; 821 unsigned int tmp; 822 823 if (np) { 824 reg_base = of_iomap(np, 0); 825 if (!reg_base) 826 panic("%s: failed to map registers\n", __func__); 827 } else { 828 panic("%s: unable to determine soc\n", __func__); 829 } 830 831 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 832 833 samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks, 834 ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), 835 ext_clk_match); 836 samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks, 837 ARRAY_SIZE(exynos5250_pll_pmux_clks)); 838 839 if (_get_rate("fin_pll") == 24 * MHZ) { 840 exynos5250_plls[epll].rate_table = epll_24mhz_tbl; 841 exynos5250_plls[apll].rate_table = apll_24mhz_tbl; 842 } 843 844 if (_get_rate("mout_vpllsrc") == 24 * MHZ) 845 exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl; 846 847 samsung_clk_register_pll(ctx, exynos5250_plls, 848 ARRAY_SIZE(exynos5250_plls), 849 reg_base); 850 samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks, 851 ARRAY_SIZE(exynos5250_fixed_rate_clks)); 852 samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks, 853 ARRAY_SIZE(exynos5250_fixed_factor_clks)); 854 samsung_clk_register_mux(ctx, exynos5250_mux_clks, 855 ARRAY_SIZE(exynos5250_mux_clks)); 856 samsung_clk_register_div(ctx, exynos5250_div_clks, 857 ARRAY_SIZE(exynos5250_div_clks)); 858 samsung_clk_register_gate(ctx, exynos5250_gate_clks, 859 ARRAY_SIZE(exynos5250_gate_clks)); 860 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 861 mout_cpu_p[0], mout_cpu_p[1], 0x200, 862 exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d), 863 CLK_CPU_HAS_DIV1); 864 865 /* 866 * Enable arm clock down (in idle) and set arm divider 867 * ratios in WFI/WFE state. 868 */ 869 tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO | 870 PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | 871 PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | 872 PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); 873 __raw_writel(tmp, reg_base + PWR_CTRL1); 874 875 /* 876 * Enable arm clock up (on exiting idle). Set arm divider 877 * ratios when not in idle along with the standby duration 878 * ratios. 879 */ 880 tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN | 881 PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL | 882 PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); 883 __raw_writel(tmp, reg_base + PWR_CTRL2); 884 885 exynos5250_clk_sleep_init(); 886 exynos5_subcmus_init(ctx, 1, &exynos5250_disp_subcmu); 887 888 samsung_clk_of_add_provider(np, ctx); 889 890 pr_info("Exynos5250: clock setup completed, armclk=%ld\n", 891 _get_rate("div_arm2")); 892 } 893 CLK_OF_DECLARE_DRIVER(exynos5250_clk, "samsung,exynos5250-clock", exynos5250_clk_init); 894