xref: /linux/drivers/clk/samsung/clk-exynos4.c (revision 507e190946297c34a27d9366b0661d5e506fdd03)
1 /*
2  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3  * Copyright (c) 2013 Linaro Ltd.
4  * Author: Thomas Abraham <thomas.ab@samsung.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * Common Clock Framework support for all Exynos4 SoCs.
11 */
12 
13 #include <dt-bindings/clock/exynos4.h>
14 #include <linux/slab.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/syscore_ops.h>
20 
21 #include "clk.h"
22 #include "clk-cpu.h"
23 
24 /* Exynos4 clock controller register offsets */
25 #define SRC_LEFTBUS		0x4200
26 #define DIV_LEFTBUS		0x4500
27 #define GATE_IP_LEFTBUS		0x4800
28 #define E4X12_GATE_IP_IMAGE	0x4930
29 #define CLKOUT_CMU_LEFTBUS	0x4a00
30 #define SRC_RIGHTBUS		0x8200
31 #define DIV_RIGHTBUS		0x8500
32 #define GATE_IP_RIGHTBUS	0x8800
33 #define E4X12_GATE_IP_PERIR	0x8960
34 #define CLKOUT_CMU_RIGHTBUS	0x8a00
35 #define EPLL_LOCK		0xc010
36 #define VPLL_LOCK		0xc020
37 #define EPLL_CON0		0xc110
38 #define EPLL_CON1		0xc114
39 #define EPLL_CON2		0xc118
40 #define VPLL_CON0		0xc120
41 #define VPLL_CON1		0xc124
42 #define VPLL_CON2		0xc128
43 #define SRC_TOP0		0xc210
44 #define SRC_TOP1		0xc214
45 #define SRC_CAM			0xc220
46 #define SRC_TV			0xc224
47 #define SRC_MFC			0xc228
48 #define SRC_G3D			0xc22c
49 #define E4210_SRC_IMAGE		0xc230
50 #define SRC_LCD0		0xc234
51 #define E4210_SRC_LCD1		0xc238
52 #define E4X12_SRC_ISP		0xc238
53 #define SRC_MAUDIO		0xc23c
54 #define SRC_FSYS		0xc240
55 #define SRC_PERIL0		0xc250
56 #define SRC_PERIL1		0xc254
57 #define E4X12_SRC_CAM1		0xc258
58 #define SRC_MASK_TOP		0xc310
59 #define SRC_MASK_CAM		0xc320
60 #define SRC_MASK_TV		0xc324
61 #define SRC_MASK_LCD0		0xc334
62 #define E4210_SRC_MASK_LCD1	0xc338
63 #define E4X12_SRC_MASK_ISP	0xc338
64 #define SRC_MASK_MAUDIO		0xc33c
65 #define SRC_MASK_FSYS		0xc340
66 #define SRC_MASK_PERIL0		0xc350
67 #define SRC_MASK_PERIL1		0xc354
68 #define DIV_TOP			0xc510
69 #define DIV_CAM			0xc520
70 #define DIV_TV			0xc524
71 #define DIV_MFC			0xc528
72 #define DIV_G3D			0xc52c
73 #define DIV_IMAGE		0xc530
74 #define DIV_LCD0		0xc534
75 #define E4210_DIV_LCD1		0xc538
76 #define E4X12_DIV_ISP		0xc538
77 #define DIV_MAUDIO		0xc53c
78 #define DIV_FSYS0		0xc540
79 #define DIV_FSYS1		0xc544
80 #define DIV_FSYS2		0xc548
81 #define DIV_FSYS3		0xc54c
82 #define DIV_PERIL0		0xc550
83 #define DIV_PERIL1		0xc554
84 #define DIV_PERIL2		0xc558
85 #define DIV_PERIL3		0xc55c
86 #define DIV_PERIL4		0xc560
87 #define DIV_PERIL5		0xc564
88 #define E4X12_DIV_CAM1		0xc568
89 #define E4X12_GATE_BUS_FSYS1	0xc744
90 #define GATE_SCLK_CAM		0xc820
91 #define GATE_IP_CAM		0xc920
92 #define GATE_IP_TV		0xc924
93 #define GATE_IP_MFC		0xc928
94 #define GATE_IP_G3D		0xc92c
95 #define E4210_GATE_IP_IMAGE	0xc930
96 #define GATE_IP_LCD0		0xc934
97 #define E4210_GATE_IP_LCD1	0xc938
98 #define E4X12_GATE_IP_ISP	0xc938
99 #define E4X12_GATE_IP_MAUDIO	0xc93c
100 #define GATE_IP_FSYS		0xc940
101 #define GATE_IP_GPS		0xc94c
102 #define GATE_IP_PERIL		0xc950
103 #define E4210_GATE_IP_PERIR	0xc960
104 #define GATE_BLOCK		0xc970
105 #define CLKOUT_CMU_TOP		0xca00
106 #define E4X12_MPLL_LOCK		0x10008
107 #define E4X12_MPLL_CON0		0x10108
108 #define SRC_DMC			0x10200
109 #define SRC_MASK_DMC		0x10300
110 #define DIV_DMC0		0x10500
111 #define DIV_DMC1		0x10504
112 #define GATE_IP_DMC		0x10900
113 #define CLKOUT_CMU_DMC		0x10a00
114 #define APLL_LOCK		0x14000
115 #define E4210_MPLL_LOCK		0x14008
116 #define APLL_CON0		0x14100
117 #define E4210_MPLL_CON0		0x14108
118 #define SRC_CPU			0x14200
119 #define DIV_CPU0		0x14500
120 #define DIV_CPU1		0x14504
121 #define GATE_SCLK_CPU		0x14800
122 #define GATE_IP_CPU		0x14900
123 #define CLKOUT_CMU_CPU		0x14a00
124 #define PWR_CTRL1		0x15020
125 #define E4X12_PWR_CTRL2		0x15024
126 #define E4X12_DIV_ISP0		0x18300
127 #define E4X12_DIV_ISP1		0x18304
128 #define E4X12_GATE_ISP0		0x18800
129 #define E4X12_GATE_ISP1		0x18804
130 
131 /* Below definitions are used for PWR_CTRL settings */
132 #define PWR_CTRL1_CORE2_DOWN_RATIO(x)		(((x) & 0x7) << 28)
133 #define PWR_CTRL1_CORE1_DOWN_RATIO(x)		(((x) & 0x7) << 16)
134 #define PWR_CTRL1_DIV2_DOWN_EN			(1 << 9)
135 #define PWR_CTRL1_DIV1_DOWN_EN			(1 << 8)
136 #define PWR_CTRL1_USE_CORE3_WFE			(1 << 7)
137 #define PWR_CTRL1_USE_CORE2_WFE			(1 << 6)
138 #define PWR_CTRL1_USE_CORE1_WFE			(1 << 5)
139 #define PWR_CTRL1_USE_CORE0_WFE			(1 << 4)
140 #define PWR_CTRL1_USE_CORE3_WFI			(1 << 3)
141 #define PWR_CTRL1_USE_CORE2_WFI			(1 << 2)
142 #define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)
143 #define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)
144 
145 /* the exynos4 soc type */
146 enum exynos4_soc {
147 	EXYNOS4210,
148 	EXYNOS4X12,
149 };
150 
151 /* list of PLLs to be registered */
152 enum exynos4_plls {
153 	apll, mpll, epll, vpll,
154 	nr_plls			/* number of PLLs */
155 };
156 
157 static void __iomem *reg_base;
158 static enum exynos4_soc exynos4_soc;
159 
160 /*
161  * Support for CMU save/restore across system suspends
162  */
163 #ifdef CONFIG_PM_SLEEP
164 static struct samsung_clk_reg_dump *exynos4_save_common;
165 static struct samsung_clk_reg_dump *exynos4_save_soc;
166 static struct samsung_clk_reg_dump *exynos4_save_pll;
167 
168 /*
169  * list of controller registers to be saved and restored during a
170  * suspend/resume cycle.
171  */
172 static const unsigned long exynos4210_clk_save[] __initconst = {
173 	E4210_SRC_IMAGE,
174 	E4210_SRC_LCD1,
175 	E4210_SRC_MASK_LCD1,
176 	E4210_DIV_LCD1,
177 	E4210_GATE_IP_IMAGE,
178 	E4210_GATE_IP_LCD1,
179 	E4210_GATE_IP_PERIR,
180 	E4210_MPLL_CON0,
181 	PWR_CTRL1,
182 };
183 
184 static const unsigned long exynos4x12_clk_save[] __initconst = {
185 	E4X12_GATE_IP_IMAGE,
186 	E4X12_GATE_IP_PERIR,
187 	E4X12_SRC_CAM1,
188 	E4X12_DIV_ISP,
189 	E4X12_DIV_CAM1,
190 	E4X12_MPLL_CON0,
191 	PWR_CTRL1,
192 	E4X12_PWR_CTRL2,
193 };
194 
195 static const unsigned long exynos4_clk_pll_regs[] __initconst = {
196 	EPLL_LOCK,
197 	VPLL_LOCK,
198 	EPLL_CON0,
199 	EPLL_CON1,
200 	EPLL_CON2,
201 	VPLL_CON0,
202 	VPLL_CON1,
203 	VPLL_CON2,
204 };
205 
206 static const unsigned long exynos4_clk_regs[] __initconst = {
207 	SRC_LEFTBUS,
208 	DIV_LEFTBUS,
209 	GATE_IP_LEFTBUS,
210 	SRC_RIGHTBUS,
211 	DIV_RIGHTBUS,
212 	GATE_IP_RIGHTBUS,
213 	SRC_TOP0,
214 	SRC_TOP1,
215 	SRC_CAM,
216 	SRC_TV,
217 	SRC_MFC,
218 	SRC_G3D,
219 	SRC_LCD0,
220 	SRC_MAUDIO,
221 	SRC_FSYS,
222 	SRC_PERIL0,
223 	SRC_PERIL1,
224 	SRC_MASK_TOP,
225 	SRC_MASK_CAM,
226 	SRC_MASK_TV,
227 	SRC_MASK_LCD0,
228 	SRC_MASK_MAUDIO,
229 	SRC_MASK_FSYS,
230 	SRC_MASK_PERIL0,
231 	SRC_MASK_PERIL1,
232 	DIV_TOP,
233 	DIV_CAM,
234 	DIV_TV,
235 	DIV_MFC,
236 	DIV_G3D,
237 	DIV_IMAGE,
238 	DIV_LCD0,
239 	DIV_MAUDIO,
240 	DIV_FSYS0,
241 	DIV_FSYS1,
242 	DIV_FSYS2,
243 	DIV_FSYS3,
244 	DIV_PERIL0,
245 	DIV_PERIL1,
246 	DIV_PERIL2,
247 	DIV_PERIL3,
248 	DIV_PERIL4,
249 	DIV_PERIL5,
250 	GATE_SCLK_CAM,
251 	GATE_IP_CAM,
252 	GATE_IP_TV,
253 	GATE_IP_MFC,
254 	GATE_IP_G3D,
255 	GATE_IP_LCD0,
256 	GATE_IP_FSYS,
257 	GATE_IP_GPS,
258 	GATE_IP_PERIL,
259 	GATE_BLOCK,
260 	SRC_MASK_DMC,
261 	SRC_DMC,
262 	DIV_DMC0,
263 	DIV_DMC1,
264 	GATE_IP_DMC,
265 	APLL_CON0,
266 	SRC_CPU,
267 	DIV_CPU0,
268 	DIV_CPU1,
269 	GATE_SCLK_CPU,
270 	GATE_IP_CPU,
271 	CLKOUT_CMU_LEFTBUS,
272 	CLKOUT_CMU_RIGHTBUS,
273 	CLKOUT_CMU_TOP,
274 	CLKOUT_CMU_DMC,
275 	CLKOUT_CMU_CPU,
276 };
277 
278 static const struct samsung_clk_reg_dump src_mask_suspend[] = {
279 	{ .offset = SRC_MASK_TOP,		.value = 0x00000001, },
280 	{ .offset = SRC_MASK_CAM,		.value = 0x11111111, },
281 	{ .offset = SRC_MASK_TV,		.value = 0x00000111, },
282 	{ .offset = SRC_MASK_LCD0,		.value = 0x00001111, },
283 	{ .offset = SRC_MASK_MAUDIO,		.value = 0x00000001, },
284 	{ .offset = SRC_MASK_FSYS,		.value = 0x01011111, },
285 	{ .offset = SRC_MASK_PERIL0,		.value = 0x01111111, },
286 	{ .offset = SRC_MASK_PERIL1,		.value = 0x01110111, },
287 	{ .offset = SRC_MASK_DMC,		.value = 0x00010000, },
288 };
289 
290 static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = {
291 	{ .offset = E4210_SRC_MASK_LCD1,	.value = 0x00001111, },
292 };
293 
294 #define PLL_ENABLED	(1 << 31)
295 #define PLL_LOCKED	(1 << 29)
296 
297 static void exynos4_clk_wait_for_pll(u32 reg)
298 {
299 	u32 pll_con;
300 
301 	pll_con = readl(reg_base + reg);
302 	if (!(pll_con & PLL_ENABLED))
303 		return;
304 
305 	while (!(pll_con & PLL_LOCKED)) {
306 		cpu_relax();
307 		pll_con = readl(reg_base + reg);
308 	}
309 }
310 
311 static int exynos4_clk_suspend(void)
312 {
313 	samsung_clk_save(reg_base, exynos4_save_common,
314 				ARRAY_SIZE(exynos4_clk_regs));
315 	samsung_clk_save(reg_base, exynos4_save_pll,
316 				ARRAY_SIZE(exynos4_clk_pll_regs));
317 
318 	if (exynos4_soc == EXYNOS4210) {
319 		samsung_clk_save(reg_base, exynos4_save_soc,
320 					ARRAY_SIZE(exynos4210_clk_save));
321 		samsung_clk_restore(reg_base, src_mask_suspend_e4210,
322 					ARRAY_SIZE(src_mask_suspend_e4210));
323 	} else {
324 		samsung_clk_save(reg_base, exynos4_save_soc,
325 					ARRAY_SIZE(exynos4x12_clk_save));
326 	}
327 
328 	samsung_clk_restore(reg_base, src_mask_suspend,
329 					ARRAY_SIZE(src_mask_suspend));
330 
331 	return 0;
332 }
333 
334 static void exynos4_clk_resume(void)
335 {
336 	samsung_clk_restore(reg_base, exynos4_save_pll,
337 				ARRAY_SIZE(exynos4_clk_pll_regs));
338 
339 	exynos4_clk_wait_for_pll(EPLL_CON0);
340 	exynos4_clk_wait_for_pll(VPLL_CON0);
341 
342 	samsung_clk_restore(reg_base, exynos4_save_common,
343 				ARRAY_SIZE(exynos4_clk_regs));
344 
345 	if (exynos4_soc == EXYNOS4210)
346 		samsung_clk_restore(reg_base, exynos4_save_soc,
347 					ARRAY_SIZE(exynos4210_clk_save));
348 	else
349 		samsung_clk_restore(reg_base, exynos4_save_soc,
350 					ARRAY_SIZE(exynos4x12_clk_save));
351 }
352 
353 static struct syscore_ops exynos4_clk_syscore_ops = {
354 	.suspend = exynos4_clk_suspend,
355 	.resume = exynos4_clk_resume,
356 };
357 
358 static void __init exynos4_clk_sleep_init(void)
359 {
360 	exynos4_save_common = samsung_clk_alloc_reg_dump(exynos4_clk_regs,
361 					ARRAY_SIZE(exynos4_clk_regs));
362 	if (!exynos4_save_common)
363 		goto err_warn;
364 
365 	if (exynos4_soc == EXYNOS4210)
366 		exynos4_save_soc = samsung_clk_alloc_reg_dump(
367 					exynos4210_clk_save,
368 					ARRAY_SIZE(exynos4210_clk_save));
369 	else
370 		exynos4_save_soc = samsung_clk_alloc_reg_dump(
371 					exynos4x12_clk_save,
372 					ARRAY_SIZE(exynos4x12_clk_save));
373 	if (!exynos4_save_soc)
374 		goto err_common;
375 
376 	exynos4_save_pll = samsung_clk_alloc_reg_dump(exynos4_clk_pll_regs,
377 					ARRAY_SIZE(exynos4_clk_pll_regs));
378 	if (!exynos4_save_pll)
379 		goto err_soc;
380 
381 	register_syscore_ops(&exynos4_clk_syscore_ops);
382 	return;
383 
384 err_soc:
385 	kfree(exynos4_save_soc);
386 err_common:
387 	kfree(exynos4_save_common);
388 err_warn:
389 	pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
390 		__func__);
391 }
392 #else
393 static void __init exynos4_clk_sleep_init(void) {}
394 #endif
395 
396 /* list of all parent clock list */
397 PNAME(mout_apll_p)	= { "fin_pll", "fout_apll", };
398 PNAME(mout_mpll_p)	= { "fin_pll", "fout_mpll", };
399 PNAME(mout_epll_p)	= { "fin_pll", "fout_epll", };
400 PNAME(mout_vpllsrc_p)	= { "fin_pll", "sclk_hdmi24m", };
401 PNAME(mout_vpll_p)	= { "fin_pll", "fout_vpll", };
402 PNAME(sclk_evpll_p)	= { "sclk_epll", "sclk_vpll", };
403 PNAME(mout_mfc_p)	= { "mout_mfc0", "mout_mfc1", };
404 PNAME(mout_g3d_p)	= { "mout_g3d0", "mout_g3d1", };
405 PNAME(mout_g2d_p)	= { "mout_g2d0", "mout_g2d1", };
406 PNAME(mout_hdmi_p)	= { "sclk_pixel", "sclk_hdmiphy", };
407 PNAME(mout_jpeg_p)	= { "mout_jpeg0", "mout_jpeg1", };
408 PNAME(mout_spdif_p)	= { "sclk_audio0", "sclk_audio1", "sclk_audio2",
409 				"spdif_extclk", };
410 PNAME(mout_onenand_p)  = {"aclk133", "aclk160", };
411 PNAME(mout_onenand1_p) = {"mout_onenand", "sclk_vpll", };
412 
413 /* Exynos 4210-specific parent groups */
414 PNAME(sclk_vpll_p4210)	= { "mout_vpllsrc", "fout_vpll", };
415 PNAME(mout_core_p4210)	= { "mout_apll", "sclk_mpll", };
416 PNAME(sclk_ampll_p4210)	= { "sclk_mpll", "sclk_apll", };
417 PNAME(group1_p4210)	= { "xxti", "xusbxti", "sclk_hdmi24m",
418 				"sclk_usbphy0", "none",	"sclk_hdmiphy",
419 				"sclk_mpll", "sclk_epll", "sclk_vpll", };
420 PNAME(mout_audio0_p4210) = { "cdclk0", "none", "sclk_hdmi24m",
421 				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
422 				"sclk_epll", "sclk_vpll" };
423 PNAME(mout_audio1_p4210) = { "cdclk1", "none", "sclk_hdmi24m",
424 				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
425 				"sclk_epll", "sclk_vpll", };
426 PNAME(mout_audio2_p4210) = { "cdclk2", "none", "sclk_hdmi24m",
427 				"sclk_usbphy0", "xxti", "xusbxti", "sclk_mpll",
428 				"sclk_epll", "sclk_vpll", };
429 PNAME(mout_mixer_p4210)	= { "sclk_dac", "sclk_hdmi", };
430 PNAME(mout_dac_p4210)	= { "sclk_vpll", "sclk_hdmiphy", };
431 PNAME(mout_pwi_p4210) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
432 				"sclk_usbphy1", "sclk_hdmiphy", "none",
433 				"sclk_epll", "sclk_vpll" };
434 PNAME(clkout_left_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
435 				"div_gdl", "div_gpl" };
436 PNAME(clkout_right_p4210) = { "sclk_mpll_div_2", "sclk_apll_div_2",
437 				"div_gdr", "div_gpr" };
438 PNAME(clkout_top_p4210) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
439 				"sclk_usbphy0", "sclk_usbphy1", "sclk_hdmiphy",
440 				"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
441 				"aclk160", "aclk133", "aclk200", "aclk100",
442 				"sclk_mfc", "sclk_g3d", "sclk_g2d",
443 				"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
444 				"s_rxbyteclkhs0_4l" };
445 PNAME(clkout_dmc_p4210) = { "div_dmcd", "div_dmcp", "div_acp_pclk", "div_dmc",
446 				"div_dphy", "none", "div_pwi" };
447 PNAME(clkout_cpu_p4210) = { "fout_apll_div_2", "none", "fout_mpll_div_2",
448 				"none", "arm_clk_div_2", "div_corem0",
449 				"div_corem1", "div_corem0", "div_atb",
450 				"div_periph", "div_pclk_dbg", "div_hpm" };
451 
452 /* Exynos 4x12-specific parent groups */
453 PNAME(mout_mpll_user_p4x12) = { "fin_pll", "sclk_mpll", };
454 PNAME(mout_core_p4x12)	= { "mout_apll", "mout_mpll_user_c", };
455 PNAME(mout_gdl_p4x12)	= { "mout_mpll_user_l", "sclk_apll", };
456 PNAME(mout_gdr_p4x12)	= { "mout_mpll_user_r", "sclk_apll", };
457 PNAME(sclk_ampll_p4x12)	= { "mout_mpll_user_t", "sclk_apll", };
458 PNAME(group1_p4x12)	= { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
459 				"none",	"sclk_hdmiphy", "mout_mpll_user_t",
460 				"sclk_epll", "sclk_vpll", };
461 PNAME(mout_audio0_p4x12) = { "cdclk0", "none", "sclk_hdmi24m",
462 				"sclk_usbphy0", "xxti", "xusbxti",
463 				"mout_mpll_user_t", "sclk_epll", "sclk_vpll" };
464 PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m",
465 				"sclk_usbphy0", "xxti", "xusbxti",
466 				"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
467 PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m",
468 				"sclk_usbphy0", "xxti", "xusbxti",
469 				"mout_mpll_user_t", "sclk_epll", "sclk_vpll", };
470 PNAME(aclk_p4412)	= { "mout_mpll_user_t", "sclk_apll", };
471 PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", };
472 PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", };
473 PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", };
474 PNAME(mout_pwi_p4x12) = { "xxti", "xusbxti", "sclk_hdmi24m", "sclk_usbphy0",
475 				"none", "sclk_hdmiphy", "sclk_mpll",
476 				"sclk_epll", "sclk_vpll" };
477 PNAME(clkout_left_p4x12) = { "sclk_mpll_user_l_div_2", "sclk_apll_div_2",
478 				"div_gdl", "div_gpl" };
479 PNAME(clkout_right_p4x12) = { "sclk_mpll_user_r_div_2", "sclk_apll_div_2",
480 				"div_gdr", "div_gpr" };
481 PNAME(clkout_top_p4x12) = { "fout_epll", "fout_vpll", "sclk_hdmi24m",
482 				"sclk_usbphy0", "none", "sclk_hdmiphy",
483 				"cdclk0", "cdclk1", "cdclk2", "spdif_extclk",
484 				"aclk160", "aclk133", "aclk200", "aclk100",
485 				"sclk_mfc", "sclk_g3d", "aclk400_mcuisp",
486 				"cam_a_pclk", "cam_b_pclk", "s_rxbyteclkhs0_2l",
487 				"s_rxbyteclkhs0_4l", "rx_half_byte_clk_csis0",
488 				"rx_half_byte_clk_csis1", "div_jpeg",
489 				"sclk_pwm_isp", "sclk_spi0_isp",
490 				"sclk_spi1_isp", "sclk_uart_isp",
491 				"sclk_mipihsi", "sclk_hdmi", "sclk_fimd0",
492 				"sclk_pcm0" };
493 PNAME(clkout_dmc_p4x12) = { "div_dmcd", "div_dmcp", "aclk_acp", "div_acp_pclk",
494 				"div_dmc", "div_dphy", "fout_mpll_div_2",
495 				"div_pwi", "none", "div_c2c", "div_c2c_aclk" };
496 PNAME(clkout_cpu_p4x12) = { "fout_apll_div_2", "none", "none", "none",
497 				"arm_clk_div_2", "div_corem0", "div_corem1",
498 				"div_cores", "div_atb", "div_periph",
499 				"div_pclk_dbg", "div_hpm" };
500 
501 /* fixed rate clocks generated outside the soc */
502 static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = {
503 	FRATE(CLK_XXTI, "xxti", NULL, 0, 0),
504 	FRATE(CLK_XUSBXTI, "xusbxti", NULL, 0, 0),
505 };
506 
507 /* fixed rate clocks generated inside the soc */
508 static const struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initconst = {
509 	FRATE(0, "sclk_hdmi24m", NULL, 0, 24000000),
510 	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
511 	FRATE(0, "sclk_usbphy0", NULL, 0, 48000000),
512 };
513 
514 static const struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initconst = {
515 	FRATE(0, "sclk_usbphy1", NULL, 0, 48000000),
516 };
517 
518 static const struct samsung_fixed_factor_clock exynos4_fixed_factor_clks[] __initconst = {
519 	FFACTOR(0, "sclk_apll_div_2", "sclk_apll", 1, 2, 0),
520 	FFACTOR(0, "fout_mpll_div_2", "fout_mpll", 1, 2, 0),
521 	FFACTOR(0, "fout_apll_div_2", "fout_apll", 1, 2, 0),
522 	FFACTOR(0, "arm_clk_div_2", "div_core2", 1, 2, 0),
523 };
524 
525 static const struct samsung_fixed_factor_clock exynos4210_fixed_factor_clks[] __initconst = {
526 	FFACTOR(0, "sclk_mpll_div_2", "sclk_mpll", 1, 2, 0),
527 };
528 
529 static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __initconst = {
530 	FFACTOR(0, "sclk_mpll_user_l_div_2", "mout_mpll_user_l", 1, 2, 0),
531 	FFACTOR(0, "sclk_mpll_user_r_div_2", "mout_mpll_user_r", 1, 2, 0),
532 	FFACTOR(0, "sclk_mpll_user_t_div_2", "mout_mpll_user_t", 1, 2, 0),
533 	FFACTOR(0, "sclk_mpll_user_c_div_2", "mout_mpll_user_c", 1, 2, 0),
534 };
535 
536 /* list of mux clocks supported in all exynos4 soc's */
537 static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
538 	MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
539 			CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,
540 			"mout_apll"),
541 	MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
542 	MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
543 	MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
544 	MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1,
545 			CLK_SET_RATE_PARENT, 0),
546 	MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1,
547 			CLK_SET_RATE_PARENT, 0),
548 	MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2),
549 	MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1),
550 	MUX(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1),
551 	MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1),
552 
553 	MUX(0, "mout_dmc_bus", sclk_ampll_p4210, SRC_DMC, 4, 1),
554 	MUX(0, "mout_dphy", sclk_ampll_p4210, SRC_DMC, 8, 1),
555 };
556 
557 /* list of mux clocks supported in exynos4210 soc */
558 static const struct samsung_mux_clock exynos4210_mux_early[] __initconst = {
559 	MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1),
560 };
561 
562 static const struct samsung_mux_clock exynos4210_mux_clks[] __initconst = {
563 	MUX(0, "mout_gdl", sclk_ampll_p4210, SRC_LEFTBUS, 0, 1),
564 	MUX(0, "mout_clkout_leftbus", clkout_left_p4210,
565 			CLKOUT_CMU_LEFTBUS, 0, 5),
566 
567 	MUX(0, "mout_gdr", sclk_ampll_p4210, SRC_RIGHTBUS, 0, 1),
568 	MUX(0, "mout_clkout_rightbus", clkout_right_p4210,
569 			CLKOUT_CMU_RIGHTBUS, 0, 5),
570 
571 	MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1),
572 	MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1),
573 	MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1),
574 	MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1),
575 	MUX(CLK_MOUT_MIXER, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1),
576 	MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1),
577 	MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1),
578 	MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1),
579 	MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1),
580 	MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4),
581 	MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4),
582 	MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1),
583 	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
584 	MUX(0, "mout_hpm", mout_core_p4210, SRC_CPU, 20, 1),
585 	MUX(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1),
586 	MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
587 	MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4),
588 	MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4),
589 	MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4),
590 	MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4),
591 	MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4),
592 	MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4),
593 	MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4),
594 	MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1),
595 	MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1,
596 			CLK_SET_RATE_PARENT, 0),
597 	MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4),
598 	MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4),
599 	MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4),
600 	MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4),
601 	MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4),
602 	MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
603 	MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
604 	MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
605 	MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
606 	MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
607 	MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
608 	MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),
609 	MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4),
610 	MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4),
611 	MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4),
612 	MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4),
613 	MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4),
614 	MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4),
615 	MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4),
616 	MUX(0, "mout_clkout_top", clkout_top_p4210, CLKOUT_CMU_TOP, 0, 5),
617 
618 	MUX(0, "mout_pwi", mout_pwi_p4210, SRC_DMC, 16, 4),
619 	MUX(0, "mout_clkout_dmc", clkout_dmc_p4210, CLKOUT_CMU_DMC, 0, 5),
620 
621 	MUX(0, "mout_clkout_cpu", clkout_cpu_p4210, CLKOUT_CMU_CPU, 0, 5),
622 };
623 
624 /* list of mux clocks supported in exynos4x12 soc */
625 static const struct samsung_mux_clock exynos4x12_mux_clks[] __initconst = {
626 	MUX(0, "mout_mpll_user_l", mout_mpll_p, SRC_LEFTBUS, 4, 1),
627 	MUX(0, "mout_gdl", mout_gdl_p4x12, SRC_LEFTBUS, 0, 1),
628 	MUX(0, "mout_clkout_leftbus", clkout_left_p4x12,
629 			CLKOUT_CMU_LEFTBUS, 0, 5),
630 
631 	MUX(0, "mout_mpll_user_r", mout_mpll_p, SRC_RIGHTBUS, 4, 1),
632 	MUX(0, "mout_gdr", mout_gdr_p4x12, SRC_RIGHTBUS, 0, 1),
633 	MUX(0, "mout_clkout_rightbus", clkout_right_p4x12,
634 			CLKOUT_CMU_RIGHTBUS, 0, 5),
635 
636 	MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12,
637 			SRC_CPU, 24, 1),
638 	MUX(0, "mout_clkout_cpu", clkout_cpu_p4x12, CLKOUT_CMU_CPU, 0, 5),
639 
640 	MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1),
641 	MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1),
642 	MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12,
643 			SRC_TOP1, 12, 1),
644 	MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12,
645 			SRC_TOP1, 16, 1),
646 	MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1),
647 	MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp",
648 		mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1),
649 	MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1),
650 	MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1),
651 	MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1),
652 	MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1),
653 	MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4),
654 	MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4),
655 	MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1),
656 	MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1),
657 	MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1),
658 	MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
659 	MUX(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1),
660 	MUX(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1),
661 	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1),
662 	MUX(0, "mout_hpm", mout_core_p4x12, SRC_CPU, 20, 1),
663 	MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4),
664 	MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4),
665 	MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4),
666 	MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4),
667 	MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4),
668 	MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4),
669 	MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4),
670 	MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4),
671 	MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1),
672 	MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1,
673 			CLK_SET_RATE_PARENT, 0),
674 	MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4),
675 	MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4),
676 	MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4),
677 	MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4),
678 	MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4),
679 	MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4),
680 	MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4),
681 	MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4),
682 	MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1),
683 	MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4),
684 	MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4),
685 	MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4),
686 	MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4),
687 	MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4),
688 	MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4),
689 	MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4),
690 	MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4),
691 	MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4),
692 	MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4),
693 	MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4),
694 	MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
695 	MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
696 	MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
697 	MUX(0, "mout_clkout_top", clkout_top_p4x12, CLKOUT_CMU_TOP, 0, 5),
698 
699 	MUX(0, "mout_c2c", sclk_ampll_p4210, SRC_DMC, 0, 1),
700 	MUX(0, "mout_pwi", mout_pwi_p4x12, SRC_DMC, 16, 4),
701 	MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
702 	MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
703 	MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
704 	MUX(0, "mout_clkout_dmc", clkout_dmc_p4x12, CLKOUT_CMU_DMC, 0, 5),
705 };
706 
707 /* list of divider clocks supported in all exynos4 soc's */
708 static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
709 	DIV(CLK_DIV_GDL, "div_gdl", "mout_gdl", DIV_LEFTBUS, 0, 3),
710 	DIV(0, "div_gpl", "div_gdl", DIV_LEFTBUS, 4, 3),
711 	DIV(0, "div_clkout_leftbus", "mout_clkout_leftbus",
712 			CLKOUT_CMU_LEFTBUS, 8, 6),
713 
714 	DIV(CLK_DIV_GDR, "div_gdr", "mout_gdr", DIV_RIGHTBUS, 0, 3),
715 	DIV(0, "div_gpr", "div_gdr", DIV_RIGHTBUS, 4, 3),
716 	DIV(0, "div_clkout_rightbus", "mout_clkout_rightbus",
717 			CLKOUT_CMU_RIGHTBUS, 8, 6),
718 
719 	DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3),
720 	DIV(0, "div_corem0", "div_core2", DIV_CPU0, 4, 3),
721 	DIV(0, "div_corem1", "div_core2", DIV_CPU0, 8, 3),
722 	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
723 	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
724 	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
725 	DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
726 	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
727 	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
728 	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
729 
730 	DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4),
731 	DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4),
732 	DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4),
733 	DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4),
734 	DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4),
735 	DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4),
736 	DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4),
737 	DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4),
738 	DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4),
739 	DIV(CLK_SCLK_G3D, "sclk_g3d", "mout_g3d", DIV_G3D, 0, 4),
740 	DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4),
741 	DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4),
742 	DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4),
743 	DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8),
744 	DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
745 	DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
746 	DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
747 	DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4),
748 	DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4),
749 	DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4),
750 	DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3),
751 	DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3),
752 	DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3),
753 	DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4),
754 	DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8),
755 	DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8),
756 	DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
757 	DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
758 	DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
759 	DIV_F(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
760 			CLK_SET_RATE_PARENT, 0),
761 	DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
762 	DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
763 	DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
764 	DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4),
765 	DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4),
766 	DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4),
767 	DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8),
768 	DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4),
769 	DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8),
770 	DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4),
771 	DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8),
772 	DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4),
773 	DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4),
774 	DIV(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
775 	DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,
776 			CLK_SET_RATE_PARENT, 0),
777 	DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8,
778 			CLK_SET_RATE_PARENT, 0),
779 	DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8,
780 			CLK_SET_RATE_PARENT, 0),
781 	DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8,
782 			CLK_SET_RATE_PARENT, 0),
783 	DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8,
784 			CLK_SET_RATE_PARENT, 0),
785 	DIV(0, "div_clkout_top", "mout_clkout_top", CLKOUT_CMU_TOP, 8, 6),
786 
787 	DIV(CLK_DIV_ACP, "div_acp", "mout_dmc_bus", DIV_DMC0, 0, 3),
788 	DIV(0, "div_acp_pclk", "div_acp", DIV_DMC0, 4, 3),
789 	DIV(0, "div_dphy", "mout_dphy", DIV_DMC0, 8, 3),
790 	DIV(CLK_DIV_DMC, "div_dmc", "mout_dmc_bus", DIV_DMC0, 12, 3),
791 	DIV(0, "div_dmcd", "div_dmc", DIV_DMC0, 16, 3),
792 	DIV(0, "div_dmcp", "div_dmcd", DIV_DMC0, 20, 3),
793 	DIV(0, "div_pwi", "mout_pwi", DIV_DMC1, 8, 4),
794 	DIV(0, "div_clkout_dmc", "mout_clkout_dmc", CLKOUT_CMU_DMC, 8, 6),
795 };
796 
797 /* list of divider clocks supported in exynos4210 soc */
798 static const struct samsung_div_clock exynos4210_div_clks[] __initconst = {
799 	DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
800 	DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
801 	DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
802 	DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
803 	DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
804 	DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4,
805 			CLK_SET_RATE_PARENT, 0),
806 };
807 
808 /* list of divider clocks supported in exynos4x12 soc */
809 static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
810 	DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4),
811 	DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4),
812 	DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4),
813 	DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4),
814 	DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4),
815 	DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3),
816 	DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3),
817 	DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp",
818 						DIV_TOP, 24, 3),
819 	DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4),
820 	DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4),
821 	DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8),
822 	DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
823 	DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
824 	DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
825 	DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
826 						CLK_GET_RATE_NOCACHE, 0),
827 	DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
828 						CLK_GET_RATE_NOCACHE, 0),
829 	DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
830 	DIV_F(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1,
831 						4, 3, CLK_GET_RATE_NOCACHE, 0),
832 	DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
833 						8, 3, CLK_GET_RATE_NOCACHE, 0),
834 	DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
835 	DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
836 	DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
837 };
838 
839 /* list of gate clocks supported in all exynos4 soc's */
840 static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
841 	/*
842 	 * After all Exynos4 based platforms are migrated to use device tree,
843 	 * the device name and clock alias names specified below for some
844 	 * of the clocks can be removed.
845 	 */
846 	GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
847 	GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
848 	GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
849 	GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
850 		0),
851 	GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
852 	GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
853 	GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
854 	GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
855 	GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
856 	GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
857 	GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0,
858 		0),
859 	GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0),
860 	GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0),
861 	GATE(CLK_G3D, "g3d", "aclk200", GATE_IP_G3D, 0, 0, 0),
862 	GATE(CLK_PPMUG3D, "ppmug3d", "aclk200", GATE_IP_G3D, 1, 0, 0),
863 	GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0),
864 	GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0),
865 	GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0),
866 	GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0),
867 	GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0),
868 	GATE(CLK_PPMUGPS, "ppmugps", "aclk200", GATE_IP_GPS, 2, 0, 0),
869 	GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0),
870 	GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4,
871 			CLK_SET_RATE_PARENT, 0),
872 	GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5,
873 			CLK_SET_RATE_PARENT, 0),
874 	GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0",
875 			SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0),
876 	GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0,
877 			CLK_SET_RATE_PARENT, 0),
878 	GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0,
879 			CLK_SET_RATE_PARENT, 0),
880 	GATE(CLK_VP, "vp", "aclk160", GATE_IP_TV, 0, 0, 0),
881 	GATE(CLK_MIXER, "mixer", "aclk160", GATE_IP_TV, 1, 0, 0),
882 	GATE(CLK_HDMI, "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0),
883 	GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
884 	GATE(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0),
885 	GATE(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0),
886 	GATE(CLK_SCLK_FIMC0, "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0,
887 			CLK_SET_RATE_PARENT, 0),
888 	GATE(CLK_SCLK_FIMC1, "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4,
889 			CLK_SET_RATE_PARENT, 0),
890 	GATE(CLK_SCLK_FIMC2, "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8,
891 			CLK_SET_RATE_PARENT, 0),
892 	GATE(CLK_SCLK_FIMC3, "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12,
893 			CLK_SET_RATE_PARENT, 0),
894 	GATE(CLK_SCLK_CSIS0, "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24,
895 			CLK_SET_RATE_PARENT, 0),
896 	GATE(CLK_SCLK_CSIS1, "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28,
897 			CLK_SET_RATE_PARENT, 0),
898 	GATE(CLK_SCLK_FIMD0, "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0,
899 			CLK_SET_RATE_PARENT, 0),
900 	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0,
901 			CLK_SET_RATE_PARENT, 0),
902 	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4,
903 			CLK_SET_RATE_PARENT, 0),
904 	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8,
905 			CLK_SET_RATE_PARENT, 0),
906 	GATE(CLK_SCLK_MMC3, "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12,
907 			CLK_SET_RATE_PARENT, 0),
908 	GATE(CLK_SCLK_MMC4, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16,
909 			CLK_SET_RATE_PARENT, 0),
910 	GATE(CLK_SCLK_UART0, "uclk0", "div_uart0", SRC_MASK_PERIL0, 0,
911 			CLK_SET_RATE_PARENT, 0),
912 	GATE(CLK_SCLK_UART1, "uclk1", "div_uart1", SRC_MASK_PERIL0, 4,
913 			CLK_SET_RATE_PARENT, 0),
914 	GATE(CLK_SCLK_UART2, "uclk2", "div_uart2", SRC_MASK_PERIL0, 8,
915 			CLK_SET_RATE_PARENT, 0),
916 	GATE(CLK_SCLK_UART3, "uclk3", "div_uart3", SRC_MASK_PERIL0, 12,
917 			CLK_SET_RATE_PARENT, 0),
918 	GATE(CLK_SCLK_UART4, "uclk4", "div_uart4", SRC_MASK_PERIL0, 16,
919 			CLK_SET_RATE_PARENT, 0),
920 	GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4,
921 			CLK_SET_RATE_PARENT, 0),
922 	GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16,
923 			CLK_SET_RATE_PARENT, 0),
924 	GATE(CLK_SCLK_SPI1, "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20,
925 			CLK_SET_RATE_PARENT, 0),
926 	GATE(CLK_SCLK_SPI2, "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24,
927 			CLK_SET_RATE_PARENT, 0),
928 	GATE(CLK_FIMC0, "fimc0", "aclk160", GATE_IP_CAM, 0,
929 			0, 0),
930 	GATE(CLK_FIMC1, "fimc1", "aclk160", GATE_IP_CAM, 1,
931 			0, 0),
932 	GATE(CLK_FIMC2, "fimc2", "aclk160", GATE_IP_CAM, 2,
933 			0, 0),
934 	GATE(CLK_FIMC3, "fimc3", "aclk160", GATE_IP_CAM, 3,
935 			0, 0),
936 	GATE(CLK_CSIS0, "csis0", "aclk160", GATE_IP_CAM, 4,
937 			0, 0),
938 	GATE(CLK_CSIS1, "csis1", "aclk160", GATE_IP_CAM, 5,
939 			0, 0),
940 	GATE(CLK_SMMU_FIMC0, "smmu_fimc0", "aclk160", GATE_IP_CAM, 7,
941 			0, 0),
942 	GATE(CLK_SMMU_FIMC1, "smmu_fimc1", "aclk160", GATE_IP_CAM, 8,
943 			0, 0),
944 	GATE(CLK_SMMU_FIMC2, "smmu_fimc2", "aclk160", GATE_IP_CAM, 9,
945 			0, 0),
946 	GATE(CLK_SMMU_FIMC3, "smmu_fimc3", "aclk160", GATE_IP_CAM, 10,
947 			0, 0),
948 	GATE(CLK_SMMU_JPEG, "smmu_jpeg", "aclk160", GATE_IP_CAM, 11,
949 			0, 0),
950 	GATE(CLK_PPMUCAMIF, "ppmucamif", "aclk160", GATE_IP_CAM, 16, 0, 0),
951 	GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0),
952 	GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0),
953 	GATE(CLK_SMMU_TV, "smmu_tv", "aclk160", GATE_IP_TV, 4,
954 			0, 0),
955 	GATE(CLK_PPMUTV, "ppmutv", "aclk160", GATE_IP_TV, 5, 0, 0),
956 	GATE(CLK_MFC, "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0),
957 	GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
958 			0, 0),
959 	GATE(CLK_SMMU_MFCR, "smmu_mfcr", "aclk100", GATE_IP_MFC, 2,
960 			0, 0),
961 	GATE(CLK_PPMUMFC_L, "ppmumfc_l", "aclk100", GATE_IP_MFC, 3, 0, 0),
962 	GATE(CLK_PPMUMFC_R, "ppmumfc_r", "aclk100", GATE_IP_MFC, 4, 0, 0),
963 	GATE(CLK_FIMD0, "fimd0", "aclk160", GATE_IP_LCD0, 0,
964 			0, 0),
965 	GATE(CLK_SMMU_FIMD0, "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4,
966 			0, 0),
967 	GATE(CLK_PPMULCD0, "ppmulcd0", "aclk160", GATE_IP_LCD0, 5, 0, 0),
968 	GATE(CLK_PDMA0, "pdma0", "aclk133", GATE_IP_FSYS, 0,
969 			0, 0),
970 	GATE(CLK_PDMA1, "pdma1", "aclk133", GATE_IP_FSYS, 1,
971 			0, 0),
972 	GATE(CLK_SDMMC0, "sdmmc0", "aclk133", GATE_IP_FSYS, 5,
973 			0, 0),
974 	GATE(CLK_SDMMC1, "sdmmc1", "aclk133", GATE_IP_FSYS, 6,
975 			0, 0),
976 	GATE(CLK_SDMMC2, "sdmmc2", "aclk133", GATE_IP_FSYS, 7,
977 			0, 0),
978 	GATE(CLK_SDMMC3, "sdmmc3", "aclk133", GATE_IP_FSYS, 8,
979 			0, 0),
980 	GATE(CLK_PPMUFILE, "ppmufile", "aclk133", GATE_IP_FSYS, 17, 0, 0),
981 	GATE(CLK_UART0, "uart0", "aclk100", GATE_IP_PERIL, 0,
982 			0, 0),
983 	GATE(CLK_UART1, "uart1", "aclk100", GATE_IP_PERIL, 1,
984 			0, 0),
985 	GATE(CLK_UART2, "uart2", "aclk100", GATE_IP_PERIL, 2,
986 			0, 0),
987 	GATE(CLK_UART3, "uart3", "aclk100", GATE_IP_PERIL, 3,
988 			0, 0),
989 	GATE(CLK_UART4, "uart4", "aclk100", GATE_IP_PERIL, 4,
990 			0, 0),
991 	GATE(CLK_I2C0, "i2c0", "aclk100", GATE_IP_PERIL, 6,
992 			0, 0),
993 	GATE(CLK_I2C1, "i2c1", "aclk100", GATE_IP_PERIL, 7,
994 			0, 0),
995 	GATE(CLK_I2C2, "i2c2", "aclk100", GATE_IP_PERIL, 8,
996 			0, 0),
997 	GATE(CLK_I2C3, "i2c3", "aclk100", GATE_IP_PERIL, 9,
998 			0, 0),
999 	GATE(CLK_I2C4, "i2c4", "aclk100", GATE_IP_PERIL, 10,
1000 			0, 0),
1001 	GATE(CLK_I2C5, "i2c5", "aclk100", GATE_IP_PERIL, 11,
1002 			0, 0),
1003 	GATE(CLK_I2C6, "i2c6", "aclk100", GATE_IP_PERIL, 12,
1004 			0, 0),
1005 	GATE(CLK_I2C7, "i2c7", "aclk100", GATE_IP_PERIL, 13,
1006 			0, 0),
1007 	GATE(CLK_I2C_HDMI, "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14,
1008 			0, 0),
1009 	GATE(CLK_SPI0, "spi0", "aclk100", GATE_IP_PERIL, 16,
1010 			0, 0),
1011 	GATE(CLK_SPI1, "spi1", "aclk100", GATE_IP_PERIL, 17,
1012 			0, 0),
1013 	GATE(CLK_SPI2, "spi2", "aclk100", GATE_IP_PERIL, 18,
1014 			0, 0),
1015 	GATE(CLK_I2S1, "i2s1", "aclk100", GATE_IP_PERIL, 20,
1016 			0, 0),
1017 	GATE(CLK_I2S2, "i2s2", "aclk100", GATE_IP_PERIL, 21,
1018 			0, 0),
1019 	GATE(CLK_PCM1, "pcm1", "aclk100", GATE_IP_PERIL, 22,
1020 			0, 0),
1021 	GATE(CLK_PCM2, "pcm2", "aclk100", GATE_IP_PERIL, 23,
1022 			0, 0),
1023 	GATE(CLK_SPDIF, "spdif", "aclk100", GATE_IP_PERIL, 26,
1024 			0, 0),
1025 	GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,
1026 			0, 0),
1027 	GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),
1028 	GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),
1029 	GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),
1030 	GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),
1031 	GATE(CLK_PPMUACP, "ppmuacp", "aclk133", GATE_IP_DMC, 16, 0, 0),
1032 
1033 	GATE(CLK_OUT_LEFTBUS, "clkout_leftbus", "div_clkout_leftbus",
1034 			CLKOUT_CMU_LEFTBUS, 16, CLK_SET_RATE_PARENT, 0),
1035 	GATE(CLK_OUT_RIGHTBUS, "clkout_rightbus", "div_clkout_rightbus",
1036 			CLKOUT_CMU_RIGHTBUS, 16, CLK_SET_RATE_PARENT, 0),
1037 	GATE(CLK_OUT_TOP, "clkout_top", "div_clkout_top",
1038 			CLKOUT_CMU_TOP, 16, CLK_SET_RATE_PARENT, 0),
1039 	GATE(CLK_OUT_DMC, "clkout_dmc", "div_clkout_dmc",
1040 			CLKOUT_CMU_DMC, 16, CLK_SET_RATE_PARENT, 0),
1041 	GATE(CLK_OUT_CPU, "clkout_cpu", "div_clkout_cpu",
1042 			CLKOUT_CMU_CPU, 16, CLK_SET_RATE_PARENT, 0),
1043 };
1044 
1045 /* list of gate clocks supported in exynos4210 soc */
1046 static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = {
1047 	GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0),
1048 	GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0),
1049 	GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0),
1050 	GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0),
1051 	GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0),
1052 	GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0,
1053 		0),
1054 	GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4210_GATE_IP_IMAGE, 9, 0,
1055 		0),
1056 	GATE(CLK_PPMULCD1, "ppmulcd1", "aclk160", E4210_GATE_IP_LCD1, 5, 0, 0),
1057 	GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0),
1058 	GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0),
1059 	GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0),
1060 	GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0),
1061 	GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
1062 	GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
1063 	GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
1064 	GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
1065 			CLK_IGNORE_UNUSED, 0),
1066 	GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0,
1067 		0),
1068 	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
1069 			E4210_GATE_IP_IMAGE, 4, 0, 0),
1070 	GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1",
1071 			E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0),
1072 	GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata",
1073 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1074 	GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0),
1075 	GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0),
1076 	GATE(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15,
1077 			0, 0),
1078 	GATE(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13,
1079 			0, 0),
1080 	GATE(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14,
1081 			0, 0),
1082 	GATE(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15,
1083 			0, 0),
1084 	GATE(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16,
1085 			0, 0),
1086 	GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0,
1087 			CLK_SET_RATE_PARENT, 0),
1088 	GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0,
1089 		0),
1090 };
1091 
1092 /* list of gate clocks supported in exynos4x12 soc */
1093 static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
1094 	GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0),
1095 	GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0),
1096 	GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0),
1097 	GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0),
1098 	GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0,
1099 		0),
1100 	GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0,
1101 		0),
1102 	GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0),
1103 	GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
1104 	GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
1105 	GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
1106 			CLK_IGNORE_UNUSED, 0),
1107 	GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0,
1108 		0),
1109 	GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0",
1110 			SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
1111 	GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0",
1112 			SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0),
1113 	GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi",
1114 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1115 	GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200",
1116 			E4X12_GATE_IP_IMAGE, 4, 0, 0),
1117 	GATE(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13,
1118 			0, 0),
1119 	GATE(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15,
1120 			0, 0),
1121 	GATE(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0),
1122 	GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "div_pwm_isp",
1123 			E4X12_GATE_IP_ISP, 0, 0, 0),
1124 	GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "div_spi0_isp_pre",
1125 			E4X12_GATE_IP_ISP, 1, 0, 0),
1126 	GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "div_spi1_isp_pre",
1127 			E4X12_GATE_IP_ISP, 2, 0, 0),
1128 	GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "div_uart_isp",
1129 			E4X12_GATE_IP_ISP, 3, 0, 0),
1130 	GATE(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0),
1131 	GATE(CLK_PCM0, "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2,
1132 			0, 0),
1133 	GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
1134 			0, 0),
1135 	GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
1136 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1137 	GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
1138 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1139 	GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2,
1140 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1141 	GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3,
1142 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1143 	GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4,
1144 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1145 	GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5,
1146 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1147 	GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7,
1148 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1149 	GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8,
1150 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1151 	GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9,
1152 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1153 	GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10,
1154 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1155 	GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
1156 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1157 	GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
1158 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1159 	GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
1160 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1161 	GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
1162 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1163 	GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
1164 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1165 	GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
1166 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1167 	GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
1168 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1169 	GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
1170 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1171 	GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
1172 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1173 	GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28,
1174 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1175 	GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30,
1176 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1177 	GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
1178 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1179 	GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
1180 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1181 	GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
1182 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1183 	GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
1184 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1185 	GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
1186 			CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1187 	GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
1188 	GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
1189 	GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
1190 		0),
1191 };
1192 
1193 static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
1194 	ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
1195 	ALIAS(CLK_ARM_CLK, NULL, "armclk"),
1196 	ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
1197 };
1198 
1199 static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
1200 	ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
1201 };
1202 
1203 static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
1204 	ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
1205 };
1206 
1207 /*
1208  * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
1209  * resides in chipid register space, outside of the clock controller memory
1210  * mapped space. So to determine the parent of fin_pll clock, the chipid
1211  * controller is first remapped and the value of XOM[0] bit is read to
1212  * determine the parent clock.
1213  */
1214 static unsigned long __init exynos4_get_xom(void)
1215 {
1216 	unsigned long xom = 0;
1217 	void __iomem *chipid_base;
1218 	struct device_node *np;
1219 
1220 	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
1221 	if (np) {
1222 		chipid_base = of_iomap(np, 0);
1223 
1224 		if (chipid_base)
1225 			xom = readl(chipid_base + 8);
1226 
1227 		iounmap(chipid_base);
1228 	}
1229 
1230 	return xom;
1231 }
1232 
1233 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
1234 {
1235 	struct samsung_fixed_rate_clock fclk;
1236 	struct clk *clk;
1237 	unsigned long finpll_f = 24000000;
1238 	char *parent_name;
1239 	unsigned int xom = exynos4_get_xom();
1240 
1241 	parent_name = xom & 1 ? "xusbxti" : "xxti";
1242 	clk = clk_get(NULL, parent_name);
1243 	if (IS_ERR(clk)) {
1244 		pr_err("%s: failed to lookup parent clock %s, assuming "
1245 			"fin_pll clock frequency is 24MHz\n", __func__,
1246 			parent_name);
1247 	} else {
1248 		finpll_f = clk_get_rate(clk);
1249 	}
1250 
1251 	fclk.id = CLK_FIN_PLL;
1252 	fclk.name = "fin_pll";
1253 	fclk.parent_name = NULL;
1254 	fclk.flags = 0;
1255 	fclk.fixed_rate = finpll_f;
1256 	samsung_clk_register_fixed_rate(ctx, &fclk, 1);
1257 
1258 }
1259 
1260 static const struct of_device_id ext_clk_match[] __initconst = {
1261 	{ .compatible = "samsung,clock-xxti", .data = (void *)0, },
1262 	{ .compatible = "samsung,clock-xusbxti", .data = (void *)1, },
1263 	{},
1264 };
1265 
1266 /* PLLs PMS values */
1267 static const struct samsung_pll_rate_table exynos4210_apll_rates[] __initconst = {
1268 	PLL_45XX_RATE(1200000000, 150,  3, 1, 28),
1269 	PLL_45XX_RATE(1000000000, 250,  6, 1, 28),
1270 	PLL_45XX_RATE( 800000000, 200,  6, 1, 28),
1271 	PLL_45XX_RATE( 666857142, 389, 14, 1, 13),
1272 	PLL_45XX_RATE( 600000000, 100,  4, 1, 13),
1273 	PLL_45XX_RATE( 533000000, 533, 24, 1,  5),
1274 	PLL_45XX_RATE( 500000000, 250,  6, 2, 28),
1275 	PLL_45XX_RATE( 400000000, 200,  6, 2, 28),
1276 	PLL_45XX_RATE( 200000000, 200,  6, 3, 28),
1277 	{ /* sentinel */ }
1278 };
1279 
1280 static const struct samsung_pll_rate_table exynos4210_epll_rates[] __initconst = {
1281 	PLL_4600_RATE(192000000, 48, 3, 1,     0, 0),
1282 	PLL_4600_RATE(180633605, 45, 3, 1, 10381, 0),
1283 	PLL_4600_RATE(180000000, 45, 3, 1,     0, 0),
1284 	PLL_4600_RATE( 73727996, 73, 3, 3, 47710, 1),
1285 	PLL_4600_RATE( 67737602, 90, 4, 3, 20762, 1),
1286 	PLL_4600_RATE( 49151992, 49, 3, 3,  9961, 0),
1287 	PLL_4600_RATE( 45158401, 45, 3, 3, 10381, 0),
1288 	{ /* sentinel */ }
1289 };
1290 
1291 static const struct samsung_pll_rate_table exynos4210_vpll_rates[] __initconst = {
1292 	PLL_4650_RATE(360000000, 44, 3, 0, 1024, 0, 14, 0),
1293 	PLL_4650_RATE(324000000, 53, 2, 1, 1024, 1,  1, 1),
1294 	PLL_4650_RATE(259617187, 63, 3, 1, 1950, 0, 20, 1),
1295 	PLL_4650_RATE(110000000, 53, 3, 2, 2048, 0, 17, 0),
1296 	PLL_4650_RATE( 55360351, 53, 3, 3, 2417, 0, 17, 0),
1297 	{ /* sentinel */ }
1298 };
1299 
1300 static const struct samsung_pll_rate_table exynos4x12_apll_rates[] __initconst = {
1301 	PLL_35XX_RATE(1704000000, 213, 3, 0),
1302 	PLL_35XX_RATE(1600000000, 200, 3, 0),
1303 	PLL_35XX_RATE(1500000000, 250, 4, 0),
1304 	PLL_35XX_RATE(1400000000, 175, 3, 0),
1305 	PLL_35XX_RATE(1300000000, 325, 6, 0),
1306 	PLL_35XX_RATE(1200000000, 200, 4, 0),
1307 	PLL_35XX_RATE(1100000000, 275, 6, 0),
1308 	PLL_35XX_RATE(1000000000, 125, 3, 0),
1309 	PLL_35XX_RATE( 900000000, 150, 4, 0),
1310 	PLL_35XX_RATE( 800000000, 100, 3, 0),
1311 	PLL_35XX_RATE( 700000000, 175, 3, 1),
1312 	PLL_35XX_RATE( 600000000, 200, 4, 1),
1313 	PLL_35XX_RATE( 500000000, 125, 3, 1),
1314 	PLL_35XX_RATE( 400000000, 100, 3, 1),
1315 	PLL_35XX_RATE( 300000000, 200, 4, 2),
1316 	PLL_35XX_RATE( 200000000, 100, 3, 2),
1317 	{ /* sentinel */ }
1318 };
1319 
1320 static const struct samsung_pll_rate_table exynos4x12_epll_rates[] __initconst = {
1321 	PLL_36XX_RATE(192000000, 48, 3, 1,     0),
1322 	PLL_36XX_RATE(180633605, 45, 3, 1, 10381),
1323 	PLL_36XX_RATE(180000000, 45, 3, 1,     0),
1324 	PLL_36XX_RATE( 73727996, 73, 3, 3, 47710),
1325 	PLL_36XX_RATE( 67737602, 90, 4, 3, 20762),
1326 	PLL_36XX_RATE( 49151992, 49, 3, 3,  9961),
1327 	PLL_36XX_RATE( 45158401, 45, 3, 3, 10381),
1328 	{ /* sentinel */ }
1329 };
1330 
1331 static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = {
1332 	PLL_36XX_RATE(533000000, 133, 3, 1, 16384),
1333 	PLL_36XX_RATE(440000000, 110, 3, 1,     0),
1334 	PLL_36XX_RATE(350000000, 175, 3, 2,     0),
1335 	PLL_36XX_RATE(266000000, 133, 3, 2,     0),
1336 	PLL_36XX_RATE(160000000, 160, 3, 3,     0),
1337 	PLL_36XX_RATE(106031250,  53, 3, 2,  1024),
1338 	PLL_36XX_RATE( 53015625,  53, 3, 3,  1024),
1339 	{ /* sentinel */ }
1340 };
1341 
1342 static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1343 	[apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1344 		APLL_LOCK, APLL_CON0, "fout_apll", NULL),
1345 	[mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1346 		E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),
1347 	[epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1348 		EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),
1349 	[vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1350 		VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),
1351 };
1352 
1353 static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
1354 	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1355 			APLL_LOCK, APLL_CON0, NULL),
1356 	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1357 			E4X12_MPLL_LOCK, E4X12_MPLL_CON0, NULL),
1358 	[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1359 			EPLL_LOCK, EPLL_CON0, NULL),
1360 	[vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
1361 			VPLL_LOCK, VPLL_CON0, NULL),
1362 };
1363 
1364 static void __init exynos4x12_core_down_clock(void)
1365 {
1366 	unsigned int tmp;
1367 
1368 	/*
1369 	 * Enable arm clock down (in idle) and set arm divider
1370 	 * ratios in WFI/WFE state.
1371 	 */
1372 	tmp = (PWR_CTRL1_CORE2_DOWN_RATIO(7) | PWR_CTRL1_CORE1_DOWN_RATIO(7) |
1373 		PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
1374 		PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
1375 		PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
1376 	/* On Exynos4412 enable it also on core 2 and 3 */
1377 	if (num_possible_cpus() == 4)
1378 		tmp |= PWR_CTRL1_USE_CORE3_WFE | PWR_CTRL1_USE_CORE2_WFE |
1379 		       PWR_CTRL1_USE_CORE3_WFI | PWR_CTRL1_USE_CORE2_WFI;
1380 	writel_relaxed(tmp, reg_base + PWR_CTRL1);
1381 
1382 	/*
1383 	 * Disable the clock up feature in case it was enabled by bootloader.
1384 	 */
1385 	writel_relaxed(0x0, reg_base + E4X12_PWR_CTRL2);
1386 }
1387 
1388 #define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0)	\
1389 		(((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) |	\
1390 		((periph) << 12) | ((corem1) << 8) | ((corem0) <<  4))
1391 #define E4210_CPU_DIV1(hpm, copy)					\
1392 		(((hpm) << 4) | ((copy) << 0))
1393 
1394 static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
1395 	{ 1200000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
1396 	{ 1000000, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
1397 	{  800000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1398 	{  500000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1399 	{  400000, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
1400 	{  200000, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
1401 	{  0 },
1402 };
1403 
1404 static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
1405 	{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
1406 	{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
1407 	{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
1408 	{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
1409 	{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
1410 	{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
1411 	{  900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
1412 	{  800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
1413 	{  700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1414 	{  600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1415 	{  500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1416 	{  400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1417 	{  300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1418 	{  200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
1419 	{  0 },
1420 };
1421 
1422 #define E4412_CPU_DIV1(cores, hpm, copy)				\
1423 		(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
1424 
1425 static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
1426 	{ 1704000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 7), },
1427 	{ 1600000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
1428 	{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },
1429 	{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },
1430 	{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },
1431 	{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },
1432 	{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },
1433 	{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },
1434 	{  900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },
1435 	{  800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },
1436 	{  700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },
1437 	{  600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
1438 	{  500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },
1439 	{  400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
1440 	{  300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },
1441 	{  200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },
1442 	{  0 },
1443 };
1444 
1445 /* register exynos4 clocks */
1446 static void __init exynos4_clk_init(struct device_node *np,
1447 				    enum exynos4_soc soc)
1448 {
1449 	struct samsung_clk_provider *ctx;
1450 	exynos4_soc = soc;
1451 
1452 	reg_base = of_iomap(np, 0);
1453 	if (!reg_base)
1454 		panic("%s: failed to map registers\n", __func__);
1455 
1456 	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1457 
1458 	samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
1459 			ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
1460 			ext_clk_match);
1461 
1462 	exynos4_clk_register_finpll(ctx);
1463 
1464 	if (exynos4_soc == EXYNOS4210) {
1465 		samsung_clk_register_mux(ctx, exynos4210_mux_early,
1466 					ARRAY_SIZE(exynos4210_mux_early));
1467 
1468 		if (_get_rate("fin_pll") == 24000000) {
1469 			exynos4210_plls[apll].rate_table =
1470 							exynos4210_apll_rates;
1471 			exynos4210_plls[epll].rate_table =
1472 							exynos4210_epll_rates;
1473 		}
1474 
1475 		if (_get_rate("mout_vpllsrc") == 24000000)
1476 			exynos4210_plls[vpll].rate_table =
1477 							exynos4210_vpll_rates;
1478 
1479 		samsung_clk_register_pll(ctx, exynos4210_plls,
1480 					ARRAY_SIZE(exynos4210_plls), reg_base);
1481 	} else {
1482 		if (_get_rate("fin_pll") == 24000000) {
1483 			exynos4x12_plls[apll].rate_table =
1484 							exynos4x12_apll_rates;
1485 			exynos4x12_plls[epll].rate_table =
1486 							exynos4x12_epll_rates;
1487 			exynos4x12_plls[vpll].rate_table =
1488 							exynos4x12_vpll_rates;
1489 		}
1490 
1491 		samsung_clk_register_pll(ctx, exynos4x12_plls,
1492 					ARRAY_SIZE(exynos4x12_plls), reg_base);
1493 	}
1494 
1495 	samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1496 			ARRAY_SIZE(exynos4_fixed_rate_clks));
1497 	samsung_clk_register_mux(ctx, exynos4_mux_clks,
1498 			ARRAY_SIZE(exynos4_mux_clks));
1499 	samsung_clk_register_div(ctx, exynos4_div_clks,
1500 			ARRAY_SIZE(exynos4_div_clks));
1501 	samsung_clk_register_gate(ctx, exynos4_gate_clks,
1502 			ARRAY_SIZE(exynos4_gate_clks));
1503 	samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1504 			ARRAY_SIZE(exynos4_fixed_factor_clks));
1505 
1506 	if (exynos4_soc == EXYNOS4210) {
1507 		samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1508 			ARRAY_SIZE(exynos4210_fixed_rate_clks));
1509 		samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1510 			ARRAY_SIZE(exynos4210_mux_clks));
1511 		samsung_clk_register_div(ctx, exynos4210_div_clks,
1512 			ARRAY_SIZE(exynos4210_div_clks));
1513 		samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1514 			ARRAY_SIZE(exynos4210_gate_clks));
1515 		samsung_clk_register_alias(ctx, exynos4210_aliases,
1516 			ARRAY_SIZE(exynos4210_aliases));
1517 		samsung_clk_register_fixed_factor(ctx,
1518 			exynos4210_fixed_factor_clks,
1519 			ARRAY_SIZE(exynos4210_fixed_factor_clks));
1520 		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1521 			mout_core_p4210[0], mout_core_p4210[1], 0x14200,
1522 			e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
1523 			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1524 	} else {
1525 		samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1526 			ARRAY_SIZE(exynos4x12_mux_clks));
1527 		samsung_clk_register_div(ctx, exynos4x12_div_clks,
1528 			ARRAY_SIZE(exynos4x12_div_clks));
1529 		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1530 			ARRAY_SIZE(exynos4x12_gate_clks));
1531 		samsung_clk_register_alias(ctx, exynos4x12_aliases,
1532 			ARRAY_SIZE(exynos4x12_aliases));
1533 		samsung_clk_register_fixed_factor(ctx,
1534 			exynos4x12_fixed_factor_clks,
1535 			ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1536 		if (of_machine_is_compatible("samsung,exynos4412")) {
1537 			exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1538 				mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
1539 				e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
1540 				CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1541 		} else {
1542 			exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1543 				mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
1544 				e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
1545 				CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1546 		}
1547 	}
1548 
1549 	samsung_clk_register_alias(ctx, exynos4_aliases,
1550 			ARRAY_SIZE(exynos4_aliases));
1551 
1552 	if (soc == EXYNOS4X12)
1553 		exynos4x12_core_down_clock();
1554 	exynos4_clk_sleep_init();
1555 
1556 	samsung_clk_of_add_provider(np, ctx);
1557 
1558 	pr_info("%s clocks: sclk_apll = %ld, sclk_mpll = %ld\n"
1559 		"\tsclk_epll = %ld, sclk_vpll = %ld, arm_clk = %ld\n",
1560 		exynos4_soc == EXYNOS4210 ? "Exynos4210" : "Exynos4x12",
1561 		_get_rate("sclk_apll"),	_get_rate("sclk_mpll"),
1562 		_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
1563 		_get_rate("div_core2"));
1564 }
1565 
1566 
1567 static void __init exynos4210_clk_init(struct device_node *np)
1568 {
1569 	exynos4_clk_init(np, EXYNOS4210);
1570 }
1571 CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
1572 
1573 static void __init exynos4412_clk_init(struct device_node *np)
1574 {
1575 	exynos4_clk_init(np, EXYNOS4X12);
1576 }
1577 CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);
1578