1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 * Author: Detlev Casanova <detlev.casanova@collabora.com> 6 * Based on Sebastien Reichel's implementation for RK3588 7 */ 8 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <dt-bindings/reset/rockchip,rk3576-cru.h> 12 #include "clk.h" 13 14 /* 0x27200000 + 0x0A00 */ 15 #define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) 16 /* 0x27208000 + 0x0A00 */ 17 #define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) 18 /* 0x27210000 + 0x0A00 */ 19 #define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) 20 /* 0x27220000 + 0x0A00 */ 21 #define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) 22 23 /* mapping table for reset ID to register offset */ 24 static const int rk3576_register_offset[] = { 25 /* SOFTRST_CON01 */ 26 RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), 27 RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5), 28 RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6), 29 RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7), 30 RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14), 31 32 /* SOFTRST_CON02 */ 33 RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0), 34 RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1), 35 36 /* SOFTRST_CON06 */ 37 RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2), 38 39 /* SOFTRST_CON07 */ 40 RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), 41 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3), 42 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4), 43 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5), 44 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6), 45 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7), 46 RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8), 47 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9), 48 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10), 49 RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12), 50 RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13), 51 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14), 52 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15), 53 54 /* SOFTRST_CON08 */ 55 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0), 56 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1), 57 RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5), 58 RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6), 59 RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8), 60 RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10), 61 RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12), 62 RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14), 63 64 /* SOFTRST_CON09 */ 65 RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0), 66 RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2), 67 RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3), 68 RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4), 69 RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5), 70 RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7), 71 RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8), 72 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9), 73 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10), 74 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11), 75 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12), 76 77 /* SOFTRST_CON11 */ 78 RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3), 79 RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4), 80 RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5), 81 RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6), 82 RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7), 83 RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8), 84 RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9), 85 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12), 86 RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13), 87 RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14), 88 RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15), 89 90 /* SOFTRST_CON12 */ 91 RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), 92 RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1), 93 RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2), 94 RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3), 95 RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4), 96 RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5), 97 RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6), 98 RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7), 99 RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8), 100 RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9), 101 RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10), 102 RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11), 103 RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12), 104 RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13), 105 RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14), 106 RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15), 107 108 /* SOFTRST_CON13 */ 109 RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0), 110 RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1), 111 RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2), 112 RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3), 113 RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4), 114 RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6), 115 RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7), 116 RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8), 117 RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9), 118 RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10), 119 RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11), 120 RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12), 121 RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13), 122 RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14), 123 RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15), 124 125 /* SOFTRST_CON14 */ 126 RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0), 127 RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1), 128 RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2), 129 RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3), 130 RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4), 131 RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5), 132 RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6), 133 RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9), 134 RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12), 135 RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15), 136 137 /* SOFTRST_CON15 */ 138 RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2), 139 RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5), 140 RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8), 141 RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9), 142 RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10), 143 RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11), 144 RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13), 145 RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14), 146 RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15), 147 148 /* SOFTRST_CON16 */ 149 RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0), 150 RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1), 151 RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2), 152 RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3), 153 RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4), 154 RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5), 155 RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6), 156 RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7), 157 RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8), 158 RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9), 159 RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10), 160 RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11), 161 162 /* SOFTRST_CON17 */ 163 RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3), 164 RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4), 165 RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6), 166 RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7), 167 RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8), 168 RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9), 169 RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10), 170 RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11), 171 RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12), 172 RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13), 173 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15), 174 175 /* SOFTRST_CON18 */ 176 RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0), 177 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1), 178 RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2), 179 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3), 180 RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4), 181 RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5), 182 RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6), 183 RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7), 184 RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8), 185 RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9), 186 RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11), 187 RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12), 188 RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13), 189 RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14), 190 RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15), 191 192 /* SOFTRST_CON19 */ 193 RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0), 194 RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1), 195 RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2), 196 RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3), 197 RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4), 198 RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5), 199 RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7), 200 RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9), 201 RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11), 202 RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12), 203 RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13), 204 205 /* SOFTRST_CON20 */ 206 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0), 207 RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1), 208 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3), 209 RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4), 210 RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5), 211 RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8), 212 RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9), 213 RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12), 214 RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13), 215 216 /* SOFTRST_CON21 */ 217 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1), 218 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2), 219 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3), 220 RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4), 221 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5), 222 RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6), 223 RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10), 224 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13), 225 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14), 226 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15), 227 228 /* SOFTRST_CON22 */ 229 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0), 230 RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1), 231 RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2), 232 RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3), 233 RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4), 234 RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6), 235 RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9), 236 RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10), 237 RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12), 238 RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13), 239 RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14), 240 RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15), 241 242 /* SOFTRST_CON23 */ 243 RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1), 244 RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2), 245 RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4), 246 RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5), 247 RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6), 248 RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7), 249 RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8), 250 RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9), 251 RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11), 252 253 /* SOFTRST_CON25 */ 254 RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1), 255 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2), 256 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3), 257 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4), 258 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5), 259 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6), 260 261 /* SOFTRST_CON26 */ 262 RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1), 263 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2), 264 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3), 265 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4), 266 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5), 267 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6), 268 269 /* SOFTRST_CON27 */ 270 RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0), 271 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1), 272 273 /* SOFTRST_CON28 */ 274 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9), 275 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11), 276 RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12), 277 278 /* SOFTRST_CON29 */ 279 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0), 280 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2), 281 RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3), 282 283 /* SOFTRST_CON31 */ 284 RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0), 285 RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1), 286 RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9), 287 RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10), 288 RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12), 289 RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13), 290 RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14), 291 RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15), 292 293 /* SOFTRST_CON32 */ 294 RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0), 295 RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1), 296 RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2), 297 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3), 298 RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4), 299 RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6), 300 RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7), 301 RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8), 302 RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11), 303 RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12), 304 RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13), 305 306 /* SOFTRST_CON33 */ 307 RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2), 308 RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3), 309 RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6), 310 RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7), 311 RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8), 312 RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9), 313 RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10), 314 RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11), 315 RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12), 316 317 /* SOFTRST_CON34 */ 318 RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1), 319 RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5), 320 RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9), 321 RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13), 322 RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15), 323 324 /* SOFTRST_CON35 */ 325 RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3), 326 RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11), 327 RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13), 328 RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14), 329 330 /* SOFTRST_CON36 */ 331 RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0), 332 RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7), 333 RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9), 334 335 /* SOFTRST_CON37 */ 336 RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0), 337 RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1), 338 RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2), 339 RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3), 340 RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4), 341 RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5), 342 RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6), 343 RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7), 344 345 /* SOFTRST_CON40 */ 346 RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2), 347 RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3), 348 349 /* SOFTRST_CON42 */ 350 RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3), 351 RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4), 352 RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5), 353 RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6), 354 RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7), 355 RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8), 356 RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9), 357 RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10), 358 RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12), 359 360 /* SOFTRST_CON43 */ 361 RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2), 362 RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3), 363 RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4), 364 RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6), 365 RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7), 366 RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8), 367 RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10), 368 RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11), 369 RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13), 370 371 /* SOFTRST_CON45 */ 372 RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3), 373 RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5), 374 RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6), 375 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8), 376 RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9), 377 378 /* SOFTRST_CON47 */ 379 RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3), 380 RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4), 381 RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5), 382 RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10), 383 RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12), 384 RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13), 385 RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15), 386 387 /* SOFTRST_CON48 */ 388 RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0), 389 RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1), 390 RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2), 391 392 /* SOFTRST_CON49 */ 393 RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6), 394 RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7), 395 RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10), 396 RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11), 397 RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12), 398 RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13), 399 RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14), 400 RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15), 401 402 /* SOFTRST_CON50 */ 403 RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0), 404 RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1), 405 RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2), 406 RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3), 407 RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4), 408 RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5), 409 RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6), 410 RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7), 411 RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10), 412 RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11), 413 RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12), 414 415 /* SOFTRST_CON51 */ 416 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2), 417 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3), 418 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4), 419 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5), 420 RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6), 421 422 /* SOFTRST_CON53 */ 423 RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3), 424 RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4), 425 RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5), 426 RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6), 427 RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7), 428 RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8), 429 RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10), 430 RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11), 431 432 /* SOFTRST_CON54 */ 433 RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1), 434 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4), 435 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5), 436 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6), 437 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7), 438 RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8), 439 440 /* SOFTRST_CON59 */ 441 RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0), 442 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1), 443 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2), 444 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3), 445 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4), 446 RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5), 447 448 /* SOFTRST_CON61 */ 449 RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4), 450 RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5), 451 RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6), 452 RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7), 453 RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8), 454 RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9), 455 RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13), 456 457 /* SOFTRST_CON62 */ 458 RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0), 459 RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1), 460 RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2), 461 RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3), 462 463 /* SOFTRST_CON63 */ 464 RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5), 465 RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7), 466 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9), 467 RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10), 468 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12), 469 RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13), 470 RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14), 471 472 /* SOFTRST_CON64 */ 473 RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5), 474 RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6), 475 RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7), 476 RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9), 477 RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13), 478 RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14), 479 480 /* SOFTRST_CON65 */ 481 RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4), 482 RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5), 483 RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8), 484 RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9), 485 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10), 486 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13), 487 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14), 488 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15), 489 490 /* SOFTRST_CON66 */ 491 RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0), 492 RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2), 493 494 /* SOFTRST_CON67 */ 495 RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5), 496 RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6), 497 RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9), 498 RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10), 499 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11), 500 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12), 501 RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13), 502 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14), 503 504 /* SOFTRST_CON68 */ 505 RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0), 506 RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2), 507 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3), 508 RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4), 509 RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5), 510 RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6), 511 RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9), 512 RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11), 513 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12), 514 RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13), 515 516 /* SOFTRST_CON69 */ 517 RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3), 518 RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6), 519 RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7), 520 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9), 521 RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13), 522 RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14), 523 RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15), 524 525 /* SOFTRST_CON72 */ 526 RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4), 527 RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5), 528 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6), 529 RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7), 530 RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8), 531 RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9), 532 RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10), 533 RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11), 534 RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12), 535 536 /* SOFTRST_CON75 */ 537 RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1), 538 539 /* SOFTRST_CON78 */ 540 RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1), 541 RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2), 542 RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3), 543 RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4), 544 545 /* SOFTRST_CON79 */ 546 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1), 547 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2), 548 RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3), 549 RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4), 550 RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5), 551 552 /* PPLL_SOFTRST_CON00 */ 553 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1), 554 RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3), 555 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5), 556 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6), 557 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7), 558 RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8), 559 560 /* PPLL_SOFTRST_CON01 */ 561 RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5), 562 RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8), 563 564 /* SECURENS_SOFTRST_CON00 */ 565 RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3), 566 RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4), 567 RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8), 568 RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9), 569 570 /* PMU1_SOFTRST_CON00 */ 571 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0), 572 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1), 573 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2), 574 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3), 575 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4), 576 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5), 577 RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6), 578 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7), 579 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8), 580 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9), 581 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10), 582 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11), 583 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12), 584 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15), 585 586 /* PMU1_SOFTRST_CON01 */ 587 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0), 588 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1), 589 RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2), 590 RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3), 591 RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4), 592 RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5), 593 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6), 594 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7), 595 RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8), 596 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9), 597 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10), 598 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11), 599 RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13), 600 601 /* PMU1_SOFTRST_CON02 */ 602 RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0), 603 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1), 604 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3), 605 606 /* PMU1_SOFTRST_CON03 */ 607 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9), 608 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10), 609 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11), 610 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12), 611 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13), 612 613 /* PMU1_SOFTRST_CON04 */ 614 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1), 615 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3), 616 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4), 617 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5), 618 RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6), 619 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7), 620 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9), 621 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10), 622 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11), 623 RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12), 624 625 /* PMU1_SOFTRST_CON05 */ 626 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1), 627 RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2), 628 RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5), 629 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6), 630 RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13), 631 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15), 632 633 /* PMU1_SOFTRST_CON06 */ 634 RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0), 635 RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1), 636 637 /* PMU1_SOFTRST_CON07 */ 638 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4), 639 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5), 640 RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6), 641 RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7), 642 }; 643 644 void rk3576_rst_init(struct device_node *np, void __iomem *reg_base) 645 { 646 rockchip_register_softrst_lut(np, 647 rk3576_register_offset, 648 ARRAY_SIZE(rk3576_register_offset), 649 reg_base + RK3576_SOFTRST_CON(0), 650 ROCKCHIP_SOFTRST_HIWORD_MASK); 651 } 652